ppcreg.h revision 28259
153537Sbrian/*- 280728Sbrian * Copyright (c) 1997 Nicolas Souchu 353537Sbrian * All rights reserved. 453537Sbrian * 553537Sbrian * Redistribution and use in source and binary forms, with or without 653537Sbrian * modification, are permitted provided that the following conditions 753537Sbrian * are met: 853537Sbrian * 1. Redistributions of source code must retain the above copyright 953537Sbrian * notice, this list of conditions and the following disclaimer. 1053537Sbrian * 2. Redistributions in binary form must reproduce the above copyright 1153537Sbrian * notice, this list of conditions and the following disclaimer in the 1253537Sbrian * documentation and/or other materials provided with the distribution. 1353537Sbrian * 1453537Sbrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1553537Sbrian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1653537Sbrian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1753537Sbrian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1853537Sbrian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1953537Sbrian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2053537Sbrian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2153537Sbrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2253537Sbrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2353537Sbrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2453537Sbrian * SUCH DAMAGE. 2553537Sbrian * 2653537Sbrian * $Id: ppcreg.h,v 1.1 1997/08/14 14:01:36 msmith Exp $ 2753537Sbrian * 2853537Sbrian */ 2953537Sbrian#ifndef __PPC_H 3053537Sbrian#define __PPC_H 3153537Sbrian 3253537Sbrian/* 3353537Sbrian * Parallel Port Chipset type. 3453537Sbrian */ 3553537Sbrian#define SMC_UNKNOWN 0x0 3653537Sbrian#define SMC_37C665GT 0x1 3753537Sbrian#define SMC_37C666GT 0x2 3853537Sbrian#define NS_UNKNOWN 0x3 3953537Sbrian#define NS_PC87332 0x4 4053537Sbrian#define NS_PC87306 0x5 4153537Sbrian#define INTEL_820191AA 0x6 4253537Sbrian#define GENERIC 0x7 4353537Sbrian 4453537Sbrian/* 4553537Sbrian * Generic structure to hold parallel port chipset info. 4653537Sbrian */ 4753537Sbrianstruct ppc_data { 4866602Sbrian 4953537Sbrian int ppc_unit; 5053537Sbrian int ppc_type; 5153537Sbrian 5253537Sbrian#define ppc_base ppc_link.base 5353537Sbrian#define ppc_mode ppc_link.mode 5453537Sbrian#define ppc_epp ppc_link.epp_protocol 5553537Sbrian#define ppc_irq ppc_link.id_irq 5653537Sbrian 5753537Sbrian unsigned char ppc_flags; 5853537Sbrian 5953537Sbrian struct ppb_link ppc_link; 6053537Sbrian}; 6153537Sbrian 6253537Sbrian/* 6353537Sbrian * Parallel Port Chipset errors. XXX 6486705Sbrian */ 6586705Sbrian#define PPC_ENOPORT 9 6696580Sbrian 6753537Sbrian/* 6890160Skris * Parallel Port Chipset registers. 6990160Skris */ 7069582Sbrian#define PPC_SPP_DTR 0 /* SPP data register */ 7169582Sbrian#define PPC_SPP_STR 1 /* SPP status register */ 7253537Sbrian#define PPC_SPP_CTR 2 /* SPP control register */ 7353537Sbrian#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */ 7453537Sbrian#define PPC_ECP_FIFO 0x400 /* ECP fifo register */ 7595258Sdes#define PPC_ECP_ECR 0x402 /* ECP extended control register */ 76141589Sru 7753537Sbrian#define r_dtr(ppc) inb((ppc)->ppc_base + PPC_SPP_DTR) 7853537Sbrian#define r_str(ppc) inb((ppc)->ppc_base + PPC_SPP_STR) 7953537Sbrian#define r_ctr(ppc) inb((ppc)->ppc_base + PPC_SPP_CTR) 8053537Sbrian#define r_epp(ppc) inb((ppc)->ppc_base + PPC_EPP_DATA) 8169582Sbrian#define r_ecr(ppc) inb((ppc)->ppc_base + PPC_ECP_ECR) 8253537Sbrian#define r_fifo(ppc) inb((ppc)->ppc_base + PPC_ECP_FIFO) 8369582Sbrian 8453537Sbrian#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte) 8553537Sbrian#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte) 8653537Sbrian#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte) 8753537Sbrian#define w_epp(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte) 8853537Sbrian#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte) 8953537Sbrian#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_FIFO, byte) 9053537Sbrian 9153537Sbrian/* 9253537Sbrian * Register defines for the PC873xx parts 9353537Sbrian */ 9453537Sbrian 9553537Sbrian#define PC873_FER 0x00 9653537Sbrian#define PC873_PPENABLE (1<<0) 9753537Sbrian#define PC873_FAR 0x01 9853537Sbrian#define PC873_PTR 0x02 9953537Sbrian#define PC873_CFGLOCK (1<<6) 10053537Sbrian#define PC873_EPPRDIR (1<<7) 10153537Sbrian#define PC873_FCR 0x03 10253537Sbrian#define PC873_ZWS (1<<5) 10353537Sbrian#define PC873_ZWSPWDN (1<<6) 10453537Sbrian#define PC873_PCR 0x04 10553537Sbrian#define PC873_EPPEN (1<<0) 10653537Sbrian#define PC873_EPP19 (1<<1) 10753537Sbrian#define PC873_ECPEN (1<<2) 10853537Sbrian#define PC873_ECPCLK (1<<3) 10953537Sbrian#define PC873_PMC 0x06 11053537Sbrian#define PC873_TUP 0x07 11153537Sbrian#define PC873_SID 0x08 11253537Sbrian 11353537Sbrian/* 11453537Sbrian * Register defines for the SMC FDC37C66xGT parts. 11553537Sbrian */ 11653537Sbrian 11753537Sbrian/* Init codes */ 11853537Sbrian#define SMC665_iCODE 0x55 11953537Sbrian#define SMC666_iCODE 0x44 12053537Sbrian 12153537Sbrian/* Base configuration ports */ 12253537Sbrian#define SMC66x_CSR 0x3F0 12353537Sbrian#define SMC666_CSR 0x370 /* hard-configured value for 666 */ 12453537Sbrian 12553537Sbrian/* Bits */ 12653537Sbrian#define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */ 12753537Sbrian#define SMC_CR1_MODE 0x8 /* bit 3 */ 12853537Sbrian#define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */ 12953537Sbrian#define SMC_CR4_EPPTYPE 0x40 /* bit 6 */ 13053537Sbrian 13153537Sbrian/* Extended modes */ 13253537Sbrian#define SMC_SPP 0x0 /* SPP */ 13353537Sbrian#define SMC_EPPSPP 0x1 /* EPP and SPP */ 13453537Sbrian#define SMC_ECP 0x2 /* ECP */ 13553537Sbrian#define SMC_ECPEPP 0x3 /* ECP and EPP */ 13653537Sbrian 13753537Sbrian#endif 13853537Sbrian 13953537Sbrian