pci_subr.c revision 69908
1/*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/dev/pci/pci_pci.c 69908 2000-12-12 13:20:35Z msmith $ 31 */ 32 33/* 34 * PCI:PCI bridge support. 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/kernel.h> 40#include <sys/bus.h> 41 42#include <machine/resource.h> 43 44#include <pci/pcivar.h> 45#include <pci/pcireg.h> 46 47#include "pcib_if.h" 48 49/* 50 * Bridge-specific data. 51 */ 52struct pcib_softc 53{ 54 device_t dev; 55 u_int8_t secbus; /* secondary bus number */ 56 u_int8_t subbus; /* subordinate bus number */ 57 pci_addr_t pmembase; /* base address of prefetchable memory */ 58 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 59 u_int32_t membase; /* base address of memory window */ 60 u_int32_t memlimit; /* topmost address of memory window */ 61 u_int32_t iobase; /* base address of port window */ 62 u_int32_t iolimit; /* topmost address of port window */ 63 u_int16_t secstat; /* secondary bus status register */ 64 u_int16_t bridgectl; /* bridge control register */ 65 u_int8_t seclat; /* secondary bus latency timer */ 66}; 67 68static int pcib_probe(device_t dev); 69static int pcib_attach(device_t dev); 70static int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result); 71static int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value); 72static struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 73 u_long start, u_long end, u_long count, u_int flags); 74static int pcib_maxslots(device_t dev); 75static u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width); 76static void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width); 77static int pcib_route_interrupt(device_t pcib, device_t dev, int pin); 78 79static device_method_t pcib_methods[] = { 80 /* Device interface */ 81 DEVMETHOD(device_probe, pcib_probe), 82 DEVMETHOD(device_attach, pcib_attach), 83 DEVMETHOD(device_shutdown, bus_generic_shutdown), 84 DEVMETHOD(device_suspend, bus_generic_suspend), 85 DEVMETHOD(device_resume, bus_generic_resume), 86 87 /* Bus interface */ 88 DEVMETHOD(bus_print_child, bus_generic_print_child), 89 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 90 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 91 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 92 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 93 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 94 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 95 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 96 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 97 98 /* pcib interface */ 99 DEVMETHOD(pcib_maxslots, pcib_maxslots), 100 DEVMETHOD(pcib_read_config, pcib_read_config), 101 DEVMETHOD(pcib_write_config, pcib_write_config), 102 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 103 104 { 0, 0 } 105}; 106 107static driver_t pcib_driver = { 108 "pcib", 109 pcib_methods, 110 sizeof(struct pcib_softc), 111}; 112 113static devclass_t pcib_devclass; 114 115DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 116 117/* 118 * Generic device interface 119 */ 120static int 121pcib_probe(device_t dev) 122{ 123 if ((pci_get_class(dev) == PCIC_BRIDGE) && 124 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 125 device_set_desc(dev, "PCI-PCI bridge"); 126 return(-10000); 127 } 128 return(ENXIO); 129} 130 131static int 132pcib_attach(device_t dev) 133{ 134 struct pcib_softc *sc; 135 device_t child; 136 u_int8_t iolow; 137 138 sc = device_get_softc(dev); 139 sc->dev = dev; 140 141 /* 142 * Get current bridge configuration. 143 */ 144 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 145 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 146 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 147 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 148 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 149 150 /* 151 * Determine current I/O decode. 152 */ 153 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 154 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 155 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 156 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 157 } else { 158 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 159 } 160 161 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 162 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 163 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 164 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 165 } else { 166 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 167 } 168 169 /* 170 * Determine current memory decode. 171 */ 172 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 173 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 174 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 175 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 176 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 177 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 178 179 /* 180 * Quirk handling. 181 */ 182 switch (pci_get_devid(dev)) { 183 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 184 { 185 u_int8_t supbus; 186 187 supbus = pci_read_config(dev, 0x41, 1); 188 if (supbus != 0xff) { 189 sc->secbus = supbus + 1; 190 sc->subbus = supbus + 1; 191 } 192 } 193 break; 194 } 195 196 197 if (bootverbose) { 198 device_printf(dev, " secondary bus %d\n", sc->secbus); 199 device_printf(dev, " subordinate bus %d\n", sc->subbus); 200 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 201 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 202 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 203 } 204 205 /* 206 * XXX If the secondary bus number is zero, we should assign a bus number 207 * since the BIOS hasn't, then initialise the bridge. 208 */ 209 210 /* 211 * XXX If the subordinate bus number is less than the secondary bus number, 212 * we should pick a better value. One sensible alternative would be to 213 * pick 255; the only tradeoff here is that configuration transactions 214 * would be more widely routed than absolutely necessary. 215 */ 216 217 if (sc->secbus != 0) { 218 child = device_add_child(dev, "pci", -1); 219 if (child != NULL) 220 return(bus_generic_attach(dev)); 221 } 222 223 /* no secondary bus; we should have fixed this */ 224 return(0); 225} 226 227static int 228pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 229{ 230 struct pcib_softc *sc = device_get_softc(dev); 231 232 switch (which) { 233 case PCIB_IVAR_BUS: 234 *result = sc->secbus; 235 return(0); 236 } 237 return(ENOENT); 238} 239 240static int 241pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 242{ 243 struct pcib_softc *sc = device_get_softc(dev); 244 245 switch (which) { 246 case PCIB_IVAR_BUS: 247 sc->secbus = value; 248 break; 249 } 250 return(ENOENT); 251} 252 253/* 254 * We have to trap resource allocation requests and ensure that the bridge 255 * is set up to, or capable of handling them. 256 */ 257static struct resource * 258pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 259 u_long start, u_long end, u_long count, u_int flags) 260{ 261 struct pcib_softc *sc = device_get_softc(dev); 262 263 /* 264 * If this is a "default" allocation against this rid, we can't work 265 * out where it's coming from (we should actually never see these) so we 266 * just have to punt. 267 */ 268 if ((start == 0) && (end == ~0)) { 269 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n", 270 *rid, device_get_name(child), device_get_unit(child)); 271 } else { 272 /* 273 * Fail the allocation for this range if it's not supported. 274 * 275 * XXX we should probably just fix up the bridge decode and soldier on. 276 */ 277 switch (type) { 278 case SYS_RES_IOPORT: 279 if ((start < sc->iobase) || (end > sc->iolimit)) { 280 device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx" 281 " (decoding 0x%x-0x%x)\n", 282 device_get_name(child), device_get_unit(child), start, end, 283 sc->iobase, sc->iolimit); 284 return(NULL); 285 } 286 if (bootverbose) 287 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n", 288 device_get_name(child), device_get_unit(child), start, end); 289 break; 290 291 /* 292 * XXX will have to decide whether the device making the request is asking 293 * for prefetchable memory or not. If it's coming from another bridge 294 * down the line, do we assume not, or ask the bridge to pass in another 295 * flag as the request bubbles up? 296 */ 297 case SYS_RES_MEMORY: 298 if (((start < sc->membase) || (end > sc->memlimit)) && 299 ((start < sc->pmembase) || (end > sc->pmemlimit))) { 300 device_printf(dev, "device %s%d requested unsupported memory range 0x%lx-0x%lx" 301 " (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 302 device_get_name(child), device_get_unit(child), start, end, 303 sc->membase, sc->memlimit, sc->pmembase, sc->pmemlimit); 304 return(NULL); 305 } 306 if (bootverbose) 307 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n", 308 device_get_name(child), device_get_unit(child), start, end); 309 break; 310 311 default: 312 break; 313 } 314 } 315 316 /* 317 * Bridge is OK decoding this resource, so pass it up. 318 */ 319 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 320} 321 322/* 323 * PCIB interface. 324 */ 325static int 326pcib_maxslots(device_t dev) 327{ 328 return(PCI_SLOTMAX); 329} 330 331/* 332 * Since we are a child of a PCI bus, its parent must support the pcib interface. 333 */ 334static u_int32_t 335pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 336{ 337 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 338} 339 340static void 341pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width) 342{ 343 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 344} 345 346/* 347 * Route an interrupt across a PCI bridge. 348 */ 349static int 350pcib_route_interrupt(device_t pcib, device_t dev, int pin) 351{ 352 device_t bus; 353 int parent_intpin; 354 int intnum; 355 356 /* 357 * 358 * The PCI standard defines a swizzle of the child-side device/intpin to 359 * the parent-side intpin as follows. 360 * 361 * device = device on child bus 362 * child_intpin = intpin on child bus slot (0-3) 363 * parent_intpin = intpin on parent bus slot (0-3) 364 * 365 * parent_intpin = (device + child_intpin) % 4 366 */ 367 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4; 368 369 /* 370 * Our parent is a PCI bus. Its parent must export the pcib interface 371 * which includes the ability to route interrupts. 372 */ 373 bus = device_get_parent(pcib); 374 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 375 device_printf(pcib, "routed slot %d INT%c to irq %d\n", pci_get_slot(dev), 376 'A' + pin - 1, intnum); 377 return(intnum); 378} 379