pci_subr.c revision 181794
1/*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/pci/pci_pci.c 181794 2008-08-16 21:51:54Z imp $"); 33 34/* 35 * PCI:PCI bridge support. 36 */ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/kernel.h> 41#include <sys/module.h> 42#include <sys/bus.h> 43#include <machine/bus.h> 44#include <sys/rman.h> 45#include <sys/sysctl.h> 46 47#include <machine/resource.h> 48 49#include <dev/pci/pcivar.h> 50#include <dev/pci/pcireg.h> 51#include <dev/pci/pcib_private.h> 52 53#include "pcib_if.h" 54 55static int pcib_probe(device_t dev); 56 57static device_method_t pcib_methods[] = { 58 /* Device interface */ 59 DEVMETHOD(device_probe, pcib_probe), 60 DEVMETHOD(device_attach, pcib_attach), 61 DEVMETHOD(device_detach, bus_generic_detach), 62 DEVMETHOD(device_shutdown, bus_generic_shutdown), 63 DEVMETHOD(device_suspend, bus_generic_suspend), 64 DEVMETHOD(device_resume, bus_generic_resume), 65 66 /* Bus interface */ 67 DEVMETHOD(bus_print_child, bus_generic_print_child), 68 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 69 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 70 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 71 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 72 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 73 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 74 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 75 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 76 77 /* pcib interface */ 78 DEVMETHOD(pcib_maxslots, pcib_maxslots), 79 DEVMETHOD(pcib_read_config, pcib_read_config), 80 DEVMETHOD(pcib_write_config, pcib_write_config), 81 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 82 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 83 DEVMETHOD(pcib_release_msi, pcib_release_msi), 84 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 85 DEVMETHOD(pcib_release_msix, pcib_release_msix), 86 DEVMETHOD(pcib_map_msi, pcib_map_msi), 87 88 { 0, 0 } 89}; 90 91static devclass_t pcib_devclass; 92 93DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 94DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 95 96/* 97 * Is the prefetch window open (eg, can we allocate memory in it?) 98 */ 99static int 100pcib_is_prefetch_open(struct pcib_softc *sc) 101{ 102 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 103} 104 105/* 106 * Is the nonprefetch window open (eg, can we allocate memory in it?) 107 */ 108static int 109pcib_is_nonprefetch_open(struct pcib_softc *sc) 110{ 111 return (sc->membase > 0 && sc->membase < sc->memlimit); 112} 113 114/* 115 * Is the io window open (eg, can we allocate ports in it?) 116 */ 117static int 118pcib_is_io_open(struct pcib_softc *sc) 119{ 120 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 121} 122 123/* 124 * Generic device interface 125 */ 126static int 127pcib_probe(device_t dev) 128{ 129 if ((pci_get_class(dev) == PCIC_BRIDGE) && 130 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 131 device_set_desc(dev, "PCI-PCI bridge"); 132 return(-10000); 133 } 134 return(ENXIO); 135} 136 137void 138pcib_attach_common(device_t dev) 139{ 140 struct pcib_softc *sc; 141 uint8_t iolow; 142 struct sysctl_ctx_list *sctx; 143 struct sysctl_oid *soid; 144 145 sc = device_get_softc(dev); 146 sc->dev = dev; 147 148 /* 149 * Get current bridge configuration. 150 */ 151 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 152 sc->domain = pci_get_domain(dev); 153 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); 154 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 155 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 156 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 157 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 158 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 159 160 /* 161 * Setup sysctl reporting nodes 162 */ 163 sctx = device_get_sysctl_ctx(dev); 164 soid = device_get_sysctl_tree(dev); 165 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 166 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 167 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 168 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 169 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 170 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); 171 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 172 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); 173 174 /* 175 * Determine current I/O decode. 176 */ 177 if (sc->command & PCIM_CMD_PORTEN) { 178 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 179 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 180 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 181 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 182 } else { 183 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 184 } 185 186 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 187 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 188 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 189 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 190 } else { 191 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 192 } 193 } 194 195 /* 196 * Determine current memory decode. 197 */ 198 if (sc->command & PCIM_CMD_MEMEN) { 199 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 200 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 201 sc->pmembase = PCI_PPBMEMBASE(pci_read_config(dev, PCIR_PMBASEH_1, 4), 202 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 203 sc->pmemlimit = PCI_PPBMEMLIMIT(pci_read_config(dev, PCIR_PMLIMITH_1, 4), 204 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 205 } 206 207 /* 208 * Quirk handling. 209 */ 210 switch (pci_get_devid(dev)) { 211 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 212 { 213 uint8_t supbus; 214 215 supbus = pci_read_config(dev, 0x41, 1); 216 if (supbus != 0xff) { 217 sc->secbus = supbus + 1; 218 sc->subbus = supbus + 1; 219 } 220 break; 221 } 222 223 /* 224 * The i82380FB mobile docking controller is a PCI-PCI bridge, 225 * and it is a subtractive bridge. However, the ProgIf is wrong 226 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 227 * happen. There's also a Toshiba bridge that behaves this 228 * way. 229 */ 230 case 0x124b8086: /* Intel 82380FB Mobile */ 231 case 0x060513d7: /* Toshiba ???? */ 232 sc->flags |= PCIB_SUBTRACTIVE; 233 break; 234 235 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 236 case 0x00dd10de: 237 { 238 char *cp; 239 240 if ((cp = getenv("smbios.planar.maker")) == NULL) 241 break; 242 if (strncmp(cp, "Compal", 6) != 0) { 243 freeenv(cp); 244 break; 245 } 246 freeenv(cp); 247 if ((cp = getenv("smbios.planar.product")) == NULL) 248 break; 249 if (strncmp(cp, "08A0", 4) != 0) { 250 freeenv(cp); 251 break; 252 } 253 freeenv(cp); 254 if (sc->subbus < 0xa) { 255 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 256 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 257 } 258 break; 259 } 260 } 261 262 if (pci_msi_device_blacklisted(dev)) 263 sc->flags |= PCIB_DISABLE_MSI; 264 265 /* 266 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 267 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 268 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 269 * This means they act as if they were subtractively decoding 270 * bridges and pass all transactions. Mark them and real ProgIf 1 271 * parts as subtractive. 272 */ 273 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 274 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 275 sc->flags |= PCIB_SUBTRACTIVE; 276 277 if (bootverbose) { 278 device_printf(dev, " domain %d\n", sc->domain); 279 device_printf(dev, " secondary bus %d\n", sc->secbus); 280 device_printf(dev, " subordinate bus %d\n", sc->subbus); 281 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 282 if (pcib_is_nonprefetch_open(sc)) 283 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 284 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 285 if (pcib_is_prefetch_open(sc)) 286 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 287 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 288 else 289 device_printf(dev, " no prefetched decode\n"); 290 if (sc->flags & PCIB_SUBTRACTIVE) 291 device_printf(dev, " Subtractively decoded bridge.\n"); 292 } 293 294 /* 295 * XXX If the secondary bus number is zero, we should assign a bus number 296 * since the BIOS hasn't, then initialise the bridge. 297 */ 298 299 /* 300 * XXX If the subordinate bus number is less than the secondary bus number, 301 * we should pick a better value. One sensible alternative would be to 302 * pick 255; the only tradeoff here is that configuration transactions 303 * would be more widely routed than absolutely necessary. 304 */ 305} 306 307int 308pcib_attach(device_t dev) 309{ 310 struct pcib_softc *sc; 311 device_t child; 312 313 pcib_attach_common(dev); 314 sc = device_get_softc(dev); 315 if (sc->secbus != 0) { 316 child = device_add_child(dev, "pci", sc->secbus); 317 if (child != NULL) 318 return(bus_generic_attach(dev)); 319 } 320 321 /* no secondary bus; we should have fixed this */ 322 return(0); 323} 324 325int 326pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 327{ 328 struct pcib_softc *sc = device_get_softc(dev); 329 330 switch (which) { 331 case PCIB_IVAR_DOMAIN: 332 *result = sc->domain; 333 return(0); 334 case PCIB_IVAR_BUS: 335 *result = sc->secbus; 336 return(0); 337 } 338 return(ENOENT); 339} 340 341int 342pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 343{ 344 struct pcib_softc *sc = device_get_softc(dev); 345 346 switch (which) { 347 case PCIB_IVAR_DOMAIN: 348 return(EINVAL); 349 case PCIB_IVAR_BUS: 350 sc->secbus = value; 351 return(0); 352 } 353 return(ENOENT); 354} 355 356/* 357 * We have to trap resource allocation requests and ensure that the bridge 358 * is set up to, or capable of handling them. 359 */ 360struct resource * 361pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 362 u_long start, u_long end, u_long count, u_int flags) 363{ 364 struct pcib_softc *sc = device_get_softc(dev); 365 const char *name, *suffix; 366 int ok; 367 368 /* 369 * Fail the allocation for this range if it's not supported. 370 */ 371 name = device_get_nameunit(child); 372 if (name == NULL) { 373 name = ""; 374 suffix = ""; 375 } else 376 suffix = " "; 377 switch (type) { 378 case SYS_RES_IOPORT: 379 ok = 0; 380 if (!pcib_is_io_open(sc)) 381 break; 382 ok = (start >= sc->iobase && end <= sc->iolimit); 383 384 /* 385 * Make sure we allow access to VGA I/O addresses when the 386 * bridge has the "VGA Enable" bit set. 387 */ 388 if (!ok && pci_is_vga_ioport_range(start, end)) 389 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 390 391 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 392 if (!ok) { 393 if (start < sc->iobase) 394 start = sc->iobase; 395 if (end > sc->iolimit) 396 end = sc->iolimit; 397 if (start < end) 398 ok = 1; 399 } 400 } else { 401 ok = 1; 402#if 1 403 if (start < sc->iobase && end > sc->iolimit) { 404 start = sc->iobase; 405 end = sc->iolimit; 406 } 407#endif 408 } 409 if (end < start) { 410 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 411 end, start); 412 start = 0; 413 end = 0; 414 ok = 0; 415 } 416 if (!ok) { 417 device_printf(dev, "%s%srequested unsupported I/O " 418 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 419 name, suffix, start, end, sc->iobase, sc->iolimit); 420 return (NULL); 421 } 422 if (bootverbose) 423 device_printf(dev, 424 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 425 name, suffix, start, end); 426 break; 427 428 case SYS_RES_MEMORY: 429 ok = 0; 430 if (pcib_is_nonprefetch_open(sc)) 431 ok = ok || (start >= sc->membase && end <= sc->memlimit); 432 if (pcib_is_prefetch_open(sc)) 433 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 434 435 /* 436 * Make sure we allow access to VGA memory addresses when the 437 * bridge has the "VGA Enable" bit set. 438 */ 439 if (!ok && pci_is_vga_memory_range(start, end)) 440 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 441 442 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 443 if (!ok) { 444 ok = 1; 445 if (flags & RF_PREFETCHABLE) { 446 if (pcib_is_prefetch_open(sc)) { 447 if (start < sc->pmembase) 448 start = sc->pmembase; 449 if (end > sc->pmemlimit) 450 end = sc->pmemlimit; 451 } else { 452 ok = 0; 453 } 454 } else { /* non-prefetchable */ 455 if (pcib_is_nonprefetch_open(sc)) { 456 if (start < sc->membase) 457 start = sc->membase; 458 if (end > sc->memlimit) 459 end = sc->memlimit; 460 } else { 461 ok = 0; 462 } 463 } 464 } 465 } else if (!ok) { 466 ok = 1; /* subtractive bridge: always ok */ 467 if (pcib_is_nonprefetch_open(sc)) { 468 if (start < sc->membase && end > sc->memlimit) { 469 start = sc->membase; 470 end = sc->memlimit; 471 } 472 } 473 if (pcib_is_prefetch_open(sc)) { 474 if (start < sc->pmembase && end > sc->pmemlimit) { 475 start = sc->pmembase; 476 end = sc->pmemlimit; 477 } 478 } 479 } 480 if (end < start) { 481 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 482 end, start); 483 start = 0; 484 end = 0; 485 ok = 0; 486 } 487 if (!ok && bootverbose) 488 device_printf(dev, 489 "%s%srequested unsupported memory range %#lx-%#lx " 490 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 491 name, suffix, start, end, 492 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 493 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 494 if (!ok) 495 return (NULL); 496 if (bootverbose) 497 device_printf(dev,"%s%srequested memory range " 498 "0x%lx-0x%lx: good\n", 499 name, suffix, start, end); 500 break; 501 502 default: 503 break; 504 } 505 /* 506 * Bridge is OK decoding this resource, so pass it up. 507 */ 508 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 509 count, flags)); 510} 511 512/* 513 * PCIB interface. 514 */ 515int 516pcib_maxslots(device_t dev) 517{ 518 return(PCI_SLOTMAX); 519} 520 521/* 522 * Since we are a child of a PCI bus, its parent must support the pcib interface. 523 */ 524uint32_t 525pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 526{ 527 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 528} 529 530void 531pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 532{ 533 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 534} 535 536/* 537 * Route an interrupt across a PCI bridge. 538 */ 539int 540pcib_route_interrupt(device_t pcib, device_t dev, int pin) 541{ 542 device_t bus; 543 int parent_intpin; 544 int intnum; 545 546 /* 547 * 548 * The PCI standard defines a swizzle of the child-side device/intpin to 549 * the parent-side intpin as follows. 550 * 551 * device = device on child bus 552 * child_intpin = intpin on child bus slot (0-3) 553 * parent_intpin = intpin on parent bus slot (0-3) 554 * 555 * parent_intpin = (device + child_intpin) % 4 556 */ 557 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 558 559 /* 560 * Our parent is a PCI bus. Its parent must export the pcib interface 561 * which includes the ability to route interrupts. 562 */ 563 bus = device_get_parent(pcib); 564 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 565 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 566 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 567 pci_get_slot(dev), 'A' + pin - 1, intnum); 568 } 569 return(intnum); 570} 571 572/* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 573int 574pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 575{ 576 struct pcib_softc *sc = device_get_softc(pcib); 577 device_t bus; 578 579 if (sc->flags & PCIB_DISABLE_MSI) 580 return (ENXIO); 581 bus = device_get_parent(pcib); 582 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 583 irqs)); 584} 585 586/* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 587int 588pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 589{ 590 device_t bus; 591 592 bus = device_get_parent(pcib); 593 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 594} 595 596/* Pass request to alloc an MSI-X message up to the parent bridge. */ 597int 598pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 599{ 600 struct pcib_softc *sc = device_get_softc(pcib); 601 device_t bus; 602 603 if (sc->flags & PCIB_DISABLE_MSI) 604 return (ENXIO); 605 bus = device_get_parent(pcib); 606 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 607} 608 609/* Pass request to release an MSI-X message up to the parent bridge. */ 610int 611pcib_release_msix(device_t pcib, device_t dev, int irq) 612{ 613 device_t bus; 614 615 bus = device_get_parent(pcib); 616 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 617} 618 619/* Pass request to map MSI/MSI-X message up to parent bridge. */ 620int 621pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 622 uint32_t *data) 623{ 624 device_t bus; 625 int error; 626 627 bus = device_get_parent(pcib); 628 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 629 if (error) 630 return (error); 631 632 pci_ht_map_msi(pcib, *addr); 633 return (0); 634} 635 636/* 637 * Try to read the bus number of a host-PCI bridge using appropriate config 638 * registers. 639 */ 640int 641host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 642 uint8_t *busnum) 643{ 644 uint32_t id; 645 646 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 647 if (id == 0xffffffff) 648 return (0); 649 650 switch (id) { 651 case 0x12258086: 652 /* Intel 824?? */ 653 /* XXX This is a guess */ 654 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 655 *busnum = bus; 656 break; 657 case 0x84c48086: 658 /* Intel 82454KX/GX (Orion) */ 659 *busnum = read_config(bus, slot, func, 0x4a, 1); 660 break; 661 case 0x84ca8086: 662 /* 663 * For the 450nx chipset, there is a whole bundle of 664 * things pretending to be host bridges. The MIOC will 665 * be seen first and isn't really a pci bridge (the 666 * actual busses are attached to the PXB's). We need to 667 * read the registers of the MIOC to figure out the 668 * bus numbers for the PXB channels. 669 * 670 * Since the MIOC doesn't have a pci bus attached, we 671 * pretend it wasn't there. 672 */ 673 return (0); 674 case 0x84cb8086: 675 switch (slot) { 676 case 0x12: 677 /* Intel 82454NX PXB#0, Bus#A */ 678 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 679 break; 680 case 0x13: 681 /* Intel 82454NX PXB#0, Bus#B */ 682 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 683 break; 684 case 0x14: 685 /* Intel 82454NX PXB#1, Bus#A */ 686 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 687 break; 688 case 0x15: 689 /* Intel 82454NX PXB#1, Bus#B */ 690 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 691 break; 692 } 693 break; 694 695 /* ServerWorks -- vendor 0x1166 */ 696 case 0x00051166: 697 case 0x00061166: 698 case 0x00081166: 699 case 0x00091166: 700 case 0x00101166: 701 case 0x00111166: 702 case 0x00171166: 703 case 0x01011166: 704 case 0x010f1014: 705 case 0x02011166: 706 case 0x03021014: 707 *busnum = read_config(bus, slot, func, 0x44, 1); 708 break; 709 710 /* Compaq/HP -- vendor 0x0e11 */ 711 case 0x60100e11: 712 *busnum = read_config(bus, slot, func, 0xc8, 1); 713 break; 714 default: 715 /* Don't know how to read bus number. */ 716 return 0; 717 } 718 719 return 1; 720} 721