pci_subr.c revision 91064
1261938Sian/*- 2261938Sian * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3261938Sian * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4261938Sian * Copyright (c) 2000 BSDi 5261938Sian * All rights reserved. 6261938Sian * 7261938Sian * Redistribution and use in source and binary forms, with or without 8261938Sian * modification, are permitted provided that the following conditions 9261938Sian * are met: 10261938Sian * 1. Redistributions of source code must retain the above copyright 11261938Sian * notice, this list of conditions and the following disclaimer. 12261938Sian * 2. Redistributions in binary form must reproduce the above copyright 13261938Sian * notice, this list of conditions and the following disclaimer in the 14261938Sian * documentation and/or other materials provided with the distribution. 15261938Sian * 3. The name of the author may not be used to endorse or promote products 16261938Sian * derived from this software without specific prior written permission. 17261938Sian * 18261938Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19261938Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20261938Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21261938Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22261938Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23261938Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24261938Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25261938Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26261938Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27261938Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28261938Sian * SUCH DAMAGE. 29261938Sian * 30261938Sian * $FreeBSD: head/sys/dev/pci/pci_pci.c 91064 2002-02-22 11:21:02Z phk $ 31261938Sian */ 32261938Sian 33261938Sian/* 34261938Sian * PCI:PCI bridge support. 35261938Sian */ 36261938Sian 37261938Sian#include <sys/param.h> 38261938Sian#include <sys/systm.h> 39261938Sian#include <sys/kernel.h> 40261938Sian#include <sys/bus.h> 41261938Sian 42261938Sian#include <machine/resource.h> 43261938Sian 44261938Sian#include <pci/pcivar.h> 45261938Sian#include <pci/pcireg.h> 46261946Sian 47261946Sian#include "pcib_if.h" 48261938Sian#include "opt_pci.h" 49266200Sian 50266200Sian/* 51266200Sian * Bridge-specific data. 52266200Sian */ 53266200Sianstruct pcib_softc 54266200Sian{ 55266200Sian device_t dev; 56266200Sian u_int16_t command; /* command register */ 57266200Sian u_int8_t secbus; /* secondary bus number */ 58266200Sian u_int8_t subbus; /* subordinate bus number */ 59266200Sian pci_addr_t pmembase; /* base address of prefetchable memory */ 60266200Sian pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 61266200Sian pci_addr_t membase; /* base address of memory window */ 62266200Sian pci_addr_t memlimit; /* topmost address of memory window */ 63266200Sian u_int32_t iobase; /* base address of port window */ 64266200Sian u_int32_t iolimit; /* topmost address of port window */ 65266200Sian u_int16_t secstat; /* secondary bus status register */ 66266200Sian u_int16_t bridgectl; /* bridge control register */ 67266200Sian u_int8_t seclat; /* secondary bus latency timer */ 68266200Sian}; 69266200Sian 70266200Sianstatic int pcib_probe(device_t dev); 71266200Sianstatic int pcib_attach(device_t dev); 72266200Sianstatic int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result); 73266200Sianstatic int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value); 74266200Sianstatic struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 75266200Sian u_long start, u_long end, u_long count, u_int flags); 76266200Sianstatic int pcib_maxslots(device_t dev); 77266200Sianstatic u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width); 78266200Sianstatic void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width); 79266200Sianstatic int pcib_route_interrupt(device_t pcib, device_t dev, int pin); 80266200Sian 81266200Sianstatic device_method_t pcib_methods[] = { 82266200Sian /* Device interface */ 83266200Sian DEVMETHOD(device_probe, pcib_probe), 84266200Sian DEVMETHOD(device_attach, pcib_attach), 85266200Sian DEVMETHOD(device_shutdown, bus_generic_shutdown), 86266200Sian DEVMETHOD(device_suspend, bus_generic_suspend), 87266200Sian DEVMETHOD(device_resume, bus_generic_resume), 88266200Sian 89266200Sian /* Bus interface */ 90266200Sian DEVMETHOD(bus_print_child, bus_generic_print_child), 91261938Sian DEVMETHOD(bus_read_ivar, pcib_read_ivar), 92261938Sian DEVMETHOD(bus_write_ivar, pcib_write_ivar), 93261938Sian DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 94261938Sian DEVMETHOD(bus_release_resource, bus_generic_release_resource), 95261938Sian DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 96261938Sian DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 97261938Sian DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 98261938Sian DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 99261938Sian 100261938Sian /* pcib interface */ 101266200Sian DEVMETHOD(pcib_maxslots, pcib_maxslots), 102261938Sian DEVMETHOD(pcib_read_config, pcib_read_config), 103261938Sian DEVMETHOD(pcib_write_config, pcib_write_config), 104261938Sian DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 105261938Sian 106261938Sian { 0, 0 } 107261938Sian}; 108261938Sian 109266200Sianstatic driver_t pcib_driver = { 110266200Sian "pcib", 111261938Sian pcib_methods, 112261938Sian sizeof(struct pcib_softc), 113261938Sian}; 114261938Sian 115261938Sianstatic devclass_t pcib_devclass; 116261938Sian 117261938SianDRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 118261938Sian 119261938Sian/* 120261938Sian * Generic device interface 121261938Sian */ 122261938Sianstatic int 123261938Sianpcib_probe(device_t dev) 124261938Sian{ 125261938Sian if ((pci_get_class(dev) == PCIC_BRIDGE) && 126261938Sian (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 127261938Sian device_set_desc(dev, "PCI-PCI bridge"); 128261938Sian return(-10000); 129261938Sian } 130261938Sian return(ENXIO); 131261938Sian} 132261938Sian 133266200Sianstatic int 134266200Sianpcib_attach(device_t dev) 135266200Sian{ 136266200Sian struct pcib_softc *sc; 137266200Sian device_t child; 138261938Sian u_int8_t iolow; 139261938Sian 140261938Sian sc = device_get_softc(dev); 141261938Sian sc->dev = dev; 142261938Sian 143261938Sian /* 144261938Sian * Get current bridge configuration. 145261938Sian */ 146261938Sian sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 147261938Sian sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 148261938Sian sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 149261938Sian sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 150261938Sian sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 151261938Sian sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 152261938Sian 153261938Sian /* 154266200Sian * Determine current I/O decode. 155261938Sian */ 156261938Sian if (sc->command & PCIM_CMD_PORTEN) { 157261938Sian iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 158266200Sian if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 159261938Sian sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 160261938Sian pci_read_config(dev, PCIR_IOBASEL_1, 1)); 161261938Sian } else { 162261938Sian sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 163261938Sian } 164261946Sian 165261938Sian iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 166261938Sian if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 167261946Sian sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 168261946Sian pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 169261938Sian } else { 170266200Sian sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 171266200Sian } 172266200Sian } 173266200Sian 174266200Sian /* 175266200Sian * Determine current memory decode. 176266200Sian */ 177266200Sian if (sc->command & PCIM_CMD_MEMEN) { 178266200Sian sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 179266200Sian sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 180266200Sian sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 181266200Sian pci_read_config(dev, PCIR_PMBASEL_1, 2)); 182266200Sian sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 183266200Sian pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 184261938Sian } 185261938Sian 186261938Sian /* 187261938Sian * Quirk handling. 188261938Sian */ 189261938Sian switch (pci_get_devid(dev)) { 190261938Sian case 0x12258086: /* Intel 82454KX/GX (Orion) */ 191261938Sian { 192261938Sian u_int8_t supbus; 193261938Sian 194261938Sian supbus = pci_read_config(dev, 0x41, 1); 195261938Sian if (supbus != 0xff) { 196261938Sian sc->secbus = supbus + 1; 197261938Sian sc->subbus = supbus + 1; 198261938Sian } 199261938Sian } 200261938Sian break; 201261938Sian } 202261938Sian 203273656Sian if (bootverbose) { 204273656Sian device_printf(dev, " secondary bus %d\n", sc->secbus); 205261938Sian device_printf(dev, " subordinate bus %d\n", sc->subbus); 206 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 207 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 208 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 209 } 210 211 /* 212 * XXX If the secondary bus number is zero, we should assign a bus number 213 * since the BIOS hasn't, then initialise the bridge. 214 */ 215 216 /* 217 * XXX If the subordinate bus number is less than the secondary bus number, 218 * we should pick a better value. One sensible alternative would be to 219 * pick 255; the only tradeoff here is that configuration transactions 220 * would be more widely routed than absolutely necessary. 221 */ 222 223 if (sc->secbus != 0) { 224 child = device_add_child(dev, "pci", -1); 225 if (child != NULL) 226 return(bus_generic_attach(dev)); 227 } 228 229 /* no secondary bus; we should have fixed this */ 230 return(0); 231} 232 233static int 234pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 235{ 236 struct pcib_softc *sc = device_get_softc(dev); 237 238 switch (which) { 239 case PCIB_IVAR_BUS: 240 *result = sc->secbus; 241 return(0); 242 } 243 return(ENOENT); 244} 245 246static int 247pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 248{ 249 struct pcib_softc *sc = device_get_softc(dev); 250 251 switch (which) { 252 case PCIB_IVAR_BUS: 253 sc->secbus = value; 254 break; 255 } 256 return(ENOENT); 257} 258 259/* 260 * Is this a decoded ISA I/O port address? Note, we need to do the mask that 261 * we do below because of the ISA alias addresses. I'm not 100% sure that 262 * this is correct. 263 */ 264static int 265pcib_is_isa_io(u_long start) 266{ 267 if ((start & 0xfffUL) > 0x3ffUL || start == 0) 268 return (0); 269 return (1); 270} 271 272/* 273 * Is this a decoded ISA memory address? 274 */ 275static int 276pcib_is_isa_mem(u_long start) 277{ 278 if (start > 0xfffffUL || start == 0) 279 return (0); 280 return (1); 281} 282 283/* 284 * We have to trap resource allocation requests and ensure that the bridge 285 * is set up to, or capable of handling them. 286 */ 287static struct resource * 288pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 289 u_long start, u_long end, u_long count, u_int flags) 290{ 291 struct pcib_softc *sc = device_get_softc(dev); 292 293 /* 294 * If this is a "default" allocation against this rid, we can't work 295 * out where it's coming from (we should actually never see these) so we 296 * just have to punt. 297 */ 298 if ((start == 0) && (end == ~0)) { 299 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n", 300 *rid, device_get_name(child), device_get_unit(child)); 301 } else { 302 /* 303 * Fail the allocation for this range if it's not supported. 304 * 305 * XXX we should probably just fix up the bridge decode and soldier on. 306 */ 307 switch (type) { 308 case SYS_RES_IOPORT: 309 if (!pcib_is_isa_io(start)) { 310#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE 311 if (start < sc->iobase) 312 start = sc->iobase; 313 if (end > sc->iolimit) 314 end = sc->iolimit; 315 if (end < start) 316 start = 0; 317#else 318 if (start < sc->iobase) 319 printf("start (%x) < sc->iobase (%x)\n", start, sc->iobase); 320 if (end > sc->iolimit) 321 printf("end (%x) > sc->iolimit (%x)\n", end, sc->iolimit); 322 if (end < start) 323 printf("end (%x) < start (%x)\n", end, start); 324#endif 325 } 326 if (!pcib_is_isa_io(start) && 327 ((start < sc->iobase) || (end > sc->iolimit))) { 328 device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx" 329 " (decoding 0x%x-0x%x)\n", 330 device_get_name(child), device_get_unit(child), start, end, 331 sc->iobase, sc->iolimit); 332 return (NULL); 333 } 334 if (bootverbose) 335 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n", 336 device_get_name(child), device_get_unit(child), start, end); 337 break; 338 339 /* 340 * XXX will have to decide whether the device making the request is asking 341 * for prefetchable memory or not. If it's coming from another bridge 342 * down the line, do we assume not, or ask the bridge to pass in another 343 * flag as the request bubbles up? 344 */ 345 case SYS_RES_MEMORY: 346 if (!pcib_is_isa_mem(start)) { 347#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE 348 if (start < sc->membase && end > sc->membase) 349 start = sc->membase; 350 if (end > sc->memlimit) 351 end = sc->memlimit; 352 if (end < start) 353 start = 0; 354#else 355 if (start < sc->membase && end > sc->membase) 356 printf("start (%x) < sc->membase (%x)\n", start, sc->membase); 357 if (end > sc->memlimit) 358 printf("end (%x) > sc->memlimit (%x)\n", end, sc->memlimit); 359 if (end < start) 360 printf("end (%x) < start (%x)\n", end, start); 361#endif 362 } 363 if (!pcib_is_isa_mem(start) && 364 (((start < sc->membase) || (end > sc->memlimit)) && 365 ((start < sc->pmembase) || (end > sc->pmemlimit)))) { 366 if (bootverbose) 367 device_printf(dev, 368 "device %s%d requested unsupported memory range " 369 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 370 device_get_name(child), device_get_unit(child), start, 371 end, sc->membase, sc->memlimit, sc->pmembase, 372 sc->pmemlimit); 373#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE 374 return(NULL); 375#endif 376 } 377 if (bootverbose) 378 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n", 379 device_get_name(child), device_get_unit(child), start, end); 380 break; 381 382 default: 383 break; 384 } 385 } 386 387 /* 388 * Bridge is OK decoding this resource, so pass it up. 389 */ 390 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 391} 392 393/* 394 * PCIB interface. 395 */ 396static int 397pcib_maxslots(device_t dev) 398{ 399 return(PCI_SLOTMAX); 400} 401 402/* 403 * Since we are a child of a PCI bus, its parent must support the pcib interface. 404 */ 405static u_int32_t 406pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 407{ 408 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 409} 410 411static void 412pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width) 413{ 414 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 415} 416 417/* 418 * Route an interrupt across a PCI bridge. 419 */ 420static int 421pcib_route_interrupt(device_t pcib, device_t dev, int pin) 422{ 423 device_t bus; 424 int parent_intpin; 425 int intnum; 426 427 /* 428 * 429 * The PCI standard defines a swizzle of the child-side device/intpin to 430 * the parent-side intpin as follows. 431 * 432 * device = device on child bus 433 * child_intpin = intpin on child bus slot (0-3) 434 * parent_intpin = intpin on parent bus slot (0-3) 435 * 436 * parent_intpin = (device + child_intpin) % 4 437 */ 438 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4; 439 440 /* 441 * Our parent is a PCI bus. Its parent must export the pcib interface 442 * which includes the ability to route interrupts. 443 */ 444 bus = device_get_parent(pcib); 445 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 446 if (PCI_INTERRUPT_VALID(intnum)) { 447 device_printf(pcib, "routed slot %d INT%c to irq %d\n", pci_get_slot(dev), 448 'A' + pin - 1, intnum); 449 } 450 return(intnum); 451} 452