pci_subr.c revision 164130
1/*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/pci/pci_pci.c 164130 2006-11-09 18:04:53Z jhb $"); 33 34/* 35 * PCI:PCI bridge support. 36 */ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/kernel.h> 41#include <sys/module.h> 42#include <sys/bus.h> 43#include <machine/bus.h> 44#include <sys/rman.h> 45#include <sys/sysctl.h> 46 47#include <machine/resource.h> 48 49#include <dev/pci/pcivar.h> 50#include <dev/pci/pcireg.h> 51#include <dev/pci/pcib_private.h> 52 53#include "pcib_if.h" 54 55static int pcib_probe(device_t dev); 56 57static device_method_t pcib_methods[] = { 58 /* Device interface */ 59 DEVMETHOD(device_probe, pcib_probe), 60 DEVMETHOD(device_attach, pcib_attach), 61 DEVMETHOD(device_detach, bus_generic_detach), 62 DEVMETHOD(device_shutdown, bus_generic_shutdown), 63 DEVMETHOD(device_suspend, bus_generic_suspend), 64 DEVMETHOD(device_resume, bus_generic_resume), 65 66 /* Bus interface */ 67 DEVMETHOD(bus_print_child, bus_generic_print_child), 68 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 69 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 70 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 71 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 72 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 73 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 74 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 75 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 76 77 /* pcib interface */ 78 DEVMETHOD(pcib_maxslots, pcib_maxslots), 79 DEVMETHOD(pcib_read_config, pcib_read_config), 80 DEVMETHOD(pcib_write_config, pcib_write_config), 81 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 82 83 { 0, 0 } 84}; 85 86static devclass_t pcib_devclass; 87 88DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 89DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 90 91/* 92 * Is the prefetch window open (eg, can we allocate memory in it?) 93 */ 94static int 95pcib_is_prefetch_open(struct pcib_softc *sc) 96{ 97 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 98} 99 100/* 101 * Is the nonprefetch window open (eg, can we allocate memory in it?) 102 */ 103static int 104pcib_is_nonprefetch_open(struct pcib_softc *sc) 105{ 106 return (sc->membase > 0 && sc->membase < sc->memlimit); 107} 108 109/* 110 * Is the io window open (eg, can we allocate ports in it?) 111 */ 112static int 113pcib_is_io_open(struct pcib_softc *sc) 114{ 115 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 116} 117 118/* 119 * Generic device interface 120 */ 121static int 122pcib_probe(device_t dev) 123{ 124 if ((pci_get_class(dev) == PCIC_BRIDGE) && 125 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 126 device_set_desc(dev, "PCI-PCI bridge"); 127 return(-10000); 128 } 129 return(ENXIO); 130} 131 132void 133pcib_attach_common(device_t dev) 134{ 135 struct pcib_softc *sc; 136 uint8_t iolow; 137 138 sc = device_get_softc(dev); 139 sc->dev = dev; 140 141 /* 142 * Get current bridge configuration. 143 */ 144 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 145 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 146 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 147 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 148 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 149 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 150 151 /* 152 * Determine current I/O decode. 153 */ 154 if (sc->command & PCIM_CMD_PORTEN) { 155 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 156 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 157 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 158 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 159 } else { 160 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 161 } 162 163 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 164 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 165 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 166 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 167 } else { 168 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 169 } 170 } 171 172 /* 173 * Determine current memory decode. 174 */ 175 if (sc->command & PCIM_CMD_MEMEN) { 176 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 177 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 178 sc->pmembase = PCI_PPBMEMBASE(pci_read_config(dev, PCIR_PMBASEH_1, 4), 179 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 180 sc->pmemlimit = PCI_PPBMEMLIMIT(pci_read_config(dev, PCIR_PMLIMITH_1, 4), 181 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 182 } 183 184 /* 185 * Quirk handling. 186 */ 187 switch (pci_get_devid(dev)) { 188 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 189 { 190 uint8_t supbus; 191 192 supbus = pci_read_config(dev, 0x41, 1); 193 if (supbus != 0xff) { 194 sc->secbus = supbus + 1; 195 sc->subbus = supbus + 1; 196 } 197 break; 198 } 199 200 /* 201 * The i82380FB mobile docking controller is a PCI-PCI bridge, 202 * and it is a subtractive bridge. However, the ProgIf is wrong 203 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 204 * happen. There's also a Toshiba bridge that behaves this 205 * way. 206 */ 207 case 0x124b8086: /* Intel 82380FB Mobile */ 208 case 0x060513d7: /* Toshiba ???? */ 209 sc->flags |= PCIB_SUBTRACTIVE; 210 break; 211 212 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 213 case 0x00dd10de: 214 { 215 char *cp; 216 217 if ((cp = getenv("smbios.planar.maker")) == NULL) 218 break; 219 if (strncmp(cp, "Compal", 6) != 0) { 220 freeenv(cp); 221 break; 222 } 223 freeenv(cp); 224 if ((cp = getenv("smbios.planar.product")) == NULL) 225 break; 226 if (strncmp(cp, "08A0", 4) != 0) { 227 freeenv(cp); 228 break; 229 } 230 freeenv(cp); 231 if (sc->subbus < 0xa) { 232 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 233 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 234 } 235 break; 236 } 237 } 238 239 /* 240 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 241 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 242 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 243 * This means they act as if they were subtractively decoding 244 * bridges and pass all transactions. Mark them and real ProgIf 1 245 * parts as subtractive. 246 */ 247 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 248 pci_read_config(dev, PCIR_PROGIF, 1) == 1) 249 sc->flags |= PCIB_SUBTRACTIVE; 250 251 if (bootverbose) { 252 device_printf(dev, " secondary bus %d\n", sc->secbus); 253 device_printf(dev, " subordinate bus %d\n", sc->subbus); 254 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 255 if (pcib_is_nonprefetch_open(sc)) 256 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 257 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 258 if (pcib_is_prefetch_open(sc)) 259 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 260 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 261 else 262 device_printf(dev, " no prefetched decode\n"); 263 if (sc->flags & PCIB_SUBTRACTIVE) 264 device_printf(dev, " Subtractively decoded bridge.\n"); 265 } 266 267 /* 268 * XXX If the secondary bus number is zero, we should assign a bus number 269 * since the BIOS hasn't, then initialise the bridge. 270 */ 271 272 /* 273 * XXX If the subordinate bus number is less than the secondary bus number, 274 * we should pick a better value. One sensible alternative would be to 275 * pick 255; the only tradeoff here is that configuration transactions 276 * would be more widely routed than absolutely necessary. 277 */ 278} 279 280int 281pcib_attach(device_t dev) 282{ 283 struct pcib_softc *sc; 284 device_t child; 285 286 pcib_attach_common(dev); 287 sc = device_get_softc(dev); 288 if (sc->secbus != 0) { 289 child = device_add_child(dev, "pci", sc->secbus); 290 if (child != NULL) 291 return(bus_generic_attach(dev)); 292 } 293 294 /* no secondary bus; we should have fixed this */ 295 return(0); 296} 297 298int 299pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 300{ 301 struct pcib_softc *sc = device_get_softc(dev); 302 303 switch (which) { 304 case PCIB_IVAR_BUS: 305 *result = sc->secbus; 306 return(0); 307 } 308 return(ENOENT); 309} 310 311int 312pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 313{ 314 struct pcib_softc *sc = device_get_softc(dev); 315 316 switch (which) { 317 case PCIB_IVAR_BUS: 318 sc->secbus = value; 319 break; 320 } 321 return(ENOENT); 322} 323 324/* 325 * We have to trap resource allocation requests and ensure that the bridge 326 * is set up to, or capable of handling them. 327 */ 328struct resource * 329pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 330 u_long start, u_long end, u_long count, u_int flags) 331{ 332 struct pcib_softc *sc = device_get_softc(dev); 333 const char *name, *suffix; 334 int ok; 335 336 /* 337 * Fail the allocation for this range if it's not supported. 338 */ 339 name = device_get_nameunit(child); 340 if (name == NULL) { 341 name = ""; 342 suffix = ""; 343 } else 344 suffix = " "; 345 switch (type) { 346 case SYS_RES_IOPORT: 347 ok = 0; 348 if (!pcib_is_io_open(sc)) 349 break; 350 ok = (start >= sc->iobase && end <= sc->iolimit); 351 352 /* 353 * Make sure we allow access to VGA I/O addresses when the 354 * bridge has the "VGA Enable" bit set. 355 */ 356 if (!ok && pci_is_vga_ioport_range(start, end)) 357 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 358 359 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 360 if (!ok) { 361 if (start < sc->iobase) 362 start = sc->iobase; 363 if (end > sc->iolimit) 364 end = sc->iolimit; 365 if (start < end) 366 ok = 1; 367 } 368 } else { 369 ok = 1; 370#if 1 371 if (start < sc->iobase && end > sc->iolimit) { 372 start = sc->iobase; 373 end = sc->iolimit; 374 } 375#endif 376 } 377 if (end < start) { 378 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 379 end, start); 380 start = 0; 381 end = 0; 382 ok = 0; 383 } 384 if (!ok) { 385 device_printf(dev, "%s%srequested unsupported I/O " 386 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 387 name, suffix, start, end, sc->iobase, sc->iolimit); 388 return (NULL); 389 } 390 if (bootverbose) 391 device_printf(dev, 392 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 393 name, suffix, start, end); 394 break; 395 396 case SYS_RES_MEMORY: 397 ok = 0; 398 if (pcib_is_nonprefetch_open(sc)) 399 ok = ok || (start >= sc->membase && end <= sc->memlimit); 400 if (pcib_is_prefetch_open(sc)) 401 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 402 403 /* 404 * Make sure we allow access to VGA memory addresses when the 405 * bridge has the "VGA Enable" bit set. 406 */ 407 if (!ok && pci_is_vga_memory_range(start, end)) 408 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 409 410 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 411 if (!ok) { 412 ok = 1; 413 if (flags & RF_PREFETCHABLE) { 414 if (pcib_is_prefetch_open(sc)) { 415 if (start < sc->pmembase) 416 start = sc->pmembase; 417 if (end > sc->pmemlimit) 418 end = sc->pmemlimit; 419 } else { 420 ok = 0; 421 } 422 } else { /* non-prefetchable */ 423 if (pcib_is_nonprefetch_open(sc)) { 424 if (start < sc->membase) 425 start = sc->membase; 426 if (end > sc->memlimit) 427 end = sc->memlimit; 428 } else { 429 ok = 0; 430 } 431 } 432 } 433 } else if (!ok) { 434 ok = 1; /* subtractive bridge: always ok */ 435#if 1 436 if (pcib_is_nonprefetch_open(sc)) { 437 if (start < sc->membase && end > sc->memlimit) { 438 start = sc->membase; 439 end = sc->memlimit; 440 } 441 } 442 if (pcib_is_prefetch_open(sc)) { 443 if (start < sc->pmembase && end > sc->pmemlimit) { 444 start = sc->pmembase; 445 end = sc->pmemlimit; 446 } 447 } 448#endif 449 } 450 if (end < start) { 451 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 452 end, start); 453 start = 0; 454 end = 0; 455 ok = 0; 456 } 457 if (!ok && bootverbose) 458 device_printf(dev, 459 "%s%srequested unsupported memory range %#lx-%#lx " 460 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 461 name, suffix, start, end, 462 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 463 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 464 if (!ok) 465 return (NULL); 466 if (bootverbose) 467 device_printf(dev,"%s%srequested memory range " 468 "0x%lx-0x%lx: good\n", 469 name, suffix, start, end); 470 break; 471 472 default: 473 break; 474 } 475 /* 476 * Bridge is OK decoding this resource, so pass it up. 477 */ 478 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 479 count, flags)); 480} 481 482/* 483 * PCIB interface. 484 */ 485int 486pcib_maxslots(device_t dev) 487{ 488 return(PCI_SLOTMAX); 489} 490 491/* 492 * Since we are a child of a PCI bus, its parent must support the pcib interface. 493 */ 494uint32_t 495pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 496{ 497 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 498} 499 500void 501pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 502{ 503 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 504} 505 506/* 507 * Route an interrupt across a PCI bridge. 508 */ 509int 510pcib_route_interrupt(device_t pcib, device_t dev, int pin) 511{ 512 device_t bus; 513 int parent_intpin; 514 int intnum; 515 516 /* 517 * 518 * The PCI standard defines a swizzle of the child-side device/intpin to 519 * the parent-side intpin as follows. 520 * 521 * device = device on child bus 522 * child_intpin = intpin on child bus slot (0-3) 523 * parent_intpin = intpin on parent bus slot (0-3) 524 * 525 * parent_intpin = (device + child_intpin) % 4 526 */ 527 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 528 529 /* 530 * Our parent is a PCI bus. Its parent must export the pcib interface 531 * which includes the ability to route interrupts. 532 */ 533 bus = device_get_parent(pcib); 534 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 535 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 536 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 537 pci_get_slot(dev), 'A' + pin - 1, intnum); 538 } 539 return(intnum); 540} 541 542/* 543 * Try to read the bus number of a host-PCI bridge using appropriate config 544 * registers. 545 */ 546int 547host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 548 uint8_t *busnum) 549{ 550 uint32_t id; 551 552 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 553 if (id == 0xffffffff) 554 return (0); 555 556 switch (id) { 557 case 0x12258086: 558 /* Intel 824?? */ 559 /* XXX This is a guess */ 560 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 561 *busnum = bus; 562 break; 563 case 0x84c48086: 564 /* Intel 82454KX/GX (Orion) */ 565 *busnum = read_config(bus, slot, func, 0x4a, 1); 566 break; 567 case 0x84ca8086: 568 /* 569 * For the 450nx chipset, there is a whole bundle of 570 * things pretending to be host bridges. The MIOC will 571 * be seen first and isn't really a pci bridge (the 572 * actual busses are attached to the PXB's). We need to 573 * read the registers of the MIOC to figure out the 574 * bus numbers for the PXB channels. 575 * 576 * Since the MIOC doesn't have a pci bus attached, we 577 * pretend it wasn't there. 578 */ 579 return (0); 580 case 0x84cb8086: 581 switch (slot) { 582 case 0x12: 583 /* Intel 82454NX PXB#0, Bus#A */ 584 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 585 break; 586 case 0x13: 587 /* Intel 82454NX PXB#0, Bus#B */ 588 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 589 break; 590 case 0x14: 591 /* Intel 82454NX PXB#1, Bus#A */ 592 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 593 break; 594 case 0x15: 595 /* Intel 82454NX PXB#1, Bus#B */ 596 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 597 break; 598 } 599 break; 600 601 /* ServerWorks -- vendor 0x1166 */ 602 case 0x00051166: 603 case 0x00061166: 604 case 0x00081166: 605 case 0x00091166: 606 case 0x00101166: 607 case 0x00111166: 608 case 0x00171166: 609 case 0x01011166: 610 case 0x010f1014: 611 case 0x02011166: 612 case 0x03021014: 613 *busnum = read_config(bus, slot, func, 0x44, 1); 614 break; 615 616 /* Compaq/HP -- vendor 0x0e11 */ 617 case 0x60100e11: 618 *busnum = read_config(bus, slot, func, 0xc8, 1); 619 break; 620 default: 621 /* Don't know how to read bus number. */ 622 return 0; 623 } 624 625 return 1; 626} 627