pci_subr.c revision 142051 
1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 *    derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/pci/pci_pci.c 142051 2005-02-18 17:35:03Z imp $");
33
34/*
35 * PCI:PCI bridge support.
36 */
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/bus.h>
43#include <machine/bus.h>
44#include <sys/rman.h>
45#include <sys/sysctl.h>
46
47#include <machine/resource.h>
48
49#include <dev/pci/pcivar.h>
50#include <dev/pci/pcireg.h>
51#include <dev/pci/pcib_private.h>
52
53#include "pcib_if.h"
54
55static int		pcib_probe(device_t dev);
56
57static device_method_t pcib_methods[] = {
58    /* Device interface */
59    DEVMETHOD(device_probe,		pcib_probe),
60    DEVMETHOD(device_attach,		pcib_attach),
61    DEVMETHOD(device_shutdown,		bus_generic_shutdown),
62    DEVMETHOD(device_suspend,		bus_generic_suspend),
63    DEVMETHOD(device_resume,		bus_generic_resume),
64
65    /* Bus interface */
66    DEVMETHOD(bus_print_child,		bus_generic_print_child),
67    DEVMETHOD(bus_read_ivar,		pcib_read_ivar),
68    DEVMETHOD(bus_write_ivar,		pcib_write_ivar),
69    DEVMETHOD(bus_alloc_resource,	pcib_alloc_resource),
70    DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
71    DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
72    DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
73    DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
74    DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
75
76    /* pcib interface */
77    DEVMETHOD(pcib_maxslots,		pcib_maxslots),
78    DEVMETHOD(pcib_read_config,		pcib_read_config),
79    DEVMETHOD(pcib_write_config,	pcib_write_config),
80    DEVMETHOD(pcib_route_interrupt,	pcib_route_interrupt),
81
82    { 0, 0 }
83};
84
85static driver_t pcib_driver = {
86    "pcib",
87    pcib_methods,
88    sizeof(struct pcib_softc),
89};
90
91devclass_t pcib_devclass;
92
93DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
94
95/*
96 * Generic device interface
97 */
98static int
99pcib_probe(device_t dev)
100{
101    if ((pci_get_class(dev) == PCIC_BRIDGE) &&
102	(pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
103	device_set_desc(dev, "PCI-PCI bridge");
104	return(-10000);
105    }
106    return(ENXIO);
107}
108
109void
110pcib_attach_common(device_t dev)
111{
112    struct pcib_softc	*sc;
113    uint8_t		iolow;
114
115    sc = device_get_softc(dev);
116    sc->dev = dev;
117
118    /*
119     * Get current bridge configuration.
120     */
121    sc->command   = pci_read_config(dev, PCIR_COMMAND, 1);
122    sc->secbus    = pci_read_config(dev, PCIR_SECBUS_1, 1);
123    sc->subbus    = pci_read_config(dev, PCIR_SUBBUS_1, 1);
124    sc->secstat   = pci_read_config(dev, PCIR_SECSTAT_1, 2);
125    sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
126    sc->seclat    = pci_read_config(dev, PCIR_SECLAT_1, 1);
127
128    /*
129     * Determine current I/O decode.
130     */
131    if (sc->command & PCIM_CMD_PORTEN) {
132	iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
133	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
134	    sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
135				       pci_read_config(dev, PCIR_IOBASEL_1, 1));
136	} else {
137	    sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
138	}
139
140	iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
141	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
142	    sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
143					 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
144	} else {
145	    sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
146	}
147    }
148
149    /*
150     * Determine current memory decode.
151     */
152    if (sc->command & PCIM_CMD_MEMEN) {
153	sc->membase   = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
154	sc->memlimit  = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
155	sc->pmembase  = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
156				       pci_read_config(dev, PCIR_PMBASEL_1, 2));
157	sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
158					pci_read_config(dev, PCIR_PMLIMITL_1, 2));
159    }
160
161    /*
162     * Quirk handling.
163     */
164    switch (pci_get_devid(dev)) {
165    case 0x12258086:		/* Intel 82454KX/GX (Orion) */
166	{
167	    uint8_t	supbus;
168
169	    supbus = pci_read_config(dev, 0x41, 1);
170	    if (supbus != 0xff) {
171		sc->secbus = supbus + 1;
172		sc->subbus = supbus + 1;
173	    }
174	    break;
175	}
176
177    /*
178     * The i82380FB mobile docking controller is a PCI-PCI bridge,
179     * and it is a subtractive bridge.  However, the ProgIf is wrong
180     * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
181     * happen.  There's also a Toshiba bridge that behaves this
182     * way.
183     */
184    case 0x124b8086:		/* Intel 82380FB Mobile */
185    case 0x060513d7:		/* Toshiba ???? */
186	sc->flags |= PCIB_SUBTRACTIVE;
187	break;
188    }
189
190    /*
191     * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
192     * but have a ProgIF of 0x80.  The 82801 family (AA, AB, BAM/CAM,
193     * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
194     * This means they act as if they were subtractively decoding
195     * bridges and pass all transactions.  Mark them and real ProgIf 1
196     * parts as subtractive.
197     */
198    if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
199      pci_read_config(dev, PCIR_PROGIF, 1) == 1)
200	sc->flags |= PCIB_SUBTRACTIVE;
201
202    if (bootverbose) {
203	device_printf(dev, "  secondary bus     %d\n", sc->secbus);
204	device_printf(dev, "  subordinate bus   %d\n", sc->subbus);
205	device_printf(dev, "  I/O decode        0x%x-0x%x\n", sc->iobase, sc->iolimit);
206	device_printf(dev, "  memory decode     0x%x-0x%x\n", sc->membase, sc->memlimit);
207	device_printf(dev, "  prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
208	if (sc->flags & PCIB_SUBTRACTIVE)
209	    device_printf(dev, "  Subtractively decoded bridge.\n");
210    }
211
212    /*
213     * XXX If the secondary bus number is zero, we should assign a bus number
214     *     since the BIOS hasn't, then initialise the bridge.
215     */
216
217    /*
218     * XXX If the subordinate bus number is less than the secondary bus number,
219     *     we should pick a better value.  One sensible alternative would be to
220     *     pick 255; the only tradeoff here is that configuration transactions
221     *     would be more widely routed than absolutely necessary.
222     */
223}
224
225int
226pcib_attach(device_t dev)
227{
228    struct pcib_softc	*sc;
229    device_t		child;
230
231    pcib_attach_common(dev);
232    sc = device_get_softc(dev);
233    if (sc->secbus != 0) {
234	child = device_add_child(dev, "pci", sc->secbus);
235	if (child != NULL)
236	    return(bus_generic_attach(dev));
237    }
238
239    /* no secondary bus; we should have fixed this */
240    return(0);
241}
242
243int
244pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
245{
246    struct pcib_softc	*sc = device_get_softc(dev);
247
248    switch (which) {
249    case PCIB_IVAR_BUS:
250	*result = sc->secbus;
251	return(0);
252    }
253    return(ENOENT);
254}
255
256int
257pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
258{
259    struct pcib_softc	*sc = device_get_softc(dev);
260
261    switch (which) {
262    case PCIB_IVAR_BUS:
263	sc->secbus = value;
264	break;
265    }
266    return(ENOENT);
267}
268
269/*
270 * Is the prefetch window open (eg, can we allocate memory in it?)
271 */
272static int
273pcib_is_prefetch_open(struct pcib_softc *sc)
274{
275	return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
276}
277
278/*
279 * Is the nonprefetch window open (eg, can we allocate memory in it?)
280 */
281static int
282pcib_is_nonprefetch_open(struct pcib_softc *sc)
283{
284	return (sc->membase > 0 && sc->membase < sc->memlimit);
285}
286
287/*
288 * Is the io window open (eg, can we allocate ports in it?)
289 */
290static int
291pcib_is_io_open(struct pcib_softc *sc)
292{
293	return (sc->iobase > 0 && sc->iobase < sc->iolimit);
294}
295
296/*
297 * We have to trap resource allocation requests and ensure that the bridge
298 * is set up to, or capable of handling them.
299 */
300struct resource *
301pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
302    u_long start, u_long end, u_long count, u_int flags)
303{
304	struct pcib_softc	*sc = device_get_softc(dev);
305	int ok;
306
307	/*
308	 * Fail the allocation for this range if it's not supported.
309	 */
310	switch (type) {
311	case SYS_RES_IOPORT:
312		ok = 0;
313		if (!pcib_is_io_open(sc))
314			break;
315		ok = (start >= sc->iobase && end <= sc->iolimit);
316		if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
317			if (!ok) {
318				if (start < sc->iobase)
319					start = sc->iobase;
320				if (end > sc->iolimit)
321					end = sc->iolimit;
322				if (start < end)
323					ok = 1;
324			}
325		} else {
326			ok = 1;
327#if 1
328			if (start < sc->iobase && end > sc->iolimit) {
329				start = sc->iobase;
330				end = sc->iolimit;
331			}
332#endif
333		}
334		if (end < start) {
335			device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
336			    end, start);
337			start = 0;
338			end = 0;
339			ok = 0;
340		}
341		if (!ok) {
342			device_printf(dev, "%s requested unsupported I/O "
343			    "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
344			    device_get_nameunit(child), start, end,
345			    sc->iobase, sc->iolimit);
346			return (NULL);
347		}
348		if (bootverbose)
349			device_printf(dev,
350			    "%s requested I/O range 0x%lx-0x%lx: in range\n",
351			    device_get_nameunit(child), start, end);
352		break;
353
354	case SYS_RES_MEMORY:
355		ok = 0;
356		if (pcib_is_nonprefetch_open(sc))
357			ok = ok || (start >= sc->membase && end <= sc->memlimit);
358		if (pcib_is_prefetch_open(sc))
359			ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
360		if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
361			if (!ok) {
362				ok = 1;
363				if (flags & RF_PREFETCHABLE) {
364					if (pcib_is_prefetch_open(sc)) {
365						if (start < sc->pmembase)
366							start = sc->pmembase;
367						if (end > sc->pmemlimit)
368							end = sc->pmemlimit;
369					} else {
370						ok = 0;
371					}
372				} else {	/* non-prefetchable */
373					if (pcib_is_nonprefetch_open(sc)) {
374						if (start < sc->membase)
375							start = sc->membase;
376						if (end > sc->memlimit)
377							end = sc->memlimit;
378					} else {
379						ok = 0;
380					}
381				}
382			}
383		} else if (!ok) {
384			ok = 1;	/* subtractive bridge: always ok */
385#if 1
386			if (pcib_is_nonprefetch_open(sc)) {
387				if (start < sc->membase && end > sc->memlimit) {
388					start = sc->membase;
389					end = sc->memlimit;
390				}
391			}
392			if (pcib_is_prefetch_open(sc)) {
393				if (start < sc->pmembase && end > sc->pmemlimit) {
394					start = sc->pmembase;
395					end = sc->pmemlimit;
396				}
397			}
398#endif
399		}
400		if (end < start) {
401			device_printf(dev, "memory: end (%lx) < start (%lx)\n",
402			    end, start);
403			start = 0;
404			end = 0;
405			ok = 0;
406		}
407		if (!ok && bootverbose)
408			device_printf(dev,
409			    "%s requested unsupported memory range "
410			    "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
411			    device_get_nameunit(child), start, end,
412			    sc->membase, sc->memlimit, sc->pmembase,
413			    sc->pmemlimit);
414		if (!ok)
415			return (NULL);
416		if (bootverbose)
417			device_printf(dev,"%s requested memory range "
418			    "0x%lx-0x%lx: good\n",
419			    device_get_nameunit(child), start, end);
420		break;
421
422	default:
423		break;
424	}
425	/*
426	 * Bridge is OK decoding this resource, so pass it up.
427	 */
428	return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
429	    count, flags));
430}
431
432/*
433 * PCIB interface.
434 */
435int
436pcib_maxslots(device_t dev)
437{
438    return(PCI_SLOTMAX);
439}
440
441/*
442 * Since we are a child of a PCI bus, its parent must support the pcib interface.
443 */
444uint32_t
445pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
446{
447    return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
448}
449
450void
451pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
452{
453    PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
454}
455
456/*
457 * Route an interrupt across a PCI bridge.
458 */
459int
460pcib_route_interrupt(device_t pcib, device_t dev, int pin)
461{
462    device_t	bus;
463    int		parent_intpin;
464    int		intnum;
465
466    /*
467     *
468     * The PCI standard defines a swizzle of the child-side device/intpin to
469     * the parent-side intpin as follows.
470     *
471     * device = device on child bus
472     * child_intpin = intpin on child bus slot (0-3)
473     * parent_intpin = intpin on parent bus slot (0-3)
474     *
475     * parent_intpin = (device + child_intpin) % 4
476     */
477    parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
478
479    /*
480     * Our parent is a PCI bus.  Its parent must export the pcib interface
481     * which includes the ability to route interrupts.
482     */
483    bus = device_get_parent(pcib);
484    intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
485    if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
486	device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
487	    pci_get_slot(dev), 'A' + pin - 1, intnum);
488    }
489    return(intnum);
490}
491
492/*
493 * Try to read the bus number of a host-PCI bridge using appropriate config
494 * registers.
495 */
496int
497host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
498    uint8_t *busnum)
499{
500	uint32_t id;
501
502	id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
503	if (id == 0xffffffff)
504		return (0);
505
506	switch (id) {
507	case 0x12258086:
508		/* Intel 824?? */
509		/* XXX This is a guess */
510		/* *busnum = read_config(bus, slot, func, 0x41, 1); */
511		*busnum = bus;
512		break;
513	case 0x84c48086:
514		/* Intel 82454KX/GX (Orion) */
515		*busnum = read_config(bus, slot, func, 0x4a, 1);
516		break;
517	case 0x84ca8086:
518		/*
519		 * For the 450nx chipset, there is a whole bundle of
520		 * things pretending to be host bridges. The MIOC will
521		 * be seen first and isn't really a pci bridge (the
522		 * actual busses are attached to the PXB's). We need to
523		 * read the registers of the MIOC to figure out the
524		 * bus numbers for the PXB channels.
525		 *
526		 * Since the MIOC doesn't have a pci bus attached, we
527		 * pretend it wasn't there.
528		 */
529		return (0);
530	case 0x84cb8086:
531		switch (slot) {
532		case 0x12:
533			/* Intel 82454NX PXB#0, Bus#A */
534			*busnum = read_config(bus, 0x10, func, 0xd0, 1);
535			break;
536		case 0x13:
537			/* Intel 82454NX PXB#0, Bus#B */
538			*busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
539			break;
540		case 0x14:
541			/* Intel 82454NX PXB#1, Bus#A */
542			*busnum = read_config(bus, 0x10, func, 0xd3, 1);
543			break;
544		case 0x15:
545			/* Intel 82454NX PXB#1, Bus#B */
546			*busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
547			break;
548		}
549		break;
550
551		/* ServerWorks -- vendor 0x1166 */
552	case 0x00051166:
553	case 0x00061166:
554	case 0x00081166:
555	case 0x00091166:
556	case 0x00101166:
557	case 0x00111166:
558	case 0x00171166:
559	case 0x01011166:
560	case 0x010f1014:
561	case 0x02011166:
562	case 0x03021014:
563		*busnum = read_config(bus, slot, func, 0x44, 1);
564		break;
565	default:
566		/* Don't know how to read bus number. */
567		return 0;
568	}
569
570	return 1;
571}
572