pci.c revision 69957
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 69957 2000-12-13 04:22:04Z msmith $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/types.h> 44 45#include <vm/vm.h> 46#include <vm/pmap.h> 47#include <vm/vm_extern.h> 48 49#include <sys/bus.h> 50#include <machine/bus.h> 51#include <sys/rman.h> 52#include <machine/resource.h> 53 54#include <sys/pciio.h> 55#include <pci/pcireg.h> 56#include <pci/pcivar.h> 57 58#include "pcib_if.h" 59#include "pci_if.h" 60 61static u_int32_t pci_mapbase(unsigned mapreg); 62static int pci_maptype(unsigned mapreg); 63static int pci_mapsize(unsigned testval); 64static int pci_maprange(unsigned mapreg); 65static void pci_fixancient(pcicfgregs *cfg); 66static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 67 pcicfgregs *cfg); 68static struct pci_devinfo *pci_read_device(device_t pcib, int b, int s, int f); 69static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 70 71static void pci_print_verbose(struct pci_devinfo *dinfo); 72static int pci_porten(device_t pcib, int b, int s, int f); 73static int pci_memen(device_t pcib, int b, int s, int f); 74static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 75 struct resource_list *rl); 76static void pci_add_resources(device_t pcib, int b, int s, int f, 77 device_t dev); 78static void pci_add_children(device_t dev, int busno); 79static int pci_probe(device_t dev); 80static int pci_print_resources(struct resource_list *rl, 81 const char *name, int type, 82 const char *format); 83static int pci_print_child(device_t dev, device_t child); 84static void pci_probe_nomatch(device_t dev, device_t child); 85static int pci_describe_parse_line(char **ptr, int *vendor, 86 int *device, char **desc); 87static char *pci_describe_device(device_t dev); 88static int pci_read_ivar(device_t dev, device_t child, int which, 89 uintptr_t *result); 90static int pci_write_ivar(device_t dev, device_t child, int which, 91 uintptr_t value); 92static struct resource *pci_alloc_resource(device_t dev, device_t child, 93 int type, int *rid, u_long start, 94 u_long end, u_long count, u_int flags); 95static void pci_delete_resource(device_t dev, device_t child, 96 int type, int rid); 97static struct resource_list *pci_get_resource_list (device_t dev, device_t child); 98static u_int32_t pci_read_config_method(device_t dev, device_t child, 99 int reg, int width); 100static void pci_write_config_method(device_t dev, device_t child, 101 int reg, u_int32_t val, int width); 102static int pci_modevent(module_t mod, int what, void *arg); 103 104static device_method_t pci_methods[] = { 105 /* Device interface */ 106 DEVMETHOD(device_probe, pci_probe), 107 DEVMETHOD(device_attach, bus_generic_attach), 108 DEVMETHOD(device_shutdown, bus_generic_shutdown), 109 DEVMETHOD(device_suspend, bus_generic_suspend), 110 DEVMETHOD(device_resume, bus_generic_resume), 111 112 /* Bus interface */ 113 DEVMETHOD(bus_print_child, pci_print_child), 114 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 115 DEVMETHOD(bus_read_ivar, pci_read_ivar), 116 DEVMETHOD(bus_write_ivar, pci_write_ivar), 117 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 118 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 119 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 120 121 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 122 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 123 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 124 DEVMETHOD(bus_delete_resource, pci_delete_resource), 125 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 126 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 127 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 128 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 129 130 /* PCI interface */ 131 DEVMETHOD(pci_read_config, pci_read_config_method), 132 DEVMETHOD(pci_write_config, pci_write_config_method), 133 134 { 0, 0 } 135}; 136 137static driver_t pci_driver = { 138 "pci", 139 pci_methods, 140 0, /* no softc */ 141}; 142 143static devclass_t pci_devclass; 144DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 145DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0); 146 147static char *pci_vendordata; 148static size_t pci_vendordata_size; 149 150 151struct pci_quirk { 152 u_int32_t devid; /* Vendor/device of the card */ 153 int type; 154#define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */ 155 int arg1; 156 int arg2; 157}; 158 159struct pci_quirk pci_quirks[] = { 160 /* 161 * The Intel 82371AB has a map register at offset 0x90. 162 */ 163 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 164 165 { 0 } 166}; 167 168/* map register information */ 169#define PCI_MAPMEM 0x01 /* memory map */ 170#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 171#define PCI_MAPPORT 0x04 /* port map */ 172 173u_int32_t pci_numdevs = 0; 174 175/* return base address of memory or port map */ 176 177static u_int32_t 178pci_mapbase(unsigned mapreg) 179{ 180 int mask = 0x03; 181 if ((mapreg & 0x01) == 0) 182 mask = 0x0f; 183 return (mapreg & ~mask); 184} 185 186/* return map type of memory or port map */ 187 188static int 189pci_maptype(unsigned mapreg) 190{ 191 static u_int8_t maptype[0x10] = { 192 PCI_MAPMEM, PCI_MAPPORT, 193 PCI_MAPMEM, 0, 194 PCI_MAPMEM, PCI_MAPPORT, 195 0, 0, 196 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 197 PCI_MAPMEM|PCI_MAPMEMP, 0, 198 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 199 0, 0, 200 }; 201 202 return maptype[mapreg & 0x0f]; 203} 204 205/* return log2 of map size decoded for memory or port map */ 206 207static int 208pci_mapsize(unsigned testval) 209{ 210 int ln2size; 211 212 testval = pci_mapbase(testval); 213 ln2size = 0; 214 if (testval != 0) { 215 while ((testval & 1) == 0) 216 { 217 ln2size++; 218 testval >>= 1; 219 } 220 } 221 return (ln2size); 222} 223 224/* return log2 of address range supported by map register */ 225 226static int 227pci_maprange(unsigned mapreg) 228{ 229 int ln2range = 0; 230 switch (mapreg & 0x07) { 231 case 0x00: 232 case 0x01: 233 case 0x05: 234 ln2range = 32; 235 break; 236 case 0x02: 237 ln2range = 20; 238 break; 239 case 0x04: 240 ln2range = 64; 241 break; 242 } 243 return (ln2range); 244} 245 246/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 247 248static void 249pci_fixancient(pcicfgregs *cfg) 250{ 251 if (cfg->hdrtype != 0) 252 return; 253 254 /* PCI to PCI bridges use header type 1 */ 255 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 256 cfg->hdrtype = 1; 257} 258 259/* extract header type specific config data */ 260 261static void 262pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 263{ 264#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 265 switch (cfg->hdrtype) { 266 case 0: 267 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 268 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 269 cfg->nummaps = PCI_MAXMAPS_0; 270 break; 271 case 1: 272 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 273 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 274 cfg->nummaps = PCI_MAXMAPS_1; 275 break; 276 case 2: 277 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 278 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 279 cfg->nummaps = PCI_MAXMAPS_2; 280 break; 281 } 282#undef REG 283} 284 285/* read configuration header into pcicfgregs structure */ 286 287static struct pci_devinfo * 288pci_read_device(device_t pcib, int b, int s, int f) 289{ 290#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 291 pcicfgregs *cfg = NULL; 292 struct pci_devinfo *devlist_entry; 293 struct devlist *devlist_head; 294 295 devlist_head = &pci_devq; 296 297 devlist_entry = NULL; 298 299 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 300 devlist_entry = malloc(sizeof(struct pci_devinfo), 301 M_DEVBUF, M_WAITOK | M_ZERO); 302 if (devlist_entry == NULL) 303 return (NULL); 304 305 cfg = &devlist_entry->cfg; 306 307 cfg->bus = b; 308 cfg->slot = s; 309 cfg->func = f; 310 cfg->vendor = REG(PCIR_VENDOR, 2); 311 cfg->device = REG(PCIR_DEVICE, 2); 312 cfg->cmdreg = REG(PCIR_COMMAND, 2); 313 cfg->statreg = REG(PCIR_STATUS, 2); 314 cfg->baseclass = REG(PCIR_CLASS, 1); 315 cfg->subclass = REG(PCIR_SUBCLASS, 1); 316 cfg->progif = REG(PCIR_PROGIF, 1); 317 cfg->revid = REG(PCIR_REVID, 1); 318 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 319 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 320 cfg->lattimer = REG(PCIR_LATTIMER, 1); 321 cfg->intpin = REG(PCIR_INTPIN, 1); 322 cfg->intline = REG(PCIR_INTLINE, 1); 323 324 cfg->mingnt = REG(PCIR_MINGNT, 1); 325 cfg->maxlat = REG(PCIR_MAXLAT, 1); 326 327 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 328 cfg->hdrtype &= ~PCIM_MFDEV; 329 330 pci_fixancient(cfg); 331 pci_hdrtypedata(pcib, b, s, f, cfg); 332 333 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 334 pci_read_extcap(pcib, cfg); 335 336 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 337 338 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 339 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 340 devlist_entry->conf.pc_sel.pc_func = cfg->func; 341 devlist_entry->conf.pc_hdr = cfg->hdrtype; 342 343 devlist_entry->conf.pc_subvendor = cfg->subvendor; 344 devlist_entry->conf.pc_subdevice = cfg->subdevice; 345 devlist_entry->conf.pc_vendor = cfg->vendor; 346 devlist_entry->conf.pc_device = cfg->device; 347 348 devlist_entry->conf.pc_class = cfg->baseclass; 349 devlist_entry->conf.pc_subclass = cfg->subclass; 350 devlist_entry->conf.pc_progif = cfg->progif; 351 devlist_entry->conf.pc_revid = cfg->revid; 352 353 pci_numdevs++; 354 pci_generation++; 355 } 356 return (devlist_entry); 357#undef REG 358} 359 360static void 361pci_read_extcap(device_t pcib, pcicfgregs *cfg) 362{ 363#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 364 int ptr, nextptr, ptrptr; 365 366 switch (cfg->hdrtype) { 367 case 0: 368 ptrptr = 0x34; 369 break; 370 case 2: 371 ptrptr = 0x14; 372 break; 373 default: 374 return; /* no extended capabilities support */ 375 } 376 nextptr = REG(ptrptr, 1); /* sanity check? */ 377 378 /* 379 * Read capability entries. 380 */ 381 while (nextptr != 0) { 382 /* Find the next entry */ 383 ptr = nextptr; 384 nextptr = REG(ptr + 1, 1); 385 386 /* Process this entry */ 387 switch (REG(ptr, 1)) { 388 case 0x01: /* PCI power management */ 389 if (cfg->pp_cap == 0) { 390 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 391 cfg->pp_status = ptr + PCIR_POWER_STATUS; 392 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 393 if ((nextptr - ptr) > PCIR_POWER_DATA) 394 cfg->pp_data = ptr + PCIR_POWER_DATA; 395 } 396 break; 397 default: 398 break; 399 } 400 } 401#undef REG 402} 403 404#if 0 405/* free pcicfgregs structure and all depending data structures */ 406 407static int 408pci_freecfg(struct pci_devinfo *dinfo) 409{ 410 struct devlist *devlist_head; 411 412 devlist_head = &pci_devq; 413 414 if (dinfo->cfg.map != NULL) 415 free(dinfo->cfg.map, M_DEVBUF); 416 /* XXX this hasn't been tested */ 417 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 418 free(dinfo, M_DEVBUF); 419 420 /* increment the generation count */ 421 pci_generation++; 422 423 /* we're losing one device */ 424 pci_numdevs--; 425 return (0); 426} 427#endif 428 429/* 430 * PCI power manangement 431 */ 432int 433pci_set_powerstate(device_t dev, int state) 434{ 435 struct pci_devinfo *dinfo = device_get_ivars(dev); 436 pcicfgregs *cfg = &dinfo->cfg; 437 u_int16_t status; 438 int result; 439 440 if (cfg->pp_cap != 0) { 441 status = pci_read_config(dev, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 442 result = 0; 443 switch (state) { 444 case PCI_POWERSTATE_D0: 445 status |= PCIM_PSTAT_D0; 446 break; 447 case PCI_POWERSTATE_D1: 448 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 449 status |= PCIM_PSTAT_D1; 450 } else { 451 result = EOPNOTSUPP; 452 } 453 break; 454 case PCI_POWERSTATE_D2: 455 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 456 status |= PCIM_PSTAT_D2; 457 } else { 458 result = EOPNOTSUPP; 459 } 460 break; 461 case PCI_POWERSTATE_D3: 462 status |= PCIM_PSTAT_D3; 463 break; 464 default: 465 result = EINVAL; 466 } 467 if (result == 0) 468 pci_write_config(dev, cfg->pp_status, status, 2); 469 } else { 470 result = ENXIO; 471 } 472 return(result); 473} 474 475int 476pci_get_powerstate(device_t dev) 477{ 478 struct pci_devinfo *dinfo = device_get_ivars(dev); 479 pcicfgregs *cfg = &dinfo->cfg; 480 u_int16_t status; 481 int result; 482 483 if (cfg->pp_cap != 0) { 484 status = pci_read_config(dev, cfg->pp_status, 2); 485 switch (status & PCIM_PSTAT_DMASK) { 486 case PCIM_PSTAT_D0: 487 result = PCI_POWERSTATE_D0; 488 break; 489 case PCIM_PSTAT_D1: 490 result = PCI_POWERSTATE_D1; 491 break; 492 case PCIM_PSTAT_D2: 493 result = PCI_POWERSTATE_D2; 494 break; 495 case PCIM_PSTAT_D3: 496 result = PCI_POWERSTATE_D3; 497 break; 498 default: 499 result = PCI_POWERSTATE_UNKNOWN; 500 break; 501 } 502 } else { 503 /* No support, device is always at D0 */ 504 result = PCI_POWERSTATE_D0; 505 } 506 return(result); 507} 508 509/* 510 * Some convenience functions for PCI device drivers. 511 */ 512 513static __inline void 514pci_set_command_bit(device_t dev, u_int16_t bit) 515{ 516 u_int16_t command; 517 518 command = pci_read_config(dev, PCIR_COMMAND, 2); 519 command |= bit; 520 pci_write_config(dev, PCIR_COMMAND, command, 2); 521} 522 523static __inline void 524pci_clear_command_bit(device_t dev, u_int16_t bit) 525{ 526 u_int16_t command; 527 528 command = pci_read_config(dev, PCIR_COMMAND, 2); 529 command &= ~bit; 530 pci_write_config(dev, PCIR_COMMAND, command, 2); 531} 532 533void 534pci_enable_busmaster(device_t dev) 535{ 536 pci_set_command_bit(dev, PCIM_CMD_BUSMASTEREN); 537} 538 539void 540pci_disable_busmaster(device_t dev) 541{ 542 pci_clear_command_bit(dev, PCIM_CMD_BUSMASTEREN); 543} 544 545void 546pci_enable_io(device_t dev, int space) 547{ 548 switch(space) { 549 case SYS_RES_IOPORT: 550 pci_set_command_bit(dev, PCIM_CMD_PORTEN); 551 break; 552 case SYS_RES_MEMORY: 553 pci_set_command_bit(dev, PCIM_CMD_MEMEN); 554 break; 555 } 556} 557 558void 559pci_disable_io(device_t dev, int space) 560{ 561 switch(space) { 562 case SYS_RES_IOPORT: 563 pci_clear_command_bit(dev, PCIM_CMD_PORTEN); 564 break; 565 case SYS_RES_MEMORY: 566 pci_clear_command_bit(dev, PCIM_CMD_MEMEN); 567 break; 568 } 569} 570 571/* 572 * New style pci driver. Parent device is either a pci-host-bridge or a 573 * pci-pci-bridge. Both kinds are represented by instances of pcib. 574 */ 575 576static void 577pci_print_verbose(struct pci_devinfo *dinfo) 578{ 579 if (bootverbose) { 580 pcicfgregs *cfg = &dinfo->cfg; 581 582 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 583 cfg->vendor, cfg->device, cfg->revid); 584 printf("\tbus=%d, slot=%d, func=%d\n", 585 cfg->bus, cfg->slot, cfg->func); 586 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 587 cfg->baseclass, cfg->subclass, cfg->progif, 588 cfg->hdrtype, cfg->mfdev); 589#ifdef PCI_DEBUG 590 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 591 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 592 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 593 cfg->lattimer, cfg->lattimer * 30, 594 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 595#endif /* PCI_DEBUG */ 596 if (cfg->intpin > 0) 597 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 598 if (cfg->pp_cap) { 599 u_int16_t status; 600 601 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 602 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 603 cfg->pp_cap & PCIM_PCAP_SPEC, 604 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 605 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 606 status & PCIM_PSTAT_DMASK); 607 } 608 } 609} 610 611static int 612pci_porten(device_t pcib, int b, int s, int f) 613{ 614 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 615 & PCIM_CMD_PORTEN) != 0; 616} 617 618static int 619pci_memen(device_t pcib, int b, int s, int f) 620{ 621 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 622 & PCIM_CMD_MEMEN) != 0; 623} 624 625/* 626 * Add a resource based on a pci map register. Return 1 if the map 627 * register is a 32bit map register or 2 if it is a 64bit register. 628 */ 629static int 630pci_add_map(device_t pcib, int b, int s, int f, int reg, 631 struct resource_list *rl) 632{ 633 u_int32_t map; 634 u_int64_t base; 635 u_int8_t ln2size; 636 u_int8_t ln2range; 637 u_int32_t testval; 638#ifdef PCI_ENABLE_IO_MODES 639 u_int16_t cmd; 640#endif 641 int type; 642 643 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 644 645 if (map == 0 || map == 0xffffffff) 646 return 1; /* skip invalid entry */ 647 648 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 649 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 650 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 651 652 base = pci_mapbase(map); 653 if (pci_maptype(map) & PCI_MAPMEM) 654 type = SYS_RES_MEMORY; 655 else 656 type = SYS_RES_IOPORT; 657 ln2size = pci_mapsize(testval); 658 ln2range = pci_maprange(testval); 659 if (ln2range == 64) { 660 /* Read the other half of a 64bit map register */ 661 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 662 } 663 664 if (bootverbose) { 665 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 666 reg, pci_maptype(map), ln2range, 667 (unsigned int) base, ln2size); 668 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 669 printf(", port disabled\n"); 670 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 671 printf(", memory disabled\n"); 672 else 673 printf(", enabled\n"); 674 } 675 676 /* 677 * This code theoretically does the right thing, but has 678 * undesirable side effects in some cases where 679 * peripherals respond oddly to having these bits 680 * enabled. Leave them alone by default. 681 */ 682#ifdef PCI_ENABLE_IO_MODES 683 /* Turn on resources that have been left off by a lazy BIOS */ 684 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 685 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 686 cmd |= PCIM_CMD_PORTEN; 687 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 688 } 689 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 690 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 691 cmd |= PCIM_CMD_MEMEN; 692 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 693 } 694#else 695 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 696 return 1; 697 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 698 return 1; 699#endif 700 701 resource_list_add(rl, type, reg, 702 base, base + (1 << ln2size) - 1, 703 (1 << ln2size)); 704 705 return (ln2range == 64) ? 2 : 1; 706} 707 708static void 709pci_add_resources(device_t pcib, int b, int s, int f, device_t dev) 710{ 711 struct pci_devinfo *dinfo = device_get_ivars(dev); 712 pcicfgregs *cfg = &dinfo->cfg; 713 struct resource_list *rl = &dinfo->resources; 714 struct pci_quirk *q; 715 int i; 716 717 for (i = 0; i < cfg->nummaps;) { 718 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 719 } 720 721 for (q = &pci_quirks[0]; q->devid; q++) { 722 if (q->devid == ((cfg->device << 16) | cfg->vendor) 723 && q->type == PCI_QUIRK_MAP_REG) 724 pci_add_map(pcib, b, s, f, q->arg1, rl); 725 } 726 727 if (cfg->intpin > 0 && cfg->intline != 255) 728 resource_list_add(rl, SYS_RES_IRQ, 0, 729 cfg->intline, cfg->intline, 1); 730} 731 732static void 733pci_add_children(device_t dev, int busno) 734{ 735 device_t pcib = device_get_parent(dev); 736 int maxslots; 737 int s, f; 738 739 maxslots = PCIB_MAXSLOTS(pcib); 740 741 for (s = 0; s <= maxslots; s++) { 742 int pcifunchigh = 0; 743 for (f = 0; f <= pcifunchigh; f++) { 744 struct pci_devinfo *dinfo = 745 pci_read_device(pcib, busno, s, f); 746 if (dinfo != NULL) { 747 if (dinfo->cfg.mfdev) 748 pcifunchigh = PCI_FUNCMAX; 749 750 dinfo->cfg.dev = device_add_child(dev, NULL, -1); 751 device_set_ivars(dinfo->cfg.dev, dinfo); 752 pci_add_resources(pcib, busno, s, f, 753 dinfo->cfg.dev); 754 pci_print_verbose(dinfo); 755 } 756 } 757 } 758} 759 760static int 761pci_probe(device_t dev) 762{ 763 static int once, busno; 764 caddr_t vendordata, info; 765 766 device_set_desc(dev, "PCI bus"); 767 768 if (bootverbose) 769 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev)); 770 771 /* 772 * Since there can be multiple independantly numbered PCI 773 * busses on some large alpha systems, we can't use the unit 774 * number to decide what bus we are probing. We ask the parent 775 * pcib what our bus number is. 776 */ 777 busno = pcib_get_bus(dev); 778 if (busno < 0) 779 return ENXIO; 780 pci_add_children(dev, busno); 781 782 if (!once) { 783 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 784 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 785 info = preload_search_info(vendordata, MODINFO_ADDR); 786 pci_vendordata = *(char **)info; 787 info = preload_search_info(vendordata, MODINFO_SIZE); 788 pci_vendordata_size = *(size_t *)info; 789 /* terminate the database */ 790 pci_vendordata[pci_vendordata_size] = '\n'; 791 } 792 once++; 793 } 794 795 return 0; 796} 797 798static int 799pci_print_resources(struct resource_list *rl, const char *name, int type, 800 const char *format) 801{ 802 struct resource_list_entry *rle; 803 int printed, retval; 804 805 printed = 0; 806 retval = 0; 807 /* Yes, this is kinda cheating */ 808 SLIST_FOREACH(rle, rl, link) { 809 if (rle->type == type) { 810 if (printed == 0) 811 retval += printf(" %s ", name); 812 else if (printed > 0) 813 retval += printf(","); 814 printed++; 815 retval += printf(format, rle->start); 816 if (rle->count > 1) { 817 retval += printf("-"); 818 retval += printf(format, rle->start + 819 rle->count - 1); 820 } 821 } 822 } 823 return retval; 824} 825 826static int 827pci_print_child(device_t dev, device_t child) 828{ 829 struct pci_devinfo *dinfo; 830 struct resource_list *rl; 831 pcicfgregs *cfg; 832 int retval = 0; 833 834 dinfo = device_get_ivars(child); 835 cfg = &dinfo->cfg; 836 rl = &dinfo->resources; 837 838 retval += bus_print_child_header(dev, child); 839 840 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 841 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 842 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 843 if (device_get_flags(dev)) 844 retval += printf(" flags %#x", device_get_flags(dev)); 845 846 retval += printf(" at device %d.%d", pci_get_slot(child), 847 pci_get_function(child)); 848 849 retval += bus_print_child_footer(dev, child); 850 851 return (retval); 852} 853 854static struct 855{ 856 int class; 857 int subclass; 858 char *desc; 859} pci_nomatch_tab[] = { 860 {PCIC_OLD, -1, "old"}, 861 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 862 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 863 {PCIC_STORAGE, -1, "mass storage"}, 864 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 865 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 866 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 867 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 868 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 869 {PCIC_NETWORK, -1, "network"}, 870 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 871 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 872 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 873 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 874 {PCIC_DISPLAY, -1, "display"}, 875 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 876 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 877 {PCIC_MULTIMEDIA, -1, "multimedia"}, 878 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 879 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 880 {PCIC_MEMORY, -1, "memory"}, 881 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 882 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 883 {PCIC_BRIDGE, -1, "bridge"}, 884 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 885 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 886 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 887 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 888 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 889 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 890 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 891 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 892 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 893 {PCIC_SIMPLECOMM, -1, "simple comms"}, 894 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 895 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 896 {PCIC_BASEPERIPH, -1, "base peripheral"}, 897 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 898 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 899 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 900 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 901 {PCIC_INPUTDEV, -1, "input device"}, 902 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 903 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 904 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 905 {PCIC_DOCKING, -1, "docking station"}, 906 {PCIC_PROCESSOR, -1, "processor"}, 907 {PCIC_SERIALBUS, -1, "serial bus"}, 908 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 909 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 910 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 911 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 912 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 913 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 914 {0, 0, NULL} 915}; 916 917static void 918pci_probe_nomatch(device_t dev, device_t child) 919{ 920 int i; 921 char *cp, *scp, *device; 922 923 /* 924 * Look for a listing for this device in a loaded device database. 925 */ 926 if ((device = pci_describe_device(child)) != NULL) { 927 device_printf(dev, "<%s>", device); 928 free(device, M_DEVBUF); 929 } else { 930 /* 931 * Scan the class/subclass descriptions for a general description. 932 */ 933 cp = "unknown"; 934 scp = NULL; 935 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 936 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 937 if (pci_nomatch_tab[i].subclass == -1) { 938 cp = pci_nomatch_tab[i].desc; 939 } else if (pci_nomatch_tab[i].subclass == pci_get_subclass(child)) { 940 scp = pci_nomatch_tab[i].desc; 941 } 942 } 943 } 944 device_printf(dev, "<%s%s%s>", 945 cp ? : "", 946 ((cp != NULL) && (scp != NULL)) ? ", " : "", 947 scp ? : ""); 948 } 949 printf(" at %d.%d (no driver attached)\n", 950 pci_get_slot(child), 951 pci_get_function(child)); 952 return; 953} 954 955/* 956 * Parse the PCI device database, if loaded, and return a pointer to a 957 * description of the device. 958 * 959 * The database is flat text formatted as follows: 960 * 961 * Any line not in a valid format is ignored. 962 * Lines are terminated with newline '\n' characters. 963 * 964 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 965 * the vendor name. 966 * 967 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 968 * - devices cannot be listed without a corresponding VENDOR line. 969 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 970 * another TAB, then the device name. 971 */ 972 973/* 974 * Assuming (ptr) points to the beginning of a line in the database, 975 * return the vendor or device and description of the next entry. 976 * The value of (vendor) or (device) inappropriate for the entry type 977 * is set to -1. Returns nonzero at the end of the database. 978 * 979 * Note that this is slightly unrobust in the face of corrupt data; 980 * we attempt to safeguard against this by spamming the end of the 981 * database with a newline when we initialise. 982 */ 983static int 984pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 985{ 986 char *cp = *ptr; 987 int left; 988 989 *device = -1; 990 *vendor = -1; 991 **desc = '\0'; 992 for (;;) { 993 left = pci_vendordata_size - (cp - pci_vendordata); 994 if (left <= 0) { 995 *ptr = cp; 996 return(1); 997 } 998 999 /* vendor entry? */ 1000 if (*cp != '\t' && sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1001 break; 1002 /* device entry? */ 1003 if (*cp == '\t' && sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1004 break; 1005 1006 /* skip to next line */ 1007 while (*cp != '\n' && left > 0) { 1008 cp++; 1009 left--; 1010 } 1011 if (*cp == '\n') { 1012 cp++; 1013 left--; 1014 } 1015 } 1016 /* skip to next line */ 1017 while (*cp != '\n' && left > 0) { 1018 cp++; 1019 left--; 1020 } 1021 if (*cp == '\n' && left > 0) 1022 cp++; 1023 *ptr = cp; 1024 return(0); 1025} 1026 1027static char * 1028pci_describe_device(device_t dev) 1029{ 1030 int vendor, device; 1031 char *desc, *vp, *dp, *line; 1032 1033 desc = vp = dp = NULL; 1034 1035 /* 1036 * If we have no vendor data, we can't do anything. 1037 */ 1038 if (pci_vendordata == NULL) 1039 goto out; 1040 1041 /* 1042 * Scan the vendor data looking for this device 1043 */ 1044 line = pci_vendordata; 1045 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1046 goto out; 1047 for (;;) { 1048 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1049 goto out; 1050 if (vendor == pci_get_vendor(dev)) 1051 break; 1052 } 1053 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1054 goto out; 1055 for (;;) { 1056 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1057 *dp = 0; 1058 break; 1059 } 1060 if (vendor != -1) { 1061 *dp = 0; 1062 break; 1063 } 1064 if (device == pci_get_device(dev)) 1065 break; 1066 } 1067 if (dp[0] == '\0') 1068 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1069 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != NULL) 1070 sprintf(desc, "%s, %s", vp, dp); 1071 out: 1072 if (vp != NULL) 1073 free(vp, M_DEVBUF); 1074 if (dp != NULL) 1075 free(dp, M_DEVBUF); 1076 return(desc); 1077} 1078 1079static int 1080pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1081{ 1082 struct pci_devinfo *dinfo; 1083 pcicfgregs *cfg; 1084 1085 dinfo = device_get_ivars(child); 1086 cfg = &dinfo->cfg; 1087 1088 switch (which) { 1089 case PCI_IVAR_SUBVENDOR: 1090 *result = cfg->subvendor; 1091 break; 1092 case PCI_IVAR_SUBDEVICE: 1093 *result = cfg->subdevice; 1094 break; 1095 case PCI_IVAR_VENDOR: 1096 *result = cfg->vendor; 1097 break; 1098 case PCI_IVAR_DEVICE: 1099 *result = cfg->device; 1100 break; 1101 case PCI_IVAR_DEVID: 1102 *result = (cfg->device << 16) | cfg->vendor; 1103 break; 1104 case PCI_IVAR_CLASS: 1105 *result = cfg->baseclass; 1106 break; 1107 case PCI_IVAR_SUBCLASS: 1108 *result = cfg->subclass; 1109 break; 1110 case PCI_IVAR_PROGIF: 1111 *result = cfg->progif; 1112 break; 1113 case PCI_IVAR_REVID: 1114 *result = cfg->revid; 1115 break; 1116 case PCI_IVAR_INTPIN: 1117 *result = cfg->intpin; 1118 break; 1119 case PCI_IVAR_IRQ: 1120 *result = cfg->intline; 1121 break; 1122 case PCI_IVAR_BUS: 1123 *result = cfg->bus; 1124 break; 1125 case PCI_IVAR_SLOT: 1126 *result = cfg->slot; 1127 break; 1128 case PCI_IVAR_FUNCTION: 1129 *result = cfg->func; 1130 break; 1131 default: 1132 return ENOENT; 1133 } 1134 return 0; 1135} 1136 1137static int 1138pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1139{ 1140 struct pci_devinfo *dinfo; 1141 pcicfgregs *cfg; 1142 1143 dinfo = device_get_ivars(child); 1144 cfg = &dinfo->cfg; 1145 1146 switch (which) { 1147 case PCI_IVAR_SUBVENDOR: 1148 case PCI_IVAR_SUBDEVICE: 1149 case PCI_IVAR_VENDOR: 1150 case PCI_IVAR_DEVICE: 1151 case PCI_IVAR_DEVID: 1152 case PCI_IVAR_CLASS: 1153 case PCI_IVAR_SUBCLASS: 1154 case PCI_IVAR_PROGIF: 1155 case PCI_IVAR_REVID: 1156 case PCI_IVAR_INTPIN: 1157 case PCI_IVAR_IRQ: 1158 case PCI_IVAR_BUS: 1159 case PCI_IVAR_SLOT: 1160 case PCI_IVAR_FUNCTION: 1161 return EINVAL; /* disallow for now */ 1162 1163 default: 1164 return ENOENT; 1165 } 1166 return 0; 1167} 1168 1169static struct resource * 1170pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1171 u_long start, u_long end, u_long count, u_int flags) 1172{ 1173 struct pci_devinfo *dinfo = device_get_ivars(child); 1174 struct resource_list *rl = &dinfo->resources; 1175 pcicfgregs *cfg = &dinfo->cfg; 1176 1177 /* 1178 * Perform lazy resource allocation 1179 * 1180 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1181 */ 1182 if (device_get_parent(child) == dev) { 1183 /* 1184 * If device doesn't have an interrupt routed, and is deserving of 1185 * an interrupt, try to assign it one. 1186 */ 1187 if ((type == SYS_RES_IRQ) && (cfg->intline == 255) && (cfg->intpin != 0)) { 1188 cfg->intline = PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1189 cfg->intpin); 1190 if (cfg->intline != 255) { 1191 pci_write_config(child, PCIR_INTLINE, cfg->intline, 1); 1192 resource_list_add(rl, SYS_RES_IRQ, 0, 1193 cfg->intline, cfg->intline, 1); 1194 } 1195 } 1196 } 1197 1198 return resource_list_alloc(rl, dev, child, type, rid, 1199 start, end, count, flags); 1200} 1201 1202static void 1203pci_delete_resource(device_t dev, device_t child, int type, int rid) 1204{ 1205 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1206} 1207 1208static struct resource_list * 1209pci_get_resource_list (device_t dev, device_t child) 1210{ 1211 struct pci_devinfo * dinfo = device_get_ivars(child); 1212 struct resource_list * rl = &dinfo->resources; 1213 1214 if (!rl) 1215 return (NULL); 1216 1217 return (rl); 1218} 1219 1220static u_int32_t 1221pci_read_config_method(device_t dev, device_t child, int reg, int width) 1222{ 1223 struct pci_devinfo *dinfo = device_get_ivars(child); 1224 pcicfgregs *cfg = &dinfo->cfg; 1225 1226 return PCIB_READ_CONFIG(device_get_parent(dev), 1227 cfg->bus, cfg->slot, cfg->func, 1228 reg, width); 1229} 1230 1231static void 1232pci_write_config_method(device_t dev, device_t child, int reg, 1233 u_int32_t val, int width) 1234{ 1235 struct pci_devinfo *dinfo = device_get_ivars(child); 1236 pcicfgregs *cfg = &dinfo->cfg; 1237 1238 PCIB_WRITE_CONFIG(device_get_parent(dev), 1239 cfg->bus, cfg->slot, cfg->func, 1240 reg, val, width); 1241} 1242 1243static int 1244pci_modevent(module_t mod, int what, void *arg) 1245{ 1246 switch (what) { 1247 case MOD_LOAD: 1248 STAILQ_INIT(&pci_devq); 1249 pci_generation = 0; 1250 break; 1251 1252 case MOD_UNLOAD: 1253 break; 1254 } 1255 1256 return 0; 1257} 1258