pci.c revision 58124
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pci.c 58124 2000-03-15 23:50:31Z mjacob $ 27 * 28 */ 29 30#include "opt_bus.h" 31 32#include "opt_simos.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/fcntl.h> 39#include <sys/conf.h> 40#include <sys/kernel.h> 41#include <sys/queue.h> 42#include <sys/types.h> 43#include <sys/buf.h> 44 45#include <vm/vm.h> 46#include <vm/pmap.h> 47#include <vm/vm_extern.h> 48 49#include <sys/bus.h> 50#include <machine/bus.h> 51#include <sys/rman.h> 52#include <machine/resource.h> 53#include <machine/md_var.h> /* For the Alpha */ 54 55#include <pci/pcireg.h> 56#include <pci/pcivar.h> 57#include <sys/pciio.h> 58 59#ifdef __alpha__ 60#include <machine/rpb.h> 61#endif 62 63#ifdef APIC_IO 64#include <machine/smp.h> 65#endif /* APIC_IO */ 66 67struct pci_quirk { 68 u_int32_t devid; /* Vendor/device of the card */ 69 int type; 70#define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */ 71 int arg1; 72 int arg2; 73}; 74 75struct pci_quirk pci_quirks[] = { 76 /* 77 * The Intel 82371AB has a map register at offset 0x90. 78 */ 79 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 80 81 { 0 } 82}; 83 84/* map register information */ 85#define PCI_MAPMEM 0x01 /* memory map */ 86#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 87#define PCI_MAPPORT 0x04 /* port map */ 88 89struct pci_devinfo { 90 STAILQ_ENTRY(pci_devinfo) pci_links; 91 struct resource_list resources; 92 pcicfgregs cfg; 93 struct pci_conf conf; 94}; 95 96static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 97u_int32_t pci_numdevs = 0; 98static u_int32_t pci_generation = 0; 99 100/* return base address of memory or port map */ 101 102static u_int32_t 103pci_mapbase(unsigned mapreg) 104{ 105 int mask = 0x03; 106 if ((mapreg & 0x01) == 0) 107 mask = 0x0f; 108 return (mapreg & ~mask); 109} 110 111/* return map type of memory or port map */ 112 113static int 114pci_maptype(unsigned mapreg) 115{ 116 static u_int8_t maptype[0x10] = { 117 PCI_MAPMEM, PCI_MAPPORT, 118 PCI_MAPMEM, 0, 119 PCI_MAPMEM, PCI_MAPPORT, 120 0, 0, 121 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 122 PCI_MAPMEM|PCI_MAPMEMP, 0, 123 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 124 0, 0, 125 }; 126 127 return maptype[mapreg & 0x0f]; 128} 129 130/* return log2 of map size decoded for memory or port map */ 131 132static int 133pci_mapsize(unsigned testval) 134{ 135 int ln2size; 136 137 testval = pci_mapbase(testval); 138 ln2size = 0; 139 if (testval != 0) { 140 while ((testval & 1) == 0) 141 { 142 ln2size++; 143 testval >>= 1; 144 } 145 } 146 return (ln2size); 147} 148 149/* return log2 of address range supported by map register */ 150 151static int 152pci_maprange(unsigned mapreg) 153{ 154 int ln2range = 0; 155 switch (mapreg & 0x07) { 156 case 0x00: 157 case 0x01: 158 case 0x05: 159 ln2range = 32; 160 break; 161 case 0x02: 162 ln2range = 20; 163 break; 164 case 0x04: 165 ln2range = 64; 166 break; 167 } 168 return (ln2range); 169} 170 171/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 172 173static void 174pci_fixancient(pcicfgregs *cfg) 175{ 176 if (cfg->hdrtype != 0) 177 return; 178 179 /* PCI to PCI bridges use header type 1 */ 180 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 181 cfg->hdrtype = 1; 182} 183 184/* read config data specific to header type 1 device (PCI to PCI bridge) */ 185 186static void * 187pci_readppb(pcicfgregs *cfg) 188{ 189 pcih1cfgregs *p; 190 191 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK); 192 if (p == NULL) 193 return (NULL); 194 195 bzero(p, sizeof *p); 196 197 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2); 198 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2); 199 200 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1); 201 202 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2), 203 pci_cfgread(cfg, PCIR_IOBASEL_1, 1)); 204 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2), 205 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1)); 206 207 p->membase = PCI_PPBMEMBASE (0, 208 pci_cfgread(cfg, PCIR_MEMBASE_1, 2)); 209 p->memlimit = PCI_PPBMEMLIMIT (0, 210 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2)); 211 212 p->pmembase = PCI_PPBMEMBASE ( 213 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4), 214 pci_cfgread(cfg, PCIR_PMBASEL_1, 2)); 215 216 p->pmemlimit = PCI_PPBMEMLIMIT ( 217 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4), 218 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2)); 219 return (p); 220} 221 222/* read config data specific to header type 2 device (PCI to CardBus bridge) */ 223 224static void * 225pci_readpcb(pcicfgregs *cfg) 226{ 227 pcih2cfgregs *p; 228 229 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK); 230 if (p == NULL) 231 return (NULL); 232 233 bzero(p, sizeof *p); 234 235 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2); 236 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2); 237 238 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1); 239 240 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4); 241 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4); 242 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4); 243 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4); 244 245 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4); 246 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4); 247 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4); 248 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4); 249 250 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4); 251 return p; 252} 253 254/* extract header type specific config data */ 255 256static void 257pci_hdrtypedata(pcicfgregs *cfg) 258{ 259 switch (cfg->hdrtype) { 260 case 0: 261 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2); 262 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2); 263 cfg->nummaps = PCI_MAXMAPS_0; 264 break; 265 case 1: 266 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2); 267 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2); 268 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1); 269 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1); 270 cfg->nummaps = PCI_MAXMAPS_1; 271 cfg->hdrspec = pci_readppb(cfg); 272 break; 273 case 2: 274 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2); 275 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2); 276 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1); 277 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1); 278 cfg->nummaps = PCI_MAXMAPS_2; 279 cfg->hdrspec = pci_readpcb(cfg); 280 break; 281 } 282} 283 284/* read configuration header into pcicfgrect structure */ 285 286static struct pci_devinfo * 287pci_readcfg(pcicfgregs *probe) 288{ 289 pcicfgregs *cfg = NULL; 290 struct pci_devinfo *devlist_entry; 291 struct devlist *devlist_head; 292 293 devlist_head = &pci_devq; 294 295 devlist_entry = NULL; 296 297 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) { 298 299 devlist_entry = malloc(sizeof(struct pci_devinfo), 300 M_DEVBUF, M_WAITOK); 301 if (devlist_entry == NULL) 302 return (NULL); 303 bzero(devlist_entry, sizeof *devlist_entry); 304 305 cfg = &devlist_entry->cfg; 306 307 cfg->hose = probe->hose; 308 cfg->bus = probe->bus; 309 cfg->slot = probe->slot; 310 cfg->func = probe->func; 311 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2); 312 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2); 313 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2); 314 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2); 315 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1); 316 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1); 317 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1); 318 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1); 319 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1); 320 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1); 321 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1); 322 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1); 323 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1); 324#ifdef __alpha__ 325 alpha_platform_assign_pciintr(cfg); 326#endif 327 328#ifdef APIC_IO 329 if (cfg->intpin != 0) { 330 int airq; 331 332 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 333 if (airq >= 0) { 334 /* PCI specific entry found in MP table */ 335 if (airq != cfg->intline) { 336 undirect_pci_irq(cfg->intline); 337 cfg->intline = airq; 338 } 339 } else { 340 /* 341 * PCI interrupts might be redirected to the 342 * ISA bus according to some MP tables. Use the 343 * same methods as used by the ISA devices 344 * devices to find the proper IOAPIC int pin. 345 */ 346 airq = isa_apic_irq(cfg->intline); 347 if ((airq >= 0) && (airq != cfg->intline)) { 348 /* XXX: undirect_pci_irq() ? */ 349 undirect_isa_irq(cfg->intline); 350 cfg->intline = airq; 351 } 352 } 353 } 354#endif /* APIC_IO */ 355 356 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1); 357 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1); 358 359 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 360 cfg->hdrtype &= ~PCIM_MFDEV; 361 362 pci_fixancient(cfg); 363 pci_hdrtypedata(cfg); 364 365 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 366 367 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 368 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 369 devlist_entry->conf.pc_sel.pc_func = cfg->func; 370 devlist_entry->conf.pc_hdr = cfg->hdrtype; 371 372 devlist_entry->conf.pc_subvendor = cfg->subvendor; 373 devlist_entry->conf.pc_subdevice = cfg->subdevice; 374 devlist_entry->conf.pc_vendor = cfg->vendor; 375 devlist_entry->conf.pc_device = cfg->device; 376 377 devlist_entry->conf.pc_class = cfg->baseclass; 378 devlist_entry->conf.pc_subclass = cfg->subclass; 379 devlist_entry->conf.pc_progif = cfg->progif; 380 devlist_entry->conf.pc_revid = cfg->revid; 381 382 pci_numdevs++; 383 pci_generation++; 384 } 385 return (devlist_entry); 386} 387 388#if 0 389/* free pcicfgregs structure and all depending data structures */ 390 391static int 392pci_freecfg(struct pci_devinfo *dinfo) 393{ 394 struct devlist *devlist_head; 395 396 devlist_head = &pci_devq; 397 398 if (dinfo->cfg.hdrspec != NULL) 399 free(dinfo->cfg.hdrspec, M_DEVBUF); 400 if (dinfo->cfg.map != NULL) 401 free(dinfo->cfg.map, M_DEVBUF); 402 /* XXX this hasn't been tested */ 403 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 404 free(dinfo, M_DEVBUF); 405 406 /* increment the generation count */ 407 pci_generation++; 408 409 /* we're losing one device */ 410 pci_numdevs--; 411 return (0); 412} 413#endif 414 415 416/* 417 * This is the user interface to PCI configuration space. 418 */ 419 420static int 421pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 422{ 423 if ((oflags & FWRITE) && securelevel > 0) { 424 return EPERM; 425 } 426 return 0; 427} 428 429static int 430pci_close(dev_t dev, int flag, int devtype, struct proc *p) 431{ 432 return 0; 433} 434 435/* 436 * Match a single pci_conf structure against an array of pci_match_conf 437 * structures. The first argument, 'matches', is an array of num_matches 438 * pci_match_conf structures. match_buf is a pointer to the pci_conf 439 * structure that will be compared to every entry in the matches array. 440 * This function returns 1 on failure, 0 on success. 441 */ 442static int 443pci_conf_match(struct pci_match_conf *matches, int num_matches, 444 struct pci_conf *match_buf) 445{ 446 int i; 447 448 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 449 return(1); 450 451 for (i = 0; i < num_matches; i++) { 452 /* 453 * I'm not sure why someone would do this...but... 454 */ 455 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 456 continue; 457 458 /* 459 * Look at each of the match flags. If it's set, do the 460 * comparison. If the comparison fails, we don't have a 461 * match, go on to the next item if there is one. 462 */ 463 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 464 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 465 continue; 466 467 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 468 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 469 continue; 470 471 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 472 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 473 continue; 474 475 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 476 && (match_buf->pc_vendor != matches[i].pc_vendor)) 477 continue; 478 479 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 480 && (match_buf->pc_device != matches[i].pc_device)) 481 continue; 482 483 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 484 && (match_buf->pc_class != matches[i].pc_class)) 485 continue; 486 487 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 488 && (match_buf->pd_unit != matches[i].pd_unit)) 489 continue; 490 491 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 492 && (strncmp(matches[i].pd_name, match_buf->pd_name, 493 sizeof(match_buf->pd_name)) != 0)) 494 continue; 495 496 return(0); 497 } 498 499 return(1); 500} 501 502/* 503 * Locate the parent of a PCI device by scanning the PCI devlist 504 * and return the entry for the parent. 505 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 506 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 507 */ 508 509pcicfgregs * 510pci_devlist_get_parent(pcicfgregs *cfg) 511{ 512 struct devlist *devlist_head; 513 struct pci_devinfo *dinfo; 514 pcicfgregs *bridge_cfg; 515 int i; 516 517 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 518 519 /* If the device is on PCI bus 0, look for the host */ 520 if (cfg->bus == 0) { 521 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 522 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 523 bridge_cfg = &dinfo->cfg; 524 if (bridge_cfg->baseclass == PCIC_BRIDGE 525 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 526 && bridge_cfg->bus == cfg->bus) { 527 return bridge_cfg; 528 } 529 } 530 } 531 532 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 533 if (cfg->bus > 0) { 534 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 535 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 536 bridge_cfg = &dinfo->cfg; 537 if (bridge_cfg->baseclass == PCIC_BRIDGE 538 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 539 && bridge_cfg->secondarybus == cfg->bus) { 540 return bridge_cfg; 541 } 542 } 543 } 544 545 return NULL; 546} 547 548static int 549pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 550{ 551 struct pci_io *io; 552 const char *name; 553 int error; 554 555 if (!(flag & FWRITE)) 556 return EPERM; 557 558 559 switch(cmd) { 560 case PCIOCGETCONF: 561 { 562 struct pci_devinfo *dinfo; 563 struct pci_conf_io *cio; 564 struct devlist *devlist_head; 565 struct pci_match_conf *pattern_buf; 566 int num_patterns; 567 size_t iolen; 568 int ionum, i; 569 570 cio = (struct pci_conf_io *)data; 571 572 num_patterns = 0; 573 dinfo = NULL; 574 575 /* 576 * Hopefully the user won't pass in a null pointer, but it 577 * can't hurt to check. 578 */ 579 if (cio == NULL) { 580 error = EINVAL; 581 break; 582 } 583 584 /* 585 * If the user specified an offset into the device list, 586 * but the list has changed since they last called this 587 * ioctl, tell them that the list has changed. They will 588 * have to get the list from the beginning. 589 */ 590 if ((cio->offset != 0) 591 && (cio->generation != pci_generation)){ 592 cio->num_matches = 0; 593 cio->status = PCI_GETCONF_LIST_CHANGED; 594 error = 0; 595 break; 596 } 597 598 /* 599 * Check to see whether the user has asked for an offset 600 * past the end of our list. 601 */ 602 if (cio->offset >= pci_numdevs) { 603 cio->num_matches = 0; 604 cio->status = PCI_GETCONF_LAST_DEVICE; 605 error = 0; 606 break; 607 } 608 609 /* get the head of the device queue */ 610 devlist_head = &pci_devq; 611 612 /* 613 * Determine how much room we have for pci_conf structures. 614 * Round the user's buffer size down to the nearest 615 * multiple of sizeof(struct pci_conf) in case the user 616 * didn't specify a multiple of that size. 617 */ 618 iolen = min(cio->match_buf_len - 619 (cio->match_buf_len % sizeof(struct pci_conf)), 620 pci_numdevs * sizeof(struct pci_conf)); 621 622 /* 623 * Since we know that iolen is a multiple of the size of 624 * the pciconf union, it's okay to do this. 625 */ 626 ionum = iolen / sizeof(struct pci_conf); 627 628 /* 629 * If this test is true, the user wants the pci_conf 630 * structures returned to match the supplied entries. 631 */ 632 if ((cio->num_patterns > 0) 633 && (cio->pat_buf_len > 0)) { 634 /* 635 * pat_buf_len needs to be: 636 * num_patterns * sizeof(struct pci_match_conf) 637 * While it is certainly possible the user just 638 * allocated a large buffer, but set the number of 639 * matches correctly, it is far more likely that 640 * their kernel doesn't match the userland utility 641 * they're using. It's also possible that the user 642 * forgot to initialize some variables. Yes, this 643 * may be overly picky, but I hazard to guess that 644 * it's far more likely to just catch folks that 645 * updated their kernel but not their userland. 646 */ 647 if ((cio->num_patterns * 648 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 649 /* The user made a mistake, return an error*/ 650 cio->status = PCI_GETCONF_ERROR; 651 printf("pci_ioctl: pat_buf_len %d != " 652 "num_patterns (%d) * sizeof(struct " 653 "pci_match_conf) (%d)\npci_ioctl: " 654 "pat_buf_len should be = %d\n", 655 cio->pat_buf_len, cio->num_patterns, 656 (int)sizeof(struct pci_match_conf), 657 (int)sizeof(struct pci_match_conf) * 658 cio->num_patterns); 659 printf("pci_ioctl: do your headers match your " 660 "kernel?\n"); 661 cio->num_matches = 0; 662 error = EINVAL; 663 break; 664 } 665 666 /* 667 * Check the user's buffer to make sure it's readable. 668 */ 669 if (!useracc((caddr_t)cio->patterns, 670 cio->pat_buf_len, VM_PROT_READ)) { 671 printf("pci_ioctl: pattern buffer %p, " 672 "length %u isn't user accessible for" 673 " READ\n", cio->patterns, 674 cio->pat_buf_len); 675 error = EACCES; 676 break; 677 } 678 /* 679 * Allocate a buffer to hold the patterns. 680 */ 681 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 682 M_WAITOK); 683 error = copyin(cio->patterns, pattern_buf, 684 cio->pat_buf_len); 685 if (error != 0) 686 break; 687 num_patterns = cio->num_patterns; 688 689 } else if ((cio->num_patterns > 0) 690 || (cio->pat_buf_len > 0)) { 691 /* 692 * The user made a mistake, spit out an error. 693 */ 694 cio->status = PCI_GETCONF_ERROR; 695 cio->num_matches = 0; 696 printf("pci_ioctl: invalid GETCONF arguments\n"); 697 error = EINVAL; 698 break; 699 } else 700 pattern_buf = NULL; 701 702 /* 703 * Make sure we can write to the match buffer. 704 */ 705 if (!useracc((caddr_t)cio->matches, 706 cio->match_buf_len, VM_PROT_WRITE)) { 707 printf("pci_ioctl: match buffer %p, length %u " 708 "isn't user accessible for WRITE\n", 709 cio->matches, cio->match_buf_len); 710 error = EACCES; 711 break; 712 } 713 714 /* 715 * Go through the list of devices and copy out the devices 716 * that match the user's criteria. 717 */ 718 for (cio->num_matches = 0, error = 0, i = 0, 719 dinfo = STAILQ_FIRST(devlist_head); 720 (dinfo != NULL) && (cio->num_matches < ionum) 721 && (error == 0) && (i < pci_numdevs); 722 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 723 724 if (i < cio->offset) 725 continue; 726 727 /* Populate pd_name and pd_unit */ 728 name = NULL; 729 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 730 name = device_get_name(dinfo->cfg.dev); 731 if (name) { 732 strncpy(dinfo->conf.pd_name, name, 733 sizeof(dinfo->conf.pd_name)); 734 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 735 dinfo->conf.pd_unit = 736 device_get_unit(dinfo->cfg.dev); 737 } 738 739 if ((pattern_buf == NULL) || 740 (pci_conf_match(pattern_buf, num_patterns, 741 &dinfo->conf) == 0)) { 742 743 /* 744 * If we've filled up the user's buffer, 745 * break out at this point. Since we've 746 * got a match here, we'll pick right back 747 * up at the matching entry. We can also 748 * tell the user that there are more matches 749 * left. 750 */ 751 if (cio->num_matches >= ionum) 752 break; 753 754 error = copyout(&dinfo->conf, 755 &cio->matches[cio->num_matches], 756 sizeof(struct pci_conf)); 757 cio->num_matches++; 758 } 759 } 760 761 /* 762 * Set the pointer into the list, so if the user is getting 763 * n records at a time, where n < pci_numdevs, 764 */ 765 cio->offset = i; 766 767 /* 768 * Set the generation, the user will need this if they make 769 * another ioctl call with offset != 0. 770 */ 771 cio->generation = pci_generation; 772 773 /* 774 * If this is the last device, inform the user so he won't 775 * bother asking for more devices. If dinfo isn't NULL, we 776 * know that there are more matches in the list because of 777 * the way the traversal is done. 778 */ 779 if (dinfo == NULL) 780 cio->status = PCI_GETCONF_LAST_DEVICE; 781 else 782 cio->status = PCI_GETCONF_MORE_DEVS; 783 784 if (pattern_buf != NULL) 785 free(pattern_buf, M_TEMP); 786 787 break; 788 } 789 case PCIOCREAD: 790 io = (struct pci_io *)data; 791 switch(io->pi_width) { 792 pcicfgregs probe; 793 case 4: 794 case 2: 795 case 1: 796 probe.hose = -1; 797 probe.bus = io->pi_sel.pc_bus; 798 probe.slot = io->pi_sel.pc_dev; 799 probe.func = io->pi_sel.pc_func; 800 io->pi_data = pci_cfgread(&probe, 801 io->pi_reg, io->pi_width); 802 error = 0; 803 break; 804 default: 805 error = ENODEV; 806 break; 807 } 808 break; 809 810 case PCIOCWRITE: 811 io = (struct pci_io *)data; 812 switch(io->pi_width) { 813 pcicfgregs probe; 814 case 4: 815 case 2: 816 case 1: 817 probe.hose = -1; 818 probe.bus = io->pi_sel.pc_bus; 819 probe.slot = io->pi_sel.pc_dev; 820 probe.func = io->pi_sel.pc_func; 821 pci_cfgwrite(&probe, 822 io->pi_reg, io->pi_data, io->pi_width); 823 error = 0; 824 break; 825 default: 826 error = ENODEV; 827 break; 828 } 829 break; 830 831 default: 832 error = ENOTTY; 833 break; 834 } 835 836 return (error); 837} 838 839#define PCI_CDEV 78 840 841static struct cdevsw pcicdev = { 842 /* open */ pci_open, 843 /* close */ pci_close, 844 /* read */ noread, 845 /* write */ nowrite, 846 /* ioctl */ pci_ioctl, 847 /* poll */ nopoll, 848 /* mmap */ nommap, 849 /* strategy */ nostrategy, 850 /* name */ "pci", 851 /* maj */ PCI_CDEV, 852 /* dump */ nodump, 853 /* psize */ nopsize, 854 /* flags */ 0, 855 /* bmaj */ -1 856}; 857 858#include "pci_if.h" 859 860/* 861 * A simple driver to wrap the old pci driver mechanism for back-compat. 862 */ 863 864static int 865pci_compat_probe(device_t dev) 866{ 867 struct pci_device *dvp; 868 struct pci_devinfo *dinfo; 869 pcicfgregs *cfg; 870 const char *name; 871 int error; 872 873 dinfo = device_get_ivars(dev); 874 cfg = &dinfo->cfg; 875 dvp = device_get_driver(dev)->priv; 876 877 /* 878 * Do the wrapped probe. 879 */ 880 error = ENXIO; 881 if (dvp && dvp->pd_probe) { 882 name = dvp->pd_probe(cfg, (cfg->device << 16) + cfg->vendor); 883 if (name) { 884 device_set_desc_copy(dev, name); 885 /* Allow newbus drivers to match "better" */ 886 error = -200; 887 } 888 } 889 890 return error; 891} 892 893static int 894pci_compat_attach(device_t dev) 895{ 896 struct pci_device *dvp; 897 struct pci_devinfo *dinfo; 898 pcicfgregs *cfg; 899 int unit; 900 901 dinfo = device_get_ivars(dev); 902 cfg = &dinfo->cfg; 903 dvp = device_get_driver(dev)->priv; 904 905 unit = device_get_unit(dev); 906 if (unit > *dvp->pd_count) 907 *dvp->pd_count = unit; 908 if (dvp->pd_attach) 909 dvp->pd_attach(cfg, unit); 910 device_printf(dev, "driver is using old-style compatability shims\n"); 911 return 0; 912} 913 914static device_method_t pci_compat_methods[] = { 915 /* Device interface */ 916 DEVMETHOD(device_probe, pci_compat_probe), 917 DEVMETHOD(device_attach, pci_compat_attach), 918 919 { 0, 0 } 920}; 921 922static devclass_t pci_devclass; 923 924/* 925 * Create a new style driver around each old pci driver. 926 */ 927int 928compat_pci_handler(module_t mod, int type, void *data) 929{ 930 struct pci_device *dvp = (struct pci_device *)data; 931 driver_t *driver; 932 933 switch (type) { 934 case MOD_LOAD: 935 driver = malloc(sizeof(driver_t), M_DEVBUF, M_NOWAIT); 936 if (!driver) 937 return ENOMEM; 938 bzero(driver, sizeof(driver_t)); 939 driver->name = dvp->pd_name; 940 driver->methods = pci_compat_methods; 941 driver->softc = sizeof(struct pci_devinfo *); 942 driver->priv = dvp; 943 devclass_add_driver(pci_devclass, driver); 944 break; 945 case MOD_UNLOAD: 946 printf("%s: module unload not supported!\n", dvp->pd_name); 947 return EOPNOTSUPP; 948 default: 949 break; 950 } 951 return 0; 952} 953 954/* 955 * New style pci driver. Parent device is either a pci-host-bridge or a 956 * pci-pci-bridge. Both kinds are represented by instances of pcib. 957 */ 958 959static void 960pci_print_verbose(struct pci_devinfo *dinfo) 961{ 962 if (bootverbose) { 963 pcicfgregs *cfg = &dinfo->cfg; 964 965 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 966 cfg->vendor, cfg->device, cfg->revid); 967 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 968 cfg->baseclass, cfg->subclass, cfg->progif, 969 cfg->hdrtype, cfg->mfdev); 970 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 971 cfg->subordinatebus, cfg->secondarybus); 972#ifdef PCI_DEBUG 973 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 974 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 975 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 976 cfg->lattimer, cfg->lattimer * 30, 977 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 978#endif /* PCI_DEBUG */ 979 if (cfg->intpin > 0) 980 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 981 } 982} 983 984static int 985pci_porten(pcicfgregs *cfg) 986{ 987 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0); 988} 989 990static int 991pci_memen(pcicfgregs *cfg) 992{ 993 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0); 994} 995 996/* 997 * Add a resource based on a pci map register. Return 1 if the map 998 * register is a 32bit map register or 2 if it is a 64bit register. 999 */ 1000static int 1001pci_add_map(device_t dev, pcicfgregs* cfg, int reg) 1002{ 1003 struct pci_devinfo *dinfo = device_get_ivars(dev); 1004 struct resource_list *rl = &dinfo->resources; 1005 u_int32_t map; 1006 u_int64_t base; 1007 u_int8_t ln2size; 1008 u_int8_t ln2range; 1009 u_int32_t testval; 1010 1011 int type; 1012 1013 map = pci_cfgread(cfg, reg, 4); 1014 1015 if (map == 0 || map == 0xffffffff) 1016 return 1; /* skip invalid entry */ 1017 1018 pci_cfgwrite(cfg, reg, 0xffffffff, 4); 1019 testval = pci_cfgread(cfg, reg, 4); 1020 pci_cfgwrite(cfg, reg, map, 4); 1021 1022 base = pci_mapbase(map); 1023 if (pci_maptype(map) & PCI_MAPMEM) 1024 type = SYS_RES_MEMORY; 1025 else 1026 type = SYS_RES_IOPORT; 1027 ln2size = pci_mapsize(testval); 1028 ln2range = pci_maprange(testval); 1029 if (ln2range == 64) { 1030 /* Read the other half of a 64bit map register */ 1031 base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32; 1032 } 1033 1034#ifdef __alpha__ 1035 /* 1036 * XXX: encode hose number in the base addr, 1037 * This will go away once the bus_space functions 1038 * can deal with multiple hoses 1039 */ 1040 1041 if (cfg->hose) { 1042 u_int32_t mask, shift, maxh; 1043 1044 switch (hwrpb->rpb_type) { 1045 case ST_DEC_21000: 1046 case ST_DEC_4100: 1047 mask = 0xf8000000; 1048 shift = 27; 1049 maxh = 32; 1050 break; 1051 case ST_DEC_6600: 1052 mask = 0x80000000; 1053 shift = 31; 1054 maxh = 2; 1055 break; 1056 default: 1057 mask = 0; 1058 shift = 0; 1059 maxh = 0; 1060 break; 1061 } 1062 if (base & mask) { 1063 printf("base addr = 0x%llx\n", (long long) base); 1064 printf("mask addr = 0x%lx\n", (long) mask); 1065 printf("hacked addr = 0x%llx\n", (long long) 1066 (base | ((u_int64_t)cfg->hose << shift))); 1067 panic("hose encoding hack would clobber base addr"); 1068 /* NOTREACHED */ 1069 } 1070 if (cfg->hose >= maxh) { 1071 panic("Hose %d - can only encode %d hose(s)", 1072 cfg->hose, maxh); 1073 /* NOTREACHED */ 1074 } 1075 base |= ((u_int64_t)cfg->hose << shift); 1076 } 1077#endif 1078 if (type == SYS_RES_IOPORT && !pci_porten(cfg)) 1079 return 1; 1080 if (type == SYS_RES_MEMORY && !pci_memen(cfg)) 1081 return 1; 1082 1083 resource_list_add(rl, type, reg, 1084 base, base + (1 << ln2size) - 1, 1085 (1 << ln2size)); 1086 1087 if (bootverbose) { 1088 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n", 1089 reg, pci_maptype(base), ln2range, 1090 (unsigned int) base, ln2size); 1091 } 1092 1093 return (ln2range == 64) ? 2 : 1; 1094} 1095 1096static void 1097pci_add_resources(device_t dev, pcicfgregs* cfg) 1098{ 1099 struct pci_devinfo *dinfo = device_get_ivars(dev); 1100 struct resource_list *rl = &dinfo->resources; 1101 struct pci_quirk *q; 1102 int i; 1103 1104 for (i = 0; i < cfg->nummaps;) { 1105 i += pci_add_map(dev, cfg, PCIR_MAPS + i*4); 1106 } 1107 1108 for (q = &pci_quirks[0]; q->devid; q++) { 1109 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1110 && q->type == PCI_QUIRK_MAP_REG) 1111 pci_add_map(dev, cfg, q->arg1); 1112 } 1113 1114 if (cfg->intpin > 0 && cfg->intline != 255) 1115 resource_list_add(rl, SYS_RES_IRQ, 0, 1116 cfg->intline, cfg->intline, 1); 1117} 1118 1119static void 1120pci_add_children(device_t dev, int busno) 1121{ 1122 pcicfgregs probe; 1123 1124#ifdef SIMOS 1125#undef PCI_SLOTMAX 1126#define PCI_SLOTMAX 0 1127#endif 1128 1129 bzero(&probe, sizeof probe); 1130#ifdef __alpha__ 1131 probe.hose = pcib_get_hose(dev); 1132#endif 1133#ifdef __i386__ 1134 probe.hose = 0; 1135#endif 1136 probe.bus = busno; 1137 1138 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) { 1139 int pcifunchigh = 0; 1140 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) { 1141 struct pci_devinfo *dinfo = pci_readcfg(&probe); 1142 if (dinfo != NULL) { 1143 if (dinfo->cfg.mfdev) 1144 pcifunchigh = 7; 1145 1146 pci_print_verbose(dinfo); 1147 dinfo->cfg.dev = device_add_child(dev, NULL, -1); 1148 device_set_ivars(dinfo->cfg.dev, dinfo); 1149 pci_add_resources(dinfo->cfg.dev, &dinfo->cfg); 1150 } 1151 } 1152 } 1153} 1154 1155static int 1156pci_new_probe(device_t dev) 1157{ 1158 static int once; 1159 1160 device_set_desc(dev, "PCI bus"); 1161 pci_add_children(dev, device_get_unit(dev)); 1162 if (!once) { 1163 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 1164 once++; 1165 } 1166 1167 return 0; 1168} 1169 1170static int 1171pci_print_resources(struct resource_list *rl, const char *name, int type, 1172 const char *format) 1173{ 1174 struct resource_list_entry *rle; 1175 int printed, retval; 1176 1177 printed = 0; 1178 retval = 0; 1179 /* Yes, this is kinda cheating */ 1180 SLIST_FOREACH(rle, rl, link) { 1181 if (rle->type == type) { 1182 if (printed == 0) 1183 retval += printf(" %s ", name); 1184 else if (printed > 0) 1185 retval += printf(","); 1186 printed++; 1187 retval += printf(format, rle->start); 1188 if (rle->count > 1) { 1189 retval += printf("-"); 1190 retval += printf(format, rle->start + 1191 rle->count - 1); 1192 } 1193 } 1194 } 1195 return retval; 1196} 1197 1198static int 1199pci_print_child(device_t dev, device_t child) 1200{ 1201 struct pci_devinfo *dinfo; 1202 struct resource_list *rl; 1203 pcicfgregs *cfg; 1204 int retval = 0; 1205 1206 dinfo = device_get_ivars(child); 1207 cfg = &dinfo->cfg; 1208 rl = &dinfo->resources; 1209 1210 retval += bus_print_child_header(dev, child); 1211 1212 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1213 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1214 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1215 if (device_get_flags(dev)) 1216 retval += printf(" flags %#x", device_get_flags(dev)); 1217 1218 retval += printf(" at device %d.%d", pci_get_slot(child), 1219 pci_get_function(child)); 1220 1221 retval += bus_print_child_footer(dev, child); 1222 1223 return (retval); 1224} 1225 1226static void 1227pci_probe_nomatch(device_t dev, device_t child) 1228{ 1229 struct pci_devinfo *dinfo; 1230 pcicfgregs *cfg; 1231 const char *desc; 1232 int unknown; 1233 1234 unknown = 0; 1235 dinfo = device_get_ivars(child); 1236 cfg = &dinfo->cfg; 1237 desc = pci_ata_match(child); 1238 if (!desc) desc = pci_usb_match(child); 1239 if (!desc) desc = pci_vga_match(child); 1240 if (!desc) { 1241 desc = "unknown card"; 1242 unknown++; 1243 } 1244 device_printf(dev, "<%s>", desc); 1245 if (bootverbose || unknown) { 1246 printf(" (vendor=0x%04x, dev=0x%04x)", 1247 cfg->vendor, 1248 cfg->device); 1249 } 1250 printf(" at %d.%d", 1251 pci_get_slot(child), 1252 pci_get_function(child)); 1253 if (cfg->intpin > 0 && cfg->intline != 255) { 1254 printf(" irq %d", cfg->intline); 1255 } 1256 printf("\n"); 1257 1258 return; 1259} 1260 1261static int 1262pci_read_ivar(device_t dev, device_t child, int which, u_long *result) 1263{ 1264 struct pci_devinfo *dinfo; 1265 pcicfgregs *cfg; 1266 1267 dinfo = device_get_ivars(child); 1268 cfg = &dinfo->cfg; 1269 1270 switch (which) { 1271 case PCI_IVAR_SUBVENDOR: 1272 *result = cfg->subvendor; 1273 break; 1274 case PCI_IVAR_SUBDEVICE: 1275 *result = cfg->subdevice; 1276 break; 1277 case PCI_IVAR_VENDOR: 1278 *result = cfg->vendor; 1279 break; 1280 case PCI_IVAR_DEVICE: 1281 *result = cfg->device; 1282 break; 1283 case PCI_IVAR_DEVID: 1284 *result = (cfg->device << 16) | cfg->vendor; 1285 break; 1286 case PCI_IVAR_CLASS: 1287 *result = cfg->baseclass; 1288 break; 1289 case PCI_IVAR_SUBCLASS: 1290 *result = cfg->subclass; 1291 break; 1292 case PCI_IVAR_PROGIF: 1293 *result = cfg->progif; 1294 break; 1295 case PCI_IVAR_REVID: 1296 *result = cfg->revid; 1297 break; 1298 case PCI_IVAR_INTPIN: 1299 *result = cfg->intpin; 1300 break; 1301 case PCI_IVAR_IRQ: 1302 *result = cfg->intline; 1303 break; 1304 case PCI_IVAR_BUS: 1305 *result = cfg->bus; 1306 break; 1307 case PCI_IVAR_SLOT: 1308 *result = cfg->slot; 1309 break; 1310 case PCI_IVAR_FUNCTION: 1311 *result = cfg->func; 1312 break; 1313 case PCI_IVAR_SECONDARYBUS: 1314 *result = cfg->secondarybus; 1315 break; 1316 case PCI_IVAR_SUBORDINATEBUS: 1317 *result = cfg->subordinatebus; 1318 break; 1319 case PCI_IVAR_HOSE: 1320 /* 1321 * Pass up to parent bridge. 1322 */ 1323 *result = pcib_get_hose(dev); 1324 break; 1325 default: 1326 return ENOENT; 1327 } 1328 return 0; 1329} 1330 1331static int 1332pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1333{ 1334 struct pci_devinfo *dinfo; 1335 pcicfgregs *cfg; 1336 1337 dinfo = device_get_ivars(child); 1338 cfg = &dinfo->cfg; 1339 1340 switch (which) { 1341 case PCI_IVAR_SUBVENDOR: 1342 case PCI_IVAR_SUBDEVICE: 1343 case PCI_IVAR_VENDOR: 1344 case PCI_IVAR_DEVICE: 1345 case PCI_IVAR_DEVID: 1346 case PCI_IVAR_CLASS: 1347 case PCI_IVAR_SUBCLASS: 1348 case PCI_IVAR_PROGIF: 1349 case PCI_IVAR_REVID: 1350 case PCI_IVAR_INTPIN: 1351 case PCI_IVAR_IRQ: 1352 case PCI_IVAR_BUS: 1353 case PCI_IVAR_SLOT: 1354 case PCI_IVAR_FUNCTION: 1355 return EINVAL; /* disallow for now */ 1356 1357 case PCI_IVAR_SECONDARYBUS: 1358 cfg->secondarybus = value; 1359 break; 1360 case PCI_IVAR_SUBORDINATEBUS: 1361 cfg->subordinatebus = value; 1362 break; 1363 default: 1364 return ENOENT; 1365 } 1366 return 0; 1367} 1368 1369static struct resource * 1370pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1371 u_long start, u_long end, u_long count, u_int flags) 1372{ 1373 struct pci_devinfo *dinfo = device_get_ivars(child); 1374 struct resource_list *rl = &dinfo->resources; 1375 1376 return resource_list_alloc(rl, dev, child, type, rid, 1377 start, end, count, flags); 1378} 1379 1380static int 1381pci_release_resource(device_t dev, device_t child, int type, int rid, 1382 struct resource *r) 1383{ 1384 struct pci_devinfo *dinfo = device_get_ivars(child); 1385 struct resource_list *rl = &dinfo->resources; 1386 1387 return resource_list_release(rl, dev, child, type, rid, r); 1388} 1389 1390static int 1391pci_set_resource(device_t dev, device_t child, int type, int rid, 1392 u_long start, u_long count) 1393{ 1394 struct pci_devinfo *dinfo = device_get_ivars(child); 1395 struct resource_list *rl = &dinfo->resources; 1396 1397 resource_list_add(rl, type, rid, start, start + count - 1, count); 1398 return 0; 1399} 1400 1401static int 1402pci_get_resource(device_t dev, device_t child, int type, int rid, 1403 u_long *startp, u_long *countp) 1404{ 1405 struct pci_devinfo *dinfo = device_get_ivars(child); 1406 struct resource_list *rl = &dinfo->resources; 1407 struct resource_list_entry *rle; 1408 1409 rle = resource_list_find(rl, type, rid); 1410 if (!rle) 1411 return ENOENT; 1412 1413 if (startp) 1414 *startp = rle->start; 1415 if (countp) 1416 *countp = rle->count; 1417 1418 return 0; 1419} 1420 1421static void 1422pci_delete_resource(device_t dev, device_t child, int type, int rid) 1423{ 1424 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1425} 1426 1427static u_int32_t 1428pci_read_config_method(device_t dev, device_t child, int reg, int width) 1429{ 1430 struct pci_devinfo *dinfo = device_get_ivars(child); 1431 pcicfgregs *cfg = &dinfo->cfg; 1432 return pci_cfgread(cfg, reg, width); 1433} 1434 1435static void 1436pci_write_config_method(device_t dev, device_t child, int reg, 1437 u_int32_t val, int width) 1438{ 1439 struct pci_devinfo *dinfo = device_get_ivars(child); 1440 pcicfgregs *cfg = &dinfo->cfg; 1441 pci_cfgwrite(cfg, reg, val, width); 1442} 1443 1444static int 1445pci_modevent(module_t mod, int what, void *arg) 1446{ 1447 switch (what) { 1448 case MOD_LOAD: 1449 STAILQ_INIT(&pci_devq); 1450 break; 1451 1452 case MOD_UNLOAD: 1453 break; 1454 } 1455 1456 return 0; 1457} 1458 1459static device_method_t pci_methods[] = { 1460 /* Device interface */ 1461 DEVMETHOD(device_probe, pci_new_probe), 1462 DEVMETHOD(device_attach, bus_generic_attach), 1463 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1464 DEVMETHOD(device_suspend, bus_generic_suspend), 1465 DEVMETHOD(device_resume, bus_generic_resume), 1466 1467 /* Bus interface */ 1468 DEVMETHOD(bus_print_child, pci_print_child), 1469 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 1470 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1471 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1472 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1473 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1474 DEVMETHOD(bus_release_resource, pci_release_resource), 1475 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1476 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1477 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1478 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1479 DEVMETHOD(bus_set_resource, pci_set_resource), 1480 DEVMETHOD(bus_get_resource, pci_get_resource), 1481 DEVMETHOD(bus_delete_resource, pci_delete_resource), 1482 1483 /* PCI interface */ 1484 DEVMETHOD(pci_read_config, pci_read_config_method), 1485 DEVMETHOD(pci_write_config, pci_write_config_method), 1486 1487 { 0, 0 } 1488}; 1489 1490static driver_t pci_driver = { 1491 "pci", 1492 pci_methods, 1493 1, /* no softc */ 1494}; 1495 1496DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1497