pci.c revision 52243
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pci.c 52243 1999-10-14 21:38:33Z dfr $ 27 * 28 */ 29 30#include "opt_bus.h" 31 32#include "opt_simos.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/fcntl.h> 39#include <sys/conf.h> 40#include <sys/kernel.h> 41#include <sys/queue.h> 42#include <sys/types.h> 43#include <sys/buf.h> 44 45#include <vm/vm.h> 46#include <vm/pmap.h> 47#include <vm/vm_extern.h> 48 49#include <sys/bus.h> 50#include <machine/bus.h> 51#include <sys/rman.h> 52#include <machine/resource.h> 53#include <machine/md_var.h> /* For the Alpha */ 54 55#include <pci/pcireg.h> 56#include <pci/pcivar.h> 57#include <pci/pci_ioctl.h> 58 59#ifdef APIC_IO 60#include <machine/smp.h> 61#endif /* APIC_IO */ 62 63/* map register information */ 64#define PCI_MAPMEM 0x01 /* memory map */ 65#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 66#define PCI_MAPPORT 0x04 /* port map */ 67 68struct pci_devinfo { 69 STAILQ_ENTRY(pci_devinfo) pci_links; 70 struct resource_list resources; 71 pcicfgregs cfg; 72 struct pci_conf conf; 73}; 74 75static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 76u_int32_t pci_numdevs = 0; 77static u_int32_t pci_generation = 0; 78 79/* return base address of memory or port map */ 80 81static u_int32_t 82pci_mapbase(unsigned mapreg) 83{ 84 int mask = 0x03; 85 if ((mapreg & 0x01) == 0) 86 mask = 0x0f; 87 return (mapreg & ~mask); 88} 89 90/* return map type of memory or port map */ 91 92static int 93pci_maptype(unsigned mapreg) 94{ 95 static u_int8_t maptype[0x10] = { 96 PCI_MAPMEM, PCI_MAPPORT, 97 PCI_MAPMEM, 0, 98 PCI_MAPMEM, PCI_MAPPORT, 99 0, 0, 100 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 101 PCI_MAPMEM|PCI_MAPMEMP, 0, 102 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 103 0, 0, 104 }; 105 106 return maptype[mapreg & 0x0f]; 107} 108 109/* return log2 of map size decoded for memory or port map */ 110 111static int 112pci_mapsize(unsigned testval) 113{ 114 int ln2size; 115 116 testval = pci_mapbase(testval); 117 ln2size = 0; 118 if (testval != 0) { 119 while ((testval & 1) == 0) 120 { 121 ln2size++; 122 testval >>= 1; 123 } 124 } 125 return (ln2size); 126} 127 128/* return log2 of address range supported by map register */ 129 130static int 131pci_maprange(unsigned mapreg) 132{ 133 int ln2range = 0; 134 switch (mapreg & 0x07) { 135 case 0x00: 136 case 0x01: 137 case 0x05: 138 ln2range = 32; 139 break; 140 case 0x02: 141 ln2range = 20; 142 break; 143 case 0x04: 144 ln2range = 64; 145 break; 146 } 147 return (ln2range); 148} 149 150/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 151 152static void 153pci_fixancient(pcicfgregs *cfg) 154{ 155 if (cfg->hdrtype != 0) 156 return; 157 158 /* PCI to PCI bridges use header type 1 */ 159 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 160 cfg->hdrtype = 1; 161} 162 163/* read config data specific to header type 1 device (PCI to PCI bridge) */ 164 165static void * 166pci_readppb(pcicfgregs *cfg) 167{ 168 pcih1cfgregs *p; 169 170 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK); 171 if (p == NULL) 172 return (NULL); 173 174 bzero(p, sizeof *p); 175 176 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2); 177 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2); 178 179 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1); 180 181 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2), 182 pci_cfgread(cfg, PCIR_IOBASEL_1, 1)); 183 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2), 184 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1)); 185 186 p->membase = PCI_PPBMEMBASE (0, 187 pci_cfgread(cfg, PCIR_MEMBASE_1, 2)); 188 p->memlimit = PCI_PPBMEMLIMIT (0, 189 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2)); 190 191 p->pmembase = PCI_PPBMEMBASE ( 192 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4), 193 pci_cfgread(cfg, PCIR_PMBASEL_1, 2)); 194 195 p->pmemlimit = PCI_PPBMEMLIMIT ( 196 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4), 197 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2)); 198 return (p); 199} 200 201/* read config data specific to header type 2 device (PCI to CardBus bridge) */ 202 203static void * 204pci_readpcb(pcicfgregs *cfg) 205{ 206 pcih2cfgregs *p; 207 208 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK); 209 if (p == NULL) 210 return (NULL); 211 212 bzero(p, sizeof *p); 213 214 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2); 215 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2); 216 217 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1); 218 219 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4); 220 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4); 221 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4); 222 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4); 223 224 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4); 225 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4); 226 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4); 227 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4); 228 229 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4); 230 return p; 231} 232 233/* extract header type specific config data */ 234 235static void 236pci_hdrtypedata(pcicfgregs *cfg) 237{ 238 switch (cfg->hdrtype) { 239 case 0: 240 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2); 241 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2); 242 cfg->nummaps = PCI_MAXMAPS_0; 243 break; 244 case 1: 245 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2); 246 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2); 247 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1); 248 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1); 249 cfg->nummaps = PCI_MAXMAPS_1; 250 cfg->hdrspec = pci_readppb(cfg); 251 break; 252 case 2: 253 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2); 254 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2); 255 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1); 256 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1); 257 cfg->nummaps = PCI_MAXMAPS_2; 258 cfg->hdrspec = pci_readpcb(cfg); 259 break; 260 } 261} 262 263/* read configuration header into pcicfgrect structure */ 264 265static struct pci_devinfo * 266pci_readcfg(pcicfgregs *probe) 267{ 268 pcicfgregs *cfg = NULL; 269 struct pci_devinfo *devlist_entry; 270 struct devlist *devlist_head; 271 272 devlist_head = &pci_devq; 273 274 devlist_entry = NULL; 275 276 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) { 277 278 devlist_entry = malloc(sizeof(struct pci_devinfo), 279 M_DEVBUF, M_WAITOK); 280 if (devlist_entry == NULL) 281 return (NULL); 282 bzero(devlist_entry, sizeof *devlist_entry); 283 284 cfg = &devlist_entry->cfg; 285 286 cfg->hose = probe->hose; 287 cfg->bus = probe->bus; 288 cfg->slot = probe->slot; 289 cfg->func = probe->func; 290 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2); 291 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2); 292 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2); 293 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2); 294 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1); 295 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1); 296 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1); 297 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1); 298 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1); 299 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1); 300 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1); 301 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1); 302 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1); 303#ifdef __alpha__ 304 alpha_platform_assign_pciintr(cfg); 305#endif 306 307#ifdef APIC_IO 308 if (cfg->intpin != 0) { 309 int airq; 310 311 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 312 if (airq >= 0) { 313 /* PCI specific entry found in MP table */ 314 if (airq != cfg->intline) { 315 undirect_pci_irq(cfg->intline); 316 cfg->intline = airq; 317 } 318 } else { 319 /* 320 * PCI interrupts might be redirected to the 321 * ISA bus according to some MP tables. Use the 322 * same methods as used by the ISA devices 323 * devices to find the proper IOAPIC int pin. 324 */ 325 airq = isa_apic_irq(cfg->intline); 326 if ((airq >= 0) && (airq != cfg->intline)) { 327 /* XXX: undirect_pci_irq() ? */ 328 undirect_isa_irq(cfg->intline); 329 cfg->intline = airq; 330 } 331 } 332 } 333#endif /* APIC_IO */ 334 335 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1); 336 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1); 337 338 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 339 cfg->hdrtype &= ~PCIM_MFDEV; 340 341 pci_fixancient(cfg); 342 pci_hdrtypedata(cfg); 343 344 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 345 346 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 347 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 348 devlist_entry->conf.pc_sel.pc_func = cfg->func; 349 devlist_entry->conf.pc_hdr = cfg->hdrtype; 350 351 devlist_entry->conf.pc_subvendor = cfg->subvendor; 352 devlist_entry->conf.pc_subdevice = cfg->subdevice; 353 devlist_entry->conf.pc_vendor = cfg->vendor; 354 devlist_entry->conf.pc_device = cfg->device; 355 356 devlist_entry->conf.pc_class = cfg->baseclass; 357 devlist_entry->conf.pc_subclass = cfg->subclass; 358 devlist_entry->conf.pc_progif = cfg->progif; 359 devlist_entry->conf.pc_revid = cfg->revid; 360 361 pci_numdevs++; 362 pci_generation++; 363 } 364 return (devlist_entry); 365} 366 367#if 0 368/* free pcicfgregs structure and all depending data structures */ 369 370static int 371pci_freecfg(struct pci_devinfo *dinfo) 372{ 373 struct devlist *devlist_head; 374 375 devlist_head = &pci_devq; 376 377 if (dinfo->cfg.hdrspec != NULL) 378 free(dinfo->cfg.hdrspec, M_DEVBUF); 379 if (dinfo->cfg.map != NULL) 380 free(dinfo->cfg.map, M_DEVBUF); 381 /* XXX this hasn't been tested */ 382 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 383 free(dinfo, M_DEVBUF); 384 385 /* increment the generation count */ 386 pci_generation++; 387 388 /* we're losing one device */ 389 pci_numdevs--; 390 return (0); 391} 392#endif 393 394 395/* 396 * This is the user interface to PCI configuration space. 397 */ 398 399static int 400pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 401{ 402 if ((oflags & FWRITE) && securelevel > 0) { 403 return EPERM; 404 } 405 return 0; 406} 407 408static int 409pci_close(dev_t dev, int flag, int devtype, struct proc *p) 410{ 411 return 0; 412} 413 414/* 415 * Match a single pci_conf structure against an array of pci_match_conf 416 * structures. The first argument, 'matches', is an array of num_matches 417 * pci_match_conf structures. match_buf is a pointer to the pci_conf 418 * structure that will be compared to every entry in the matches array. 419 * This function returns 1 on failure, 0 on success. 420 */ 421static int 422pci_conf_match(struct pci_match_conf *matches, int num_matches, 423 struct pci_conf *match_buf) 424{ 425 int i; 426 427 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 428 return(1); 429 430 for (i = 0; i < num_matches; i++) { 431 /* 432 * I'm not sure why someone would do this...but... 433 */ 434 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 435 continue; 436 437 /* 438 * Look at each of the match flags. If it's set, do the 439 * comparison. If the comparison fails, we don't have a 440 * match, go on to the next item if there is one. 441 */ 442 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 443 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 444 continue; 445 446 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 447 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 448 continue; 449 450 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 451 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 452 continue; 453 454 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 455 && (match_buf->pc_vendor != matches[i].pc_vendor)) 456 continue; 457 458 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 459 && (match_buf->pc_device != matches[i].pc_device)) 460 continue; 461 462 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 463 && (match_buf->pc_class != matches[i].pc_class)) 464 continue; 465 466 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 467 && (match_buf->pd_unit != matches[i].pd_unit)) 468 continue; 469 470 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 471 && (strncmp(matches[i].pd_name, match_buf->pd_name, 472 sizeof(match_buf->pd_name)) != 0)) 473 continue; 474 475 return(0); 476 } 477 478 return(1); 479} 480 481/* 482 * Locate the parent of a PCI device by scanning the PCI devlist 483 * and return the entry for the parent. 484 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 485 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 486 */ 487 488pcicfgregs * 489pci_devlist_get_parent(pcicfgregs *cfg) 490{ 491 struct devlist *devlist_head; 492 struct pci_devinfo *dinfo; 493 pcicfgregs *bridge_cfg; 494 int i; 495 496 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 497 498 /* If the device is on PCI bus 0, look for the host */ 499 if (cfg->bus == 0) { 500 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 501 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 502 bridge_cfg = &dinfo->cfg; 503 if (bridge_cfg->baseclass == PCIC_BRIDGE 504 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 505 && bridge_cfg->bus == cfg->bus) { 506 return bridge_cfg; 507 } 508 } 509 } 510 511 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 512 if (cfg->bus > 0) { 513 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 514 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 515 bridge_cfg = &dinfo->cfg; 516 if (bridge_cfg->baseclass == PCIC_BRIDGE 517 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 518 && bridge_cfg->secondarybus == cfg->bus) { 519 return bridge_cfg; 520 } 521 } 522 } 523 524 return NULL; 525} 526 527static int 528pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 529{ 530 struct pci_io *io; 531 const char *name; 532 int error; 533 534 if (!(flag & FWRITE)) 535 return EPERM; 536 537 538 switch(cmd) { 539 case PCIOCGETCONF: 540 { 541 struct pci_devinfo *dinfo; 542 struct pci_conf_io *cio; 543 struct devlist *devlist_head; 544 struct pci_match_conf *pattern_buf; 545 int num_patterns; 546 size_t iolen; 547 int ionum, i; 548 549 cio = (struct pci_conf_io *)data; 550 551 num_patterns = 0; 552 dinfo = NULL; 553 554 /* 555 * Hopefully the user won't pass in a null pointer, but it 556 * can't hurt to check. 557 */ 558 if (cio == NULL) { 559 error = EINVAL; 560 break; 561 } 562 563 /* 564 * If the user specified an offset into the device list, 565 * but the list has changed since they last called this 566 * ioctl, tell them that the list has changed. They will 567 * have to get the list from the beginning. 568 */ 569 if ((cio->offset != 0) 570 && (cio->generation != pci_generation)){ 571 cio->num_matches = 0; 572 cio->status = PCI_GETCONF_LIST_CHANGED; 573 error = 0; 574 break; 575 } 576 577 /* 578 * Check to see whether the user has asked for an offset 579 * past the end of our list. 580 */ 581 if (cio->offset >= pci_numdevs) { 582 cio->num_matches = 0; 583 cio->status = PCI_GETCONF_LAST_DEVICE; 584 error = 0; 585 break; 586 } 587 588 /* get the head of the device queue */ 589 devlist_head = &pci_devq; 590 591 /* 592 * Determine how much room we have for pci_conf structures. 593 * Round the user's buffer size down to the nearest 594 * multiple of sizeof(struct pci_conf) in case the user 595 * didn't specify a multiple of that size. 596 */ 597 iolen = min(cio->match_buf_len - 598 (cio->match_buf_len % sizeof(struct pci_conf)), 599 pci_numdevs * sizeof(struct pci_conf)); 600 601 /* 602 * Since we know that iolen is a multiple of the size of 603 * the pciconf union, it's okay to do this. 604 */ 605 ionum = iolen / sizeof(struct pci_conf); 606 607 /* 608 * If this test is true, the user wants the pci_conf 609 * structures returned to match the supplied entries. 610 */ 611 if ((cio->num_patterns > 0) 612 && (cio->pat_buf_len > 0)) { 613 /* 614 * pat_buf_len needs to be: 615 * num_patterns * sizeof(struct pci_match_conf) 616 * While it is certainly possible the user just 617 * allocated a large buffer, but set the number of 618 * matches correctly, it is far more likely that 619 * their kernel doesn't match the userland utility 620 * they're using. It's also possible that the user 621 * forgot to initialize some variables. Yes, this 622 * may be overly picky, but I hazard to guess that 623 * it's far more likely to just catch folks that 624 * updated their kernel but not their userland. 625 */ 626 if ((cio->num_patterns * 627 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 628 /* The user made a mistake, return an error*/ 629 cio->status = PCI_GETCONF_ERROR; 630 printf("pci_ioctl: pat_buf_len %d != " 631 "num_patterns (%d) * sizeof(struct " 632 "pci_match_conf) (%d)\npci_ioctl: " 633 "pat_buf_len should be = %d\n", 634 cio->pat_buf_len, cio->num_patterns, 635 (int)sizeof(struct pci_match_conf), 636 (int)sizeof(struct pci_match_conf) * 637 cio->num_patterns); 638 printf("pci_ioctl: do your headers match your " 639 "kernel?\n"); 640 cio->num_matches = 0; 641 error = EINVAL; 642 break; 643 } 644 645 /* 646 * Check the user's buffer to make sure it's readable. 647 */ 648 if ((error = useracc((caddr_t)cio->patterns, 649 cio->pat_buf_len, B_READ)) != 1){ 650 printf("pci_ioctl: pattern buffer %p, " 651 "length %u isn't user accessible for" 652 " READ\n", cio->patterns, 653 cio->pat_buf_len); 654 error = EACCES; 655 break; 656 } 657 /* 658 * Allocate a buffer to hold the patterns. 659 */ 660 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 661 M_WAITOK); 662 error = copyin(cio->patterns, pattern_buf, 663 cio->pat_buf_len); 664 if (error != 0) 665 break; 666 num_patterns = cio->num_patterns; 667 668 } else if ((cio->num_patterns > 0) 669 || (cio->pat_buf_len > 0)) { 670 /* 671 * The user made a mistake, spit out an error. 672 */ 673 cio->status = PCI_GETCONF_ERROR; 674 cio->num_matches = 0; 675 printf("pci_ioctl: invalid GETCONF arguments\n"); 676 error = EINVAL; 677 break; 678 } else 679 pattern_buf = NULL; 680 681 /* 682 * Make sure we can write to the match buffer. 683 */ 684 if ((error = useracc((caddr_t)cio->matches, cio->match_buf_len, 685 B_WRITE)) != 1) { 686 printf("pci_ioctl: match buffer %p, length %u " 687 "isn't user accessible for WRITE\n", 688 cio->matches, cio->match_buf_len); 689 error = EACCES; 690 break; 691 } 692 693 /* 694 * Go through the list of devices and copy out the devices 695 * that match the user's criteria. 696 */ 697 for (cio->num_matches = 0, error = 0, i = 0, 698 dinfo = STAILQ_FIRST(devlist_head); 699 (dinfo != NULL) && (cio->num_matches < ionum) 700 && (error == 0) && (i < pci_numdevs); 701 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 702 703 if (i < cio->offset) 704 continue; 705 706 /* Populate pd_name and pd_unit */ 707 name = NULL; 708 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 709 name = device_get_name(dinfo->cfg.dev); 710 if (name) { 711 strncpy(dinfo->conf.pd_name, name, 712 sizeof(dinfo->conf.pd_name)); 713 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 714 dinfo->conf.pd_unit = 715 device_get_unit(dinfo->cfg.dev); 716 } 717 718 if ((pattern_buf == NULL) || 719 (pci_conf_match(pattern_buf, num_patterns, 720 &dinfo->conf) == 0)) { 721 722 /* 723 * If we've filled up the user's buffer, 724 * break out at this point. Since we've 725 * got a match here, we'll pick right back 726 * up at the matching entry. We can also 727 * tell the user that there are more matches 728 * left. 729 */ 730 if (cio->num_matches >= ionum) 731 break; 732 733 error = copyout(&dinfo->conf, 734 &cio->matches[cio->num_matches], 735 sizeof(struct pci_conf)); 736 cio->num_matches++; 737 } 738 } 739 740 /* 741 * Set the pointer into the list, so if the user is getting 742 * n records at a time, where n < pci_numdevs, 743 */ 744 cio->offset = i; 745 746 /* 747 * Set the generation, the user will need this if they make 748 * another ioctl call with offset != 0. 749 */ 750 cio->generation = pci_generation; 751 752 /* 753 * If this is the last device, inform the user so he won't 754 * bother asking for more devices. If dinfo isn't NULL, we 755 * know that there are more matches in the list because of 756 * the way the traversal is done. 757 */ 758 if (dinfo == NULL) 759 cio->status = PCI_GETCONF_LAST_DEVICE; 760 else 761 cio->status = PCI_GETCONF_MORE_DEVS; 762 763 if (pattern_buf != NULL) 764 free(pattern_buf, M_TEMP); 765 766 break; 767 } 768 case PCIOCREAD: 769 io = (struct pci_io *)data; 770 switch(io->pi_width) { 771 pcicfgregs probe; 772 case 4: 773 case 2: 774 case 1: 775 probe.hose = -1; 776 probe.bus = io->pi_sel.pc_bus; 777 probe.slot = io->pi_sel.pc_dev; 778 probe.func = io->pi_sel.pc_func; 779 io->pi_data = pci_cfgread(&probe, 780 io->pi_reg, io->pi_width); 781 error = 0; 782 break; 783 default: 784 error = ENODEV; 785 break; 786 } 787 break; 788 789 case PCIOCWRITE: 790 io = (struct pci_io *)data; 791 switch(io->pi_width) { 792 pcicfgregs probe; 793 case 4: 794 case 2: 795 case 1: 796 probe.hose = -1; 797 probe.bus = io->pi_sel.pc_bus; 798 probe.slot = io->pi_sel.pc_dev; 799 probe.func = io->pi_sel.pc_func; 800 pci_cfgwrite(&probe, 801 io->pi_reg, io->pi_data, io->pi_width); 802 error = 0; 803 break; 804 default: 805 error = ENODEV; 806 break; 807 } 808 break; 809 810 default: 811 error = ENOTTY; 812 break; 813 } 814 815 return (error); 816} 817 818#define PCI_CDEV 78 819 820static struct cdevsw pcicdev = { 821 /* open */ pci_open, 822 /* close */ pci_close, 823 /* read */ noread, 824 /* write */ nowrite, 825 /* ioctl */ pci_ioctl, 826 /* poll */ nopoll, 827 /* mmap */ nommap, 828 /* strategy */ nostrategy, 829 /* name */ "pci", 830 /* maj */ PCI_CDEV, 831 /* dump */ nodump, 832 /* psize */ nopsize, 833 /* flags */ 0, 834 /* bmaj */ -1 835}; 836 837#include "pci_if.h" 838 839/* 840 * A simple driver to wrap the old pci driver mechanism for back-compat. 841 */ 842 843static int 844pci_compat_probe(device_t dev) 845{ 846 struct pci_device *dvp; 847 struct pci_devinfo *dinfo; 848 pcicfgregs *cfg; 849 const char *name; 850 int error; 851 852 dinfo = device_get_ivars(dev); 853 cfg = &dinfo->cfg; 854 dvp = device_get_driver(dev)->priv; 855 856 /* 857 * Do the wrapped probe. 858 */ 859 error = ENXIO; 860 if (dvp && dvp->pd_probe) { 861 name = dvp->pd_probe(cfg, (cfg->device << 16) + cfg->vendor); 862 if (name) { 863 device_set_desc_copy(dev, name); 864 error = 0; 865 } 866 } 867 868 return error; 869} 870 871static int 872pci_compat_attach(device_t dev) 873{ 874 struct pci_device *dvp; 875 struct pci_devinfo *dinfo; 876 pcicfgregs *cfg; 877 int unit; 878 879 dinfo = device_get_ivars(dev); 880 cfg = &dinfo->cfg; 881 dvp = device_get_driver(dev)->priv; 882 883 unit = device_get_unit(dev); 884 if (unit > *dvp->pd_count) 885 *dvp->pd_count = unit; 886 if (dvp->pd_attach) 887 dvp->pd_attach(cfg, unit); 888 return 0; 889} 890 891static device_method_t pci_compat_methods[] = { 892 /* Device interface */ 893 DEVMETHOD(device_probe, pci_compat_probe), 894 DEVMETHOD(device_attach, pci_compat_attach), 895 896 { 0, 0 } 897}; 898 899static devclass_t pci_devclass; 900 901/* 902 * Create a new style driver around each old pci driver. 903 */ 904int 905compat_pci_handler(module_t mod, int type, void *data) 906{ 907 struct pci_device *dvp = (struct pci_device *)data; 908 driver_t *driver; 909 910 switch (type) { 911 case MOD_LOAD: 912 driver = malloc(sizeof(driver_t), M_DEVBUF, M_NOWAIT); 913 if (!driver) 914 return ENOMEM; 915 bzero(driver, sizeof(driver_t)); 916 driver->name = dvp->pd_name; 917 driver->methods = pci_compat_methods; 918 driver->softc = sizeof(struct pci_devinfo *); 919 driver->priv = dvp; 920 devclass_add_driver(pci_devclass, driver); 921 break; 922 case MOD_UNLOAD: 923 printf("%s: module unload not supported!\n", dvp->pd_name); 924 return EOPNOTSUPP; 925 default: 926 break; 927 } 928 return 0; 929} 930 931/* 932 * New style pci driver. Parent device is either a pci-host-bridge or a 933 * pci-pci-bridge. Both kinds are represented by instances of pcib. 934 */ 935 936static void 937pci_print_verbose(struct pci_devinfo *dinfo) 938{ 939 if (bootverbose) { 940 pcicfgregs *cfg = &dinfo->cfg; 941 942 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 943 cfg->vendor, cfg->device, cfg->revid); 944 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 945 cfg->baseclass, cfg->subclass, cfg->progif, 946 cfg->hdrtype, cfg->mfdev); 947 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 948 cfg->subordinatebus, cfg->secondarybus); 949#ifdef PCI_DEBUG 950 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 951 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 952 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 953 cfg->lattimer, cfg->lattimer * 30, 954 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 955#endif /* PCI_DEBUG */ 956 if (cfg->intpin > 0) 957 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 958 } 959} 960 961static int 962pci_porten(pcicfgregs *cfg) 963{ 964 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0); 965} 966 967static int 968pci_memen(pcicfgregs *cfg) 969{ 970 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0); 971} 972 973static void 974pci_add_resources(device_t dev, pcicfgregs* cfg) 975{ 976 977 struct pci_devinfo *dinfo = device_get_ivars(dev); 978 struct resource_list *rl = &dinfo->resources; 979 int i; 980 981 for (i = 0; i < cfg->nummaps; i++) { 982 int reg = PCIR_MAPS + i*4; 983 u_int32_t map; 984 u_int64_t base; 985 u_int8_t ln2size; 986 u_int8_t ln2range; 987 u_int32_t testval; 988 989 int type; 990 991 map = pci_cfgread(cfg, reg, 4); 992 993 if (map == 0 || map == 0xffffffff) 994 continue; /* skip invalid entry */ 995 996 pci_cfgwrite(cfg, reg, 0xffffffff, 4); 997 testval = pci_cfgread(cfg, reg, 4); 998 pci_cfgwrite(cfg, reg, map, 4); 999 1000 base = pci_mapbase(map); 1001 if (pci_maptype(map) & PCI_MAPMEM) 1002 type = SYS_RES_MEMORY; 1003 else 1004 type = SYS_RES_IOPORT; 1005 ln2size = pci_mapsize(testval); 1006 ln2range = pci_maprange(testval); 1007 if (ln2range == 64) { 1008 /* Read the other half of a 64bit map register */ 1009 base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32; 1010 i++; 1011 } 1012 1013#ifdef __alpha__ 1014 /* 1015 * XXX: encode hose number in the base addr, 1016 * This will go away once the bus_space functions 1017 * can deal with multiple hoses 1018 */ 1019 1020 if(cfg->hose){ 1021 if (base & 0x80000000) { 1022 printf("base addr = 0x%x\n", base); 1023 printf("hacked addr = 0x%x\n", 1024 base | (cfg->hose << 31)); 1025 1026 panic("hose encoding hack would clobber base addr"); 1027 } 1028 if (cfg->hose > 1) 1029 panic("only one hose supported!"); 1030 base |= (cfg->hose << 31); 1031 } 1032#endif 1033 if (type == SYS_RES_IOPORT && !pci_porten(cfg)) 1034 continue; 1035 if (type == SYS_RES_IOPORT && !pci_memen(cfg)) 1036 continue; 1037 1038 resource_list_add(rl, type, reg, 1039 base, base + (1 << ln2size) - 1, 1040 (1 << ln2size)); 1041 1042 if (bootverbose) { 1043 printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n", 1044 i, pci_maptype(base), ln2range, 1045 (unsigned int) base, ln2size); 1046 } 1047 } 1048 if (cfg->intline) 1049 resource_list_add(rl, SYS_RES_IRQ, 0, 1050 cfg->intline, cfg->intline, 1); 1051} 1052 1053static void 1054pci_add_children(device_t dev, int busno) 1055{ 1056 pcicfgregs probe; 1057 1058#ifdef SIMOS 1059#undef PCI_SLOTMAX 1060#define PCI_SLOTMAX 0 1061#endif 1062 1063 bzero(&probe, sizeof probe); 1064#ifdef __alpha__ 1065 probe.hose = pcib_get_hose(dev); 1066#endif 1067#ifdef __i386__ 1068 probe.hose = 0; 1069#endif 1070 probe.bus = busno; 1071 1072 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) { 1073 int pcifunchigh = 0; 1074 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) { 1075 struct pci_devinfo *dinfo = pci_readcfg(&probe); 1076 if (dinfo != NULL) { 1077 if (dinfo->cfg.mfdev) 1078 pcifunchigh = 7; 1079 1080 pci_print_verbose(dinfo); 1081 dinfo->cfg.dev = 1082 device_add_child(dev, NULL, -1, dinfo); 1083 pci_add_resources(dinfo->cfg.dev, &dinfo->cfg); 1084 } 1085 } 1086 } 1087} 1088 1089static int 1090pci_new_probe(device_t dev) 1091{ 1092 static int once; 1093 1094 device_set_desc(dev, "PCI bus"); 1095 pci_add_children(dev, device_get_unit(dev)); 1096 if (!once) { 1097 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 1098 once++; 1099 } 1100 1101 return 0; 1102} 1103 1104static int 1105pci_print_child(device_t dev, device_t child) 1106{ 1107 struct pci_devinfo *dinfo; 1108 pcicfgregs *cfg; 1109 int retval = 0; 1110 1111 dinfo = device_get_ivars(child); 1112 cfg = &dinfo->cfg; 1113 1114 retval += bus_print_child_header(dev, child); 1115 1116 if (cfg->intpin > 0 && cfg->intline != 255) 1117 retval += printf(" irq %d", cfg->intline); 1118 retval += printf(" at device %d.%d", pci_get_slot(child), 1119 pci_get_function(child)); 1120 1121 retval += bus_print_child_footer(dev, child); 1122 1123 return (retval); 1124} 1125 1126static void 1127pci_probe_nomatch(device_t dev, device_t child) 1128{ 1129 struct pci_devinfo *dinfo; 1130 pcicfgregs *cfg; 1131 1132 dinfo = device_get_ivars(child); 1133 cfg = &dinfo->cfg; 1134 1135 device_printf(dev, "unknown card (vendor=0x%04x, dev=0x%04x) at %d.%d", 1136 cfg->vendor, 1137 cfg->device, 1138 pci_get_slot(child), 1139 pci_get_function(child)); 1140 if (cfg->intpin > 0 && cfg->intline != 255) { 1141 printf(" irq %d", cfg->intline); 1142 } 1143 printf("\n"); 1144 1145 return; 1146} 1147 1148static int 1149pci_read_ivar(device_t dev, device_t child, int which, u_long *result) 1150{ 1151 struct pci_devinfo *dinfo; 1152 pcicfgregs *cfg; 1153 1154 dinfo = device_get_ivars(child); 1155 cfg = &dinfo->cfg; 1156 1157 switch (which) { 1158 case PCI_IVAR_SUBVENDOR: 1159 *result = cfg->subvendor; 1160 break; 1161 case PCI_IVAR_SUBDEVICE: 1162 *result = cfg->subdevice; 1163 break; 1164 case PCI_IVAR_VENDOR: 1165 *result = cfg->vendor; 1166 break; 1167 case PCI_IVAR_DEVICE: 1168 *result = cfg->device; 1169 break; 1170 case PCI_IVAR_DEVID: 1171 *result = (cfg->device << 16) | cfg->vendor; 1172 break; 1173 case PCI_IVAR_CLASS: 1174 *result = cfg->baseclass; 1175 break; 1176 case PCI_IVAR_SUBCLASS: 1177 *result = cfg->subclass; 1178 break; 1179 case PCI_IVAR_PROGIF: 1180 *result = cfg->progif; 1181 break; 1182 case PCI_IVAR_REVID: 1183 *result = cfg->revid; 1184 break; 1185 case PCI_IVAR_INTPIN: 1186 *result = cfg->intpin; 1187 break; 1188 case PCI_IVAR_IRQ: 1189 *result = cfg->intline; 1190 break; 1191 case PCI_IVAR_BUS: 1192 *result = cfg->bus; 1193 break; 1194 case PCI_IVAR_SLOT: 1195 *result = cfg->slot; 1196 break; 1197 case PCI_IVAR_FUNCTION: 1198 *result = cfg->func; 1199 break; 1200 case PCI_IVAR_SECONDARYBUS: 1201 *result = cfg->secondarybus; 1202 break; 1203 case PCI_IVAR_SUBORDINATEBUS: 1204 *result = cfg->subordinatebus; 1205 break; 1206 case PCI_IVAR_HOSE: 1207 /* 1208 * Pass up to parent bridge. 1209 */ 1210 *result = pcib_get_hose(dev); 1211 break; 1212 default: 1213 return ENOENT; 1214 } 1215 return 0; 1216} 1217 1218static int 1219pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1220{ 1221 struct pci_devinfo *dinfo; 1222 pcicfgregs *cfg; 1223 1224 dinfo = device_get_ivars(child); 1225 cfg = &dinfo->cfg; 1226 1227 switch (which) { 1228 case PCI_IVAR_SUBVENDOR: 1229 case PCI_IVAR_SUBDEVICE: 1230 case PCI_IVAR_VENDOR: 1231 case PCI_IVAR_DEVICE: 1232 case PCI_IVAR_DEVID: 1233 case PCI_IVAR_CLASS: 1234 case PCI_IVAR_SUBCLASS: 1235 case PCI_IVAR_PROGIF: 1236 case PCI_IVAR_REVID: 1237 case PCI_IVAR_INTPIN: 1238 case PCI_IVAR_IRQ: 1239 case PCI_IVAR_BUS: 1240 case PCI_IVAR_SLOT: 1241 case PCI_IVAR_FUNCTION: 1242 return EINVAL; /* disallow for now */ 1243 1244 case PCI_IVAR_SECONDARYBUS: 1245 cfg->secondarybus = value; 1246 break; 1247 case PCI_IVAR_SUBORDINATEBUS: 1248 cfg->subordinatebus = value; 1249 break; 1250 default: 1251 return ENOENT; 1252 } 1253 return 0; 1254} 1255 1256static struct resource * 1257pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1258 u_long start, u_long end, u_long count, u_int flags) 1259{ 1260 struct pci_devinfo *dinfo = device_get_ivars(child); 1261 struct resource_list *rl = &dinfo->resources; 1262 1263 return resource_list_alloc(rl, dev, child, type, rid, 1264 start, end, count, flags); 1265} 1266 1267static int 1268pci_release_resource(device_t dev, device_t child, int type, int rid, 1269 struct resource *r) 1270{ 1271 struct pci_devinfo *dinfo = device_get_ivars(child); 1272 struct resource_list *rl = &dinfo->resources; 1273 1274 return resource_list_release(rl, dev, child, type, rid, r); 1275} 1276 1277static int 1278pci_set_resource(device_t dev, device_t child, int type, int rid, 1279 u_long start, u_long count) 1280{ 1281 printf("pci_set_resource: PCI resources can not be changed\n"); 1282 return EINVAL; 1283} 1284 1285static int 1286pci_get_resource(device_t dev, device_t child, int type, int rid, 1287 u_long *startp, u_long *countp) 1288{ 1289 struct pci_devinfo *dinfo = device_get_ivars(child); 1290 struct resource_list *rl = &dinfo->resources; 1291 struct resource_list_entry *rle; 1292 1293 rle = resource_list_find(rl, type, rid); 1294 if (!rle) 1295 return ENOENT; 1296 1297 *startp = rle->start; 1298 *countp = rle->count; 1299 1300 return 0; 1301} 1302 1303static void 1304pci_delete_resource(device_t dev, device_t child, int type, int rid) 1305{ 1306 printf("pci_set_resource: PCI resources can not be deleted\n"); 1307 return EINVAL; 1308} 1309 1310static u_int32_t 1311pci_read_config_method(device_t dev, device_t child, int reg, int width) 1312{ 1313 struct pci_devinfo *dinfo = device_get_ivars(child); 1314 pcicfgregs *cfg = &dinfo->cfg; 1315 return pci_cfgread(cfg, reg, width); 1316} 1317 1318static void 1319pci_write_config_method(device_t dev, device_t child, int reg, 1320 u_int32_t val, int width) 1321{ 1322 struct pci_devinfo *dinfo = device_get_ivars(child); 1323 pcicfgregs *cfg = &dinfo->cfg; 1324 pci_cfgwrite(cfg, reg, val, width); 1325} 1326 1327static int 1328pci_modevent(module_t mod, int what, void *arg) 1329{ 1330 switch (what) { 1331 case MOD_LOAD: 1332 STAILQ_INIT(&pci_devq); 1333 break; 1334 1335 case MOD_UNLOAD: 1336 break; 1337 } 1338 1339 return 0; 1340} 1341 1342static device_method_t pci_methods[] = { 1343 /* Device interface */ 1344 DEVMETHOD(device_probe, pci_new_probe), 1345 DEVMETHOD(device_attach, bus_generic_attach), 1346 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1347 DEVMETHOD(device_suspend, bus_generic_suspend), 1348 DEVMETHOD(device_resume, bus_generic_resume), 1349 1350 /* Bus interface */ 1351 DEVMETHOD(bus_print_child, pci_print_child), 1352 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 1353 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1354 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1355 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1356 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1357 DEVMETHOD(bus_release_resource, pci_release_resource), 1358 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1359 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1360 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1361 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1362 DEVMETHOD(bus_set_resource, pci_set_resource), 1363 DEVMETHOD(bus_get_resource, pci_get_resource), 1364 DEVMETHOD(bus_delete_resource, pci_delete_resource), 1365 1366 /* PCI interface */ 1367 DEVMETHOD(pci_read_config, pci_read_config_method), 1368 DEVMETHOD(pci_write_config, pci_write_config_method), 1369 1370 { 0, 0 } 1371}; 1372 1373static driver_t pci_driver = { 1374 "pci", 1375 pci_methods, 1376 1, /* no softc */ 1377}; 1378 1379DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1380