pci.c revision 47612
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $Id: pci.c,v 1.104 1999/05/20 15:33:31 gallatin Exp $ 27 * 28 */ 29 30#include "opt_bus.h" 31 32#include "pci.h" 33#if NPCI > 0 34 35#include "opt_devfs.h" 36#include "opt_simos.h" 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/fcntl.h> 43#include <sys/conf.h> 44#include <sys/kernel.h> 45#include <sys/queue.h> 46#include <sys/types.h> 47#include <sys/buf.h> 48#ifdef DEVFS 49#include <sys/devfsext.h> 50#endif /* DEVFS */ 51 52#include <vm/vm.h> 53#include <vm/pmap.h> 54#include <vm/vm_extern.h> 55 56#include <sys/bus.h> 57#include <machine/bus.h> 58#include <sys/rman.h> 59#include <machine/resource.h> 60 61#include <pci/pcireg.h> 62#include <pci/pcivar.h> 63#include <pci/pci_ioctl.h> 64 65#ifdef APIC_IO 66#include <machine/smp.h> 67#endif /* APIC_IO */ 68 69static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 70u_int32_t pci_numdevs = 0; 71static u_int32_t pci_generation = 0; 72 73/* return base address of memory or port map */ 74 75static int 76pci_mapbase(unsigned mapreg) 77{ 78 int mask = 0x03; 79 if ((mapreg & 0x01) == 0) 80 mask = 0x0f; 81 return (mapreg & ~mask); 82} 83 84/* return map type of memory or port map */ 85 86static int 87pci_maptype(unsigned mapreg) 88{ 89 static u_int8_t maptype[0x10] = { 90 PCI_MAPMEM, PCI_MAPPORT, 91 PCI_MAPMEM, 0, 92 PCI_MAPMEM, PCI_MAPPORT, 93 0, 0, 94 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 95 PCI_MAPMEM|PCI_MAPMEMP, 0, 96 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 97 0, 0, 98 }; 99 100 return maptype[mapreg & 0x0f]; 101} 102 103/* return log2 of map size decoded for memory or port map */ 104 105static int 106pci_mapsize(unsigned testval) 107{ 108 int ln2size; 109 110 testval = pci_mapbase(testval); 111 ln2size = 0; 112 if (testval != 0) { 113 while ((testval & 1) == 0) 114 { 115 ln2size++; 116 testval >>= 1; 117 } 118 } 119 return (ln2size); 120} 121 122/* return log2 of address range supported by map register */ 123 124static int 125pci_maprange(unsigned mapreg) 126{ 127 int ln2range = 0; 128 switch (mapreg & 0x07) { 129 case 0x00: 130 case 0x01: 131 case 0x05: 132 ln2range = 32; 133 break; 134 case 0x02: 135 ln2range = 20; 136 break; 137 case 0x04: 138 ln2range = 64; 139 break; 140 } 141 return (ln2range); 142} 143 144/* extract map parameters into newly allocated array of pcimap structures */ 145 146static pcimap * 147pci_readmaps(pcicfgregs *cfg, int maxmaps) 148{ 149 int i, j = 0; 150 pcimap *map; 151 int map64 = 0; 152 int reg = PCIR_MAPS; 153 154 for (i = 0; i < maxmaps; i++) { 155 int reg = PCIR_MAPS + i*4; 156 u_int32_t base; 157 u_int32_t ln2range; 158 159 base = pci_cfgread(cfg, reg, 4); 160 ln2range = pci_maprange(base); 161 162 if (base == 0 || ln2range == 0 || base == 0xffffffff) 163 continue; /* skip invalid entry */ 164 else { 165 j++; 166 if (ln2range > 32) { 167 i++; 168 j++; 169 } 170 } 171 } 172 173 map = malloc(j * sizeof (pcimap), M_DEVBUF, M_WAITOK); 174 if (map != NULL) { 175 bzero(map, sizeof(pcimap) * j); 176 cfg->nummaps = j; 177 178 for (i = 0, j = 0; i < maxmaps; i++, reg += 4) { 179 u_int32_t base; 180 u_int32_t testval; 181 182 base = pci_cfgread(cfg, reg, 4); 183 184 if (map64 == 0) { 185 if (base == 0 || base == 0xffffffff) 186 continue; /* skip invalid entry */ 187 pci_cfgwrite(cfg, reg, 0xffffffff, 4); 188 testval = pci_cfgread(cfg, reg, 4); 189 pci_cfgwrite(cfg, reg, base, 4); 190 191 map[j].reg = reg; 192 map[j].base = pci_mapbase(base); 193 map[j].type = pci_maptype(base); 194 map[j].ln2size = pci_mapsize(testval); 195 map[j].ln2range = pci_maprange(testval); 196 map64 = map[j].ln2range == 64; 197 } else { 198 /* only fill in base, other fields are 0 */ 199 map[j].base = base; 200 map64 = 0; 201 } 202#ifdef __alpha__ 203 /* 204 * XXX: encode hose number in the base addr, 205 * This will go away once the bus_space functions 206 * can deal with multiple hoses 207 */ 208 209 if(cfg->hose){ 210 if(map[j].base & 0x80000000){ 211 printf("base addr = 0x%x\n", map[j].base); 212 printf("hacked addr = 0x%x\n", 213 map[j].base | (cfg->hose << 31)); 214 215 panic("hose encoding hack would clobber base addr"); 216 } 217 if(cfg->hose > 1 ) 218 panic("only one hose supported!"); 219 map[j].base |= (cfg->hose << 31); 220 } 221#endif 222 j++; 223 } 224 } 225 return (map); 226} 227 228/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 229 230static void 231pci_fixancient(pcicfgregs *cfg) 232{ 233 if (cfg->hdrtype != 0) 234 return; 235 236 /* PCI to PCI bridges use header type 1 */ 237 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 238 cfg->hdrtype = 1; 239} 240 241/* read config data specific to header type 1 device (PCI to PCI bridge) */ 242 243static void * 244pci_readppb(pcicfgregs *cfg) 245{ 246 pcih1cfgregs *p; 247 248 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK); 249 if (p == NULL) 250 return (NULL); 251 252 bzero(p, sizeof *p); 253 254 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2); 255 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2); 256 257 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1); 258 259 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2), 260 pci_cfgread(cfg, PCIR_IOBASEL_1, 1)); 261 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2), 262 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1)); 263 264 p->membase = PCI_PPBMEMBASE (0, 265 pci_cfgread(cfg, PCIR_MEMBASE_1, 2)); 266 p->memlimit = PCI_PPBMEMLIMIT (0, 267 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2)); 268 269 p->pmembase = PCI_PPBMEMBASE ( 270 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4), 271 pci_cfgread(cfg, PCIR_PMBASEL_1, 2)); 272 273 p->pmemlimit = PCI_PPBMEMLIMIT ( 274 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4), 275 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2)); 276 return (p); 277} 278 279/* read config data specific to header type 2 device (PCI to CardBus bridge) */ 280 281static void * 282pci_readpcb(pcicfgregs *cfg) 283{ 284 pcih2cfgregs *p; 285 286 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK); 287 if (p == NULL) 288 return (NULL); 289 290 bzero(p, sizeof *p); 291 292 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2); 293 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2); 294 295 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1); 296 297 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4); 298 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4); 299 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4); 300 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4); 301 302 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4); 303 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4); 304 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4); 305 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4); 306 307 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4); 308 return p; 309} 310 311/* extract header type specific config data */ 312 313static void 314pci_hdrtypedata(pcicfgregs *cfg) 315{ 316 switch (cfg->hdrtype) { 317 case 0: 318 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2); 319 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2); 320 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_0); 321 break; 322 case 1: 323 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2); 324 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2); 325 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1); 326 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1); 327 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_1); 328 cfg->hdrspec = pci_readppb(cfg); 329 break; 330 case 2: 331 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2); 332 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2); 333 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1); 334 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1); 335 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_2); 336 cfg->hdrspec = pci_readpcb(cfg); 337 break; 338 } 339} 340 341/* read configuration header into pcicfgrect structure */ 342 343static struct pci_devinfo * 344pci_readcfg(pcicfgregs *probe) 345{ 346 pcicfgregs *cfg = NULL; 347 struct pci_devinfo *devlist_entry; 348 struct devlist *devlist_head; 349 350 devlist_head = &pci_devq; 351 352 devlist_entry = NULL; 353 354 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) { 355 devlist_entry = malloc(sizeof(struct pci_devinfo), 356 M_DEVBUF, M_WAITOK); 357 if (devlist_entry == NULL) 358 return (NULL); 359 bzero(devlist_entry, sizeof *devlist_entry); 360 361 cfg = &devlist_entry->cfg; 362 363 cfg->hose = probe->hose; 364 cfg->bus = probe->bus; 365 cfg->slot = probe->slot; 366 cfg->func = probe->func; 367 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2); 368 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2); 369 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2); 370 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2); 371 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1); 372 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1); 373 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1); 374 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1); 375 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1); 376 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1); 377 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1); 378 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1); 379 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1); 380#ifdef __alpha__ 381 alpha_platform_assign_pciintr(cfg); 382#endif 383 384#ifdef APIC_IO 385 if (cfg->intpin != 0) { 386 int airq; 387 388 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 389 if (airq >= 0) { 390 /* PCI specific entry found in MP table */ 391 if (airq != cfg->intline) { 392 undirect_pci_irq(cfg->intline); 393 cfg->intline = airq; 394 } 395 } else { 396 /* 397 * PCI interrupts might be redirected to the 398 * ISA bus according to some MP tables. Use the 399 * same methods as used by the ISA devices 400 * devices to find the proper IOAPIC int pin. 401 */ 402 airq = isa_apic_irq(cfg->intline); 403 if ((airq >= 0) && (airq != cfg->intline)) { 404 /* XXX: undirect_pci_irq() ? */ 405 undirect_isa_irq(cfg->intline); 406 cfg->intline = airq; 407 } 408 } 409 } 410#endif /* APIC_IO */ 411 412 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1); 413 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1); 414 415 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 416 cfg->hdrtype &= ~PCIM_MFDEV; 417 418 pci_fixancient(cfg); 419 pci_hdrtypedata(cfg); 420 421 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 422 423 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 424 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 425 devlist_entry->conf.pc_sel.pc_func = cfg->func; 426 devlist_entry->conf.pc_hdr = cfg->hdrtype; 427 428 devlist_entry->conf.pc_subvendor = cfg->subvendor; 429 devlist_entry->conf.pc_subdevice = cfg->subdevice; 430 devlist_entry->conf.pc_vendor = cfg->vendor; 431 devlist_entry->conf.pc_device = cfg->device; 432 433 devlist_entry->conf.pc_class = cfg->baseclass; 434 devlist_entry->conf.pc_subclass = cfg->subclass; 435 devlist_entry->conf.pc_progif = cfg->progif; 436 devlist_entry->conf.pc_revid = cfg->revid; 437 438 pci_numdevs++; 439 pci_generation++; 440 } 441 return (devlist_entry); 442} 443 444#if 0 445/* free pcicfgregs structure and all depending data structures */ 446 447static int 448pci_freecfg(struct pci_devinfo *dinfo) 449{ 450 struct devlist *devlist_head; 451 452 devlist_head = &pci_devq; 453 454 if (dinfo->cfg.hdrspec != NULL) 455 free(dinfo->cfg.hdrspec, M_DEVBUF); 456 if (dinfo->cfg.map != NULL) 457 free(dinfo->cfg.map, M_DEVBUF); 458 /* XXX this hasn't been tested */ 459 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 460 free(dinfo, M_DEVBUF); 461 462 /* increment the generation count */ 463 pci_generation++; 464 465 /* we're losing one device */ 466 pci_numdevs--; 467 return (0); 468} 469#endif 470 471 472/* 473 * This is the user interface to PCI configuration space. 474 */ 475 476static int 477pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 478{ 479 if ((oflags & FWRITE) && securelevel > 0) { 480 return EPERM; 481 } 482 return 0; 483} 484 485static int 486pci_close(dev_t dev, int flag, int devtype, struct proc *p) 487{ 488 return 0; 489} 490 491/* 492 * Match a single pci_conf structure against an array of pci_match_conf 493 * structures. The first argument, 'matches', is an array of num_matches 494 * pci_match_conf structures. match_buf is a pointer to the pci_conf 495 * structure that will be compared to every entry in the matches array. 496 * This function returns 1 on failure, 0 on success. 497 */ 498static int 499pci_conf_match(struct pci_match_conf *matches, int num_matches, 500 struct pci_conf *match_buf) 501{ 502 int i; 503 504 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 505 return(1); 506 507 for (i = 0; i < num_matches; i++) { 508 /* 509 * I'm not sure why someone would do this...but... 510 */ 511 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 512 continue; 513 514 /* 515 * Look at each of the match flags. If it's set, do the 516 * comparison. If the comparison fails, we don't have a 517 * match, go on to the next item if there is one. 518 */ 519 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 520 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 521 continue; 522 523 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 524 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 525 continue; 526 527 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 528 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 529 continue; 530 531 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 532 && (match_buf->pc_vendor != matches[i].pc_vendor)) 533 continue; 534 535 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 536 && (match_buf->pc_device != matches[i].pc_device)) 537 continue; 538 539 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 540 && (match_buf->pc_class != matches[i].pc_class)) 541 continue; 542 543 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 544 && (match_buf->pd_unit != matches[i].pd_unit)) 545 continue; 546 547 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 548 && (strncmp(matches[i].pd_name, match_buf->pd_name, 549 sizeof(match_buf->pd_name)) != 0)) 550 continue; 551 552 return(0); 553 } 554 555 return(1); 556} 557 558static int 559pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 560{ 561 struct pci_io *io; 562 const char *name; 563 int error; 564 565 if (!(flag & FWRITE)) 566 return EPERM; 567 568 569 switch(cmd) { 570 case PCIOCGETCONF: 571 { 572 struct pci_devinfo *dinfo; 573 struct pci_conf_io *cio; 574 struct devlist *devlist_head; 575 struct pci_match_conf *pattern_buf; 576 int num_patterns; 577 size_t iolen; 578 int ionum, i; 579 580 cio = (struct pci_conf_io *)data; 581 582 num_patterns = 0; 583 dinfo = NULL; 584 585 /* 586 * Hopefully the user won't pass in a null pointer, but it 587 * can't hurt to check. 588 */ 589 if (cio == NULL) { 590 error = EINVAL; 591 break; 592 } 593 594 /* 595 * If the user specified an offset into the device list, 596 * but the list has changed since they last called this 597 * ioctl, tell them that the list has changed. They will 598 * have to get the list from the beginning. 599 */ 600 if ((cio->offset != 0) 601 && (cio->generation != pci_generation)){ 602 cio->num_matches = 0; 603 cio->status = PCI_GETCONF_LIST_CHANGED; 604 error = 0; 605 break; 606 } 607 608 /* 609 * Check to see whether the user has asked for an offset 610 * past the end of our list. 611 */ 612 if (cio->offset >= pci_numdevs) { 613 cio->num_matches = 0; 614 cio->status = PCI_GETCONF_LAST_DEVICE; 615 error = 0; 616 break; 617 } 618 619 /* get the head of the device queue */ 620 devlist_head = &pci_devq; 621 622 /* 623 * Determine how much room we have for pci_conf structures. 624 * Round the user's buffer size down to the nearest 625 * multiple of sizeof(struct pci_conf) in case the user 626 * didn't specify a multiple of that size. 627 */ 628 iolen = min(cio->match_buf_len - 629 (cio->match_buf_len % sizeof(struct pci_conf)), 630 pci_numdevs * sizeof(struct pci_conf)); 631 632 /* 633 * Since we know that iolen is a multiple of the size of 634 * the pciconf union, it's okay to do this. 635 */ 636 ionum = iolen / sizeof(struct pci_conf); 637 638 /* 639 * If this test is true, the user wants the pci_conf 640 * structures returned to match the supplied entries. 641 */ 642 if ((cio->num_patterns > 0) 643 && (cio->pat_buf_len > 0)) { 644 /* 645 * pat_buf_len needs to be: 646 * num_patterns * sizeof(struct pci_match_conf) 647 * While it is certainly possible the user just 648 * allocated a large buffer, but set the number of 649 * matches correctly, it is far more likely that 650 * their kernel doesn't match the userland utility 651 * they're using. It's also possible that the user 652 * forgot to initialize some variables. Yes, this 653 * may be overly picky, but I hazard to guess that 654 * it's far more likely to just catch folks that 655 * updated their kernel but not their userland. 656 */ 657 if ((cio->num_patterns * 658 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 659 /* The user made a mistake, return an error*/ 660 cio->status = PCI_GETCONF_ERROR; 661 printf("pci_ioctl: pat_buf_len %d != " 662 "num_patterns (%d) * sizeof(struct " 663 "pci_match_conf) (%d)\npci_ioctl: " 664 "pat_buf_len should be = %d\n", 665 cio->pat_buf_len, cio->num_patterns, 666 (int)sizeof(struct pci_match_conf), 667 (int)sizeof(struct pci_match_conf) * 668 cio->num_patterns); 669 printf("pci_ioctl: do your headers match your " 670 "kernel?\n"); 671 cio->num_matches = 0; 672 error = EINVAL; 673 break; 674 } 675 676 /* 677 * Check the user's buffer to make sure it's readable. 678 */ 679 if ((error = useracc((caddr_t)cio->patterns, 680 cio->pat_buf_len, B_READ)) != 1){ 681 printf("pci_ioctl: pattern buffer %p, " 682 "length %u isn't user accessible for" 683 " READ\n", cio->patterns, 684 cio->pat_buf_len); 685 error = EACCES; 686 break; 687 } 688 /* 689 * Allocate a buffer to hold the patterns. 690 */ 691 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 692 M_WAITOK); 693 error = copyin(cio->patterns, pattern_buf, 694 cio->pat_buf_len); 695 if (error != 0) 696 break; 697 num_patterns = cio->num_patterns; 698 699 } else if ((cio->num_patterns > 0) 700 || (cio->pat_buf_len > 0)) { 701 /* 702 * The user made a mistake, spit out an error. 703 */ 704 cio->status = PCI_GETCONF_ERROR; 705 cio->num_matches = 0; 706 printf("pci_ioctl: invalid GETCONF arguments\n"); 707 error = EINVAL; 708 break; 709 } else 710 pattern_buf = NULL; 711 712 /* 713 * Make sure we can write to the match buffer. 714 */ 715 if ((error = useracc((caddr_t)cio->matches, cio->match_buf_len, 716 B_WRITE)) != 1) { 717 printf("pci_ioctl: match buffer %p, length %u " 718 "isn't user accessible for WRITE\n", 719 cio->matches, cio->match_buf_len); 720 error = EACCES; 721 break; 722 } 723 724 /* 725 * Go through the list of devices and copy out the devices 726 * that match the user's criteria. 727 */ 728 for (cio->num_matches = 0, error = 0, i = 0, 729 dinfo = STAILQ_FIRST(devlist_head); 730 (dinfo != NULL) && (cio->num_matches < ionum) 731 && (error == 0) && (i < pci_numdevs); 732 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 733 734 if (i < cio->offset) 735 continue; 736 737 /* Populate pd_name and pd_unit */ 738 name = NULL; 739 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 740 name = device_get_name(dinfo->cfg.dev); 741 if (name) { 742 strncpy(dinfo->conf.pd_name, name, 743 sizeof(dinfo->conf.pd_name)); 744 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 745 dinfo->conf.pd_unit = 746 device_get_unit(dinfo->cfg.dev); 747 } 748 749 if ((pattern_buf == NULL) || 750 (pci_conf_match(pattern_buf, num_patterns, 751 &dinfo->conf) == 0)) { 752 753 /* 754 * If we've filled up the user's buffer, 755 * break out at this point. Since we've 756 * got a match here, we'll pick right back 757 * up at the matching entry. We can also 758 * tell the user that there are more matches 759 * left. 760 */ 761 if (cio->num_matches >= ionum) 762 break; 763 764 error = copyout(&dinfo->conf, 765 &cio->matches[cio->num_matches], 766 sizeof(struct pci_conf)); 767 cio->num_matches++; 768 } 769 } 770 771 /* 772 * Set the pointer into the list, so if the user is getting 773 * n records at a time, where n < pci_numdevs, 774 */ 775 cio->offset = i; 776 777 /* 778 * Set the generation, the user will need this if they make 779 * another ioctl call with offset != 0. 780 */ 781 cio->generation = pci_generation; 782 783 /* 784 * If this is the last device, inform the user so he won't 785 * bother asking for more devices. If dinfo isn't NULL, we 786 * know that there are more matches in the list because of 787 * the way the traversal is done. 788 */ 789 if (dinfo == NULL) 790 cio->status = PCI_GETCONF_LAST_DEVICE; 791 else 792 cio->status = PCI_GETCONF_MORE_DEVS; 793 794 if (pattern_buf != NULL) 795 free(pattern_buf, M_TEMP); 796 797 break; 798 } 799 case PCIOCREAD: 800 io = (struct pci_io *)data; 801 switch(io->pi_width) { 802 pcicfgregs probe; 803 case 4: 804 case 2: 805 case 1: 806 probe.bus = io->pi_sel.pc_bus; 807 probe.slot = io->pi_sel.pc_dev; 808 probe.func = io->pi_sel.pc_func; 809 io->pi_data = pci_cfgread(&probe, 810 io->pi_reg, io->pi_width); 811 error = 0; 812 break; 813 default: 814 error = ENODEV; 815 break; 816 } 817 break; 818 819 case PCIOCWRITE: 820 io = (struct pci_io *)data; 821 switch(io->pi_width) { 822 pcicfgregs probe; 823 case 4: 824 case 2: 825 case 1: 826 probe.bus = io->pi_sel.pc_bus; 827 probe.slot = io->pi_sel.pc_dev; 828 probe.func = io->pi_sel.pc_func; 829 pci_cfgwrite(&probe, 830 io->pi_reg, io->pi_data, io->pi_width); 831 error = 0; 832 break; 833 default: 834 error = ENODEV; 835 break; 836 } 837 break; 838 839 default: 840 error = ENOTTY; 841 break; 842 } 843 844 return (error); 845} 846 847#define PCI_CDEV 78 848 849static struct cdevsw pcicdev = { 850 pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset, 851 nodevtotty, seltrue, nommap, nostrategy, "pci", 0, PCI_CDEV 852}; 853 854#ifdef DEVFS 855static void *pci_devfs_token; 856#endif 857 858static void 859pci_cdevinit(void *dummy) 860{ 861 dev_t dev; 862 863 dev = makedev(PCI_CDEV, 0); 864 cdevsw_add(&dev, &pcicdev, NULL); 865#ifdef DEVFS 866 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 867 UID_ROOT, GID_WHEEL, 0644, "pci"); 868#endif 869} 870 871SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 872 873#include "pci_if.h" 874 875/* 876 * A simple driver to wrap the old pci driver mechanism for back-compat. 877 */ 878 879static int 880pci_compat_probe(device_t dev) 881{ 882 struct pci_device *dvp; 883 struct pci_devinfo *dinfo; 884 pcicfgregs *cfg; 885 const char *name; 886 int error; 887 888 dinfo = device_get_ivars(dev); 889 cfg = &dinfo->cfg; 890 dvp = device_get_driver(dev)->priv; 891 892 /* 893 * Do the wrapped probe. 894 */ 895 error = ENXIO; 896 if (dvp && dvp->pd_probe) { 897 name = dvp->pd_probe(cfg, (cfg->device << 16) + cfg->vendor); 898 if (name) { 899 device_set_desc_copy(dev, name); 900 error = 0; 901 } 902 } 903 904 return error; 905} 906 907static int 908pci_compat_attach(device_t dev) 909{ 910 struct pci_device *dvp; 911 struct pci_devinfo *dinfo; 912 pcicfgregs *cfg; 913 int unit; 914 915 dinfo = device_get_ivars(dev); 916 cfg = &dinfo->cfg; 917 dvp = device_get_driver(dev)->priv; 918 919 unit = device_get_unit(dev); 920 if (unit > *dvp->pd_count) 921 *dvp->pd_count = unit; 922 if (dvp->pd_attach) 923 dvp->pd_attach(cfg, unit); 924 return 0; 925} 926 927static device_method_t pci_compat_methods[] = { 928 /* Device interface */ 929 DEVMETHOD(device_probe, pci_compat_probe), 930 DEVMETHOD(device_attach, pci_compat_attach), 931 932 { 0, 0 } 933}; 934 935static devclass_t pci_devclass; 936 937/* 938 * Create a new style driver around each old pci driver. 939 */ 940int 941compat_pci_handler(module_t mod, int type, void *data) 942{ 943 struct pci_device *dvp = (struct pci_device *)data; 944 driver_t *driver; 945 946 switch (type) { 947 case MOD_LOAD: 948 driver = malloc(sizeof(driver_t), M_DEVBUF, M_NOWAIT); 949 if (!driver) 950 return ENOMEM; 951 bzero(driver, sizeof(driver_t)); 952 driver->name = dvp->pd_name; 953 driver->methods = pci_compat_methods; 954 driver->softc = sizeof(struct pci_devinfo *); 955 driver->priv = dvp; 956 devclass_add_driver(pci_devclass, driver); 957 break; 958 case MOD_UNLOAD: 959 printf("%s: module unload not supported!\n", dvp->pd_name); 960 return EOPNOTSUPP; 961 default: 962 break; 963 } 964 return 0; 965} 966 967/* 968 * New style pci driver. Parent device is either a pci-host-bridge or a 969 * pci-pci-bridge. Both kinds are represented by instances of pcib. 970 */ 971 972static void 973pci_print_verbose(struct pci_devinfo *dinfo) 974{ 975 if (bootverbose) { 976 int i; 977 pcicfgregs *cfg = &dinfo->cfg; 978 979 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 980 cfg->vendor, cfg->device, cfg->revid); 981 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 982 cfg->baseclass, cfg->subclass, cfg->progif, 983 cfg->hdrtype, cfg->mfdev); 984 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 985 cfg->subordinatebus, cfg->secondarybus); 986#ifdef PCI_DEBUG 987 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 988 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 989 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 990 cfg->lattimer, cfg->lattimer * 30, 991 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 992#endif /* PCI_DEBUG */ 993 if (cfg->intpin > 0) 994 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 995 996 for (i = 0; i < cfg->nummaps; i++) { 997 pcimap *m = &cfg->map[i]; 998 printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n", 999 i, m->type, m->ln2range, m->base, m->ln2size); 1000 } 1001 } 1002} 1003 1004static int 1005pci_add_children(device_t dev, int busno) 1006{ 1007 pcicfgregs probe; 1008 int bushigh = busno; 1009 1010#ifdef SIMOS 1011#undef PCI_SLOTMAX 1012#define PCI_SLOTMAX 0 1013#endif 1014 1015 bzero(&probe, sizeof probe); 1016#ifdef __alpha__ 1017 probe.hose = pcib_get_hose(dev); 1018#endif 1019#ifdef __i386__ 1020 probe.hose = 0; 1021#endif 1022 probe.bus = busno; 1023 1024 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) { 1025 int pcifunchigh = 0; 1026 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) { 1027 struct pci_devinfo *dinfo = pci_readcfg(&probe); 1028 if (dinfo != NULL) { 1029 if (dinfo->cfg.mfdev) 1030 pcifunchigh = 7; 1031 1032 pci_print_verbose(dinfo); 1033 dinfo->cfg.dev = 1034 device_add_child(dev, NULL, -1, dinfo); 1035 1036 if (bushigh < dinfo->cfg.subordinatebus) 1037 bushigh = dinfo->cfg.subordinatebus; 1038 if (bushigh < dinfo->cfg.secondarybus) 1039 bushigh = dinfo->cfg.secondarybus; 1040 } 1041 } 1042 } 1043 1044 return bushigh; 1045} 1046 1047static int 1048pci_new_probe(device_t dev) 1049{ 1050 device_set_desc(dev, "PCI bus"); 1051 1052 pci_add_children(dev, device_get_unit(dev)); 1053 1054 return 0; 1055} 1056 1057static void 1058pci_print_child(device_t dev, device_t child) 1059{ 1060 struct pci_devinfo *dinfo; 1061 pcicfgregs *cfg; 1062 1063 dinfo = device_get_ivars(child); 1064 cfg = &dinfo->cfg; 1065 if (cfg->intpin > 0 && cfg->intline != 255) 1066 printf(" irq %d", cfg->intline); 1067 printf(" at device %d.%d", pci_get_slot(child), pci_get_function(child)); 1068 printf(" on %s%d", device_get_name(dev), device_get_unit(dev)); 1069} 1070 1071static int 1072pci_read_ivar(device_t dev, device_t child, int which, u_long *result) 1073{ 1074 struct pci_devinfo *dinfo; 1075 pcicfgregs *cfg; 1076 1077 dinfo = device_get_ivars(child); 1078 cfg = &dinfo->cfg; 1079 1080 switch (which) { 1081 case PCI_IVAR_SUBVENDOR: 1082 *result = cfg->subvendor; 1083 break; 1084 case PCI_IVAR_SUBDEVICE: 1085 *result = cfg->subdevice; 1086 break; 1087 case PCI_IVAR_VENDOR: 1088 *result = cfg->vendor; 1089 break; 1090 case PCI_IVAR_DEVICE: 1091 *result = cfg->device; 1092 break; 1093 case PCI_IVAR_DEVID: 1094 *result = (cfg->device << 16) | cfg->vendor; 1095 break; 1096 case PCI_IVAR_CLASS: 1097 *result = cfg->baseclass; 1098 break; 1099 case PCI_IVAR_SUBCLASS: 1100 *result = cfg->subclass; 1101 break; 1102 case PCI_IVAR_PROGIF: 1103 *result = cfg->progif; 1104 break; 1105 case PCI_IVAR_REVID: 1106 *result = cfg->revid; 1107 break; 1108 case PCI_IVAR_INTPIN: 1109 *result = cfg->intpin; 1110 break; 1111 case PCI_IVAR_IRQ: 1112 *result = cfg->intline; 1113 break; 1114 case PCI_IVAR_BUS: 1115 *result = cfg->bus; 1116 break; 1117 case PCI_IVAR_SLOT: 1118 *result = cfg->slot; 1119 break; 1120 case PCI_IVAR_FUNCTION: 1121 *result = cfg->func; 1122 break; 1123 case PCI_IVAR_SECONDARYBUS: 1124 *result = cfg->secondarybus; 1125 break; 1126 case PCI_IVAR_SUBORDINATEBUS: 1127 *result = cfg->subordinatebus; 1128 break; 1129 case PCI_IVAR_HOSE: 1130 /* 1131 * Pass up to parent bridge. 1132 */ 1133 *result = pcib_get_hose(dev); 1134 break; 1135 default: 1136 return ENOENT; 1137 } 1138 return 0; 1139} 1140 1141static int 1142pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1143{ 1144 struct pci_devinfo *dinfo; 1145 pcicfgregs *cfg; 1146 1147 dinfo = device_get_ivars(child); 1148 cfg = &dinfo->cfg; 1149 1150 switch (which) { 1151 case PCI_IVAR_SUBVENDOR: 1152 case PCI_IVAR_SUBDEVICE: 1153 case PCI_IVAR_VENDOR: 1154 case PCI_IVAR_DEVICE: 1155 case PCI_IVAR_DEVID: 1156 case PCI_IVAR_CLASS: 1157 case PCI_IVAR_SUBCLASS: 1158 case PCI_IVAR_PROGIF: 1159 case PCI_IVAR_REVID: 1160 case PCI_IVAR_INTPIN: 1161 case PCI_IVAR_IRQ: 1162 case PCI_IVAR_BUS: 1163 case PCI_IVAR_SLOT: 1164 case PCI_IVAR_FUNCTION: 1165 return EINVAL; /* disallow for now */ 1166 1167 case PCI_IVAR_SECONDARYBUS: 1168 cfg->secondarybus = value; 1169 break; 1170 case PCI_IVAR_SUBORDINATEBUS: 1171 cfg->subordinatebus = value; 1172 break; 1173 default: 1174 return ENOENT; 1175 } 1176 return 0; 1177} 1178 1179static int 1180pci_mapno(pcicfgregs *cfg, int reg) 1181{ 1182 int i, nummaps; 1183 pcimap *map; 1184 1185 nummaps = cfg->nummaps; 1186 map = cfg->map; 1187 1188 for (i = 0; i < nummaps; i++) 1189 if (map[i].reg == reg) 1190 return (i); 1191 return (-1); 1192} 1193 1194static int 1195pci_porten(pcicfgregs *cfg) 1196{ 1197 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0); 1198} 1199 1200static int 1201pci_isportmap(pcicfgregs *cfg, int map) 1202 1203{ 1204 return ((unsigned)map < cfg->nummaps 1205 && (cfg->map[map].type & PCI_MAPPORT) != 0); 1206} 1207 1208static int 1209pci_memen(pcicfgregs *cfg) 1210{ 1211 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0); 1212} 1213 1214static int 1215pci_ismemmap(pcicfgregs *cfg, int map) 1216{ 1217 return ((unsigned)map < cfg->nummaps 1218 && (cfg->map[map].type & PCI_MAPMEM) != 0); 1219} 1220 1221static struct resource * 1222pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1223 u_long start, u_long end, u_long count, u_int flags) 1224{ 1225 int isdefault; 1226 struct pci_devinfo *dinfo = device_get_ivars(child); 1227 pcicfgregs *cfg = &dinfo->cfg; 1228 struct resource *rv, **rvp = 0; 1229 int map; 1230 1231 isdefault = (device_get_parent(child) == dev 1232 && start == 0UL && end == ~0UL); 1233 1234 switch (type) { 1235 case SYS_RES_IRQ: 1236 if (*rid != 0) 1237 return 0; 1238 if (isdefault && cfg->intline != 255) { 1239 start = cfg->intline; 1240 end = cfg->intline; 1241 count = 1; 1242 } 1243 break; 1244 1245 case SYS_RES_DRQ: /* passthru for child isa */ 1246 break; 1247 1248 case SYS_RES_MEMORY: 1249 if (isdefault) { 1250 map = pci_mapno(cfg, *rid); 1251 if (pci_memen(cfg) && pci_ismemmap(cfg, map)) { 1252 start = cfg->map[map].base; 1253 count = 1 << cfg->map[map].ln2size; 1254 end = start + count; 1255 rvp = &cfg->map[map].res; 1256 } else 1257 return 0; 1258 } 1259 break; 1260 1261 case SYS_RES_IOPORT: 1262 if (isdefault) { 1263 map = pci_mapno(cfg, *rid); 1264 if (pci_porten(cfg) && pci_isportmap(cfg, map)) { 1265 start = cfg->map[map].base; 1266 count = 1 << cfg->map[map].ln2size; 1267 end = start + count; 1268 rvp = &cfg->map[map].res; 1269 } else 1270 return 0; 1271 } 1272 break; 1273 1274 default: 1275 return 0; 1276 } 1277 1278 rv = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 1279 type, rid, start, end, count, flags); 1280 if (rvp) 1281 *rvp = rv; 1282 1283 return rv; 1284} 1285 1286static int 1287pci_release_resource(device_t dev, device_t child, int type, int rid, 1288 struct resource *r) 1289{ 1290 int rv; 1291 struct pci_devinfo *dinfo = device_get_ivars(child); 1292 pcicfgregs *cfg = &dinfo->cfg; 1293 int map = 0; 1294 1295 switch (type) { 1296 case SYS_RES_IRQ: 1297 if (rid != 0) 1298 return EINVAL; 1299 break; 1300 1301 case SYS_RES_DRQ: /* passthru for child isa */ 1302 break; 1303 1304 case SYS_RES_MEMORY: 1305 case SYS_RES_IOPORT: 1306 /* 1307 * Only check the map registers if this is a direct 1308 * descendant. 1309 */ 1310 if (device_get_parent(child) == dev) 1311 map = pci_mapno(cfg, rid); 1312 else 1313 map = -1; 1314 break; 1315 1316 default: 1317 return (ENOENT); 1318 } 1319 1320 rv = BUS_RELEASE_RESOURCE(device_get_parent(dev), child, type, rid, r); 1321 1322 if (rv == 0) { 1323 switch (type) { 1324 case SYS_RES_IRQ: 1325 cfg->irqres = 0; 1326 break; 1327 1328 case SYS_RES_DRQ: /* passthru for child isa */ 1329 break; 1330 1331 case SYS_RES_MEMORY: 1332 case SYS_RES_IOPORT: 1333 if (map != -1) 1334 cfg->map[map].res = 0; 1335 break; 1336 1337 default: 1338 return ENOENT; 1339 } 1340 } 1341 1342 return rv; 1343} 1344 1345static u_int32_t 1346pci_read_config_method(device_t dev, device_t child, int reg, int width) 1347{ 1348 struct pci_devinfo *dinfo = device_get_ivars(child); 1349 pcicfgregs *cfg = &dinfo->cfg; 1350 return pci_cfgread(cfg, reg, width); 1351} 1352 1353static void 1354pci_write_config_method(device_t dev, device_t child, int reg, 1355 u_int32_t val, int width) 1356{ 1357 struct pci_devinfo *dinfo = device_get_ivars(child); 1358 pcicfgregs *cfg = &dinfo->cfg; 1359 pci_cfgwrite(cfg, reg, val, width); 1360} 1361 1362static int 1363pci_modevent(module_t mod, int what, void *arg) 1364{ 1365 switch (what) { 1366 case MOD_LOAD: 1367 STAILQ_INIT(&pci_devq); 1368 break; 1369 1370 case MOD_UNLOAD: 1371 break; 1372 } 1373 1374 return 0; 1375} 1376 1377static device_method_t pci_methods[] = { 1378 /* Device interface */ 1379 DEVMETHOD(device_probe, pci_new_probe), 1380 DEVMETHOD(device_attach, bus_generic_attach), 1381 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1382 DEVMETHOD(device_suspend, bus_generic_suspend), 1383 DEVMETHOD(device_resume, bus_generic_resume), 1384 1385 /* Bus interface */ 1386 DEVMETHOD(bus_print_child, pci_print_child), 1387 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1388 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1389 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1390 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1391 DEVMETHOD(bus_release_resource, pci_release_resource), 1392 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1393 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1394 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1395 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1396 1397 /* PCI interface */ 1398 DEVMETHOD(pci_read_config, pci_read_config_method), 1399 DEVMETHOD(pci_write_config, pci_write_config_method), 1400 1401 { 0, 0 } 1402}; 1403 1404static driver_t pci_driver = { 1405 "pci", 1406 pci_methods, 1407 1, /* no softc */ 1408}; 1409 1410DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1411 1412#endif /* NPCI > 0 */ 1413