pci.c revision 46023
1239160Sjilles/* 2239160Sjilles * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3239160Sjilles * All rights reserved. 4239160Sjilles * 5239160Sjilles * Redistribution and use in source and binary forms, with or without 6239160Sjilles * modification, are permitted provided that the following conditions 7239160Sjilles * are met: 8239160Sjilles * 1. Redistributions of source code must retain the above copyright 9239160Sjilles * notice unmodified, this list of conditions, and the following 10239160Sjilles * disclaimer. 11239160Sjilles * 2. Redistributions in binary form must reproduce the above copyright 12239160Sjilles * notice, this list of conditions and the following disclaimer in the 13239160Sjilles * documentation and/or other materials provided with the distribution. 14239160Sjilles * 15239160Sjilles * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16239160Sjilles * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17239160Sjilles * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18239160Sjilles * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19239160Sjilles * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20239160Sjilles * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21239160Sjilles * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22239160Sjilles * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23239160Sjilles * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24239160Sjilles * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25239160Sjilles * 26239160Sjilles * $Id: pci.c,v 1.95 1999/04/16 21:22:52 peter Exp $ 27239160Sjilles * 28239160Sjilles */ 29239160Sjilles 30239160Sjilles#include "opt_bus.h" 31239160Sjilles 32239160Sjilles#include "pci.h" 33239160Sjilles#if NPCI > 0 34239160Sjilles 35239160Sjilles#include "opt_devfs.h" 36239160Sjilles#include "opt_simos.h" 37253403Skevlo 38239160Sjilles#include <sys/param.h> 39239160Sjilles#include <sys/systm.h> 40239160Sjilles#include <sys/malloc.h> 41239160Sjilles#include <sys/module.h> 42239160Sjilles#include <sys/fcntl.h> 43239160Sjilles#include <sys/conf.h> 44239160Sjilles#include <sys/kernel.h> 45253403Skevlo#include <sys/queue.h> 46239160Sjilles#include <sys/types.h> 47239160Sjilles#include <sys/buf.h> 48239160Sjilles#ifdef DEVFS 49239160Sjilles#include <sys/devfsext.h> 50239160Sjilles#endif /* DEVFS */ 51239160Sjilles 52239160Sjilles#include <vm/vm.h> 53239160Sjilles#include <vm/pmap.h> 54239160Sjilles#include <vm/vm_extern.h> 55239160Sjilles 56239160Sjilles#include <sys/bus.h> 57239160Sjilles#include <machine/bus.h> 58239160Sjilles#include <sys/rman.h> 59239160Sjilles#include <machine/resource.h> 60239160Sjilles 61239160Sjilles#include <pci/pcireg.h> 62239160Sjilles#include <pci/pcivar.h> 63239160Sjilles#include <pci/pci_ioctl.h> 64239160Sjilles 65239160Sjilles#ifdef APIC_IO 66239160Sjilles#include <machine/smp.h> 67239160Sjilles#endif /* APIC_IO */ 68239160Sjilles 69239160Sjillesstatic STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 70239160Sjillesu_int32_t pci_numdevs = 0; 71239160Sjillesstatic u_int32_t pci_generation = 0; 72239160Sjilles 73239160Sjilles/* return highest PCI bus number known to be used, or -1 if none */ 74239160Sjilles 75239160Sjillesstatic int 76239160Sjillespci_bushigh(void) 77239160Sjilles{ 78239160Sjilles if (pci_cfgopen() == 0) 79239160Sjilles return (-1); 80239160Sjilles return (0); 81239160Sjilles} 82239160Sjilles 83239160Sjilles/* return base address of memory or port map */ 84239160Sjilles 85239160Sjillesstatic int 86239160Sjillespci_mapbase(unsigned mapreg) 87239160Sjilles{ 88239160Sjilles int mask = 0x03; 89239160Sjilles if ((mapreg & 0x01) == 0) 90239160Sjilles mask = 0x0f; 91239160Sjilles return (mapreg & ~mask); 92239160Sjilles} 93239160Sjilles 94239160Sjilles/* return map type of memory or port map */ 95239160Sjilles 96239160Sjillesstatic int 97239160Sjillespci_maptype(unsigned mapreg) 98239160Sjilles{ 99239160Sjilles static u_int8_t maptype[0x10] = { 100239160Sjilles PCI_MAPMEM, PCI_MAPPORT, 101239160Sjilles PCI_MAPMEM, 0, 102239160Sjilles PCI_MAPMEM, PCI_MAPPORT, 103239160Sjilles 0, 0, 104239160Sjilles PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 105239160Sjilles PCI_MAPMEM|PCI_MAPMEMP, 0, 106239160Sjilles PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 107239160Sjilles 0, 0, 108239160Sjilles }; 109239160Sjilles 110239160Sjilles return maptype[mapreg & 0x0f]; 111239160Sjilles} 112239160Sjilles 113239160Sjilles/* return log2 of map size decoded for memory or port map */ 114239160Sjilles 115239160Sjillesstatic int 116239160Sjillespci_mapsize(unsigned testval) 117239160Sjilles{ 118239160Sjilles int ln2size; 119239160Sjilles 120239160Sjilles testval = pci_mapbase(testval); 121239160Sjilles ln2size = 0; 122239160Sjilles if (testval != 0) { 123239160Sjilles while ((testval & 1) == 0) 124239160Sjilles { 125239160Sjilles ln2size++; 126239160Sjilles testval >>= 1; 127239160Sjilles } 128239160Sjilles } 129239160Sjilles return (ln2size); 130239160Sjilles} 131239160Sjilles 132239160Sjilles/* return log2 of address range supported by map register */ 133239160Sjilles 134239160Sjillesstatic int 135239160Sjillespci_maprange(unsigned mapreg) 136239160Sjilles{ 137239160Sjilles int ln2range = 0; 138239160Sjilles switch (mapreg & 0x07) { 139239160Sjilles case 0x00: 140239160Sjilles case 0x01: 141239160Sjilles case 0x05: 142239160Sjilles ln2range = 32; 143239160Sjilles break; 144 case 0x02: 145 ln2range = 20; 146 break; 147 case 0x04: 148 ln2range = 64; 149 break; 150 } 151 return (ln2range); 152} 153 154/* extract map parameters into newly allocated array of pcimap structures */ 155 156static pcimap * 157pci_readmaps(pcicfgregs *cfg, int maxmaps) 158{ 159 int i, j = 0; 160 pcimap *map; 161 int map64 = 0; 162 int reg = PCIR_MAPS; 163 164 for (i = 0; i < maxmaps; i++) { 165 int reg = PCIR_MAPS + i*4; 166 u_int32_t base; 167 u_int32_t ln2range; 168 169 base = pci_cfgread(cfg, reg, 4); 170 ln2range = pci_maprange(base); 171 172 if (base == 0 || ln2range == 0 || base == 0xffffffff) 173 continue; /* skip invalid entry */ 174 else { 175 j++; 176 if (ln2range > 32) { 177 i++; 178 j++; 179 } 180 } 181 } 182 183 map = malloc(j * sizeof (pcimap), M_DEVBUF, M_WAITOK); 184 if (map != NULL) { 185 bzero(map, sizeof(pcimap) * j); 186 cfg->nummaps = j; 187 188 for (i = 0, j = 0; i < maxmaps; i++, reg += 4) { 189 u_int32_t base; 190 u_int32_t testval; 191 192 base = pci_cfgread(cfg, reg, 4); 193 194 if (map64 == 0) { 195 if (base == 0 || base == 0xffffffff) 196 continue; /* skip invalid entry */ 197 pci_cfgwrite(cfg, reg, 0xffffffff, 4); 198 testval = pci_cfgread(cfg, reg, 4); 199 pci_cfgwrite(cfg, reg, base, 4); 200 201 map[j].reg = reg; 202 map[j].base = pci_mapbase(base); 203 map[j].type = pci_maptype(base); 204 map[j].ln2size = pci_mapsize(testval); 205 map[j].ln2range = pci_maprange(testval); 206 map64 = map[j].ln2range == 64; 207 } else { 208 /* only fill in base, other fields are 0 */ 209 map[j].base = base; 210 map64 = 0; 211 } 212 j++; 213 } 214 } 215 return (map); 216} 217 218/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 219 220static void 221pci_fixancient(pcicfgregs *cfg) 222{ 223 if (cfg->hdrtype != 0) 224 return; 225 226 /* PCI to PCI bridges use header type 1 */ 227 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 228 cfg->hdrtype = 1; 229} 230 231/* read config data specific to header type 1 device (PCI to PCI bridge) */ 232 233static void * 234pci_readppb(pcicfgregs *cfg) 235{ 236 pcih1cfgregs *p; 237 238 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK); 239 if (p == NULL) 240 return (NULL); 241 242 bzero(p, sizeof *p); 243 244 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2); 245 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2); 246 247 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1); 248 249 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2), 250 pci_cfgread(cfg, PCIR_IOBASEL_1, 1)); 251 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2), 252 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1)); 253 254 p->membase = PCI_PPBMEMBASE (0, 255 pci_cfgread(cfg, PCIR_MEMBASE_1, 2)); 256 p->memlimit = PCI_PPBMEMLIMIT (0, 257 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2)); 258 259 p->pmembase = PCI_PPBMEMBASE ( 260 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4), 261 pci_cfgread(cfg, PCIR_PMBASEL_1, 2)); 262 263 p->pmemlimit = PCI_PPBMEMLIMIT ( 264 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4), 265 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2)); 266 return (p); 267} 268 269/* read config data specific to header type 2 device (PCI to CardBus bridge) */ 270 271static void * 272pci_readpcb(pcicfgregs *cfg) 273{ 274 pcih2cfgregs *p; 275 276 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK); 277 if (p == NULL) 278 return (NULL); 279 280 bzero(p, sizeof *p); 281 282 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2); 283 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2); 284 285 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1); 286 287 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4); 288 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4); 289 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4); 290 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4); 291 292 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4); 293 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4); 294 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4); 295 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4); 296 297 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4); 298 return p; 299} 300 301/* extract header type specific config data */ 302 303static void 304pci_hdrtypedata(pcicfgregs *cfg) 305{ 306 switch (cfg->hdrtype) { 307 case 0: 308 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2); 309 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2); 310 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_0); 311 break; 312 case 1: 313 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2); 314 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2); 315 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1); 316 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1); 317 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_1); 318 cfg->hdrspec = pci_readppb(cfg); 319 break; 320 case 2: 321 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2); 322 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2); 323 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1); 324 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1); 325 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_2); 326 cfg->hdrspec = pci_readpcb(cfg); 327 break; 328 } 329} 330 331/* read configuration header into pcicfgrect structure */ 332 333static struct pci_devinfo * 334pci_readcfg(pcicfgregs *probe) 335{ 336 pcicfgregs *cfg = NULL; 337 struct pci_devinfo *devlist_entry; 338 struct devlist *devlist_head; 339 340 devlist_head = &pci_devq; 341 342 devlist_entry = NULL; 343 344 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) { 345 devlist_entry = malloc(sizeof(struct pci_devinfo), 346 M_DEVBUF, M_WAITOK); 347 if (devlist_entry == NULL) 348 return (NULL); 349 bzero(devlist_entry, sizeof *devlist_entry); 350 351 cfg = &devlist_entry->cfg; 352 353 cfg->bus = probe->bus; 354 cfg->slot = probe->slot; 355 cfg->func = probe->func; 356 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2); 357 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2); 358 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2); 359 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2); 360 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1); 361 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1); 362 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1); 363 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1); 364 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1); 365 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1); 366 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1); 367 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1); 368 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1); 369#ifdef __alpha__ 370 alpha_platform_assign_pciintr(cfg); 371#endif 372 373#ifdef APIC_IO 374 if (cfg->intpin != 0) { 375 int airq; 376 377 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 378 if (airq >= 0) { 379 /* PCI specific entry found in MP table */ 380 if (airq != cfg->intline) { 381 undirect_pci_irq(cfg->intline); 382 cfg->intline = airq; 383 } 384 } else { 385 /* 386 * PCI interrupts might be redirected to the 387 * ISA bus according to some MP tables. Use the 388 * same methods as used by the ISA devices 389 * devices to find the proper IOAPIC int pin. 390 */ 391 airq = isa_apic_irq(cfg->intline); 392 if ((airq >= 0) && (airq != cfg->intline)) { 393 /* XXX: undirect_pci_irq() ? */ 394 undirect_isa_irq(cfg->intline); 395 cfg->intline = airq; 396 } 397 } 398 } 399#endif /* APIC_IO */ 400 401 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1); 402 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1); 403 404 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 405 cfg->hdrtype &= ~PCIM_MFDEV; 406 407 pci_fixancient(cfg); 408 pci_hdrtypedata(cfg); 409 410 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 411 412 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 413 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 414 devlist_entry->conf.pc_sel.pc_func = cfg->func; 415 devlist_entry->conf.pc_hdr = cfg->hdrtype; 416 417 devlist_entry->conf.pc_subvendor = cfg->subvendor; 418 devlist_entry->conf.pc_subdevice = cfg->subdevice; 419 devlist_entry->conf.pc_vendor = cfg->vendor; 420 devlist_entry->conf.pc_device = cfg->device; 421 422 devlist_entry->conf.pc_class = cfg->baseclass; 423 devlist_entry->conf.pc_subclass = cfg->subclass; 424 devlist_entry->conf.pc_progif = cfg->progif; 425 devlist_entry->conf.pc_revid = cfg->revid; 426 427 pci_numdevs++; 428 pci_generation++; 429 } 430 return (devlist_entry); 431} 432 433#if 0 434/* free pcicfgregs structure and all depending data structures */ 435 436static int 437pci_freecfg(struct pci_devinfo *dinfo) 438{ 439 struct devlist *devlist_head; 440 441 devlist_head = &pci_devq; 442 443 if (dinfo->cfg.hdrspec != NULL) 444 free(dinfo->cfg.hdrspec, M_DEVBUF); 445 if (dinfo->cfg.map != NULL) 446 free(dinfo->cfg.map, M_DEVBUF); 447 /* XXX this hasn't been tested */ 448 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 449 free(dinfo, M_DEVBUF); 450 451 /* increment the generation count */ 452 pci_generation++; 453 454 /* we're losing one device */ 455 pci_numdevs--; 456 return (0); 457} 458#endif 459 460/* 461 * This is the user interface to PCI configuration space. 462 */ 463 464static int 465pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 466{ 467 if ((oflags & FWRITE) && securelevel > 0) { 468 return EPERM; 469 } 470 return 0; 471} 472 473static int 474pci_close(dev_t dev, int flag, int devtype, struct proc *p) 475{ 476 return 0; 477} 478 479/* 480 * Match a single pci_conf structure against an array of pci_match_conf 481 * structures. The first argument, 'matches', is an array of num_matches 482 * pci_match_conf structures. match_buf is a pointer to the pci_conf 483 * structure that will be compared to every entry in the matches array. 484 * This function returns 1 on failure, 0 on success. 485 */ 486static int 487pci_conf_match(struct pci_match_conf *matches, int num_matches, 488 struct pci_conf *match_buf) 489{ 490 int i; 491 492 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 493 return(1); 494 495 for (i = 0; i < num_matches; i++) { 496 /* 497 * I'm not sure why someone would do this...but... 498 */ 499 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 500 continue; 501 502 /* 503 * Look at each of the match flags. If it's set, do the 504 * comparison. If the comparison fails, we don't have a 505 * match, go on to the next item if there is one. 506 */ 507 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 508 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 509 continue; 510 511 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 512 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 513 continue; 514 515 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 516 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 517 continue; 518 519 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 520 && (match_buf->pc_vendor != matches[i].pc_vendor)) 521 continue; 522 523 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 524 && (match_buf->pc_device != matches[i].pc_device)) 525 continue; 526 527 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 528 && (match_buf->pc_class != matches[i].pc_class)) 529 continue; 530 531 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 532 && (match_buf->pd_unit != matches[i].pd_unit)) 533 continue; 534 535 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 536 && (strncmp(matches[i].pd_name, match_buf->pd_name, 537 sizeof(match_buf->pd_name)) != 0)) 538 continue; 539 540 return(0); 541 } 542 543 return(1); 544} 545 546static int 547pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 548{ 549 struct pci_io *io; 550 int error; 551 552 if (!(flag & FWRITE)) 553 return EPERM; 554 555 556 switch(cmd) { 557 case PCIOCGETCONF: 558 { 559 struct pci_devinfo *dinfo; 560 struct pci_conf_io *cio; 561 struct devlist *devlist_head; 562 struct pci_match_conf *pattern_buf; 563 int num_patterns; 564 size_t iolen; 565 int ionum, i; 566 567 cio = (struct pci_conf_io *)data; 568 569 num_patterns = 0; 570 dinfo = NULL; 571 572 /* 573 * Hopefully the user won't pass in a null pointer, but it 574 * can't hurt to check. 575 */ 576 if (cio == NULL) { 577 error = EINVAL; 578 break; 579 } 580 581 /* 582 * If the user specified an offset into the device list, 583 * but the list has changed since they last called this 584 * ioctl, tell them that the list has changed. They will 585 * have to get the list from the beginning. 586 */ 587 if ((cio->offset != 0) 588 && (cio->generation != pci_generation)){ 589 cio->num_matches = 0; 590 cio->status = PCI_GETCONF_LIST_CHANGED; 591 error = 0; 592 break; 593 } 594 595 /* 596 * Check to see whether the user has asked for an offset 597 * past the end of our list. 598 */ 599 if (cio->offset >= pci_numdevs) { 600 cio->num_matches = 0; 601 cio->status = PCI_GETCONF_LAST_DEVICE; 602 error = 0; 603 break; 604 } 605 606 /* get the head of the device queue */ 607 devlist_head = &pci_devq; 608 609 /* 610 * Determine how much room we have for pci_conf structures. 611 * Round the user's buffer size down to the nearest 612 * multiple of sizeof(struct pci_conf) in case the user 613 * didn't specify a multiple of that size. 614 */ 615 iolen = min(cio->match_buf_len - 616 (cio->match_buf_len % sizeof(struct pci_conf)), 617 pci_numdevs * sizeof(struct pci_conf)); 618 619 /* 620 * Since we know that iolen is a multiple of the size of 621 * the pciconf union, it's okay to do this. 622 */ 623 ionum = iolen / sizeof(struct pci_conf); 624 625 /* 626 * If this test is true, the user wants the pci_conf 627 * structures returned to match the supplied entries. 628 */ 629 if ((cio->num_patterns > 0) 630 && (cio->pat_buf_len > 0)) { 631 /* 632 * pat_buf_len needs to be: 633 * num_patterns * sizeof(struct pci_match_conf) 634 * While it is certainly possible the user just 635 * allocated a large buffer, but set the number of 636 * matches correctly, it is far more likely that 637 * their kernel doesn't match the userland utility 638 * they're using. It's also possible that the user 639 * forgot to initialize some variables. Yes, this 640 * may be overly picky, but I hazard to guess that 641 * it's far more likely to just catch folks that 642 * updated their kernel but not their userland. 643 */ 644 if ((cio->num_patterns * 645 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 646 /* The user made a mistake, return an error*/ 647 cio->status = PCI_GETCONF_ERROR; 648 printf("pci_ioctl: pat_buf_len %d != " 649 "num_patterns (%d) * sizeof(struct " 650 "pci_match_conf) (%d)\npci_ioctl: " 651 "pat_buf_len should be = %d\n", 652 cio->pat_buf_len, cio->num_patterns, 653 (int)sizeof(struct pci_match_conf), 654 (int)sizeof(struct pci_match_conf) * 655 cio->num_patterns); 656 printf("pci_ioctl: do your headers match your " 657 "kernel?\n"); 658 cio->num_matches = 0; 659 error = EINVAL; 660 break; 661 } 662 663 /* 664 * Check the user's buffer to make sure it's readable. 665 */ 666 if ((error = useracc((caddr_t)cio->patterns, 667 cio->pat_buf_len, B_READ)) != 1){ 668 printf("pci_ioctl: pattern buffer %p, " 669 "length %u isn't user accessible for" 670 " READ\n", cio->patterns, 671 cio->pat_buf_len); 672 error = EACCES; 673 break; 674 } 675 /* 676 * Allocate a buffer to hold the patterns. 677 */ 678 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 679 M_WAITOK); 680 error = copyin(cio->patterns, pattern_buf, 681 cio->pat_buf_len); 682 if (error != 0) 683 break; 684 num_patterns = cio->num_patterns; 685 686 } else if ((cio->num_patterns > 0) 687 || (cio->pat_buf_len > 0)) { 688 /* 689 * The user made a mistake, spit out an error. 690 */ 691 cio->status = PCI_GETCONF_ERROR; 692 cio->num_matches = 0; 693 printf("pci_ioctl: invalid GETCONF arguments\n"); 694 error = EINVAL; 695 break; 696 } else 697 pattern_buf = NULL; 698 699 /* 700 * Make sure we can write to the match buffer. 701 */ 702 if ((error = useracc((caddr_t)cio->matches, cio->match_buf_len, 703 B_WRITE)) != 1) { 704 printf("pci_ioctl: match buffer %p, length %u " 705 "isn't user accessible for WRITE\n", 706 cio->matches, cio->match_buf_len); 707 error = EACCES; 708 break; 709 } 710 711 /* 712 * Go through the list of devices and copy out the devices 713 * that match the user's criteria. 714 */ 715 for (cio->num_matches = 0, error = 0, i = 0, 716 dinfo = STAILQ_FIRST(devlist_head); 717 (dinfo != NULL) && (cio->num_matches < ionum) 718 && (error == 0) && (i < pci_numdevs); 719 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 720 721 if (i < cio->offset) 722 continue; 723 724 if ((pattern_buf == NULL) || 725 (pci_conf_match(pattern_buf, num_patterns, 726 &dinfo->conf) == 0)) { 727 728 /* 729 * If we've filled up the user's buffer, 730 * break out at this point. Since we've 731 * got a match here, we'll pick right back 732 * up at the matching entry. We can also 733 * tell the user that there are more matches 734 * left. 735 */ 736 if (cio->num_matches >= ionum) 737 break; 738 739 error = copyout(&dinfo->conf, 740 &cio->matches[cio->num_matches], 741 sizeof(struct pci_conf)); 742 cio->num_matches++; 743 } 744 } 745 746 /* 747 * Set the pointer into the list, so if the user is getting 748 * n records at a time, where n < pci_numdevs, 749 */ 750 cio->offset = i; 751 752 /* 753 * Set the generation, the user will need this if they make 754 * another ioctl call with offset != 0. 755 */ 756 cio->generation = pci_generation; 757 758 /* 759 * If this is the last device, inform the user so he won't 760 * bother asking for more devices. If dinfo isn't NULL, we 761 * know that there are more matches in the list because of 762 * the way the traversal is done. 763 */ 764 if (dinfo == NULL) 765 cio->status = PCI_GETCONF_LAST_DEVICE; 766 else 767 cio->status = PCI_GETCONF_MORE_DEVS; 768 769 if (pattern_buf != NULL) 770 free(pattern_buf, M_TEMP); 771 772 break; 773 } 774 case PCIOCREAD: 775 io = (struct pci_io *)data; 776 switch(io->pi_width) { 777 pcicfgregs probe; 778 case 4: 779 case 2: 780 case 1: 781 probe.bus = io->pi_sel.pc_bus; 782 probe.slot = io->pi_sel.pc_dev; 783 probe.func = io->pi_sel.pc_func; 784 io->pi_data = pci_cfgread(&probe, 785 io->pi_reg, io->pi_width); 786 error = 0; 787 break; 788 default: 789 error = ENODEV; 790 break; 791 } 792 break; 793 794 case PCIOCWRITE: 795 io = (struct pci_io *)data; 796 switch(io->pi_width) { 797 pcicfgregs probe; 798 case 4: 799 case 2: 800 case 1: 801 probe.bus = io->pi_sel.pc_bus; 802 probe.slot = io->pi_sel.pc_dev; 803 probe.func = io->pi_sel.pc_func; 804 pci_cfgwrite(&probe, 805 io->pi_reg, io->pi_data, io->pi_width); 806 error = 0; 807 break; 808 default: 809 error = ENODEV; 810 break; 811 } 812 break; 813 814 default: 815 error = ENOTTY; 816 break; 817 } 818 819 return (error); 820} 821 822#define PCI_CDEV 78 823 824static struct cdevsw pcicdev = { 825 pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset, 826 nodevtotty, seltrue, nommap, nostrategy, "pci", 0, PCI_CDEV 827}; 828 829#ifdef DEVFS 830static void *pci_devfs_token; 831#endif 832 833static void 834pci_cdevinit(void *dummy) 835{ 836 dev_t dev; 837 838 dev = makedev(PCI_CDEV, 0); 839 cdevsw_add(&dev, &pcicdev, NULL); 840#ifdef DEVFS 841 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 842 UID_ROOT, GID_WHEEL, 0644, "pci"); 843#endif 844} 845 846SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 847 848#include "pci_if.h" 849 850/* 851 * A simple driver to wrap the old pci driver mechanism for back-compat. 852 */ 853 854static int 855pci_compat_probe(device_t dev) 856{ 857 struct pci_device *dvp; 858 struct pci_devinfo *dinfo; 859 pcicfgregs *cfg; 860 const char *name; 861 int error; 862 863 dinfo = device_get_ivars(dev); 864 cfg = &dinfo->cfg; 865 dvp = device_get_driver(dev)->priv; 866 867 /* 868 * Do the wrapped probe. 869 */ 870 error = ENXIO; 871 if (dvp && dvp->pd_probe) { 872 name = dvp->pd_probe(cfg, (cfg->device << 16) + cfg->vendor); 873 if (name) { 874 device_set_desc_copy(dev, name); 875 error = 0; 876 } 877 } 878 879 return error; 880} 881 882static int 883pci_compat_attach(device_t dev) 884{ 885 struct pci_device *dvp; 886 struct pci_devinfo *dinfo; 887 pcicfgregs *cfg; 888 int unit; 889 890 dinfo = device_get_ivars(dev); 891 cfg = &dinfo->cfg; 892 dvp = device_get_driver(dev)->priv; 893 894 unit = device_get_unit(dev); 895 if (unit > *dvp->pd_count) 896 *dvp->pd_count = unit; 897 if (dvp->pd_attach) 898 dvp->pd_attach(cfg, unit); 899 900 /* 901 * XXX KDM for some devices, dvp->pd_name winds up NULL. 902 * I haven't investigated enough to figure out why this 903 * would happen. 904 */ 905 if (dvp->pd_name != NULL) 906 strncpy(dinfo->conf.pd_name, dvp->pd_name, 907 sizeof(dinfo->conf.pd_name)); 908 else 909 strncpy(dinfo->conf.pd_name, "????", 910 sizeof(dinfo->conf.pd_name)); 911 dinfo->conf.pd_name[sizeof(dinfo->conf.pd_name) - 1] = 0; 912 dinfo->conf.pd_unit = unit; 913 914 return 0; 915} 916 917static device_method_t pci_compat_methods[] = { 918 /* Device interface */ 919 DEVMETHOD(device_probe, pci_compat_probe), 920 DEVMETHOD(device_attach, pci_compat_attach), 921 922 { 0, 0 } 923}; 924 925static devclass_t pci_devclass; 926 927/* 928 * Create a new style driver around each old pci driver. 929 */ 930int 931compat_pci_handler(struct moduledata *mod, int type, void *data) 932{ 933 struct pci_device *dvp = (struct pci_device *)data; 934 driver_t *driver; 935 936 switch (type) { 937 case MOD_LOAD: 938 driver = malloc(sizeof(driver_t), M_DEVBUF, M_NOWAIT); 939 if (!driver) 940 return ENOMEM; 941 bzero(driver, sizeof(driver_t)); 942 driver->name = dvp->pd_name; 943 driver->methods = pci_compat_methods; 944 driver->type = 0; /* XXX fixup in pci_map_int() */ 945 driver->softc = sizeof(struct pci_devinfo *); 946 driver->priv = dvp; 947 devclass_add_driver(pci_devclass, driver); 948 break; 949 case MOD_UNLOAD: 950 printf("%s: module unload not supported!\n", mod->name); 951 return EOPNOTSUPP; 952 default: 953 break; 954 } 955 return 0; 956} 957 958/* 959 * New style pci driver. Parent device is either a pci-host-bridge or a 960 * pci-pci-bridge. Both kinds are represented by instances of pcib. 961 */ 962 963static void 964pci_print_verbose(struct pci_devinfo *dinfo) 965{ 966 if (bootverbose) { 967 int i; 968 pcicfgregs *cfg = &dinfo->cfg; 969 970 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 971 cfg->vendor, cfg->device, cfg->revid); 972 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 973 cfg->baseclass, cfg->subclass, cfg->progif, 974 cfg->hdrtype, cfg->mfdev); 975 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 976 cfg->subordinatebus, cfg->secondarybus); 977#ifdef PCI_DEBUG 978 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 979 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 980 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 981 cfg->lattimer, cfg->lattimer * 30, 982 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 983#endif /* PCI_DEBUG */ 984 if (cfg->intpin > 0) 985 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 986 987 for (i = 0; i < cfg->nummaps; i++) { 988 pcimap *m = &cfg->map[i]; 989 printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n", 990 i, m->type, m->ln2range, m->base, m->ln2size); 991 } 992 } 993} 994 995static int 996pci_add_children(device_t dev, int busno) 997{ 998 pcicfgregs probe; 999 int bushigh = busno; 1000 1001#ifdef SIMOS 1002#undef PCI_SLOTMAX 1003#define PCI_SLOTMAX 0 1004#endif 1005 1006 bzero(&probe, sizeof probe); 1007 /* XXX KDM */ 1008 /* probe.parent = pci_bridgeto(bus); */ 1009 probe.bus = busno; 1010 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) { 1011 int pcifunchigh = 0; 1012 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) { 1013 struct pci_devinfo *dinfo = pci_readcfg(&probe); 1014 if (dinfo != NULL) { 1015 if (dinfo->cfg.mfdev) 1016 pcifunchigh = 7; 1017 1018 pci_print_verbose(dinfo); 1019 dinfo->cfg.dev = 1020 device_add_child(dev, NULL, -1, dinfo); 1021 1022 if (bushigh < dinfo->cfg.subordinatebus) 1023 bushigh = dinfo->cfg.subordinatebus; 1024 if (bushigh < dinfo->cfg.secondarybus) 1025 bushigh = dinfo->cfg.secondarybus; 1026 } 1027 } 1028 } 1029 1030 return bushigh; 1031} 1032 1033static int 1034pci_new_probe(device_t dev) 1035{ 1036 STAILQ_INIT(&pci_devq); 1037 device_set_desc(dev, "PCI bus"); 1038 1039 pci_add_children(dev, device_get_unit(dev)); 1040 1041 return 0; 1042} 1043 1044static void 1045pci_print_child(device_t dev, device_t child) 1046{ 1047 printf(" at device %d.%d", pci_get_slot(child), pci_get_function(child)); 1048 printf(" on %s%d", device_get_name(dev), device_get_unit(dev)); 1049} 1050 1051static int 1052pci_read_ivar(device_t dev, device_t child, int which, u_long *result) 1053{ 1054 struct pci_devinfo *dinfo; 1055 pcicfgregs *cfg; 1056 1057 dinfo = device_get_ivars(child); 1058 cfg = &dinfo->cfg; 1059 1060 switch (which) { 1061 case PCI_IVAR_SUBVENDOR: 1062 *result = cfg->subvendor; 1063 break; 1064 case PCI_IVAR_SUBDEVICE: 1065 *result = cfg->subdevice; 1066 break; 1067 case PCI_IVAR_VENDOR: 1068 *result = cfg->vendor; 1069 break; 1070 case PCI_IVAR_DEVICE: 1071 *result = cfg->device; 1072 break; 1073 case PCI_IVAR_DEVID: 1074 *result = (cfg->device << 16) | cfg->vendor; 1075 break; 1076 case PCI_IVAR_CLASS: 1077 *result = cfg->baseclass; 1078 break; 1079 case PCI_IVAR_SUBCLASS: 1080 *result = cfg->subclass; 1081 break; 1082 case PCI_IVAR_PROGIF: 1083 *result = cfg->progif; 1084 break; 1085 case PCI_IVAR_REVID: 1086 *result = cfg->revid; 1087 break; 1088 case PCI_IVAR_INTPIN: 1089 *result = cfg->intpin; 1090 break; 1091 case PCI_IVAR_IRQ: 1092 *result = cfg->intline; 1093 break; 1094 case PCI_IVAR_BUS: 1095 *result = cfg->bus; 1096 break; 1097 case PCI_IVAR_SLOT: 1098 *result = cfg->slot; 1099 break; 1100 case PCI_IVAR_FUNCTION: 1101 *result = cfg->func; 1102 break; 1103 case PCI_IVAR_SECONDARYBUS: 1104 *result = cfg->secondarybus; 1105 break; 1106 case PCI_IVAR_SUBORDINATEBUS: 1107 *result = cfg->subordinatebus; 1108 break; 1109 default: 1110 return ENOENT; 1111 } 1112 return 0; 1113} 1114 1115static int 1116pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1117{ 1118 struct pci_devinfo *dinfo; 1119 pcicfgregs *cfg; 1120 1121 dinfo = device_get_ivars(child); 1122 cfg = &dinfo->cfg; 1123 1124 switch (which) { 1125 case PCI_IVAR_SUBVENDOR: 1126 case PCI_IVAR_SUBDEVICE: 1127 case PCI_IVAR_VENDOR: 1128 case PCI_IVAR_DEVICE: 1129 case PCI_IVAR_DEVID: 1130 case PCI_IVAR_CLASS: 1131 case PCI_IVAR_SUBCLASS: 1132 case PCI_IVAR_PROGIF: 1133 case PCI_IVAR_REVID: 1134 case PCI_IVAR_INTPIN: 1135 case PCI_IVAR_IRQ: 1136 case PCI_IVAR_BUS: 1137 case PCI_IVAR_SLOT: 1138 case PCI_IVAR_FUNCTION: 1139 return EINVAL; /* disallow for now */ 1140 1141 case PCI_IVAR_SECONDARYBUS: 1142 cfg->secondarybus = value; 1143 break; 1144 case PCI_IVAR_SUBORDINATEBUS: 1145 cfg->subordinatebus = value; 1146 break; 1147 default: 1148 return ENOENT; 1149 } 1150 return 0; 1151} 1152 1153static int 1154pci_mapno(pcicfgregs *cfg, int reg) 1155{ 1156 int i, nummaps; 1157 pcimap *map; 1158 1159 nummaps = cfg->nummaps; 1160 map = cfg->map; 1161 1162 for (i = 0; i < nummaps; i++) 1163 if (map[i].reg == reg) 1164 return (i); 1165 return (-1); 1166} 1167 1168static int 1169pci_porten(pcicfgregs *cfg) 1170{ 1171 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0); 1172} 1173 1174static int 1175pci_isportmap(pcicfgregs *cfg, int map) 1176 1177{ 1178 return ((unsigned)map < cfg->nummaps 1179 && (cfg->map[map].type & PCI_MAPPORT) != 0); 1180} 1181 1182static int 1183pci_memen(pcicfgregs *cfg) 1184{ 1185 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0); 1186} 1187 1188static int 1189pci_ismemmap(pcicfgregs *cfg, int map) 1190{ 1191 return ((unsigned)map < cfg->nummaps 1192 && (cfg->map[map].type & PCI_MAPMEM) != 0); 1193} 1194 1195static struct resource * 1196pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1197 u_long start, u_long end, u_long count, u_int flags) 1198{ 1199 int isdefault; 1200 struct pci_devinfo *dinfo = device_get_ivars(child); 1201 pcicfgregs *cfg = &dinfo->cfg; 1202 struct resource *rv, **rvp = 0; 1203 int map; 1204 1205 isdefault = (device_get_parent(child) == dev 1206 && start == 0UL && end == ~0UL && count == 1); 1207 1208 switch (type) { 1209 case SYS_RES_IRQ: 1210 if (*rid != 0) 1211 return 0; 1212 if (isdefault && cfg->intline != 255) { 1213 start = cfg->intline; 1214 end = cfg->intline; 1215 count = 1; 1216 } 1217 break; 1218 1219 case SYS_RES_DRQ: /* passthru for child isa */ 1220 break; 1221 1222 case SYS_RES_MEMORY: 1223 if (isdefault) { 1224 map = pci_mapno(cfg, *rid); 1225 if (pci_memen(cfg) && pci_ismemmap(cfg, map)) { 1226 start = cfg->map[map].base; 1227 count = 1 << cfg->map[map].ln2size; 1228 end = start + count; 1229 rvp = &cfg->map[map].res; 1230 } else 1231 return 0; 1232 } 1233 break; 1234 1235 case SYS_RES_IOPORT: 1236 if (isdefault) { 1237 map = pci_mapno(cfg, *rid); 1238 if (pci_porten(cfg) && pci_isportmap(cfg, map)) { 1239 start = cfg->map[map].base; 1240 count = 1 << cfg->map[map].ln2size; 1241 end = start + count; 1242 rvp = &cfg->map[map].res; 1243 } else 1244 return 0; 1245 } 1246 break; 1247 1248 default: 1249 return 0; 1250 } 1251 1252 rv = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 1253 type, rid, start, end, count, flags); 1254 if (rvp) 1255 *rvp = rv; 1256 1257 return rv; 1258} 1259 1260static int 1261pci_release_resource(device_t dev, device_t child, int type, int rid, 1262 struct resource *r) 1263{ 1264 int rv; 1265 struct pci_devinfo *dinfo = device_get_ivars(child); 1266 pcicfgregs *cfg = &dinfo->cfg; 1267 int map = 0; 1268 1269 switch (type) { 1270 case SYS_RES_IRQ: 1271 if (rid != 0) 1272 return EINVAL; 1273 break; 1274 1275 case SYS_RES_DRQ: /* passthru for child isa */ 1276 break; 1277 1278 case SYS_RES_MEMORY: 1279 case SYS_RES_IOPORT: 1280 /* 1281 * Only check the map registers if this is a direct 1282 * descendant. 1283 */ 1284 if (device_get_parent(child) == dev) 1285 map = pci_mapno(cfg, rid); 1286 else 1287 map = -1; 1288 break; 1289 1290 default: 1291 return (ENOENT); 1292 } 1293 1294 rv = BUS_RELEASE_RESOURCE(device_get_parent(dev), child, type, rid, r); 1295 1296 if (rv == 0) { 1297 switch (type) { 1298 case SYS_RES_IRQ: 1299 cfg->irqres = 0; 1300 break; 1301 1302 case SYS_RES_DRQ: /* passthru for child isa */ 1303 break; 1304 1305 case SYS_RES_MEMORY: 1306 case SYS_RES_IOPORT: 1307 if (map != -1) 1308 cfg->map[map].res = 0; 1309 break; 1310 1311 default: 1312 return ENOENT; 1313 } 1314 } 1315 1316 return rv; 1317} 1318 1319static u_int32_t 1320pci_read_config_method(device_t dev, device_t child, int reg, int width) 1321{ 1322 struct pci_devinfo *dinfo = device_get_ivars(child); 1323 pcicfgregs *cfg = &dinfo->cfg; 1324 return pci_cfgread(cfg, reg, width); 1325} 1326 1327static void 1328pci_write_config_method(device_t dev, device_t child, int reg, 1329 u_int32_t val, int width) 1330{ 1331 struct pci_devinfo *dinfo = device_get_ivars(child); 1332 pcicfgregs *cfg = &dinfo->cfg; 1333 pci_cfgwrite(cfg, reg, val, width); 1334} 1335 1336static int 1337pci_modevent(module_t mod, int what, void *arg) 1338{ 1339 switch (what) { 1340 case MOD_LOAD: 1341 /* pci_wrap_old_drivers(); */ 1342 break; 1343 1344 case MOD_UNLOAD: 1345 break; 1346 } 1347 1348 return 0; 1349} 1350 1351static device_method_t pci_methods[] = { 1352 /* Device interface */ 1353 DEVMETHOD(device_probe, pci_new_probe), 1354 DEVMETHOD(device_attach, bus_generic_attach), 1355 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1356 1357 /* Bus interface */ 1358 DEVMETHOD(bus_print_child, pci_print_child), 1359 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1360 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1361 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1362 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1363 DEVMETHOD(bus_release_resource, pci_release_resource), 1364 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1365 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1366 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1367 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1368 1369 /* PCI interface */ 1370 DEVMETHOD(pci_read_config, pci_read_config_method), 1371 DEVMETHOD(pci_write_config, pci_write_config_method), 1372 1373 { 0, 0 } 1374}; 1375 1376static driver_t pci_driver = { 1377 "pci", 1378 pci_methods, 1379 DRIVER_TYPE_MISC, 1380 1, /* no softc */ 1381}; 1382 1383DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1384 1385#endif /* NPCI > 0 */ 1386