pci.c revision 25417
1/************************************************************************** 2** 3** $Id: pci.c,v 1.70 1997/04/26 11:46:18 peter Exp $ 4** 5** General subroutines for the PCI bus. 6** pci_configure () 7** 8** FreeBSD 9** 10**------------------------------------------------------------------------- 11** 12** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 13** 14** Redistribution and use in source and binary forms, with or without 15** modification, are permitted provided that the following conditions 16** are met: 17** 1. Redistributions of source code must retain the above copyright 18** notice, this list of conditions and the following disclaimer. 19** 2. Redistributions in binary form must reproduce the above copyright 20** notice, this list of conditions and the following disclaimer in the 21** documentation and/or other materials provided with the distribution. 22** 3. The name of the author may not be used to endorse or promote products 23** derived from this software without specific prior written permission. 24** 25** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35** 36*************************************************************************** 37*/ 38 39#include "pci.h" 40#if NPCI > 0 41 42/*======================================================== 43** 44** #includes and declarations 45** 46**======================================================== 47*/ 48 49#include "opt_smp.h" 50 51#include <sys/param.h> 52#include <sys/systm.h> 53#include <sys/malloc.h> 54#include <sys/errno.h> 55#include <sys/kernel.h> 56#include <sys/proc.h> /* declaration of wakeup(), used by vm.h */ 57#include <sys/conf.h> 58#ifdef DEVFS 59#include <sys/devfsext.h> 60#endif /* DEVFS */ 61#include <sys/fcntl.h> 62 63#include <vm/vm.h> 64#include <vm/vm_param.h> 65#include <vm/pmap.h> 66 67 68#include <i386/isa/isa_device.h> /* XXX inthand2_t */ 69 70#include <pci/pcivar.h> 71#include <pci/pcireg.h> 72#include <pci/pcibus.h> 73#include <pci/pci_ioctl.h> 74 75/*======================================================== 76** 77** Structs and Functions 78** 79**======================================================== 80*/ 81 82struct pcicb { 83 struct pcicb *pcicb_next; 84 struct pcicb *pcicb_up; 85 struct pcicb *pcicb_down; 86 pcici_t pcicb_bridge; 87 88 u_char pcicb_bus; 89 u_char pcicb_subordinate; 90 u_int pcicb_mfrom; 91 u_int pcicb_mupto; 92 u_int pcicb_mamount; 93 u_short pcicb_pfrom; 94 u_short pcicb_pupto; 95 u_short pcicb_pamount; 96 u_char pcicb_bfrom; 97 u_char pcicb_bupto; 98 99 u_long pcicb_iobase; 100 u_long pcicb_iolimit; 101 u_long pcicb_membase; 102 u_long pcicb_memlimit; 103 u_long pcicb_p_membase; 104 u_long pcicb_p_memlimit; 105}; 106 107struct pci_lkm { 108 struct pci_device *dvp; 109 struct pci_lkm *next; 110}; 111 112static void 113not_supported (pcici_t tag, u_long type); 114 115static void 116pci_bus_config (void); 117 118static void 119pci_rescan (void); 120 121static void pci_attach (int bus, int dev, int func, 122 struct pci_device *dvp, const char *name); 123 124static int 125pci_bridge_config (void); 126 127static int 128pci_mfdev (int bus, int device); 129 130static void pci_remember (int bus, int dev, int func, struct pci_device *dvp); 131 132/*======================================================== 133** 134** Variables 135** 136**======================================================== 137*/ 138 139/* 140** log2 of safe burst len (in words) 141*/ 142 143unsigned pci_max_burst_len = 3; /* 2=16Byte, 3=32Byte, 4=64Byte, ... */ 144unsigned pci_mechanism = 0; 145unsigned pci_maxdevice = 0; 146unsigned pciroots = 0; /* XXX pcisupport.c increments this 147 * for the Orion host to PCI bridge 148 * UGLY hack ... :( Will be changed :) 149 */ 150/*-------------------------------------------------------- 151** 152** Local variables. 153** 154**-------------------------------------------------------- 155*/ 156 157static struct pcibus *pcibus; 158 159static int pci_conf_count; 160static int pci_info_done; 161static int pcibusmax; 162static struct pcicb *pcicb; 163 164static struct pci_conf *pci_dev_list; 165static unsigned pci_dev_list_count; 166static unsigned pci_dev_list_size; 167 168static struct pci_lkm *pci_lkm_head; 169 170/*----------------------------------------------------------------- 171** 172** The following functions are provided for the device driver 173** to read/write the configuration space. 174** 175** pci_conf_read(): 176** Read a long word from the pci configuration space. 177** Requires a tag (from pcitag) and the register 178** number (should be a long word alligned one). 179** 180** pci_conf_write(): 181** Writes a long word to the pci configuration space. 182** Requires a tag (from pcitag), the register number 183** (should be a long word alligned one), and a value. 184** 185**----------------------------------------------------------------- 186*/ 187 188u_long 189pci_conf_read (pcici_t tag, u_long reg) 190{ 191 return (pcibus->pb_read (tag, reg)); 192} 193 194void 195pci_conf_write (pcici_t tag, u_long reg, u_long data) 196{ 197 pcibus->pb_write (tag, reg, data); 198} 199 200/*======================================================== 201** 202** Subroutines for configuration. 203** 204**======================================================== 205*/ 206 207static void 208pci_register_io (struct pcicb * cb, u_int base, u_int limit) 209{ 210#ifdef PCI_BRIDGE_DEBUG 211 if (bootverbose) 212 printf ("register_io: bus=%d base=%x limit=%x\n", 213 cb->pcicb_bus, base, limit); 214#endif 215 216 if (!cb->pcicb_pfrom || base < cb->pcicb_pfrom) 217 cb->pcicb_pfrom = base; 218 if (limit > cb->pcicb_pupto) 219 cb->pcicb_pupto = limit; 220 221 /* 222 ** XXX should set bridge io mapping here 223 ** but it can be mapped in 4k blocks only, 224 ** leading to conflicts with isa/eisa .. 225 */ 226} 227 228static void 229pci_register_memory (struct pcicb * cb, u_int base, u_int limit) 230{ 231#ifdef PCI_BRIDGE_DEBUG 232 if (bootverbose) 233 printf ("register_mem: bus=%d base=%x limit=%x\n", 234 cb->pcicb_bus, base, limit); 235#endif 236 237 if (!cb->pcicb_mfrom || base < cb->pcicb_mfrom) 238 cb->pcicb_mfrom = base; 239 if (limit > cb->pcicb_mupto) 240 cb->pcicb_mupto = limit; 241 /* 242 ** set the bridges mapping 243 ** 244 ** XXX should handle the 1Mb granularity. 245 */ 246 if (cb->pcicb_bridge.tag) { 247 pci_conf_write(cb->pcicb_bridge, 248 PCI_PCI_BRIDGE_MEM_REG, 249 (cb->pcicb_memlimit & 0xffff0000) | 250 (cb->pcicb_membase >> 16)); 251 if (bootverbose) 252 printf ("\t[pci%d uses memory from %x to %x]\n", 253 cb->pcicb_bus, 254 (unsigned) cb->pcicb_membase, 255 (unsigned) cb->pcicb_memlimit); 256 } 257} 258 259/* 260** XXX This function is neither complete nor tested. 261** It's only used if the bios hasn't done it's job 262** of mapping the pci devices in the physical memory. 263*/ 264 265static u_int 266pci_memalloc (struct pcicb * cb, u_int addr, u_int size) 267{ 268 u_int result = 0, limit=0, newbase=0; 269#ifdef PCI_BRIDGE_DEBUG 270 if (bootverbose) 271 printf ("memalloc: bus=%d addr=%x size=%x ..\n", 272 cb->pcicb_bus, addr, size); 273#endif 274 275 if (!cb) goto done; 276 277 if (!cb->pcicb_membase) { 278 printf ("memalloc: bus%d: membase not set.\n", 279 cb->pcicb_bus); 280 goto done; 281 } 282 283 /* 284 ** get upper allocation limit 285 */ 286 limit = cb->pcicb_memlimit; 287 if (cb->pcicb_mfrom && cb->pcicb_mfrom <= limit) 288 limit = cb->pcicb_mfrom-1; 289 290 /* 291 ** address fixed, and impossible to allocate ? 292 */ 293 if (addr && addr+size-1 > limit) 294 goto done; 295 296 /* 297 ** get possible address 298 */ 299 300 result = addr; 301 if (!result) result = ((limit + 1) / size - 1) * size; 302 303 /* 304 ** if not local available, request from parent. 305 */ 306 307 if (result < cb->pcicb_membase) { 308 newbase = pci_memalloc (cb->pcicb_up, result, size); 309 if (newbase) cb->pcicb_membase = result; 310 else result=0; 311 } 312done: 313 if (result) 314 pci_register_memory (cb, result, result+size-1); 315 316#ifdef PCI_BRIDGE_DEBUG 317 printf ("memalloc: bus=%d addr=%x size=%x --> %x (limit=%x).\n", 318 cb->pcicb_bus, addr, size, result, limit); 319#endif 320 321 return (result); 322} 323 324/*======================================================== 325** 326** pci_bridge_config() 327** 328** Configuration of a pci bridge. 329** 330**======================================================== 331*/ 332 333static int 334pci_bridge_config (void) 335{ 336 pcici_t tag; 337 struct pcicb* parent; 338 339 tag = pcicb->pcicb_bridge; 340 if (tag.tag) { 341 342 if (!pcicb->pcicb_bus) { 343 u_int data; 344 /* 345 ** Get the lowest available bus number. 346 */ 347 pcicb->pcicb_bus = ++pcibusmax; 348 349 /* 350 ** and configure the bridge 351 */ 352 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 353 data = PCI_PRIMARY_BUS_INSERT(data, pcicb->pcicb_up->pcicb_bus); 354 data = PCI_SECONDARY_BUS_INSERT(data, pcicb->pcicb_bus); 355 data = PCI_SUBORDINATE_BUS_INSERT(data, pcicb->pcicb_bus); 356 pci_conf_write (tag, PCI_PCI_BRIDGE_BUS_REG, data); 357 358 /* 359 ** Propagate the new upper bus number limit. 360 */ 361 for (parent = pcicb->pcicb_up; parent != NULL; 362 parent = parent->pcicb_up) 363 { 364 if (parent->pcicb_subordinate >= pcicb->pcicb_bus) 365 continue; 366 parent->pcicb_subordinate = pcicb->pcicb_bus; 367 if (!parent->pcicb_bridge.tag) 368 continue; 369 data = pci_conf_read 370 (parent->pcicb_bridge, PCI_PCI_BRIDGE_BUS_REG); 371 data = PCI_SUBORDINATE_BUS_INSERT 372 (data, pcicb->pcicb_bus); 373 pci_conf_write (parent->pcicb_bridge, 374 PCI_PCI_BRIDGE_BUS_REG, data); 375 } 376 } 377 378 if (!pcicb->pcicb_membase) { 379 u_int size = 0x100000; 380 pcicb->pcicb_membase = pci_memalloc (pcicb->pcicb_up, 0, size); 381 if (pcicb->pcicb_membase) 382 pcicb->pcicb_memlimit = pcicb->pcicb_membase+size-1; 383 } 384 } 385 return pcicb->pcicb_bus; 386} 387 388/*======================================================== 389** 390** pci_attach() 391** 392** Attach one device 393** 394**======================================================== 395*/ 396 397static void pci_attach (int bus, int dev, int func, 398 struct pci_device *dvp, const char *name) 399{ 400 u_long data; 401 int unit; 402 u_char reg; 403 u_char pciint; 404 int irq; 405#if defined(APIC_IO) 406 u_char airq = 0xff; 407 u_char rirq = 0xff; 408#endif /* APIC_IO */ 409 pcici_t tag = pcibus->pb_tag (bus, dev, func); 410 411 /* 412 ** Get and increment the unit. 413 */ 414 415 unit = (*dvp->pd_count)++; 416 417 /* 418 ** Announce this device 419 */ 420 421 printf ("%s%d <%s> rev %d", dvp->pd_name, unit, name, 422 (unsigned) pci_conf_read (tag, PCI_CLASS_REG) & 0xff); 423 424 /* 425 ** Get the int pin number (pci interrupt number a-d) 426 ** from the pci configuration space. 427 */ 428 429 data = pci_conf_read (tag, PCI_INTERRUPT_REG); 430 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 431 432 if (pciint) { 433 434 printf (" int %c irq ", 0x60+pciint); 435 436 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 437 438 /* 439 ** If it's zero, the isa irq number is unknown, 440 ** and we cannot bind the pci interrupt. 441 */ 442 443#if defined(APIC_IO) 444 if (irq && (irq != 0xff)) { 445 airq = get_pci_apic_irq (bus, dev, pciint); 446 if (airq != 0xff) { /* APIC IRQ exists */ 447 rirq = irq; /* 're-directed' IRQ */ 448 irq = airq; /* use APIC IRQ */ 449 } 450 printf ("%d", irq); 451 } 452#else 453 if (irq && (irq != 0xff)) 454 printf ("%d", irq); 455#endif /* APIC_IO */ 456 else 457 printf ("??"); 458 }; 459 460 printf (" on pci%d:%d:%d\n", bus, dev, func); 461 462#if defined(APIC_IO) 463 if (airq != 0xff) { /* APIC IRQ exists */ 464 data = PCI_INTERRUPT_LINE_INSERT(data, airq); 465 pci_conf_write (tag, PCI_INTERRUPT_REG, data); 466 undirect_pci_irq (rirq); /* free for ISA card */ 467 } 468#endif /* APIC_IO */ 469 470 /* 471 ** Read the current mapping, 472 ** and update the pcicb fields. 473 */ 474 475 data = pci_conf_read(tag, PCI_CLASS_REG); 476 data &= (PCI_CLASS_MASK|PCI_SUBCLASS_MASK); 477 switch (data) { 478 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 479 break; 480 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_CARDBUS: { 481 u_int map, addr, size; 482 map = pci_conf_read(tag, PCI_CARDBUS_SOCKET_REG); 483 pci_conf_write (tag, PCI_CARDBUS_SOCKET_REG, 0xffffffff); 484 size = pci_conf_read(tag, PCI_CARDBUS_SOCKET_REG); 485 size = (~size) + 1; 486 addr = pci_memalloc (pcicb, map, size); 487 pci_conf_write (tag, PCI_CARDBUS_SOCKET_REG, addr); 488 pcicb->pcicb_mamount += size; 489 break; 490 } 491 default: 492 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) { 493 u_int map, addr, size; 494 495 496 map = pci_conf_read (tag, reg); 497 if (!(map & PCI_MAP_MEMORY_ADDRESS_MASK)) 498 continue; 499 500 pci_conf_write (tag, reg, 0xffffffff); 501 data = pci_conf_read (tag, reg); 502 pci_conf_write (tag, reg, map); 503 504 switch (data & 7) { 505 506 default: 507 continue; 508 case 1: 509 case 5: 510 addr = map & PCI_MAP_IO_ADDRESS_MASK; 511 size = -(data & PCI_MAP_IO_ADDRESS_MASK); 512 size &= ~(addr ^ -addr); 513 514 pci_register_io (pcicb, addr, addr+size-1); 515 pcicb->pcicb_pamount += size; 516 break; 517 518 case 0: 519 case 2: 520 case 4: 521 size = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 522 addr = map & PCI_MAP_MEMORY_ADDRESS_MASK; 523 if (addr >= 0x100000) { 524 pci_register_memory (pcicb, addr, addr+size-1); 525 pcicb->pcicb_mamount += size; 526 }; 527 break; 528 } 529 if (bootverbose) 530 printf ("\tmapreg[%02x] type=%d addr=%08x size=%04x.\n", 531 reg, map&7, addr, size); 532 } 533 } 534 535 /* 536 ** attach device 537 ** may produce additional log messages, 538 ** i.e. when installing subdevices. 539 */ 540 541 (*dvp->pd_attach) (tag, unit); 542 543 /* 544 ** Special processing of certain classes 545 */ 546 547 data = pci_conf_read(tag, PCI_CLASS_REG); 548 549 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 550 struct pcicb *this, **link; 551 unsigned char primary, secondary, subordinate; 552 u_int command; 553 554 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 555 556 /* 557 ** get current configuration of the bridge. 558 */ 559 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 560 primary = PCI_PRIMARY_BUS_EXTRACT (data); 561 secondary = PCI_SECONDARY_BUS_EXTRACT(data); 562 subordinate = PCI_SUBORDINATE_BUS_EXTRACT(data); 563#ifndef PCI_QUIET 564 if (bootverbose) { 565 printf ("\tbridge from pci%d to pci%d through %d.\n", 566 primary, secondary, subordinate); 567 printf ("\tmapping regs: io:%08lx mem:%08lx pmem:%08lx\n", 568 pci_conf_read (tag, PCI_PCI_BRIDGE_IO_REG), 569 pci_conf_read (tag, PCI_PCI_BRIDGE_MEM_REG), 570 pci_conf_read (tag, PCI_PCI_BRIDGE_PMEM_REG)); 571 } 572#endif 573 /* 574 ** check for uninitialized bridge. 575 */ 576 if (!(primary < secondary 577 && secondary <= subordinate 578 && bus == primary)) { 579 580 printf ("\tINCORRECTLY or NEVER CONFIGURED.\n"); 581 /* 582 ** disable this bridge 583 */ 584 pci_conf_write (tag, PCI_COMMAND_STATUS_REG, 0xffff0000); 585 secondary = 0; 586 subordinate = 0; 587 }; 588 589 /* 590 ** allocate bus descriptor for bus behind the bridge 591 */ 592 link = &pcicb->pcicb_down; 593 while (*link && (*link)->pcicb_bus < secondary) 594 link = &(*link)->pcicb_next; 595 596 this = malloc (sizeof (*this), M_DEVBUF, M_WAITOK); 597 598 /* 599 ** Initialize this descriptor so far. 600 ** (the initialization is completed just before 601 ** scanning the bus behind the bridge. 602 */ 603 bzero (this, sizeof(*this)); 604 this->pcicb_next = *link; 605 this->pcicb_up = pcicb; 606 this->pcicb_bridge = tag; 607 this->pcicb_bus = secondary; 608 this->pcicb_subordinate = subordinate; 609 610 command = pci_conf_read(tag,PCI_COMMAND_STATUS_REG); 611 612 if (command & PCI_COMMAND_IO_ENABLE){ 613 /* 614 ** Bridge was configured by the bios. 615 ** Read out the mapped io region. 616 */ 617 unsigned reg; 618 619 reg = pci_conf_read (tag, PCI_PCI_BRIDGE_IO_REG); 620 this->pcicb_iobase = PCI_PPB_IOBASE_EXTRACT (reg); 621 this->pcicb_iolimit = PCI_PPB_IOLIMIT_EXTRACT(reg); 622 623 /* 624 ** Note the used io space. 625 */ 626 pci_register_io (pcicb, this->pcicb_iobase, 627 this->pcicb_iolimit); 628 629 }; 630 631 if (command & PCI_COMMAND_MEM_ENABLE) { 632 /* 633 ** Bridge was configured by the bios. 634 ** Read out the mapped memory regions. 635 */ 636 unsigned reg; 637 638 /* 639 ** non prefetchable memory 640 */ 641 reg = pci_conf_read (tag, PCI_PCI_BRIDGE_MEM_REG); 642 this->pcicb_membase = PCI_PPB_MEMBASE_EXTRACT (reg); 643 this->pcicb_memlimit = PCI_PPB_MEMLIMIT_EXTRACT(reg); 644 645 /* 646 ** Register used memory space. 647 */ 648 pci_register_memory (pcicb, 649 this->pcicb_membase, 650 this->pcicb_memlimit); 651 652 /* 653 ** prefetchable memory 654 */ 655 reg = pci_conf_read (tag, PCI_PCI_BRIDGE_PMEM_REG); 656 this->pcicb_p_membase = PCI_PPB_MEMBASE_EXTRACT (reg); 657 this->pcicb_p_memlimit = PCI_PPB_MEMLIMIT_EXTRACT(reg); 658 659 /* 660 ** Register used memory space. 661 */ 662 pci_register_memory (pcicb, 663 this->pcicb_p_membase, 664 this->pcicb_p_memlimit); 665 } 666 667 /* 668 ** Link it in chain. 669 */ 670 *link=this; 671 672 /* 673 ** Update mapping info of parent bus. 674 */ 675 if (!pcicb->pcicb_bfrom||secondary< pcicb->pcicb_bfrom) 676 pcicb->pcicb_bfrom = secondary; 677 if (subordinate > pcicb->pcicb_bupto) 678 pcicb->pcicb_bupto = subordinate; 679 } 680} 681 682/*======================================================== 683** 684** pci_bus_config() 685** 686** Autoconfiguration of one pci bus. 687** 688**======================================================== 689*/ 690 691static int 692pci_mfdev (int bus, int device) 693{ 694 pcici_t tag0,tag1; 695 unsigned pci_id0, pci_id1; 696 697 /* 698 ** Detect a multi-function device that complies to the PCI 2.0 spec 699 */ 700 tag0 = pcibus->pb_tag (bus, device, 0); 701 if (pci_conf_read (tag0, PCI_HEADER_MISC) & PCI_HEADER_MULTIFUNCTION) 702 return 1; 703 704 /* 705 ** Well, as always: Theory and implementation of PCI ... 706 ** 707 ** If there is a valid device ID returned for function 1 AND 708 ** the device ID of function 0 and 1 is different OR 709 ** the first mapping register of 0 and 1 differs, 710 ** then assume a multi-function device anyway ... 711 ** 712 ** Example of such a broken device: ISA and IDE chip i83371FB (Triton) 713 */ 714 tag1 = pcibus->pb_tag (bus, device, 1); 715 pci_id1 = pci_conf_read (tag1, PCI_ID_REG); 716 717 if (pci_id1 != 0xffffffff) { 718 719 pci_id0 = pci_conf_read (tag0, PCI_ID_REG); 720 721 if (pci_id0 != pci_id1) 722 return 1; 723 724 if (pci_conf_read (tag0, PCI_MAP_REG_START) 725 != pci_conf_read (tag1, PCI_MAP_REG_START)) 726 return 1; 727 } 728 return 0; 729} 730 731static void 732pci_bus_config (void) 733{ 734 int bus_no; 735 u_char device; 736 u_char reg; 737 pcici_t tag, mtag; 738 pcidi_t type; 739 740 struct pci_device *dvp; 741 742 /* 743 ** first initialize the bridge (bus controller chip) 744 */ 745 bus_no = pci_bridge_config (); 746 747 printf ("Probing for devices on PCI bus %d:\n", bus_no); 748#ifndef PCI_QUIET 749 if (bootverbose && !pci_info_done) { 750 pci_info_done=1; 751 printf ("\tconfiguration mode %d allows %d devices.\n", 752 pci_mechanism, pci_maxdevice); 753 }; 754#endif 755 for (device=0; device<pci_maxdevice; device ++) { 756 char *name = NULL; 757 struct pci_device **dvpp; 758 int func, maxfunc = 0; 759 760 for (func=0; func <= maxfunc; func++) { 761 tag = pcibus->pb_tag (bus_no, device, func); 762 type = pci_conf_read (tag, PCI_ID_REG); 763 764 if ((!type) || (type==0xfffffffful)) continue; 765 766 /* 767 ** lookup device in ioconfiguration: 768 */ 769 770 dvpp = (struct pci_device **)pcidevice_set.ls_items; 771 772 while (dvp = *dvpp++) { 773 if (dvp->pd_probe) { 774 if (name=(*dvp->pd_probe)(tag, type)) 775 break; 776 } 777 }; 778 /* 779 ** check for mirrored devices. 780 */ 781 if (func != 0) { 782 goto real_device; 783 } 784 if (device & 0x10) { 785 mtag=pcibus->pb_tag (bus_no, 786 (u_char)(device & ~0x10), 0); 787 } else if (device & 0x08) { 788 mtag=pcibus->pb_tag (bus_no, 789 (u_char)(device & ~0x08), 0); 790 } else goto real_device; 791 792 if (type!=pci_conf_read (mtag, PCI_ID_REG)) 793 goto real_device; 794 795 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) 796 if (pci_conf_read(tag,reg)!=pci_conf_read(mtag,reg)) 797 goto real_device; 798 799#ifndef PCI_QUIET 800 if (dvp==NULL) continue; 801 if (bootverbose) 802 printf ("%s? <%s> mirrored on pci%d:%d\n", 803 dvp->pd_name, name, bus_no, device); 804#endif 805 continue; 806 807 real_device: 808 809#ifndef PCI_QUIET 810#ifdef PCI_BRIDGE_DEBUG 811 if (bootverbose) { 812 printf ("\tconfig header: 0x%08x 0x%08x 0x%08x 0x%08x\n", 813 pci_conf_read (tag, 0), 814 pci_conf_read (tag, 4), 815 pci_conf_read (tag, 8), 816 pci_conf_read (tag, 12)); 817 } 818#endif 819#endif 820 821 if (func == 0 && pci_mfdev (bus_no, device)) { 822 maxfunc = 7; 823 } 824 825 pci_remember(bus_no, device, func, dvp); 826 827 if (dvp==NULL) { 828#ifndef PCI_QUIET 829 if (pci_conf_count) 830 continue; 831 832 if (maxfunc == 0) 833 printf("%s%d:%d: ", 834 pcibus->pb_name, bus_no, device); 835 else 836 printf("%s%d:%d:%d: ", 837 pcibus->pb_name, bus_no, device, func); 838 not_supported (tag, type); 839#endif 840 continue; 841 }; 842 843 if (*name) { 844 pci_attach (bus_no, device, func, dvp, name); 845 } 846 } 847 } 848 849#ifndef PCI_QUIET 850 if (bootverbose) { 851 if (pcicb->pcicb_mamount) 852 printf ("%s%d: uses %ud bytes of memory from %x upto %x.\n", 853 pcibus->pb_name, bus_no, 854 pcicb->pcicb_mamount, 855 pcicb->pcicb_mfrom, pcicb->pcicb_mupto); 856 if (pcicb->pcicb_pamount) 857 printf ("%s%d: uses %ud bytes of I/O space from %x upto %x.\n", 858 pcibus->pb_name, bus_no, 859 pcicb->pcicb_pamount, 860 pcicb->pcicb_pfrom, pcicb->pcicb_pupto); 861 if (pcicb->pcicb_bfrom) 862 printf ("%s%d: subordinate busses from %x upto %x.\n", 863 pcibus->pb_name, bus_no, 864 pcicb->pcicb_bfrom, pcicb->pcicb_bupto); 865 } 866#endif 867} 868 869/*======================================================== 870** 871** pci_configure () 872** 873** Autoconfiguration of pci devices. 874** 875** Has to take care of mirrored devices, which are 876** entailed by incomplete decoding of pci address lines. 877** 878**======================================================== 879*/ 880 881void pci_configure() 882{ 883 struct pcibus **pbp = (struct pcibus**) pcibus_set.ls_items; 884 885 /* 886 ** check pci bus present 887 */ 888 889 while (!pci_maxdevice && (pcibus = *pbp++)) { 890 (*pcibus->pb_setup)(); 891 } 892 893 if (!pci_maxdevice) return; 894 895 /* 896 ** hello world .. 897 */ 898 899 pciroots = 1; 900 while (pciroots--) { 901 902 pcicb = malloc (sizeof (struct pcicb), M_DEVBUF, M_WAITOK); 903 if (pcicb == NULL) { 904 return; 905 } 906 bzero (pcicb, sizeof (struct pcicb)); 907 pcicb->pcicb_bus = pcibusmax; 908 pcicb->pcicb_iolimit = 0xffff; 909 pcicb->pcicb_membase = 0x02000000; 910 pcicb->pcicb_p_membase = 0x02000000; 911 pcicb->pcicb_memlimit = 0xffffffff; 912 pcicb->pcicb_p_memlimit = 0xffffffff; 913 914 while (pcicb != NULL) { 915 pci_bus_config (); 916 917 if (pcibusmax < pcicb->pcicb_bus) 918 (pcibusmax = pcicb->pcicb_bus); 919 920 if (pcicb->pcicb_down) { 921 pcicb = pcicb->pcicb_down; 922 continue; 923 }; 924 925 while (pcicb && !pcicb->pcicb_next) 926 pcicb = pcicb->pcicb_up; 927 928 if (pcicb) 929 pcicb = pcicb->pcicb_next; 930 } 931 pcibusmax++; 932 } 933 pci_conf_count++; 934} 935 936/*======================================================== 937** 938** pci_rescan () 939** 940** try to find lkm driver for device 941** 942** May be called more than once. 943** Any device is attached only once. 944** 945**======================================================== 946*/ 947 948static void pci_rescan() 949{ 950 int i; 951 for (i = 0; i < pci_dev_list_count; i++) 952 { 953 struct pci_lkm *lkm; 954 pcici_t tag; 955 struct pci_device *dvp; 956 pcidi_t type = pci_dev_list[i].pc_devid; 957 char *name = NULL; 958 int bus, dev, func; 959 960 if (pci_dev_list[i].pc_dvp) 961 continue; 962 963 bus = pci_dev_list[i].pc_sel.pc_bus; 964 dev = pci_dev_list[i].pc_sel.pc_dev; 965 func = pci_dev_list[i].pc_sel.pc_func; 966 967 tag = pcibus->pb_tag (bus, dev, func); 968 969 for (lkm = pci_lkm_head; lkm; lkm = lkm->next) { 970 dvp = lkm->dvp; 971 if (name=(*dvp->pd_probe)(tag, type)) 972 break; 973 } 974 if (name && *name) { 975 pcicb = pci_dev_list[i].pc_cb; 976 pci_attach (bus, dev, func, dvp, name); 977 pci_dev_list[i].pc_dvp = dvp; 978 } 979 } 980} 981 982/*======================================================== 983** 984** pci_register_lkm () 985** 986** Add LKM PCI driver's struct pci_device to pci_lkm chain 987** 988**======================================================== 989*/ 990 991int pci_register_lkm (struct pci_device *dvp, int if_revision) 992{ 993 struct pci_lkm *lkm; 994 995 if (if_revision != 0) { 996 return -1; 997 } 998 999 if (!dvp || !dvp->pd_probe || !dvp->pd_attach) { 1000 return -1; 1001 } 1002 1003 lkm = malloc (sizeof (*lkm), M_DEVBUF, M_WAITOK); 1004 if (!lkm) { 1005 return -1; 1006 } 1007 1008 lkm->dvp = dvp; 1009 lkm->next = pci_lkm_head; 1010 pci_lkm_head = lkm; 1011 pci_rescan(); 1012 return 0; 1013} 1014 1015/*----------------------------------------------------------------------- 1016** 1017** Map device into port space. 1018** 1019** Actually the device should have been mapped by the bios. 1020** This function only reads and verifies the value. 1021** 1022** PCI-Specification: 6.2.5.1: address maps 1023** 1024**----------------------------------------------------------------------- 1025*/ 1026 1027int pci_map_port (pcici_t tag, u_long reg, u_short* pa) 1028{ 1029 unsigned data, ioaddr, iosize; 1030 struct pcicb *link = pcicb; 1031 1032 /* 1033 ** sanity check 1034 */ 1035 1036 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 1037 printf ("pci_map_port failed: bad register=0x%x\n", 1038 (unsigned)reg); 1039 return (0); 1040 }; 1041 1042 /* 1043 ** get size and type of port 1044 ** 1045 ** type is in the lowest two bits. 1046 ** If device requires 2^n bytes, the next 1047 ** n-2 bits are hardwired as 0. 1048 */ 1049 1050 ioaddr = pci_conf_read (tag, reg) & PCI_MAP_IO_ADDRESS_MASK; 1051 if (!ioaddr) { 1052 printf ("pci_map_port failed: not configured by bios.\n"); 1053 return (0); 1054 }; 1055 1056 pci_conf_write (tag, reg, 0xfffffffful); 1057 data = pci_conf_read (tag, reg); 1058 pci_conf_write (tag, reg, ioaddr); 1059 1060 if ((data & 0x03) != PCI_MAP_IO) { 1061 printf ("pci_map_port failed: bad port type=0x%x\n", 1062 (unsigned) data); 1063 return (0); 1064 }; 1065 iosize = -(data & PCI_MAP_IO_ADDRESS_MASK); 1066 iosize &= ~(ioaddr ^ -ioaddr); 1067 if (ioaddr < pcicb->pcicb_iobase 1068 || ioaddr + iosize -1 > pcicb->pcicb_iolimit) { 1069 printf ("pci_map_port failed: device's iorange 0x%x-0x%x " 1070 "is incompatible with its bridge's range 0x%x-0x%x\n", 1071 (unsigned) ioaddr, (unsigned) ioaddr + iosize - 1, 1072 (unsigned) pcicb->pcicb_iobase, 1073 (unsigned) pcicb->pcicb_iolimit); 1074 return (0); 1075 } 1076 1077#ifndef PCI_QUIET 1078 if (bootverbose) 1079 printf ("\treg%d: ioaddr=0x%x size=0x%x\n", 1080 (unsigned) reg, (unsigned) ioaddr, (unsigned) iosize); 1081#endif 1082 /* 1083 ** set the configuration register of and 1084 ** return the address to the driver. 1085 ** Make sure to enable each upstream bridge 1086 ** so I/O and DMA can go all the way. 1087 */ 1088 1089 for (;;) { 1090 data = pci_conf_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 1091 data |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1092 (void) pci_conf_write(tag, PCI_COMMAND_STATUS_REG, data); 1093 if ((link = link->pcicb_up) == NULL) 1094 break; 1095 tag = link->pcicb_bridge; 1096 } 1097 1098 *pa = ioaddr; 1099 1100 return (1); 1101} 1102 1103/*----------------------------------------------------------------------- 1104** 1105** Map device into virtual and physical space 1106** 1107** Actually the device should have been mapped by the bios. 1108** This function only reads and verifies the value. 1109** 1110** PCI-Specification: 6.2.5.1: address maps 1111** 1112**----------------------------------------------------------------------- 1113*/ 1114 1115int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa) 1116{ 1117 struct pcicb *link = pcicb; 1118 unsigned data ,paddr; 1119 vm_size_t psize, poffs; 1120 vm_offset_t vaddr; 1121 1122 /* 1123 ** sanity check 1124 */ 1125 1126 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 1127 printf ("pci_map_mem failed: bad register=0x%x\n", 1128 (unsigned)reg); 1129 return (0); 1130 }; 1131 1132 /* 1133 ** save old mapping, get size and type of memory 1134 ** 1135 ** type is in the lowest four bits. 1136 ** If device requires 2^n bytes, the next 1137 ** n-4 bits are read as 0. 1138 */ 1139 1140 paddr = pci_conf_read (tag, reg) & PCI_MAP_MEMORY_ADDRESS_MASK; 1141 pci_conf_write (tag, reg, 0xfffffffful); 1142 data = pci_conf_read (tag, reg); 1143 pci_conf_write (tag, reg, paddr); 1144 1145 /* 1146 ** check the type 1147 */ 1148 1149 if (!((data & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_32BIT_1M 1150 && (paddr & ~0xfffff) == 0) 1151 && (data & PCI_MAP_MEMORY_TYPE_MASK) != PCI_MAP_MEMORY_TYPE_32BIT){ 1152 printf ("pci_map_mem failed: bad memory type=0x%x\n", 1153 (unsigned) data); 1154 return (0); 1155 }; 1156 1157 /* 1158 ** get the size. 1159 */ 1160 1161 psize = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 1162 1163 if (!paddr || paddr == PCI_MAP_MEMORY_ADDRESS_MASK) { 1164 paddr = pci_memalloc (pcicb, 0, psize); 1165 if (!paddr) { 1166 printf ("pci_map_mem: not configured by bios.\n"); 1167 return (0); 1168 }; 1169 pci_register_memory (pcicb, paddr, paddr+psize-1); 1170 }; 1171 1172 if (paddr < pcicb->pcicb_membase || 1173 paddr + psize - 1 > pcicb->pcicb_memlimit) { 1174 printf ("pci_map_mem failed: device's memrange 0x%x-0x%x is " 1175 "incompatible with its bridge's memrange 0x%x-0x%x\n", 1176 (unsigned) paddr, 1177 (unsigned) (paddr + psize - 1), 1178 (unsigned) pcicb->pcicb_membase, 1179 (unsigned) pcicb->pcicb_memlimit); 1180/* return (0);*/ 1181/* ACHTUNG: Ist der Code richtig, wenn eine PCI-PCI-Bridge fuer 1182 * die PCI-Slots verwendet wird, aber die Onboard-Devices direkt 1183 * an der CPU-PCI-Bridge haengen (Siehe Compaq Prolinea Problem) ??? 1184 */ 1185 } 1186 pci_conf_write (tag, reg, paddr); 1187 1188 /* 1189 ** Truncate paddr to page boundary. 1190 ** (Or does pmap_mapdev the job?) 1191 */ 1192 1193 poffs = paddr - trunc_page (paddr); 1194 vaddr = (vm_offset_t) pmap_mapdev (paddr-poffs, psize+poffs); 1195 1196 if (!vaddr) return (0); 1197 1198 vaddr += poffs; 1199 1200#ifndef PCI_QUIET 1201 /* 1202 ** display values. 1203 */ 1204 1205 if (bootverbose) 1206 printf ("\treg%d: virtual=0x%lx physical=0x%lx size=0x%lx\n", 1207 (unsigned) reg, (u_long)vaddr, (u_long)paddr, (u_long)psize); 1208#endif 1209 /* 1210 ** set the configuration register and 1211 ** return the address to the driver 1212 ** Make sure to enable each upstream bridge 1213 ** so memory and DMA can go all the way. 1214 */ 1215 1216 for (;;) { 1217 data = pci_conf_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 1218 data |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1219 (void) pci_conf_write(tag, PCI_COMMAND_STATUS_REG, data); 1220 if ((link = link->pcicb_up) == NULL) 1221 break; 1222 tag = link->pcicb_bridge; 1223 } 1224 1225 *va = vaddr; 1226 *pa = paddr; 1227 1228 return (1); 1229} 1230 1231/*----------------------------------------------------------------------- 1232** 1233** Pci meta interrupt handler 1234** 1235** This handler assumes level triggered interrupts. 1236** It's possible to build a kernel which handles shared 1237** edge triggered interrupts by the options "PCI_EDGE_INT". 1238** But there is a performance penalty. 1239** 1240** (Of course you can delete the #ifdef PCI_EDGE_INT bracketed 1241** code at all :-) :-) :-) 1242** 1243**----------------------------------------------------------------------- 1244*/ 1245 1246static struct pci_int_desc* 1247 pci_int_desc [PCI_MAX_IRQ]; 1248 1249#ifndef NO_SHARED_IRQ 1250 1251static inline unsigned 1252splq (unsigned mask) 1253{ 1254 unsigned temp=cpl; 1255 cpl |= mask; 1256 return temp; 1257} 1258 1259static void 1260pci_int (int irq) 1261{ 1262 struct pci_int_desc * p; 1263 int s; 1264 1265 if (irq<0 || irq >= PCI_MAX_IRQ) { 1266 printf ("pci_int: irq %d out of range, ignored\n", irq); 1267 return; 1268 }; 1269 for (p = pci_int_desc[irq]; p!=NULL; p=p->pcid_next) { 1270 s = splq (*p->pcid_maskptr); 1271 (*p->pcid_handler) (p->pcid_argument); 1272 p-> pcid_tally++; 1273 splx (s); 1274#if 0 1275 if (p->pcid_tally<20) 1276 printf ("PCI_INT: irq=%d h=%p cpl o=%x n=%x val=%d\n", 1277 irq, p->pcid_handler, s, cpl, c); 1278#endif 1279 }; 1280} 1281#endif 1282 1283/*----------------------------------------------------------------------- 1284** 1285** Auxiliary function for interrupt (un)mapping. 1286** 1287**----------------------------------------------------------------------- 1288*/ 1289 1290static u_int 1291getirq (pcici_t tag) 1292{ 1293 u_int irq; 1294 1295 irq = PCI_INTERRUPT_LINE_EXTRACT( 1296 pci_conf_read (tag, PCI_INTERRUPT_REG)); 1297 1298 if (irq == 0 || irq == 0xff) { 1299 printf ("\tint line register not set by bios\n"); 1300 return (0xff); 1301 } 1302 1303 if (irq >= PCI_MAX_IRQ) { 1304 printf ("\tirq %d out of bounds (must be < %d).\n", 1305 irq, PCI_MAX_IRQ); 1306 return (0xff); 1307 } 1308 1309 return (irq); 1310} 1311 1312static struct pci_int_desc ** 1313getintdescbytag (u_int irq, pcici_t tag) 1314{ 1315 struct pci_int_desc *p, **pp; 1316 1317 pp=&pci_int_desc[irq]; 1318 while (((p=*pp)) && !sametag(p->pcid_tag,tag)) 1319 pp=&p->pcid_next; 1320 1321 if (!p) return (NULL); 1322 1323 return (pp); 1324} 1325 1326static struct pci_int_desc * 1327getintdescbymptr (u_int irq, unsigned * mptr) 1328{ 1329 struct pci_int_desc *p; 1330 1331 for (p=pci_int_desc[irq];p;p=p->pcid_next) 1332 if (p->pcid_maskptr == mptr) break; 1333 return (p); 1334} 1335 1336/*----------------------------------------------------------------------- 1337** 1338** Map pci interrupt. 1339** 1340**----------------------------------------------------------------------- 1341*/ 1342 1343static unsigned pci_mask0 = 0; 1344 1345int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr) 1346{ 1347 u_int irq; 1348 int result, oldspl; 1349 unsigned mask; 1350 struct pci_int_desc *tail, *mdp=NULL, *new=NULL; 1351 1352 /* 1353 ** Get irq line from configuration space, 1354 ** and check for consistency. 1355 */ 1356 1357 irq = getirq (tag); 1358 if (irq == 0xff) { 1359 return (0); 1360 }; 1361 mask= 1ul << irq; 1362 1363 /* 1364 ** disable this interrupt. 1365 */ 1366 1367 oldspl = splq (mask); 1368 1369 /* 1370 ** If handler for this tag already installed, 1371 ** remove it first. 1372 */ 1373 1374 if (getintdescbytag (irq, tag) != NULL) 1375 pci_unmap_int (tag); 1376 1377 /* 1378 ** If this irq not yet included in the mask, include it. 1379 */ 1380 1381 mdp = getintdescbymptr (irq, maskptr); 1382 if (!mdp) { 1383 result = pcibus->pb_imaskinc (irq, maskptr); 1384 if (result) 1385 goto conflict; 1386 }; 1387 1388 /* 1389 ** Allocate descriptor and initialize it. 1390 */ 1391 1392 tail = pci_int_desc[irq]; 1393 1394 new = malloc (sizeof (*new), M_DEVBUF, M_WAITOK); 1395 bzero (new, sizeof (*new)); 1396 1397 new->pcid_next = tail; 1398 new->pcid_tag = tag; 1399 new->pcid_handler = func; 1400 new->pcid_argument = arg; 1401 new->pcid_maskptr = maskptr; 1402 new->pcid_tally = 0; 1403 new->pcid_mask = mask; 1404 1405 /* 1406 ** If first handler: install it. 1407 ** If second handler: install shared-int-handler. 1408 */ 1409 1410 if (!tail) { 1411 /* 1412 ** first handler for this irq. 1413 */ 1414 1415 result = pcibus->pb_iattach 1416 /* 1417 * XXX if we get here, then `func' must be pci_int 1418 * so the bogus casts are almost OK since they just 1419 * undo the bogus casts that were needed to pass 1420 * pci_int and its arg to pci_map_int(). 1421 */ 1422 (irq, (inthand2_t *) func, (int) arg, maskptr); 1423 if (result) goto conflict; 1424 1425#ifdef NO_SHARED_IRQ 1426 } else goto conflict; 1427#else 1428 } else if (!tail->pcid_next) { 1429 /* 1430 ** Second handler for this irq. 1431 */ 1432 1433 if (bootverbose) 1434 printf ("\tusing shared irq %d.\n", irq); 1435 1436 /* 1437 ** replace old handler by shared-int-handler. 1438 */ 1439 1440 result = pcibus->pb_idetach (irq, 1441 (inthand2_t *) tail->pcid_handler); 1442 if (result) 1443 printf ("\tCANNOT DETACH INT HANDLER.\n"); 1444 1445 result = pcibus->pb_iattach (irq, pci_int, irq, &pci_mask0); 1446 if (result) { 1447 printf ("\tCANNOT ATTACH SHARED INT HANDLER.\n"); 1448 goto fail; 1449 }; 1450 } 1451#endif 1452 /* 1453 ** Link new descriptor, reenable ints and done. 1454 */ 1455 1456 pci_int_desc[irq] = new; 1457 splx (oldspl); 1458 return (1); 1459 1460 /* 1461 ** Handle some problems. 1462 */ 1463 1464conflict: 1465 printf ("\tirq %d already in use.\n", irq); 1466fail: 1467 /* 1468 ** If descriptor allocated, free it. 1469 ** If included in mask, remove it. 1470 */ 1471 1472 if (new) free(new, M_DEVBUF); 1473 if (!mdp) (void) pcibus->pb_imaskexc (irq, maskptr); 1474 splx (oldspl); 1475 return (0); 1476} 1477 1478/*----------------------------------------------------------------------- 1479** 1480** Unmap pci interrupt. 1481** 1482**----------------------------------------------------------------------- 1483*/ 1484 1485int pci_unmap_int (pcici_t tag) 1486{ 1487 int result, oldspl; 1488 struct pci_int_desc *this, **hook, *tail; 1489 unsigned irq; 1490 1491 /* 1492 ** Get irq line from configuration space, 1493 ** and check for consistency. 1494 */ 1495 1496 irq = getirq (tag); 1497 if (irq == 0xff) { 1498 return (0); 1499 }; 1500 1501 /* 1502 ** Search and unlink interrupt descriptor. 1503 */ 1504 1505 hook = getintdescbytag (irq, tag); 1506 if (hook == NULL) { 1507 printf ("\tno irq %d handler for pci %x\n", 1508 irq, tag.tag); 1509 return (0); 1510 }; 1511 1512 this = *hook; 1513 *hook= this->pcid_next; 1514 1515 /* 1516 ** Message 1517 */ 1518 1519 printf ("\tirq %d handler %p(%p) unmapped for pci %x after %d ints.\n", 1520 irq, this->pcid_handler, this->pcid_argument, 1521 this->pcid_tag.tag, this->pcid_tally); 1522 1523 /* 1524 ** If this irq no longer included in the mask, remove it. 1525 */ 1526 1527 if (!getintdescbymptr (irq, this->pcid_maskptr)) 1528 (void) pcibus->pb_imaskexc (irq, this->pcid_maskptr); 1529 1530 tail = pci_int_desc[irq]; 1531 1532 if (tail == NULL) { 1533 1534 /* 1535 ** Remove the old handler. 1536 */ 1537 1538 result = pcibus->pb_idetach (irq, 1539 (inthand2_t *) this->pcid_handler); 1540 if (result) 1541 printf ("\tirq %d: cannot remove handler.\n", irq); 1542 1543 } else if (tail->pcid_next == NULL) { 1544 1545 /* 1546 ** Remove the shared int handler. 1547 ** Install the last remaining handler. 1548 */ 1549 1550 oldspl = splq (1ul << irq); 1551 1552 result = pcibus->pb_idetach (irq, pci_int); 1553 if (result) 1554 printf ("\tirq %d: cannot remove handler.\n", irq); 1555 1556 result = pcibus->pb_iattach (irq, 1557 (inthand2_t *) tail->pcid_handler, 1558 (int) tail->pcid_argument, 1559 tail->pcid_maskptr); 1560 1561 if (result) 1562 printf ("\tirq %d: cannot install handler.\n", irq); 1563 1564 splx (oldspl); 1565 }; 1566 1567 free (this, M_DEVBUF); 1568 return (1); 1569} 1570 1571/*----------------------------------------------------------- 1572** 1573** Display of unknown devices. 1574** 1575**----------------------------------------------------------- 1576*/ 1577struct vt { 1578 u_short ident; 1579 char* name; 1580}; 1581 1582static struct vt VendorTable[] = { 1583 {0x0e11, "Compaq"}, 1584 {0x1000, "NCR/Symbios"}, 1585 {0x1002, "ATI Technologies Inc."}, 1586 {0x1004, "VLSI"}, 1587 {0x100B, "National Semiconductor"}, 1588 {0x100E, "Weitek"}, 1589 {0x1011, "Digital Equipment Corporation"}, 1590 {0x1013, "Cirrus Logic"}, 1591 {0x101A, "NCR"}, 1592 {0x1022, "AMD"}, 1593 {0x102B, "Matrox"}, 1594 {0x102C, "Chips & Technologies"}, 1595 {0x1039, "Silicon Integrated Systems"}, 1596 {0x1042, "SMC"}, 1597 {0x1044, "DPT"}, 1598 {0x1045, "OPTI"}, 1599 {0x104B, "Bus Logic"}, 1600 {0x104C, "TI"}, 1601 {0x1060, "UMC"}, 1602 {0x1080, "Contaq"}, 1603 {0x1095, "CMD"}, 1604 {0x10b9, "ACER Labs"}, 1605 {0x10c8, "NeoMagic"}, 1606 {0x1106, "VIA Technologies"}, 1607 {0x5333, "S3 Inc."}, 1608 {0x8086, "Intel Corporation"}, 1609 {0x9004, "Adaptec"}, 1610 {0,0} 1611}; 1612 1613typedef struct { 1614 const int subclass; 1615 const char *name; 1616} subclass_name; 1617 1618/* 0x00 prehistoric subclasses */ 1619static const subclass_name old_subclasses[] = 1620{ 1621 { 0x00, "misc" }, 1622 { 0x01, "vga" }, 1623 { 0x00, NULL } 1624}; 1625 1626/* 0x01 mass storage subclasses */ 1627static const subclass_name storage_subclasses[] = 1628{ 1629 { 0x00, "scsi" }, 1630 { 0x01, "ide" }, 1631 { 0x02, "floppy"}, 1632 { 0x03, "ipi" }, 1633 { 0x80, "misc" }, 1634 { 0x00, NULL } 1635}; 1636 1637/* 0x02 network subclasses */ 1638static const subclass_name network_subclasses[] = 1639{ 1640 { 0x00, "ethernet" }, 1641 { 0x01, "tokenring" }, 1642 { 0x02, "fddi" }, 1643 { 0x80, "misc" }, 1644 { 0x00, NULL } 1645}; 1646 1647/* 0x03 display subclasses */ 1648static const subclass_name display_subclasses[] = 1649{ 1650 { 0x00, "vga" }, 1651 { 0x01, "xga" }, 1652 { 0x80, "misc" }, 1653 { 0x00, NULL } 1654}; 1655 1656/* 0x04 multimedia subclasses */ 1657static const subclass_name multimedia_subclasses[] = 1658{ 1659 { 0x00, "video" }, 1660 { 0x01, "audio" }, 1661 { 0x80, "misc" }, 1662 { 0x00, NULL } 1663}; 1664 1665/* 0x05 memory subclasses */ 1666static const subclass_name memory_subclasses[] = 1667{ 1668 { 0x00, "ram" }, 1669 { 0x01, "flash" }, 1670 { 0x80, "misc" }, 1671 { 0x00, NULL } 1672}; 1673 1674/* 0x06 bridge subclasses */ 1675static const subclass_name bridge_subclasses[] = 1676{ 1677 { 0x00, "host" }, 1678 { 0x01, "isa" }, 1679 { 0x02, "eisa" }, 1680 { 0x03, "mc" }, 1681 { 0x04, "pci" }, 1682 { 0x05, "pcmcia"}, 1683 { 0x07, "cardbus"}, 1684 { 0x80, "misc" }, 1685 { 0x00, NULL } 1686}; 1687 1688static const subclass_name *const subclasses[] = { 1689 old_subclasses, 1690 storage_subclasses, 1691 network_subclasses, 1692 display_subclasses, 1693 multimedia_subclasses, 1694 memory_subclasses, 1695 bridge_subclasses, 1696}; 1697 1698static const char *const majclasses[] = { 1699 "old", 1700 "storage", 1701 "network", 1702 "display", 1703 "multimedia", 1704 "memory", 1705 "bridge", 1706 "comms", 1707 "system", 1708 "input", 1709 "docking", 1710 "processor", 1711 "serial" 1712}; 1713 1714 1715void not_supported (pcici_t tag, u_long type) 1716{ 1717 u_long reg; 1718 u_long data; 1719 u_char class; 1720 u_char subclass; 1721 struct vt * vp; 1722 int pciint; 1723 int irq; 1724 1725 /* 1726 ** lookup the names. 1727 */ 1728 1729 for (vp=VendorTable; vp->ident; vp++) 1730 if (vp->ident == (type & 0xffff)) 1731 break; 1732 1733 /* 1734 ** and display them. 1735 */ 1736 1737 if (vp->ident) printf (vp->name); 1738 else printf ("vendor=0x%04lx", type & 0xffff); 1739 1740 printf (", device=0x%04lx", type >> 16); 1741 1742 data = pci_conf_read(tag, PCI_CLASS_REG); 1743 class = (data >> 24) & 0xff; 1744 subclass = (data >> 16) & 0xff; 1745 1746 if (class < sizeof(majclasses) / sizeof(majclasses[0])) { 1747 printf(", class=%s", majclasses[class]); 1748 } else { 1749 printf(", class=0x%02x", class); 1750 } 1751 1752 if (class < sizeof(subclasses) / sizeof(subclasses[0])) { 1753 const subclass_name *p = subclasses[class]; 1754 while (p->name && (p->subclass != subclass)) 1755 p++; 1756 if (p->name) { 1757 printf(" (%s)", p->name); 1758 } else { 1759 printf(" (unknown subclass 0x%02lx)", subclass); 1760 } 1761 } else { 1762 printf(", subclass=0x%02x", subclass); 1763 } 1764 1765 data = pci_conf_read (tag, PCI_INTERRUPT_REG); 1766 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 1767 1768 if (pciint) { 1769 1770 printf (" int %c irq ", 0x60+pciint); 1771 1772 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 1773 1774 /* 1775 ** If it's zero, the isa irq number is unknown, 1776 ** and we cannot bind the pci interrupt. 1777 */ 1778 1779 if (irq && (irq != 0xff)) 1780 printf ("%d", irq); 1781 else 1782 printf ("??"); 1783 }; 1784 1785 if (class != (PCI_CLASS_BRIDGE >> 24)) 1786 printf (" [no driver assigned]"); 1787 printf ("\n"); 1788 1789 if (bootverbose) { 1790 if (class == (PCI_CLASS_BRIDGE >> 24)) { 1791 printf ("configuration space registers:"); 1792 for (reg = 0; reg < 0x100; reg+=4) { 1793 if ((reg & 0x0f) == 0) printf ("\n%02x:\t", reg); 1794 printf ("%08x ", pci_conf_read (tag, reg)); 1795 } 1796 printf ("\n"); 1797 } else { 1798 for (reg=PCI_MAP_REG_START; reg<PCI_MAP_REG_END; reg+=4) { 1799 data = pci_conf_read (tag, reg); 1800 if ((data&~7)==0) continue; 1801 switch (data&7) { 1802 1803 case 1: 1804 case 5: 1805 printf ("\tmap(%x): io(%04lx)\n", 1806 reg, data & ~3); 1807 break; 1808 case 0: 1809 printf ("\tmap(%x): mem32(%08lx)\n", 1810 reg, data & ~7); 1811 break; 1812 case 2: 1813 printf ("\tmap(%x): mem20(%05lx)\n", 1814 reg, data & ~7); 1815 break; 1816 case 4: 1817 printf ("\tmap(%x): mem64(%08x%08lx)\n", 1818 reg, pci_conf_read (tag, reg +4), data & ~7); 1819 reg += 4; 1820 break; 1821 } 1822 } 1823 } 1824 } 1825} 1826 1827/* 1828 * This is the user interface to the PCI configuration space. 1829 */ 1830 1831 1832static void 1833pci_remember(int bus, int dev, int func, struct pci_device *dvp) 1834{ 1835 struct pci_conf *p; 1836 pcici_t tag; 1837 1838 if (++pci_dev_list_count > pci_dev_list_size) { 1839 struct pci_conf *new; 1840 1841 pci_dev_list_size += 8; 1842 MALLOC(new, struct pci_conf *, pci_dev_list_size * sizeof *new, 1843 M_DEVL, M_NOWAIT); 1844 if (!new) { 1845 pci_dev_list_size -= 8; 1846 pci_dev_list_count--; 1847 return; 1848 } 1849 1850 if (pci_dev_list) { 1851 bcopy(pci_dev_list, new, ((pci_dev_list_size - 8) * 1852 sizeof *new)); 1853 FREE(pci_dev_list, M_DEVL); 1854 } 1855 pci_dev_list = new; 1856 } 1857 1858 p = &pci_dev_list[pci_dev_list_count - 1]; 1859 p->pc_sel.pc_bus = bus; 1860 p->pc_sel.pc_dev = dev; 1861 p->pc_sel.pc_func = func; 1862 p->pc_dvp = dvp; 1863 p->pc_cb = pcicb; 1864 1865 tag = pcibus->pb_tag (bus, dev, func); 1866 p->pc_hdr = (pci_conf_read (tag, PCI_HEADER_MISC) >> 16) & 0xff; 1867 p->pc_devid = pci_conf_read(tag, PCI_ID_REG); 1868 p->pc_class = pci_conf_read(tag, PCI_CLASS_REG); 1869 switch (p->pc_hdr & 0x7f) { 1870 case 0: 1871 p->pc_subid = pci_conf_read(tag, PCI_SUBID_REG0); 1872 break; 1873 case 1: 1874 p->pc_subid = pci_conf_read(tag, PCI_SUBID_REG1); 1875 break; 1876 case 2: 1877 p->pc_subid = pci_conf_read(tag, PCI_SUBID_REG2); 1878 break; 1879 default: 1880 p->pc_subid = 0; 1881 } 1882} 1883 1884static int 1885pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 1886{ 1887 if ((oflags & FWRITE) && securelevel > 0) { 1888 return EPERM; 1889 } 1890 1891 return 0; 1892} 1893 1894static int 1895pci_close(dev_t dev, int flag, int devtype, struct proc *p) 1896{ 1897 return 0; 1898} 1899 1900static int 1901pci_ioctl(dev_t dev, int cmd, caddr_t data, int flag, struct proc *p) 1902{ 1903 struct pci_conf_io *cio; 1904 struct pci_io *io; 1905 size_t iolen; 1906 int error; 1907 pcici_t tag; 1908 1909 if (cmd != PCIOCGETCONF && !(flag & FWRITE)) 1910 return EPERM; 1911 1912 switch(cmd) { 1913 case PCIOCGETCONF: 1914 cio = (struct pci_conf_io *)data; 1915 iolen = min(cio->pci_len, 1916 pci_dev_list_count * sizeof(struct pci_conf)); 1917 cio->pci_len = pci_dev_list_count * sizeof(struct pci_conf); 1918 1919 error = copyout(pci_dev_list, cio->pci_buf, iolen); 1920 break; 1921 1922 case PCIOCREAD: 1923 io = (struct pci_io *)data; 1924 switch(io->pi_width) { 1925 case 4: 1926 tag = pcibus->pb_tag (io->pi_sel.pc_bus, 1927 io->pi_sel.pc_dev, 1928 io->pi_sel.pc_func); 1929 io->pi_data = pci_conf_read(tag, io->pi_reg); 1930 error = 0; 1931 break; 1932 case 2: 1933 case 1: 1934 default: 1935 error = ENODEV; 1936 break; 1937 } 1938 break; 1939 1940 case PCIOCWRITE: 1941 io = (struct pci_io *)data; 1942 switch(io->pi_width) { 1943 case 4: 1944 tag = pcibus->pb_tag (io->pi_sel.pc_bus, 1945 io->pi_sel.pc_dev, 1946 io->pi_sel.pc_func); 1947 pci_conf_write(tag, io->pi_reg, io->pi_data); 1948 error = 0; 1949 break; 1950 case 2: 1951 case 1: 1952 default: 1953 error = ENODEV; 1954 break; 1955 } 1956 break; 1957 1958 case PCIOCATTACHED: 1959 io = (struct pci_io *)data; 1960 switch(io->pi_width) { 1961 case 4: 1962 { 1963 int i = pci_dev_list_count; 1964 struct pci_conf *p = pci_dev_list; 1965 error = ENODEV; 1966 while (i--) { 1967 if (io->pi_sel.pc_bus == p->pc_sel.pc_bus && 1968 io->pi_sel.pc_dev == p->pc_sel.pc_dev && 1969 io->pi_sel.pc_func == p->pc_sel.pc_func) { 1970 io->pi_data = (u_int32_t)p->pc_dvp; 1971 error = 0; 1972 break; 1973 } 1974 p++; 1975 } 1976 } 1977 break; 1978 case 2: 1979 case 1: 1980 default: 1981 error = ENODEV; 1982 break; 1983 } 1984 break; 1985 1986 default: 1987 error = ENOTTY; 1988 break; 1989 } 1990 1991 return (error); 1992} 1993 1994#define PCI_CDEV 78 1995 1996static struct cdevsw pcicdev = { 1997 pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset, 1998 nodevtotty, noselect, nommap, nostrategy, "pci", 0, PCI_CDEV 1999}; 2000 2001#ifdef DEVFS 2002static void *pci_devfs_token; 2003#endif 2004 2005static void 2006pci_cdevinit(void *dummy) 2007{ 2008 dev_t dev; 2009 2010 dev = makedev(PCI_CDEV, 0); 2011 cdevsw_add(&dev, &pcicdev, NULL); 2012#ifdef DEVFS 2013 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 2014 UID_ROOT, GID_WHEEL, 0644, "pci"); 2015#endif 2016} 2017 2018SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 2019 2020#endif /* NPCI */ 2021