pci.c revision 19695
1/************************************************************************** 2** 3** $Id: pci.c,v 1.57 1996/10/22 20:20:11 se Exp $ 4** 5** General subroutines for the PCI bus. 6** pci_configure () 7** 8** FreeBSD 9** 10**------------------------------------------------------------------------- 11** 12** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 13** 14** Redistribution and use in source and binary forms, with or without 15** modification, are permitted provided that the following conditions 16** are met: 17** 1. Redistributions of source code must retain the above copyright 18** notice, this list of conditions and the following disclaimer. 19** 2. Redistributions in binary form must reproduce the above copyright 20** notice, this list of conditions and the following disclaimer in the 21** documentation and/or other materials provided with the distribution. 22** 3. The name of the author may not be used to endorse or promote products 23** derived from this software without specific prior written permission. 24** 25** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35** 36*************************************************************************** 37*/ 38 39#include "pci.h" 40#if NPCI > 0 41 42/*======================================================== 43** 44** #includes and declarations 45** 46**======================================================== 47*/ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/malloc.h> 52#include <sys/errno.h> 53#include <sys/kernel.h> 54#include <sys/proc.h> /* declaration of wakeup(), used by vm.h */ 55#include <sys/conf.h> 56#ifdef DEVFS 57#include <sys/devfsext.h> 58#endif /* DEVFS */ 59#include <sys/fcntl.h> 60 61#include <vm/vm.h> 62#include <vm/vm_param.h> 63#include <vm/pmap.h> 64 65 66#include <i386/isa/isa_device.h> /* XXX inthand2_t */ 67 68#include <pci/pcivar.h> 69#include <pci/pcireg.h> 70#include <pci/pcibus.h> 71#include <pci/pci_ioctl.h> 72 73#define PCI_MAX_IRQ (16) 74 75 76/*======================================================== 77** 78** Structs and Functions 79** 80**======================================================== 81*/ 82 83struct pcicb { 84 struct pcicb *pcicb_next; 85 struct pcicb *pcicb_up; 86 struct pcicb *pcicb_down; 87 pcici_t pcicb_bridge; 88 89 u_long pcicb_seen; 90 u_char pcicb_bus; 91 u_char pcicb_subordinate; 92 u_char pcicb_flags; 93#define PCICB_ISAMEM 0x01 94 u_int pcicb_mfrom; 95 u_int pcicb_mupto; 96 u_int pcicb_mamount; 97 u_short pcicb_pfrom; 98 u_short pcicb_pupto; 99 u_short pcicb_pamount; 100 u_char pcicb_bfrom; 101 u_char pcicb_bupto; 102 103 u_long pcicb_iobase; 104 u_long pcicb_iolimit; 105 u_long pcicb_membase; 106 u_long pcicb_memlimit; 107 u_long pcicb_p_membase; 108 u_long pcicb_p_memlimit; 109}; 110 111static void 112not_supported (pcici_t tag, u_long type); 113 114static void 115pci_bus_config (void); 116 117static int 118pci_bridge_config (void); 119 120static int 121pci_mfdev (int bus, int device); 122 123static void pci_remember (int bus, int dev, int func); 124 125/*======================================================== 126** 127** Variables 128** 129**======================================================== 130*/ 131 132/* 133** log2 of safe burst len (in words) 134*/ 135 136unsigned pci_max_burst_len = 3; /* 2=16Byte, 3=32Byte, 4=64Byte, ... */ 137unsigned pci_mechanism = 0; 138unsigned pci_maxdevice = 0; 139unsigned pciroots = 0; /* XXX pcisupport.c increments this 140 * for the Orion host to PCI bridge 141 * UGLY hack ... :( Will be changed :) 142 */ 143static struct pcibus* pcibus; 144 145/*-------------------------------------------------------- 146** 147** Local variables. 148** 149**-------------------------------------------------------- 150*/ 151 152static int pci_conf_count; 153static int pci_info_done; 154static int pcibusmax; 155static struct pcicb *pcicb; 156 157/*----------------------------------------------------------------- 158** 159** The following functions are provided for the device driver 160** to read/write the configuration space. 161** 162** pci_conf_read(): 163** Read a long word from the pci configuration space. 164** Requires a tag (from pcitag) and the register 165** number (should be a long word alligned one). 166** 167** pci_conf_write(): 168** Writes a long word to the pci configuration space. 169** Requires a tag (from pcitag), the register number 170** (should be a long word alligned one), and a value. 171** 172**----------------------------------------------------------------- 173*/ 174 175u_long 176pci_conf_read (pcici_t tag, u_long reg) 177{ 178 return (pcibus->pb_read (tag, reg)); 179} 180 181void 182pci_conf_write (pcici_t tag, u_long reg, u_long data) 183{ 184 pcibus->pb_write (tag, reg, data); 185} 186 187/*======================================================== 188** 189** Subroutines for configuration. 190** 191**======================================================== 192*/ 193 194static void 195pci_register_io (struct pcicb * cb, u_int base, u_int limit) 196{ 197#ifdef PCI_BRIDGE_DEBUG 198 if (bootverbose) 199 printf ("register_io: bus=%d base=%x limit=%x\n", 200 cb->pcicb_bus, base, limit); 201#endif 202 203 if (!cb->pcicb_pfrom || base < cb->pcicb_pfrom) 204 cb->pcicb_pfrom = base; 205 if (limit > cb->pcicb_pupto) 206 cb->pcicb_pupto = limit; 207 208 /* 209 ** XXX should set bridge io mapping here 210 ** but it can be mapped in 4k blocks only, 211 ** leading to conflicts with isa/eisa .. 212 */ 213} 214 215static void 216pci_register_memory (struct pcicb * cb, u_int base, u_int limit) 217{ 218#ifdef PCI_BRIDGE_DEBUG 219 if (bootverbose) 220 printf ("register_mem: bus=%d base=%x limit=%x\n", 221 cb->pcicb_bus, base, limit); 222#endif 223 224 if (!cb->pcicb_mfrom || base < cb->pcicb_mfrom) 225 cb->pcicb_mfrom = base; 226 if (limit > cb->pcicb_mupto) 227 cb->pcicb_mupto = limit; 228 /* 229 ** set the bridges mapping 230 ** 231 ** XXX should handle the 1Mb granularity. 232 */ 233 if (cb->pcicb_bridge.tag) { 234 pci_conf_write(cb->pcicb_bridge, 235 PCI_PCI_BRIDGE_MEM_REG, 236 (cb->pcicb_memlimit & 0xffff0000) | 237 (cb->pcicb_membase >> 16)); 238 if (bootverbose) 239 printf ("\t[pci%d uses memory from %x to %x]\n", 240 cb->pcicb_bus, 241 (unsigned) cb->pcicb_membase, 242 (unsigned) cb->pcicb_memlimit); 243 } 244} 245 246/* 247** XXX This function is neither complete nor tested. 248** It's only used if the bios hasn't done it's job 249** of mapping the pci devices in the physical memory. 250*/ 251 252static u_int 253pci_memalloc (struct pcicb * cb, u_int addr, u_int size) 254{ 255 u_int result = 0, limit=0, newbase=0; 256#ifdef PCI_BRIDGE_DEBUG 257 if (bootverbose) 258 printf ("memalloc: bus=%d addr=%x size=%x ..\n", 259 cb->pcicb_bus, addr, size); 260#endif 261 262 if (!cb) goto done; 263 264 if (!cb->pcicb_membase) { 265 printf ("memalloc: bus%d: membase not set.\n", 266 cb->pcicb_bus); 267 goto done; 268 } 269 270 /* 271 ** get upper allocation limit 272 */ 273 limit = cb->pcicb_memlimit; 274 if (cb->pcicb_mfrom && cb->pcicb_mfrom <= limit) 275 limit = cb->pcicb_mfrom-1; 276 277 /* 278 ** address fixed, and impossible to allocate ? 279 */ 280 if (addr && addr+size-1 > limit) 281 goto done; 282 283 /* 284 ** get possible address 285 */ 286 287 result = addr; 288 if (!result) result = ((limit + 1) / size - 1) * size; 289 290 /* 291 ** if not local available, request from parent. 292 */ 293 294 if (result < cb->pcicb_membase) { 295 newbase = pci_memalloc (cb->pcicb_up, result, size); 296 if (newbase) cb->pcicb_membase = result; 297 else result=0; 298 } 299done: 300 if (result) 301 pci_register_memory (cb, result, result+size-1); 302 303#ifdef PCI_BRIDGE_DEBUG 304 printf ("memalloc: bus=%d addr=%x size=%x --> %x (limit=%x).\n", 305 cb->pcicb_bus, addr, size, result, limit); 306#endif 307 308 return (result); 309} 310 311/*======================================================== 312** 313** pci_bridge_config() 314** 315** Configuration of a pci bridge. 316** 317**======================================================== 318*/ 319 320static int 321pci_bridge_config (void) 322{ 323 pcici_t tag; 324 struct pcicb* parent; 325 326 tag = pcicb->pcicb_bridge; 327 if (tag.tag) { 328 329 if (!pcicb->pcicb_bus) { 330 u_int data; 331 /* 332 ** Get the lowest available bus number. 333 */ 334 pcicb->pcicb_bus = ++pcibusmax; 335 336 /* 337 ** and configure the bridge 338 */ 339 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 340 data = PCI_PRIMARY_BUS_INSERT(data, pcicb->pcicb_up->pcicb_bus); 341 data = PCI_SECONDARY_BUS_INSERT(data, pcicb->pcicb_bus); 342 data = PCI_SUBORDINATE_BUS_INSERT(data, pcicb->pcicb_bus); 343 pci_conf_write (tag, PCI_PCI_BRIDGE_BUS_REG, data); 344 345 /* 346 ** Propagate the new upper bus number limit. 347 */ 348 for (parent = pcicb->pcicb_up; parent != NULL; 349 parent = parent->pcicb_up) 350 { 351 if (parent->pcicb_subordinate >= pcicb->pcicb_bus) 352 continue; 353 parent->pcicb_subordinate = pcicb->pcicb_bus; 354 if (!parent->pcicb_bridge.tag) 355 continue; 356 data = pci_conf_read 357 (parent->pcicb_bridge, PCI_PCI_BRIDGE_BUS_REG); 358 data = PCI_SUBORDINATE_BUS_INSERT 359 (data, pcicb->pcicb_bus); 360 pci_conf_write (parent->pcicb_bridge, 361 PCI_PCI_BRIDGE_BUS_REG, data); 362 } 363 } 364 365 if (!pcicb->pcicb_membase) { 366 u_int size = 0x100000; 367 pcicb->pcicb_membase = pci_memalloc (pcicb->pcicb_up, 0, size); 368 if (pcicb->pcicb_membase) 369 pcicb->pcicb_memlimit = pcicb->pcicb_membase+size-1; 370 } 371 } 372 return pcicb->pcicb_bus; 373} 374 375/*======================================================== 376** 377** pci_bus_config() 378** 379** Autoconfiguration of one pci bus. 380** 381**======================================================== 382*/ 383 384static int 385pci_mfdev (int bus, int device) 386{ 387 pcici_t tag0,tag1; 388 unsigned pci_id0, pci_id1; 389 390 /* 391 ** Detect a multi-function device that complies to the PCI 2.0 spec 392 */ 393 tag0 = pcibus->pb_tag (bus, device, 0); 394 if (pci_conf_read (tag0, PCI_HEADER_MISC) & PCI_HEADER_MULTIFUNCTION) 395 return 1; 396 397 /* 398 ** Well, as always: Theory and implementation of PCI ... 399 ** 400 ** If there is a valid device ID returned for function 1 AND 401 ** the device ID of function 0 and 1 is different OR 402 ** the first mapping register of 0 and 1 differs, 403 ** then assume a multi-function device anyway ... 404 ** 405 ** Example of such a broken device: ISA and IDE chip i83371FB (Triton) 406 */ 407 tag1 = pcibus->pb_tag (bus, device, 1); 408 pci_id1 = pci_conf_read (tag1, PCI_ID_REG); 409 410 if (pci_id1 != 0xffffffff) { 411 412 pci_id0 = pci_conf_read (tag0, PCI_ID_REG); 413 414 if (pci_id0 != pci_id1) 415 return 1; 416 417 if (pci_conf_read (tag0, PCI_MAP_REG_START) 418 != pci_conf_read (tag1, PCI_MAP_REG_START)) 419 return 1; 420 } 421 return 0; 422} 423 424static void 425pci_bus_config (void) 426{ 427 int bus_no; 428 u_char device; 429 u_char reg; 430 pcici_t tag, mtag; 431 pcidi_t type; 432 u_long data; 433 int unit; 434 u_char pciint; 435 int irq; 436 437 struct pci_device *dvp; 438 439 /* 440 ** first initialize the bridge (bus controller chip) 441 */ 442 bus_no = pci_bridge_config (); 443 444 printf ("Probing for devices on PCI bus %d:\n", bus_no); 445#ifndef PCI_QUIET 446 if (bootverbose && !pci_info_done) { 447 pci_info_done=1; 448 printf ("\tconfiguration mode %d allows %d devices.\n", 449 pci_mechanism, pci_maxdevice); 450 }; 451#endif 452 for (device=0; device<pci_maxdevice; device ++) { 453 char *name = NULL; 454 struct pci_device **dvpp; 455 int func, maxfunc = 0; 456 457 if ((pcicb->pcicb_seen >> device) & 1) 458 continue; 459 460 for (func=0; func <= maxfunc; func++) { 461 tag = pcibus->pb_tag (bus_no, device, func); 462 type = pci_conf_read (tag, PCI_ID_REG); 463 464 if ((!type) || (type==0xfffffffful)) continue; 465 466 /* 467 ** lookup device in ioconfiguration: 468 */ 469 470 dvpp = (struct pci_device **)pcidevice_set.ls_items; 471 472 while (dvp = *dvpp++) { 473 if (dvp->pd_probe) { 474 if (name=(*dvp->pd_probe)(tag, type)) 475 break; 476 } 477 }; 478 /* 479 ** check for mirrored devices. 480 */ 481 if (func != 0) { 482 goto real_device; 483 } 484 if (device & 0x10) { 485 mtag=pcibus->pb_tag (bus_no, 486 (u_char)(device & ~0x10), 0); 487 } else if (device & 0x08) { 488 mtag=pcibus->pb_tag (bus_no, 489 (u_char)(device & ~0x08), 0); 490 } else goto real_device; 491 492 if (type!=pci_conf_read (mtag, PCI_ID_REG)) 493 goto real_device; 494 495 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) 496 if (pci_conf_read(tag,reg)!=pci_conf_read(mtag,reg)) 497 goto real_device; 498 499#ifndef PCI_QUIET 500 if (dvp==NULL) continue; 501 if (bootverbose) 502 printf ("%s? <%s> mirrored on pci%d:%d\n", 503 dvp->pd_name, name, bus_no, device); 504#endif 505 continue; 506 507 real_device: 508 509#ifndef PCI_QUIET 510#ifdef PCI_BRIDGE_DEBUG 511 if (bootverbose) { 512 printf ("\tconfig header: 0x%08x 0x%08x 0x%08x 0x%08x\n", 513 pci_conf_read (tag, 0), 514 pci_conf_read (tag, 4), 515 pci_conf_read (tag, 8), 516 pci_conf_read (tag, 12)); 517 } 518#endif 519#endif 520 521 if (func == 0 && pci_mfdev (bus_no, device)) { 522 maxfunc = 7; 523 } 524 525 pci_remember(bus_no, device, func); 526 527 if (dvp==NULL) { 528#ifndef PCI_QUIET 529 if (pci_conf_count) 530 continue; 531 532 if (maxfunc == 0) 533 printf("%s%d:%d: ", 534 pcibus->pb_name, bus_no, device); 535 else 536 printf("%s%d:%d:%d: ", 537 pcibus->pb_name, bus_no, device, func); 538 not_supported (tag, type); 539#endif 540 continue; 541 }; 542 543 pcicb->pcicb_seen |= (1ul << device); 544 545 /* 546 ** Get and increment the unit. 547 */ 548 549 unit = (*dvp->pd_count)++; 550 551 /* 552 ** ignore device ? 553 */ 554 555 if (!*name) continue; 556 557 /* 558 ** Announce this device 559 */ 560 561 printf ("%s%d <%s> rev %d", dvp->pd_name, unit, name, 562 (unsigned) pci_conf_read (tag, PCI_CLASS_REG) & 0xff); 563 564 /* 565 ** Get the int pin number (pci interrupt number a-d) 566 ** from the pci configuration space. 567 */ 568 569 data = pci_conf_read (tag, PCI_INTERRUPT_REG); 570 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 571 572 if (pciint) { 573 574 printf (" int %c irq ", 0x60+pciint); 575 576 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 577 578 /* 579 ** If it's zero, the isa irq number is unknown, 580 ** and we cannot bind the pci interrupt. 581 */ 582 583 if (irq && (irq != 0xff)) 584 printf ("%d", irq); 585 else 586 printf ("??"); 587 }; 588 589 if (maxfunc == 0) 590 printf (" on pci%d:%d\n", bus_no, device); 591 else 592 printf (" on pci%d:%d:%d\n", bus_no, device, func); 593 594 /* 595 ** Read the current mapping, 596 ** and update the pcicb fields. 597 */ 598 599 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) { 600 u_int map, addr, size; 601 602 data = pci_conf_read(tag, PCI_CLASS_REG); 603 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 604 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 605 continue; 606 }; 607 608 map = pci_conf_read (tag, reg); 609 if (!(map & PCI_MAP_MEMORY_ADDRESS_MASK)) 610 continue; 611 612 pci_conf_write (tag, reg, 0xffffffff); 613 data = pci_conf_read (tag, reg); 614 pci_conf_write (tag, reg, map); 615 616 switch (data & 7) { 617 618 default: 619 continue; 620 case 1: 621 case 5: 622 addr = map & PCI_MAP_IO_ADDRESS_MASK; 623 size = -(data & PCI_MAP_IO_ADDRESS_MASK); 624 size &= ~(addr ^ -addr); 625 626 pci_register_io (pcicb, addr, addr+size-1); 627 pcicb->pcicb_pamount += size; 628 break; 629 630 case 0: 631 case 2: 632 case 4: 633 size = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 634 addr = map & PCI_MAP_MEMORY_ADDRESS_MASK; 635 if (addr >= 0x100000) { 636 pci_register_memory 637 (pcicb, addr, addr+size-1); 638 pcicb->pcicb_mamount += size; 639 } else { 640 pcicb->pcicb_flags |= PCICB_ISAMEM; 641 }; 642 break; 643 }; 644 if (bootverbose) 645 printf ("\tmapreg[%02x] type=%d addr=%08x size=%04x.\n", 646 reg, map&7, addr, size); 647 }; 648 649 /* 650 ** attach device 651 ** may produce additional log messages, 652 ** i.e. when installing subdevices. 653 */ 654 655 (*dvp->pd_attach) (tag, unit); 656 657 /* 658 ** Special processing of certain classes 659 */ 660 661 data = pci_conf_read(tag, PCI_CLASS_REG); 662 663 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 664 struct pcicb *this, **link; 665 unsigned char primary, secondary, subordinate; 666 u_int command; 667 668 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 669 670 /* 671 ** get current configuration of the bridge. 672 */ 673 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 674 primary = PCI_PRIMARY_BUS_EXTRACT (data); 675 secondary = PCI_SECONDARY_BUS_EXTRACT(data); 676 subordinate = PCI_SUBORDINATE_BUS_EXTRACT(data); 677#ifndef PCI_QUIET 678 if (bootverbose) { 679 printf ("\tbridge from pci%d to pci%d through %d.\n", 680 primary, secondary, subordinate); 681 printf ("\tmapping regs: io:%08lx mem:%08lx pmem:%08lx\n", 682 pci_conf_read (tag, PCI_PCI_BRIDGE_IO_REG), 683 pci_conf_read (tag, PCI_PCI_BRIDGE_MEM_REG), 684 pci_conf_read (tag, PCI_PCI_BRIDGE_PMEM_REG)); 685 } 686#endif 687 /* 688 ** check for uninitialized bridge. 689 */ 690 if (!(primary < secondary 691 && secondary <= subordinate 692 && bus_no == primary)) 693 { 694 printf ("\tINCORRECTLY or NEVER CONFIGURED.\n"); 695 /* 696 ** disable this bridge 697 */ 698 pci_conf_write (tag, PCI_COMMAND_STATUS_REG, 699 0xffff0000); 700 secondary = 0; 701 subordinate = 0; 702 }; 703 704 /* 705 ** allocate bus descriptor for bus behind the bridge 706 */ 707 link = &pcicb->pcicb_down; 708 while (*link && (*link)->pcicb_bus < secondary) 709 link = &(*link)->pcicb_next; 710 711 this = malloc (sizeof (*this), M_DEVBUF, M_WAITOK); 712 713 /* 714 ** Initialize this descriptor so far. 715 ** (the initialization is completed just before 716 ** scanning the bus behind the bridge. 717 */ 718 bzero (this, sizeof(*this)); 719 this->pcicb_next = *link; 720 this->pcicb_up = pcicb; 721 this->pcicb_bridge = tag; 722 this->pcicb_bus = secondary; 723 this->pcicb_subordinate = subordinate; 724 725 command = pci_conf_read(tag,PCI_COMMAND_STATUS_REG); 726 727 if (command & PCI_COMMAND_IO_ENABLE){ 728 /* 729 ** Bridge was configured by the bios. 730 ** Read out the mapped io region. 731 */ 732 unsigned reg; 733 734 reg = pci_conf_read (tag, 735 PCI_PCI_BRIDGE_IO_REG); 736 this->pcicb_iobase = 737 PCI_PPB_IOBASE_EXTRACT (reg); 738 this->pcicb_iolimit = 739 PCI_PPB_IOLIMIT_EXTRACT(reg); 740 741 /* 742 ** Note the used io space. 743 */ 744 pci_register_io (pcicb, this->pcicb_iobase, 745 this->pcicb_iolimit); 746 747 }; 748 749 if (command & PCI_COMMAND_MEM_ENABLE) { 750 /* 751 ** Bridge was configured by the bios. 752 ** Read out the mapped memory regions. 753 */ 754 unsigned reg; 755 756 /* 757 ** non prefetchable memory 758 */ 759 reg = pci_conf_read (tag, 760 PCI_PCI_BRIDGE_MEM_REG); 761 this->pcicb_membase = 762 PCI_PPB_MEMBASE_EXTRACT (reg); 763 this->pcicb_memlimit = 764 PCI_PPB_MEMLIMIT_EXTRACT(reg); 765 766 /* 767 ** Register used memory space. 768 */ 769 pci_register_memory (pcicb, 770 this->pcicb_membase, 771 this->pcicb_memlimit); 772 773 /* 774 ** prefetchable memory 775 */ 776 reg = pci_conf_read (tag, 777 PCI_PCI_BRIDGE_PMEM_REG); 778 this->pcicb_p_membase= 779 PCI_PPB_MEMBASE_EXTRACT (reg); 780 this->pcicb_p_memlimit= 781 PCI_PPB_MEMLIMIT_EXTRACT(reg); 782 783 /* 784 ** Register used memory space. 785 */ 786 pci_register_memory (pcicb, 787 this->pcicb_p_membase, 788 this->pcicb_p_memlimit); 789 } 790 791 /* 792 ** Link it in chain. 793 */ 794 *link=this; 795 796 /* 797 ** Update mapping info of parent bus. 798 */ 799 if (!pcicb->pcicb_bfrom||secondary< pcicb->pcicb_bfrom) 800 pcicb->pcicb_bfrom = secondary; 801 if (subordinate > pcicb->pcicb_bupto) 802 pcicb->pcicb_bupto = subordinate; 803 804 break; 805 } 806 } 807 } 808 809#ifndef PCI_QUIET 810 if (bootverbose) { 811 if (pcicb->pcicb_mamount) 812 printf ("%s%d: uses %d bytes of memory from %x upto %x.\n", 813 pcibus->pb_name, bus_no, 814 pcicb->pcicb_mamount, 815 pcicb->pcicb_mfrom, pcicb->pcicb_mupto); 816 if (pcicb->pcicb_pamount) 817 printf ("%s%d: uses %d bytes of I/O space from %x upto %x.\n", 818 pcibus->pb_name, bus_no, 819 pcicb->pcicb_pamount, 820 pcicb->pcicb_pfrom, pcicb->pcicb_pupto); 821 if (pcicb->pcicb_bfrom) 822 printf ("%s%d: subordinate busses from %x upto %x.\n", 823 pcibus->pb_name, bus_no, 824 pcicb->pcicb_bfrom, pcicb->pcicb_bupto); 825 } 826#endif 827} 828 829/*======================================================== 830** 831** pci_configure () 832** 833** Autoconfiguration of pci devices. 834** 835** May be called more than once. 836** Any device is attached only once. 837** 838** Has to take care of mirrored devices, which are 839** entailed by incomplete decoding of pci address lines. 840** 841**======================================================== 842*/ 843 844void pci_configure() 845{ 846 struct pcibus **pbp = (struct pcibus**) pcibus_set.ls_items; 847 848 /* 849 ** check pci bus present 850 */ 851 852 while (!pci_maxdevice && (pcibus = *pbp++)) { 853 (*pcibus->pb_setup)(); 854 } 855 856 if (!pci_maxdevice) return; 857 858 /* 859 ** hello world .. 860 */ 861 862 pciroots = 1; 863 while (pciroots--) { 864 865 pcicb = malloc (sizeof (struct pcicb), M_DEVBUF, M_WAITOK); 866 if (pcicb == NULL) { 867 return; 868 } 869 bzero (pcicb, sizeof (struct pcicb)); 870 pcicb->pcicb_bus = pcibusmax; 871 pcicb->pcicb_iolimit = 0xffff; 872 pcicb->pcicb_membase = 0x02000000; 873 pcicb->pcicb_p_membase = 0x02000000; 874 pcicb->pcicb_memlimit = 0xffffffff; 875 pcicb->pcicb_p_memlimit = 0xffffffff; 876 877 while (pcicb != NULL) { 878 pci_bus_config (); 879 880 if (pcibusmax < pcicb->pcicb_bus) 881 (pcibusmax = pcicb->pcicb_bus); 882 883 if (pcicb->pcicb_down) { 884 pcicb = pcicb->pcicb_down; 885 continue; 886 }; 887 888 while (pcicb && !pcicb->pcicb_next) 889 pcicb = pcicb->pcicb_up; 890 891 if (pcicb) 892 pcicb = pcicb->pcicb_next; 893 } 894 pcibusmax++; 895 } 896 pci_conf_count++; 897} 898 899/*----------------------------------------------------------------------- 900** 901** Map device into port space. 902** 903** Actually the device should have been mapped by the bios. 904** This function only reads and verifies the value. 905** 906** PCI-Specification: 6.2.5.1: address maps 907** 908**----------------------------------------------------------------------- 909*/ 910 911int pci_map_port (pcici_t tag, u_long reg, u_short* pa) 912{ 913 unsigned data, ioaddr, iosize; 914 struct pcicb *link = pcicb; 915 916 /* 917 ** sanity check 918 */ 919 920 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 921 printf ("pci_map_port failed: bad register=0x%x\n", 922 (unsigned)reg); 923 return (0); 924 }; 925 926 /*if (pcicb->pcicb_flags & PCICB_NOIOSET) { 927 printf ("pci_map_port failed: pci%d has not been configured for I/O access\n", 928 pcicb->pcicb_bus); 929 return (0); 930 }*/ 931 932 /* 933 ** get size and type of port 934 ** 935 ** type is in the lowest two bits. 936 ** If device requires 2^n bytes, the next 937 ** n-2 bits are hardwired as 0. 938 */ 939 940 ioaddr = pci_conf_read (tag, reg) & PCI_MAP_IO_ADDRESS_MASK; 941 if (!ioaddr) { 942 printf ("pci_map_port failed: not configured by bios.\n"); 943 return (0); 944 }; 945 946 pci_conf_write (tag, reg, 0xfffffffful); 947 data = pci_conf_read (tag, reg); 948 pci_conf_write (tag, reg, ioaddr); 949 950 if ((data & 0x03) != PCI_MAP_IO) { 951 printf ("pci_map_port failed: bad port type=0x%x\n", 952 (unsigned) data); 953 return (0); 954 }; 955 iosize = -(data & PCI_MAP_IO_ADDRESS_MASK); 956 iosize &= ~(ioaddr ^ -ioaddr); 957 if (ioaddr < pcicb->pcicb_iobase 958 || ioaddr + iosize -1 > pcicb->pcicb_iolimit) { 959 printf ("pci_map_port failed: device's iorange 0x%x-0x%x " 960 "is incompatible with its bridge's range 0x%x-0x%x\n", 961 (unsigned) ioaddr, (unsigned) ioaddr + iosize - 1, 962 (unsigned) pcicb->pcicb_iobase, 963 (unsigned) pcicb->pcicb_iolimit); 964 return (0); 965 } 966 967#ifndef PCI_QUIET 968 if (bootverbose) 969 printf ("\treg%d: ioaddr=0x%x size=0x%x\n", 970 (unsigned) reg, (unsigned) ioaddr, (unsigned) iosize); 971#endif 972 /* 973 ** set the configuration register of and 974 ** return the address to the driver. 975 ** Make sure to enable each upstream bridge 976 ** so I/O and DMA can go all the way. 977 */ 978 979 for (;;) { 980 data = pci_conf_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 981 data |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 982 (void) pci_conf_write(tag, PCI_COMMAND_STATUS_REG, data); 983 if ((link = link->pcicb_up) == NULL) 984 break; 985 tag = link->pcicb_bridge; 986 } 987 988 *pa = ioaddr; 989 990 return (1); 991} 992 993/*----------------------------------------------------------------------- 994** 995** Map device into virtual and physical space 996** 997** Actually the device should have been mapped by the bios. 998** This function only reads and verifies the value. 999** 1000** PCI-Specification: 6.2.5.1: address maps 1001** 1002**----------------------------------------------------------------------- 1003*/ 1004 1005int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa) 1006{ 1007 struct pcicb *link = pcicb; 1008 unsigned data ,paddr; 1009 vm_size_t psize, poffs; 1010 vm_offset_t vaddr; 1011 1012 /* 1013 ** sanity check 1014 */ 1015 1016 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 1017 printf ("pci_map_mem failed: bad register=0x%x\n", 1018 (unsigned)reg); 1019 return (0); 1020 }; 1021 1022 /* 1023 ** save old mapping, get size and type of memory 1024 ** 1025 ** type is in the lowest four bits. 1026 ** If device requires 2^n bytes, the next 1027 ** n-4 bits are read as 0. 1028 */ 1029 1030 paddr = pci_conf_read (tag, reg) & PCI_MAP_MEMORY_ADDRESS_MASK; 1031 pci_conf_write (tag, reg, 0xfffffffful); 1032 data = pci_conf_read (tag, reg); 1033 pci_conf_write (tag, reg, paddr); 1034 1035 /* 1036 ** check the type 1037 */ 1038 1039 if (!((data & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_32BIT_1M 1040 && (paddr & ~0xfffff) == 0) 1041 && (data & PCI_MAP_MEMORY_TYPE_MASK) != PCI_MAP_MEMORY_TYPE_32BIT){ 1042 printf ("pci_map_mem failed: bad memory type=0x%x\n", 1043 (unsigned) data); 1044 return (0); 1045 }; 1046 1047 /* 1048 ** get the size. 1049 */ 1050 1051 psize = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 1052 1053 if (!paddr || paddr == PCI_MAP_MEMORY_ADDRESS_MASK) { 1054 paddr = pci_memalloc (pcicb, 0, psize); 1055 if (!paddr) { 1056 printf ("pci_map_mem: not configured by bios.\n"); 1057 return (0); 1058 }; 1059 pci_register_memory (pcicb, paddr, paddr+psize-1); 1060 }; 1061 1062 if (paddr < pcicb->pcicb_membase || 1063 paddr + psize - 1 > pcicb->pcicb_memlimit) { 1064 printf ("pci_map_mem failed: device's memrange 0x%x-0x%x is " 1065 "incompatible with its bridge's memrange 0x%x-0x%x\n", 1066 (unsigned) paddr, 1067 (unsigned) (paddr + psize - 1), 1068 (unsigned) pcicb->pcicb_membase, 1069 (unsigned) pcicb->pcicb_memlimit); 1070/* return (0);*/ 1071/* ACHTUNG: Ist der Code richtig, wenn eine PCI-PCI-Bridge fuer 1072 * die PCI-Slots verwendet wird, aber die Onboard-Devices direkt 1073 * an der CPU-PCI-Bridge haengen (Siehe Compaq Prolinea Problem) ??? 1074 */ 1075 } 1076 pci_conf_write (tag, reg, paddr); 1077 1078 /* 1079 ** Truncate paddr to page boundary. 1080 ** (Or does pmap_mapdev the job?) 1081 */ 1082 1083 poffs = paddr - trunc_page (paddr); 1084 vaddr = (vm_offset_t) pmap_mapdev (paddr-poffs, psize+poffs); 1085 1086 if (!vaddr) return (0); 1087 1088 vaddr += poffs; 1089 1090#ifndef PCI_QUIET 1091 /* 1092 ** display values. 1093 */ 1094 1095 if (bootverbose) 1096 printf ("\treg%d: virtual=0x%lx physical=0x%lx size=0x%lx\n", 1097 (unsigned) reg, (u_long)vaddr, (u_long)paddr, (u_long)psize); 1098#endif 1099 /* 1100 ** set the configuration register and 1101 ** return the address to the driver 1102 ** Make sure to enable each upstream bridge 1103 ** so memory and DMA can go all the way. 1104 */ 1105 1106 for (;;) { 1107 data = pci_conf_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 1108 data |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1109 (void) pci_conf_write(tag, PCI_COMMAND_STATUS_REG, data); 1110 if ((link = link->pcicb_up) == NULL) 1111 break; 1112 tag = link->pcicb_bridge; 1113 } 1114 1115 *va = vaddr; 1116 *pa = paddr; 1117 1118 return (1); 1119} 1120 1121/*----------------------------------------------------------------------- 1122** 1123** Pci meta interrupt handler 1124** 1125** This handler assumes level triggered interrupts. 1126** It's possible to build a kernel which handles shared 1127** edge triggered interrupts by the options "PCI_EDGE_INT". 1128** But there is a performance penalty. 1129** 1130** (Of course you can delete the #ifdef PCI_EDGE_INT bracketed 1131** code at all :-) :-) :-) 1132** 1133**----------------------------------------------------------------------- 1134*/ 1135 1136static struct pci_int_desc* 1137 pci_int_desc [PCI_MAX_IRQ]; 1138 1139#ifndef NO_SHARED_IRQ 1140 1141static inline unsigned 1142splq (unsigned mask) 1143{ 1144 unsigned temp=cpl; 1145 cpl |= mask; 1146 return temp; 1147} 1148 1149static void 1150pci_int (int irq) 1151{ 1152 struct pci_int_desc * p; 1153 int s; 1154 1155 if (irq<0 || irq >= PCI_MAX_IRQ) { 1156 printf ("pci_int: irq %d out of range, ignored\n", irq); 1157 return; 1158 }; 1159 for (p = pci_int_desc[irq]; p!=NULL; p=p->pcid_next) { 1160 s = splq (*p->pcid_maskptr); 1161 (*p->pcid_handler) (p->pcid_argument); 1162 p-> pcid_tally++; 1163 splx (s); 1164#if 0 1165 if (p->pcid_tally<20) 1166 printf ("PCI_INT: irq=%d h=%p cpl o=%x n=%x val=%d\n", 1167 irq, p->pcid_handler, s, cpl, c); 1168#endif 1169 }; 1170} 1171#endif 1172 1173/*----------------------------------------------------------------------- 1174** 1175** Auxiliary function for interrupt (un)mapping. 1176** 1177**----------------------------------------------------------------------- 1178*/ 1179 1180static u_int 1181getirq (pcici_t tag) 1182{ 1183 u_int irq; 1184 1185 irq = PCI_INTERRUPT_LINE_EXTRACT( 1186 pci_conf_read (tag, PCI_INTERRUPT_REG)); 1187 1188 if (irq <= 0) { 1189 printf ("\tint line register not set by bios\n"); 1190 return (0); 1191 } 1192 1193 if (irq >= pcibus->pb_maxirq || irq >= PCI_MAX_IRQ) { 1194 printf ("\tirq %d invalid.\n", irq); 1195 return (0); 1196 } 1197 1198 return (irq); 1199} 1200 1201static struct pci_int_desc ** 1202getintdescbytag (u_int irq, pcici_t tag) 1203{ 1204 struct pci_int_desc *p, **pp; 1205 1206 pp=&pci_int_desc[irq]; 1207 while (((p=*pp)) && !sametag(p->pcid_tag,tag)) 1208 pp=&p->pcid_next; 1209 1210 if (!p) return (NULL); 1211 1212 return (pp); 1213} 1214 1215static struct pci_int_desc * 1216getintdescbymptr (u_int irq, unsigned * mptr) 1217{ 1218 struct pci_int_desc *p; 1219 1220 for (p=pci_int_desc[irq];p;p=p->pcid_next) 1221 if (p->pcid_maskptr == mptr) break; 1222 return (p); 1223} 1224 1225/*----------------------------------------------------------------------- 1226** 1227** Map pci interrupt. 1228** 1229**----------------------------------------------------------------------- 1230*/ 1231 1232static unsigned pci_mask0 = 0; 1233 1234int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr) 1235{ 1236 u_int irq; 1237 int result, oldspl; 1238 unsigned mask; 1239 struct pci_int_desc *tail, *mdp=NULL, *new=NULL; 1240 1241 /* 1242 ** Get irq line from configuration space, 1243 ** and check for consistency. 1244 */ 1245 1246 irq = getirq (tag); 1247 if (irq >= PCI_MAX_IRQ) { 1248 printf ("\tillegal irq %d.\n", irq); 1249 return (0); 1250 }; 1251 mask= 1ul << irq; 1252 1253 /* 1254 ** disable this interrupt. 1255 */ 1256 1257 oldspl = splq (mask); 1258 1259 /* 1260 ** If handler for this tag already installed, 1261 ** remove it first. 1262 */ 1263 1264 if (getintdescbytag (irq, tag) != NULL) 1265 pci_unmap_int (tag); 1266 1267 /* 1268 ** If this irq not yet included in the mask, include it. 1269 */ 1270 1271 mdp = getintdescbymptr (irq, maskptr); 1272 if (!mdp) { 1273 result = pcibus->pb_imaskinc (irq, maskptr); 1274 if (result) 1275 goto conflict; 1276 }; 1277 1278 /* 1279 ** Allocate descriptor and initialize it. 1280 */ 1281 1282 tail = pci_int_desc[irq]; 1283 1284 new = malloc (sizeof (*new), M_DEVBUF, M_WAITOK); 1285 bzero (new, sizeof (*new)); 1286 1287 new->pcid_next = tail; 1288 new->pcid_tag = tag; 1289 new->pcid_handler = func; 1290 new->pcid_argument = arg; 1291 new->pcid_maskptr = maskptr; 1292 new->pcid_tally = 0; 1293 new->pcid_mask = mask; 1294 1295 /* 1296 ** If first handler: install it. 1297 ** If second handler: install shared-int-handler. 1298 */ 1299 1300 if (!tail) { 1301 /* 1302 ** first handler for this irq. 1303 */ 1304 1305 result = pcibus->pb_iattach 1306 /* 1307 * XXX if we get here, then `func' must be pci_int 1308 * so the bogus casts are almost OK since they just 1309 * undo the bogus casts that were needed to pass 1310 * pci_int and its arg to pci_map_int(). 1311 */ 1312 (irq, (inthand2_t *) func, (int) arg, maskptr); 1313 if (result) goto conflict; 1314 1315#ifdef NO_SHARED_IRQ 1316 } else goto conflict; 1317#else 1318 } else if (!tail->pcid_next) { 1319 /* 1320 ** Second handler for this irq. 1321 */ 1322 1323 if (bootverbose) 1324 printf ("\tusing shared irq %d.\n", irq); 1325 1326 /* 1327 ** replace old handler by shared-int-handler. 1328 */ 1329 1330 result = pcibus->pb_idetach (irq, 1331 (inthand2_t *) tail->pcid_handler); 1332 if (result) 1333 printf ("\tCANNOT DETACH INT HANDLER.\n"); 1334 1335 result = pcibus->pb_iattach (irq, pci_int, irq, &pci_mask0); 1336 if (result) { 1337 printf ("\tCANNOT ATTACH SHARED INT HANDLER.\n"); 1338 goto fail; 1339 }; 1340 } 1341#endif 1342 /* 1343 ** Link new descriptor, reenable ints and done. 1344 */ 1345 1346 pci_int_desc[irq] = new; 1347 splx (oldspl); 1348 return (1); 1349 1350 /* 1351 ** Handle some problems. 1352 */ 1353 1354conflict: 1355 printf ("\tirq %d already in use.\n", irq); 1356fail: 1357 /* 1358 ** If descriptor allocated, free it. 1359 ** If included in mask, remove it. 1360 */ 1361 1362 if (new) free(new, M_DEVBUF); 1363 if (!mdp) (void) pcibus->pb_imaskexc (irq, maskptr); 1364 splx (oldspl); 1365 return (0); 1366} 1367 1368/*----------------------------------------------------------------------- 1369** 1370** Unmap pci interrupt. 1371** 1372**----------------------------------------------------------------------- 1373*/ 1374 1375int pci_unmap_int (pcici_t tag) 1376{ 1377 int result, oldspl; 1378 struct pci_int_desc *this, **hook, *tail; 1379 unsigned irq; 1380 1381 /* 1382 ** Get irq line from configuration space, 1383 ** and check for consistency. 1384 */ 1385 1386 irq = getirq (tag); 1387 if (irq >= PCI_MAX_IRQ) { 1388 printf ("\tillegal irq %d.\n", irq); 1389 return (0); 1390 }; 1391 1392 /* 1393 ** Search and unlink interrupt descriptor. 1394 */ 1395 1396 hook = getintdescbytag (irq, tag); 1397 if (hook == NULL) { 1398 printf ("\tno irq %d handler for pci %x\n", 1399 irq, tag.tag); 1400 return (0); 1401 }; 1402 1403 this = *hook; 1404 *hook= this->pcid_next; 1405 1406 /* 1407 ** Message 1408 */ 1409 1410 printf ("\tirq %d handler %p(%p) unmapped for pci %x after %d ints.\n", 1411 irq, this->pcid_handler, this->pcid_argument, 1412 this->pcid_tag.tag, this->pcid_tally); 1413 1414 /* 1415 ** If this irq no longer included in the mask, remove it. 1416 */ 1417 1418 if (!getintdescbymptr (irq, this->pcid_maskptr)) 1419 (void) pcibus->pb_imaskexc (irq, this->pcid_maskptr); 1420 1421 tail = pci_int_desc[irq]; 1422 1423 if (tail == NULL) { 1424 1425 /* 1426 ** Remove the old handler. 1427 */ 1428 1429 result = pcibus->pb_idetach (irq, 1430 (inthand2_t *) this->pcid_handler); 1431 if (result) 1432 printf ("\tirq %d: cannot remove handler.\n", irq); 1433 1434 } else if (tail->pcid_next == NULL) { 1435 1436 /* 1437 ** Remove the shared int handler. 1438 ** Install the last remaining handler. 1439 */ 1440 1441 oldspl = splq (1ul << irq); 1442 1443 result = pcibus->pb_idetach (irq, pci_int); 1444 if (result) 1445 printf ("\tirq %d: cannot remove handler.\n", irq); 1446 1447 result = pcibus->pb_iattach (irq, 1448 (inthand2_t *) tail->pcid_handler, 1449 (int) tail->pcid_argument, 1450 tail->pcid_maskptr); 1451 1452 if (result) 1453 printf ("\tirq %d: cannot install handler.\n", irq); 1454 1455 splx (oldspl); 1456 }; 1457 1458 free (this, M_DEVBUF); 1459 return (1); 1460} 1461 1462/*----------------------------------------------------------- 1463** 1464** Display of unknown devices. 1465** 1466**----------------------------------------------------------- 1467*/ 1468struct vt { 1469 u_short ident; 1470 char* name; 1471}; 1472 1473static struct vt VendorTable[] = { 1474 {0x0e11, "Compaq"}, 1475 {0x1000, "NCR/Symbios"}, 1476 {0x1002, "ATI Technologies Inc."}, 1477 {0x1004, "VLSI"}, 1478 {0x100B, "National Semiconductor"}, 1479 {0x100E, "Weitek"}, 1480 {0x1011, "Digital Equipment Corporation"}, 1481 {0x1013, "Cirrus Logic"}, 1482 {0x101A, "NCR"}, 1483 {0x1022, "AMD"}, 1484 {0x102B, "Matrox"}, 1485 {0x102C, "Chips & Technologies"}, 1486 {0x1039, "Silicon Integrated Systems"}, 1487 {0x1042, "SMC"}, 1488 {0x1044, "DPT"}, 1489 {0x1045, "OPTI"}, 1490 {0x104B, "Bus Logic"}, 1491 {0x1060, "UMC"}, 1492 {0x1080, "Contaq"}, 1493 {0x1095, "CMD"}, 1494 {0x10b9, "ACER Labs"}, 1495 {0x1106, "VIA Technologies"}, 1496 {0x5333, "S3 Inc."}, 1497 {0x8086, "Intel Corporation"}, 1498 {0x9004, "Adaptec"}, 1499 {0,0} 1500}; 1501 1502typedef struct { 1503 const int subclass; 1504 const char *name; 1505} subclass_name; 1506 1507/* 0x00 prehistoric subclasses */ 1508static const subclass_name old_subclasses[] = 1509{ 1510 { 0x00, "misc" }, 1511 { 0x01, "vga" }, 1512 { 0x00, NULL } 1513}; 1514 1515/* 0x01 mass storage subclasses */ 1516static const subclass_name storage_subclasses[] = 1517{ 1518 { 0x00, "scsi" }, 1519 { 0x01, "ide" }, 1520 { 0x02, "floppy"}, 1521 { 0x03, "ipi" }, 1522 { 0x80, "misc" }, 1523 { 0x00, NULL } 1524}; 1525 1526/* 0x02 network subclasses */ 1527static const subclass_name network_subclasses[] = 1528{ 1529 { 0x00, "ethernet" }, 1530 { 0x01, "tokenring" }, 1531 { 0x02, "fddi" }, 1532 { 0x80, "misc" }, 1533 { 0x00, NULL } 1534}; 1535 1536/* 0x03 display subclasses */ 1537static const subclass_name display_subclasses[] = 1538{ 1539 { 0x00, "vga" }, 1540 { 0x01, "xga" }, 1541 { 0x80, "misc" }, 1542 { 0x00, NULL } 1543}; 1544 1545/* 0x04 multimedia subclasses */ 1546static const subclass_name multimedia_subclasses[] = 1547{ 1548 { 0x00, "video" }, 1549 { 0x01, "audio" }, 1550 { 0x80, "misc" }, 1551 { 0x00, NULL } 1552}; 1553 1554/* 0x05 memory subclasses */ 1555static const subclass_name memory_subclasses[] = 1556{ 1557 { 0x00, "ram" }, 1558 { 0x01, "flash" }, 1559 { 0x80, "misc" }, 1560 { 0x00, NULL } 1561}; 1562 1563/* 0x06 bridge subclasses */ 1564static const subclass_name bridge_subclasses[] = 1565{ 1566 { 0x00, "host" }, 1567 { 0x01, "isa" }, 1568 { 0x02, "eisa" }, 1569 { 0x03, "mc" }, 1570 { 0x04, "pci" }, 1571 { 0x05, "pcmcia"}, 1572 { 0x80, "misc" }, 1573 { 0x00, NULL } 1574}; 1575 1576static const subclass_name *const subclasses[] = { 1577 old_subclasses, 1578 storage_subclasses, 1579 network_subclasses, 1580 display_subclasses, 1581 multimedia_subclasses, 1582 memory_subclasses, 1583 bridge_subclasses, 1584}; 1585 1586static const char *const majclasses[] = { 1587 "old", 1588 "storage", 1589 "network", 1590 "display", 1591 "multimedia", 1592 "memory", 1593 "bridge" 1594}; 1595 1596 1597void not_supported (pcici_t tag, u_long type) 1598{ 1599 u_long reg; 1600 u_long data; 1601 u_char class; 1602 u_char subclass; 1603 struct vt * vp; 1604 int pciint; 1605 int irq; 1606 1607 /* 1608 ** lookup the names. 1609 */ 1610 1611 for (vp=VendorTable; vp->ident; vp++) 1612 if (vp->ident == (type & 0xffff)) 1613 break; 1614 1615 /* 1616 ** and display them. 1617 */ 1618 1619 if (vp->ident) printf (vp->name); 1620 else printf ("vendor=0x%04lx", type & 0xffff); 1621 1622 printf (", device=0x%04lx", type >> 16); 1623 1624 data = pci_conf_read(tag, PCI_CLASS_REG); 1625 class = (data >> 24) & 0xff; 1626 subclass = (data >> 16) & 0xff; 1627 1628 if (class < sizeof(majclasses) / sizeof(majclasses[0])) { 1629 printf(", class=%s", majclasses[class]); 1630 } else { 1631 printf(", class=0x%02x", class); 1632 } 1633 1634 if (class < sizeof(subclasses) / sizeof(subclasses[0])) { 1635 const subclass_name *p = subclasses[class]; 1636 while (p->name && (p->subclass != subclass)) 1637 p++; 1638 if (p->name) { 1639 printf(" (%s)", p->name); 1640 } else { 1641 printf(" (unknown subclass 0x%02lx)", subclass); 1642 } 1643 } else { 1644 printf(", subclass=0x%02x", subclass); 1645 } 1646 1647 data = pci_conf_read (tag, PCI_INTERRUPT_REG); 1648 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 1649 1650 if (pciint) { 1651 1652 printf (" int %c irq ", 0x60+pciint); 1653 1654 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 1655 1656 /* 1657 ** If it's zero, the isa irq number is unknown, 1658 ** and we cannot bind the pci interrupt. 1659 */ 1660 1661 if (irq && (irq != 0xff)) 1662 printf ("%d", irq); 1663 else 1664 printf ("??"); 1665 }; 1666 1667 if (class != (PCI_CLASS_BRIDGE >> 24)) 1668 printf (" [no driver assigned]"); 1669 printf ("\n"); 1670 1671 if (bootverbose) { 1672 if (class == (PCI_CLASS_BRIDGE >> 24)) { 1673 printf ("configuration space registers:"); 1674 for (reg = 0; reg < 0x100; reg+=4) { 1675 if ((reg & 0x0f) == 0) printf ("\n%02x:\t", reg); 1676 printf ("%08x ", pci_conf_read (tag, reg)); 1677 } 1678 printf ("\n"); 1679 } else { 1680 for (reg=PCI_MAP_REG_START; reg<PCI_MAP_REG_END; reg+=4) { 1681 data = pci_conf_read (tag, reg); 1682 if ((data&~7)==0) continue; 1683 switch (data&7) { 1684 1685 case 1: 1686 case 5: 1687 printf ("\tmap(%x): io(%04lx)\n", 1688 reg, data & ~3); 1689 break; 1690 case 0: 1691 printf ("\tmap(%x): mem32(%08lx)\n", 1692 reg, data & ~7); 1693 break; 1694 case 2: 1695 printf ("\tmap(%x): mem20(%05lx)\n", 1696 reg, data & ~7); 1697 break; 1698 case 4: 1699 printf ("\tmap(%x): mem64(%08x%08lx)\n", 1700 reg, pci_conf_read (tag, reg +4), data & ~7); 1701 reg += 4; 1702 break; 1703 } 1704 } 1705 } 1706 } 1707} 1708 1709/* 1710 * This is the user interface to the PCI configuration space. 1711 */ 1712static struct pci_conf *pci_dev_list; 1713static unsigned pci_dev_list_count; 1714static unsigned pci_dev_list_size; 1715 1716static void 1717pci_remember(int bus, int dev, int func) 1718{ 1719 struct pci_conf *p; 1720 pcici_t tag; 1721 1722 if (++pci_dev_list_count > pci_dev_list_size) { 1723 struct pci_conf *new; 1724 1725 pci_dev_list_size += 8; 1726 MALLOC(new, struct pci_conf *, pci_dev_list_size * sizeof *new, 1727 M_DEVL, M_NOWAIT); 1728 if (!new) { 1729 pci_dev_list_size -= 8; 1730 pci_dev_list_count--; 1731 return; 1732 } 1733 1734 if (pci_dev_list) { 1735 bcopy(pci_dev_list, new, ((pci_dev_list_size - 8) * 1736 sizeof *new)); 1737 FREE(pci_dev_list, M_DEVL); 1738 } 1739 pci_dev_list = new; 1740 } 1741 1742 p = &pci_dev_list[pci_dev_list_count - 1]; 1743 p->pc_sel.pc_bus = bus; 1744 p->pc_sel.pc_dev = dev; 1745 p->pc_sel.pc_func = func; 1746 tag = pcibus->pb_tag (bus, dev, func); 1747 p->pc_devid = pci_conf_read(tag, PCI_ID_REG); 1748 p->pc_subid = pci_conf_read(tag, PCI_SUBID_REG); 1749 p->pc_class = pci_conf_read(tag, PCI_CLASS_REG); 1750} 1751 1752static int 1753pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 1754{ 1755 if ((oflags & FWRITE) && securelevel > 0) { 1756 return EPERM; 1757 } 1758 1759 return 0; 1760} 1761 1762static int 1763pci_close(dev_t dev, int flag, int devtype, struct proc *p) 1764{ 1765 return 0; 1766} 1767 1768static int 1769pci_ioctl(dev_t dev, int cmd, caddr_t data, int flag, struct proc *p) 1770{ 1771 struct pci_conf_io *cio; 1772 struct pci_io *io; 1773 size_t iolen; 1774 int error; 1775 pcici_t tag; 1776 1777 if (cmd != PCIOCGETCONF && !(flag & FWRITE)) 1778 return EPERM; 1779 1780 switch(cmd) { 1781 case PCIOCGETCONF: 1782 cio = (struct pci_conf_io *)data; 1783 iolen = min(cio->pci_len, 1784 pci_dev_list_count * sizeof(struct pci_conf)); 1785 cio->pci_len = pci_dev_list_count * sizeof(struct pci_conf); 1786 1787 error = copyout(pci_dev_list, cio->pci_buf, iolen); 1788 break; 1789 1790 case PCIOCREAD: 1791 io = (struct pci_io *)data; 1792 switch(io->pi_width) { 1793 case 4: 1794 tag = pcibus->pb_tag (io->pi_sel.pc_bus, 1795 io->pi_sel.pc_dev, 1796 io->pi_sel.pc_func); 1797 io->pi_data = pci_conf_read(tag, io->pi_reg); 1798 error = 0; 1799 break; 1800 case 2: 1801 case 1: 1802 default: 1803 error = ENODEV; 1804 break; 1805 } 1806 break; 1807 1808 case PCIOCWRITE: 1809 io = (struct pci_io *)data; 1810 switch(io->pi_width) { 1811 case 4: 1812 tag = pcibus->pb_tag (io->pi_sel.pc_bus, 1813 io->pi_sel.pc_dev, 1814 io->pi_sel.pc_func); 1815 pci_conf_write(tag, io->pi_reg, io->pi_data); 1816 error = 0; 1817 break; 1818 case 2: 1819 case 1: 1820 default: 1821 error = ENODEV; 1822 break; 1823 } 1824 break; 1825 1826 default: 1827 error = ENOTTY; 1828 break; 1829 } 1830 1831 return (error); 1832} 1833 1834#define PCI_CDEV 78 1835 1836static struct cdevsw pcicdev = { 1837 pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset, 1838 nodevtotty, noselect, nommap, nostrategy, "pci", 0, PCI_CDEV 1839}; 1840 1841#ifdef DEVFS 1842static void *pci_devfs_token; 1843#endif 1844 1845static void 1846pci_cdevinit(void *dummy) 1847{ 1848 dev_t dev; 1849 1850 dev = makedev(PCI_CDEV, 0); 1851 cdevsw_add(&dev, &pcicdev, NULL); 1852#ifdef DEVFS 1853 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 1854 UID_ROOT, GID_WHEEL, 0644, "pci"); 1855#endif 1856} 1857 1858SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 1859 1860#endif /* NPCI */ 1861