pci.c revision 166714
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 166714 2007-02-14 17:02:15Z jhb $"); 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/endian.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#if defined(__i386__) || defined(__amd64__) 56#include <machine/intr_machdep.h> 57#endif 58 59#include <sys/pciio.h> 60#include <dev/pci/pcireg.h> 61#include <dev/pci/pcivar.h> 62#include <dev/pci/pci_private.h> 63 64#include "pcib_if.h" 65#include "pci_if.h" 66 67#ifdef __HAVE_ACPI 68#include <contrib/dev/acpica/acpi.h> 69#include "acpi_if.h" 70#else 71#define ACPI_PWR_FOR_SLEEP(x, y, z) 72#endif 73 74static uint32_t pci_mapbase(unsigned mapreg); 75static int pci_maptype(unsigned mapreg); 76static int pci_mapsize(unsigned testval); 77static int pci_maprange(unsigned mapreg); 78static void pci_fixancient(pcicfgregs *cfg); 79 80static int pci_porten(device_t pcib, int b, int s, int f); 81static int pci_memen(device_t pcib, int b, int s, int f); 82static void pci_assign_interrupt(device_t bus, device_t dev, 83 int force_route); 84static int pci_add_map(device_t pcib, device_t bus, device_t dev, 85 int b, int s, int f, int reg, 86 struct resource_list *rl, int force, int prefetch); 87static int pci_probe(device_t dev); 88static int pci_attach(device_t dev); 89static void pci_load_vendor_data(void); 90static int pci_describe_parse_line(char **ptr, int *vendor, 91 int *device, char **desc); 92static char *pci_describe_device(device_t dev); 93static int pci_modevent(module_t mod, int what, void *arg); 94static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 95 pcicfgregs *cfg); 96static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 97static uint32_t pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 98 int reg); 99#if 0 100static void pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 101 int reg, uint32_t data); 102#endif 103static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 104static int pci_msi_blacklisted(void); 105 106static device_method_t pci_methods[] = { 107 /* Device interface */ 108 DEVMETHOD(device_probe, pci_probe), 109 DEVMETHOD(device_attach, pci_attach), 110 DEVMETHOD(device_detach, bus_generic_detach), 111 DEVMETHOD(device_shutdown, bus_generic_shutdown), 112 DEVMETHOD(device_suspend, pci_suspend), 113 DEVMETHOD(device_resume, pci_resume), 114 115 /* Bus interface */ 116 DEVMETHOD(bus_print_child, pci_print_child), 117 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 118 DEVMETHOD(bus_read_ivar, pci_read_ivar), 119 DEVMETHOD(bus_write_ivar, pci_write_ivar), 120 DEVMETHOD(bus_driver_added, pci_driver_added), 121 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 122 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 123 124 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 125 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 126 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 127 DEVMETHOD(bus_delete_resource, pci_delete_resource), 128 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 129 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 130 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 131 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 132 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 133 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 134 135 /* PCI interface */ 136 DEVMETHOD(pci_read_config, pci_read_config_method), 137 DEVMETHOD(pci_write_config, pci_write_config_method), 138 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 139 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 140 DEVMETHOD(pci_enable_io, pci_enable_io_method), 141 DEVMETHOD(pci_disable_io, pci_disable_io_method), 142 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 143 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 144 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 145 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 146 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 147 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 148 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 149 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 150 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 151 DEVMETHOD(pci_release_msi, pci_release_msi_method), 152 DEVMETHOD(pci_msi_count, pci_msi_count_method), 153 DEVMETHOD(pci_msix_count, pci_msix_count_method), 154 155 { 0, 0 } 156}; 157 158DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 159 160static devclass_t pci_devclass; 161DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 162MODULE_VERSION(pci, 1); 163 164static char *pci_vendordata; 165static size_t pci_vendordata_size; 166 167 168struct pci_quirk { 169 uint32_t devid; /* Vendor/device of the card */ 170 int type; 171#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 172#define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */ 173 int arg1; 174 int arg2; 175}; 176 177struct pci_quirk pci_quirks[] = { 178 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 179 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 180 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 181 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 182 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 183 184 /* 185 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 186 * or the CMIC-SL (AKA ServerWorks GC_LE). 187 */ 188 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 189 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 190 191 /* 192 * MSI doesn't work on earlier Intel chipsets including 193 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 194 */ 195 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 196 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 197 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 198 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 199 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 200 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 201 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 202 203 /* 204 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 205 * bridge. 206 */ 207 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 208 209 { 0 } 210}; 211 212/* map register information */ 213#define PCI_MAPMEM 0x01 /* memory map */ 214#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 215#define PCI_MAPPORT 0x04 /* port map */ 216 217struct devlist pci_devq; 218uint32_t pci_generation; 219uint32_t pci_numdevs = 0; 220 221/* sysctl vars */ 222SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 223 224static int pci_enable_io_modes = 1; 225TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 226SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 227 &pci_enable_io_modes, 1, 228 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 229enable these bits correctly. We'd like to do this all the time, but there\n\ 230are some peripherals that this causes problems with."); 231 232static int pci_do_power_nodriver = 0; 233TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 234SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 235 &pci_do_power_nodriver, 0, 236 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 237disable. 1 means conservatively place devices into D3 state. 2 means\n\ 238agressively place devices into D3 state. 3 means put absolutely everything\n\ 239in D3 state."); 240 241static int pci_do_power_resume = 1; 242TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 243SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 244 &pci_do_power_resume, 1, 245 "Transition from D3 -> D0 on resume."); 246 247static int pci_do_vpd = 1; 248TUNABLE_INT("hw.pci.enable_vpd", &pci_do_vpd); 249SYSCTL_INT(_hw_pci, OID_AUTO, enable_vpd, CTLFLAG_RW, &pci_do_vpd, 1, 250 "Enable support for VPD."); 251 252static int pci_do_msi = 1; 253TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi); 254SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1, 255 "Enable support for MSI interrupts"); 256 257static int pci_do_msix = 1; 258TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix); 259SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1, 260 "Enable support for MSI-X interrupts"); 261 262static int pci_honor_msi_blacklist = 1; 263TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist); 264SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD, 265 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI"); 266 267/* Find a device_t by bus/slot/function */ 268 269device_t 270pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 271{ 272 struct pci_devinfo *dinfo; 273 274 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 275 if ((dinfo->cfg.bus == bus) && 276 (dinfo->cfg.slot == slot) && 277 (dinfo->cfg.func == func)) { 278 return (dinfo->cfg.dev); 279 } 280 } 281 282 return (NULL); 283} 284 285/* Find a device_t by vendor/device ID */ 286 287device_t 288pci_find_device(uint16_t vendor, uint16_t device) 289{ 290 struct pci_devinfo *dinfo; 291 292 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 293 if ((dinfo->cfg.vendor == vendor) && 294 (dinfo->cfg.device == device)) { 295 return (dinfo->cfg.dev); 296 } 297 } 298 299 return (NULL); 300} 301 302/* return base address of memory or port map */ 303 304static uint32_t 305pci_mapbase(uint32_t mapreg) 306{ 307 int mask = 0x03; 308 if ((mapreg & 0x01) == 0) 309 mask = 0x0f; 310 return (mapreg & ~mask); 311} 312 313/* return map type of memory or port map */ 314 315static int 316pci_maptype(unsigned mapreg) 317{ 318 static uint8_t maptype[0x10] = { 319 PCI_MAPMEM, PCI_MAPPORT, 320 PCI_MAPMEM, 0, 321 PCI_MAPMEM, PCI_MAPPORT, 322 0, 0, 323 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 324 PCI_MAPMEM|PCI_MAPMEMP, 0, 325 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 326 0, 0, 327 }; 328 329 return maptype[mapreg & 0x0f]; 330} 331 332/* return log2 of map size decoded for memory or port map */ 333 334static int 335pci_mapsize(uint32_t testval) 336{ 337 int ln2size; 338 339 testval = pci_mapbase(testval); 340 ln2size = 0; 341 if (testval != 0) { 342 while ((testval & 1) == 0) 343 { 344 ln2size++; 345 testval >>= 1; 346 } 347 } 348 return (ln2size); 349} 350 351/* return log2 of address range supported by map register */ 352 353static int 354pci_maprange(unsigned mapreg) 355{ 356 int ln2range = 0; 357 switch (mapreg & 0x07) { 358 case 0x00: 359 case 0x01: 360 case 0x05: 361 ln2range = 32; 362 break; 363 case 0x02: 364 ln2range = 20; 365 break; 366 case 0x04: 367 ln2range = 64; 368 break; 369 } 370 return (ln2range); 371} 372 373/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 374 375static void 376pci_fixancient(pcicfgregs *cfg) 377{ 378 if (cfg->hdrtype != 0) 379 return; 380 381 /* PCI to PCI bridges use header type 1 */ 382 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 383 cfg->hdrtype = 1; 384} 385 386/* extract header type specific config data */ 387 388static void 389pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 390{ 391#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 392 switch (cfg->hdrtype) { 393 case 0: 394 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 395 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 396 cfg->nummaps = PCI_MAXMAPS_0; 397 break; 398 case 1: 399 cfg->nummaps = PCI_MAXMAPS_1; 400 break; 401 case 2: 402 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 403 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 404 cfg->nummaps = PCI_MAXMAPS_2; 405 break; 406 } 407#undef REG 408} 409 410/* read configuration header into pcicfgregs structure */ 411struct pci_devinfo * 412pci_read_device(device_t pcib, int b, int s, int f, size_t size) 413{ 414#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 415 pcicfgregs *cfg = NULL; 416 struct pci_devinfo *devlist_entry; 417 struct devlist *devlist_head; 418 419 devlist_head = &pci_devq; 420 421 devlist_entry = NULL; 422 423 if (REG(PCIR_DEVVENDOR, 4) != -1) { 424 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 425 if (devlist_entry == NULL) 426 return (NULL); 427 428 cfg = &devlist_entry->cfg; 429 430 cfg->bus = b; 431 cfg->slot = s; 432 cfg->func = f; 433 cfg->vendor = REG(PCIR_VENDOR, 2); 434 cfg->device = REG(PCIR_DEVICE, 2); 435 cfg->cmdreg = REG(PCIR_COMMAND, 2); 436 cfg->statreg = REG(PCIR_STATUS, 2); 437 cfg->baseclass = REG(PCIR_CLASS, 1); 438 cfg->subclass = REG(PCIR_SUBCLASS, 1); 439 cfg->progif = REG(PCIR_PROGIF, 1); 440 cfg->revid = REG(PCIR_REVID, 1); 441 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 442 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 443 cfg->lattimer = REG(PCIR_LATTIMER, 1); 444 cfg->intpin = REG(PCIR_INTPIN, 1); 445 cfg->intline = REG(PCIR_INTLINE, 1); 446 447 cfg->mingnt = REG(PCIR_MINGNT, 1); 448 cfg->maxlat = REG(PCIR_MAXLAT, 1); 449 450 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 451 cfg->hdrtype &= ~PCIM_MFDEV; 452 453 pci_fixancient(cfg); 454 pci_hdrtypedata(pcib, b, s, f, cfg); 455 456 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 457 pci_read_extcap(pcib, cfg); 458 459 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 460 461 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 462 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 463 devlist_entry->conf.pc_sel.pc_func = cfg->func; 464 devlist_entry->conf.pc_hdr = cfg->hdrtype; 465 466 devlist_entry->conf.pc_subvendor = cfg->subvendor; 467 devlist_entry->conf.pc_subdevice = cfg->subdevice; 468 devlist_entry->conf.pc_vendor = cfg->vendor; 469 devlist_entry->conf.pc_device = cfg->device; 470 471 devlist_entry->conf.pc_class = cfg->baseclass; 472 devlist_entry->conf.pc_subclass = cfg->subclass; 473 devlist_entry->conf.pc_progif = cfg->progif; 474 devlist_entry->conf.pc_revid = cfg->revid; 475 476 pci_numdevs++; 477 pci_generation++; 478 } 479 return (devlist_entry); 480#undef REG 481} 482 483static void 484pci_read_extcap(device_t pcib, pcicfgregs *cfg) 485{ 486#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 487#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 488#if defined(__i386__) || defined(__amd64__) 489 uint64_t addr; 490#endif 491 uint32_t val; 492 int ptr, nextptr, ptrptr; 493 494 switch (cfg->hdrtype & PCIM_HDRTYPE) { 495 case 0: 496 case 1: 497 ptrptr = PCIR_CAP_PTR; 498 break; 499 case 2: 500 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 501 break; 502 default: 503 return; /* no extended capabilities support */ 504 } 505 nextptr = REG(ptrptr, 1); /* sanity check? */ 506 507 /* 508 * Read capability entries. 509 */ 510 while (nextptr != 0) { 511 /* Sanity check */ 512 if (nextptr > 255) { 513 printf("illegal PCI extended capability offset %d\n", 514 nextptr); 515 return; 516 } 517 /* Find the next entry */ 518 ptr = nextptr; 519 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 520 521 /* Process this entry */ 522 switch (REG(ptr + PCICAP_ID, 1)) { 523 case PCIY_PMG: /* PCI power management */ 524 if (cfg->pp.pp_cap == 0) { 525 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 526 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 527 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 528 if ((nextptr - ptr) > PCIR_POWER_DATA) 529 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 530 } 531 break; 532#if defined(__i386__) || defined(__amd64__) 533 case PCIY_HT: /* HyperTransport */ 534 /* Determine HT-specific capability type. */ 535 val = REG(ptr + PCIR_HT_COMMAND, 2); 536 switch (val & PCIM_HTCMD_CAP_MASK) { 537 case PCIM_HTCAP_MSI_MAPPING: 538 /* Sanity check the mapping window. */ 539 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4); 540 addr <<= 32; 541 addr = REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4); 542 if (addr != MSI_INTEL_ADDR_BASE) 543 device_printf(pcib, 544 "HT Bridge at %d:%d:%d has non-default MSI window 0x%llx\n", 545 cfg->bus, cfg->slot, cfg->func, 546 (long long)addr); 547 548 /* Enable MSI -> HT mapping. */ 549 val |= PCIM_HTCMD_MSI_ENABLE; 550 WREG(ptr + PCIR_HT_COMMAND, val, 2); 551 break; 552 } 553 break; 554#endif 555 case PCIY_MSI: /* PCI MSI */ 556 cfg->msi.msi_location = ptr; 557 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 558 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 559 PCIM_MSICTRL_MMC_MASK)>>1); 560 break; 561 case PCIY_MSIX: /* PCI MSI-X */ 562 cfg->msix.msix_location = ptr; 563 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 564 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 565 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 566 val = REG(ptr + PCIR_MSIX_TABLE, 4); 567 cfg->msix.msix_table_bar = PCIR_BAR(val & 568 PCIM_MSIX_BIR_MASK); 569 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 570 val = REG(ptr + PCIR_MSIX_PBA, 4); 571 cfg->msix.msix_pba_bar = PCIR_BAR(val & 572 PCIM_MSIX_BIR_MASK); 573 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 574 break; 575 case PCIY_VPD: /* PCI Vital Product Data */ 576 if (pci_do_vpd) { 577 cfg->vpd.vpd_reg = ptr; 578 pci_read_vpd(pcib, cfg); 579 } 580 break; 581 case PCIY_SUBVENDOR: 582 /* Should always be true. */ 583 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) { 584 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 585 cfg->subvendor = val & 0xffff; 586 cfg->subdevice = val >> 16; 587 } 588 break; 589 default: 590 break; 591 } 592 } 593/* REG and WREG use carry through to next functions */ 594} 595 596/* 597 * PCI Vital Product Data 598 */ 599static uint32_t 600pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg) 601{ 602 603 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 604 605 WREG(cfg->vpd.vpd_reg + 2, reg, 2); 606 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) != 0x8000) 607 DELAY(1); /* limit looping */ 608 609 return REG(cfg->vpd.vpd_reg + 4, 4); 610} 611 612#if 0 613static void 614pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 615{ 616 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 617 618 WREG(cfg->vpd.vpd_reg + 4, data, 4); 619 WREG(cfg->vpd.vpd_reg + 2, reg | 0x8000, 2); 620 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) == 0x8000) 621 DELAY(1); /* limit looping */ 622 623 return; 624} 625#endif 626 627struct vpd_readstate { 628 device_t pcib; 629 pcicfgregs *cfg; 630 uint32_t val; 631 int bytesinval; 632 int off; 633 uint8_t cksum; 634}; 635 636static uint8_t 637vpd_nextbyte(struct vpd_readstate *vrs) 638{ 639 uint8_t byte; 640 641 if (vrs->bytesinval == 0) { 642 vrs->val = le32toh(pci_read_vpd_reg(vrs->pcib, vrs->cfg, 643 vrs->off)); 644 vrs->off += 4; 645 byte = vrs->val & 0xff; 646 vrs->bytesinval = 3; 647 } else { 648 vrs->val = vrs->val >> 8; 649 byte = vrs->val & 0xff; 650 vrs->bytesinval--; 651 } 652 653 vrs->cksum += byte; 654 return byte; 655} 656 657static void 658pci_read_vpd(device_t pcib, pcicfgregs *cfg) 659{ 660 struct vpd_readstate vrs; 661 int state; 662 int name; 663 int remain; 664 int end; 665 int i; 666 uint8_t byte; 667 int alloc, off; /* alloc/off for RO/W arrays */ 668 int cksumvalid; 669 int dflen; 670 671 /* init vpd reader */ 672 vrs.bytesinval = 0; 673 vrs.off = 0; 674 vrs.pcib = pcib; 675 vrs.cfg = cfg; 676 vrs.cksum = 0; 677 678 state = 0; 679 name = remain = i = 0; /* shut up stupid gcc */ 680 alloc = off = 0; /* shut up stupid gcc */ 681 dflen = 0; /* shut up stupid gcc */ 682 end = 0; 683 cksumvalid = -1; 684 for (; !end;) { 685 byte = vpd_nextbyte(&vrs); 686#if 0 687 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 688 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 689 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 690#endif 691 switch (state) { 692 case 0: /* item name */ 693 if (byte & 0x80) { 694 remain = vpd_nextbyte(&vrs); 695 remain |= vpd_nextbyte(&vrs) << 8; 696 if (remain > (0x7f*4 - vrs.off)) { 697 end = 1; 698 printf( 699 "pci%d:%d:%d: invalid vpd data, remain %#x\n", 700 cfg->bus, cfg->slot, cfg->func, 701 remain); 702 } 703 name = byte & 0x7f; 704 } else { 705 remain = byte & 0x7; 706 name = (byte >> 3) & 0xf; 707 } 708 switch (name) { 709 case 0x2: /* String */ 710 cfg->vpd.vpd_ident = malloc(remain + 1, 711 M_DEVBUF, M_WAITOK); 712 i = 0; 713 state = 1; 714 break; 715 case 0xf: /* End */ 716 end = 1; 717 state = -1; 718 break; 719 case 0x10: /* VPD-R */ 720 alloc = 8; 721 off = 0; 722 cfg->vpd.vpd_ros = malloc(alloc * 723 sizeof *cfg->vpd.vpd_ros, M_DEVBUF, 724 M_WAITOK); 725 state = 2; 726 break; 727 case 0x11: /* VPD-W */ 728 alloc = 8; 729 off = 0; 730 cfg->vpd.vpd_w = malloc(alloc * 731 sizeof *cfg->vpd.vpd_w, M_DEVBUF, 732 M_WAITOK); 733 state = 5; 734 break; 735 default: /* Invalid data, abort */ 736 end = 1; 737 continue; 738 } 739 break; 740 741 case 1: /* Identifier String */ 742 cfg->vpd.vpd_ident[i++] = byte; 743 remain--; 744 if (remain == 0) { 745 cfg->vpd.vpd_ident[i] = '\0'; 746 state = 0; 747 } 748 break; 749 750 case 2: /* VPD-R Keyword Header */ 751 if (off == alloc) { 752 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 753 (alloc *= 2) * sizeof *cfg->vpd.vpd_ros, 754 M_DEVBUF, M_WAITOK); 755 } 756 cfg->vpd.vpd_ros[off].keyword[0] = byte; 757 cfg->vpd.vpd_ros[off].keyword[1] = vpd_nextbyte(&vrs); 758 dflen = vpd_nextbyte(&vrs); 759 if (dflen == 0 && 760 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 761 2) == 0) { 762 /* 763 * if this happens, we can't trust the rest 764 * of the VPD. 765 */ 766 printf("pci%d:%d:%d: bad keyword length: %d\n", 767 cfg->bus, cfg->slot, cfg->func, dflen); 768 cksumvalid = 0; 769 end = 1; 770 break; 771 } else if (dflen == 0) { 772 cfg->vpd.vpd_ros[off].value = malloc(1 * 773 sizeof *cfg->vpd.vpd_ros[off].value, 774 M_DEVBUF, M_WAITOK); 775 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 776 } else 777 cfg->vpd.vpd_ros[off].value = malloc( 778 (dflen + 1) * 779 sizeof *cfg->vpd.vpd_ros[off].value, 780 M_DEVBUF, M_WAITOK); 781 remain -= 3; 782 i = 0; 783 /* keep in sync w/ state 3's transistions */ 784 if (dflen == 0 && remain == 0) 785 state = 0; 786 else if (dflen == 0) 787 state = 2; 788 else 789 state = 3; 790 break; 791 792 case 3: /* VPD-R Keyword Value */ 793 cfg->vpd.vpd_ros[off].value[i++] = byte; 794 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 795 "RV", 2) == 0 && cksumvalid == -1) { 796 if (vrs.cksum == 0) 797 cksumvalid = 1; 798 else { 799 printf( 800 "pci%d:%d:%d: bad VPD cksum, remain %hhu\n", 801 cfg->bus, cfg->slot, cfg->func, 802 vrs.cksum); 803 cksumvalid = 0; 804 end = 1; 805 break; 806 } 807 } 808 dflen--; 809 remain--; 810 /* keep in sync w/ state 2's transistions */ 811 if (dflen == 0) 812 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 813 if (dflen == 0 && remain == 0) { 814 cfg->vpd.vpd_rocnt = off; 815 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 816 off * sizeof *cfg->vpd.vpd_ros, 817 M_DEVBUF, M_WAITOK); 818 state = 0; 819 } else if (dflen == 0) 820 state = 2; 821 break; 822 823 case 4: 824 remain--; 825 if (remain == 0) 826 state = 0; 827 break; 828 829 case 5: /* VPD-W Keyword Header */ 830 if (off == alloc) { 831 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 832 (alloc *= 2) * sizeof *cfg->vpd.vpd_w, 833 M_DEVBUF, M_WAITOK); 834 } 835 cfg->vpd.vpd_w[off].keyword[0] = byte; 836 cfg->vpd.vpd_w[off].keyword[1] = vpd_nextbyte(&vrs); 837 cfg->vpd.vpd_w[off].len = dflen = vpd_nextbyte(&vrs); 838 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 839 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 840 sizeof *cfg->vpd.vpd_w[off].value, 841 M_DEVBUF, M_WAITOK); 842 remain -= 3; 843 i = 0; 844 /* keep in sync w/ state 6's transistions */ 845 if (dflen == 0 && remain == 0) 846 state = 0; 847 else if (dflen == 0) 848 state = 5; 849 else 850 state = 6; 851 break; 852 853 case 6: /* VPD-W Keyword Value */ 854 cfg->vpd.vpd_w[off].value[i++] = byte; 855 dflen--; 856 remain--; 857 /* keep in sync w/ state 5's transistions */ 858 if (dflen == 0) 859 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 860 if (dflen == 0 && remain == 0) { 861 cfg->vpd.vpd_wcnt = off; 862 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 863 off * sizeof *cfg->vpd.vpd_w, 864 M_DEVBUF, M_WAITOK); 865 state = 0; 866 } else if (dflen == 0) 867 state = 5; 868 break; 869 870 default: 871 printf("pci%d:%d:%d: invalid state: %d\n", 872 cfg->bus, cfg->slot, cfg->func, state); 873 end = 1; 874 break; 875 } 876 } 877 878 if (cksumvalid == 0) { 879 /* read-only data bad, clean up */ 880 for (; off; off--) 881 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 882 883 free(cfg->vpd.vpd_ros, M_DEVBUF); 884 cfg->vpd.vpd_ros = NULL; 885 } 886#undef REG 887#undef WREG 888} 889 890int 891pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 892{ 893 struct pci_devinfo *dinfo = device_get_ivars(child); 894 pcicfgregs *cfg = &dinfo->cfg; 895 896 *identptr = cfg->vpd.vpd_ident; 897 898 if (*identptr == NULL) 899 return ENXIO; 900 901 return 0; 902} 903 904int 905pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 906 const char **vptr) 907{ 908 struct pci_devinfo *dinfo = device_get_ivars(child); 909 pcicfgregs *cfg = &dinfo->cfg; 910 int i; 911 912 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 913 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 914 sizeof cfg->vpd.vpd_ros[i].keyword) == 0) { 915 *vptr = cfg->vpd.vpd_ros[i].value; 916 } 917 918 if (i != cfg->vpd.vpd_rocnt) 919 return 0; 920 921 *vptr = NULL; 922 return ENXIO; 923} 924 925/* 926 * Return the offset in configuration space of the requested extended 927 * capability entry or 0 if the specified capability was not found. 928 */ 929int 930pci_find_extcap_method(device_t dev, device_t child, int capability, 931 int *capreg) 932{ 933 struct pci_devinfo *dinfo = device_get_ivars(child); 934 pcicfgregs *cfg = &dinfo->cfg; 935 u_int32_t status; 936 u_int8_t ptr; 937 938 /* 939 * Check the CAP_LIST bit of the PCI status register first. 940 */ 941 status = pci_read_config(child, PCIR_STATUS, 2); 942 if (!(status & PCIM_STATUS_CAPPRESENT)) 943 return (ENXIO); 944 945 /* 946 * Determine the start pointer of the capabilities list. 947 */ 948 switch (cfg->hdrtype & PCIM_HDRTYPE) { 949 case 0: 950 case 1: 951 ptr = PCIR_CAP_PTR; 952 break; 953 case 2: 954 ptr = PCIR_CAP_PTR_2; 955 break; 956 default: 957 /* XXX: panic? */ 958 return (ENXIO); /* no extended capabilities support */ 959 } 960 ptr = pci_read_config(child, ptr, 1); 961 962 /* 963 * Traverse the capabilities list. 964 */ 965 while (ptr != 0) { 966 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 967 if (capreg != NULL) 968 *capreg = ptr; 969 return (0); 970 } 971 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 972 } 973 974 return (ENOENT); 975} 976 977/* 978 * Support for MSI-X message interrupts. 979 */ 980void 981pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 982{ 983 struct pci_devinfo *dinfo = device_get_ivars(dev); 984 pcicfgregs *cfg = &dinfo->cfg; 985 uint32_t offset; 986 987 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 988 offset = cfg->msix.msix_table_offset + index * 16; 989 bus_write_4(cfg->msix.msix_table_res, offset, address & 0xffffffff); 990 bus_write_4(cfg->msix.msix_table_res, offset + 4, address >> 32); 991 bus_write_4(cfg->msix.msix_table_res, offset + 8, data); 992} 993 994void 995pci_mask_msix(device_t dev, u_int index) 996{ 997 struct pci_devinfo *dinfo = device_get_ivars(dev); 998 pcicfgregs *cfg = &dinfo->cfg; 999 uint32_t offset, val; 1000 1001 KASSERT(cfg->msix.msix_msgnum > index, ("bogus index")); 1002 offset = cfg->msix.msix_table_offset + index * 16 + 12; 1003 val = bus_read_4(cfg->msix.msix_table_res, offset); 1004 if (!(val & PCIM_MSIX_VCTRL_MASK)) { 1005 val |= PCIM_MSIX_VCTRL_MASK; 1006 bus_write_4(cfg->msix.msix_table_res, offset, val); 1007 } 1008} 1009 1010void 1011pci_unmask_msix(device_t dev, u_int index) 1012{ 1013 struct pci_devinfo *dinfo = device_get_ivars(dev); 1014 pcicfgregs *cfg = &dinfo->cfg; 1015 uint32_t offset, val; 1016 1017 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 1018 offset = cfg->msix.msix_table_offset + index * 16 + 12; 1019 val = bus_read_4(cfg->msix.msix_table_res, offset); 1020 if (val & PCIM_MSIX_VCTRL_MASK) { 1021 val &= ~PCIM_MSIX_VCTRL_MASK; 1022 bus_write_4(cfg->msix.msix_table_res, offset, val); 1023 } 1024} 1025 1026int 1027pci_pending_msix(device_t dev, u_int index) 1028{ 1029 struct pci_devinfo *dinfo = device_get_ivars(dev); 1030 pcicfgregs *cfg = &dinfo->cfg; 1031 uint32_t offset, bit; 1032 1033 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 1034 offset = cfg->msix.msix_pba_offset + (index / 4) * 4; 1035 bit = 1 << index % 32; 1036 return (bus_read_4(cfg->msix.msix_pba_res, offset) & bit); 1037} 1038 1039/* 1040 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1041 * returned in *count. After this function returns, each message will be 1042 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1043 */ 1044int 1045pci_alloc_msix_method(device_t dev, device_t child, int *count) 1046{ 1047 struct pci_devinfo *dinfo = device_get_ivars(child); 1048 pcicfgregs *cfg = &dinfo->cfg; 1049 struct resource_list_entry *rle; 1050 int actual, error, i, irq, max; 1051 1052 /* Don't let count == 0 get us into trouble. */ 1053 if (*count == 0) 1054 return (EINVAL); 1055 1056 /* If rid 0 is allocated, then fail. */ 1057 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1058 if (rle != NULL && rle->res != NULL) 1059 return (ENXIO); 1060 1061 /* Already have allocated messages? */ 1062 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1063 return (ENXIO); 1064 1065 /* If MSI is blacklisted for this system, fail. */ 1066 if (pci_msi_blacklisted()) 1067 return (ENXIO); 1068 1069 /* MSI-X capability present? */ 1070 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1071 return (ENODEV); 1072 1073 /* Make sure the appropriate BARs are mapped. */ 1074 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1075 cfg->msix.msix_table_bar); 1076 if (rle == NULL || rle->res == NULL || 1077 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1078 return (ENXIO); 1079 cfg->msix.msix_table_res = rle->res; 1080 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1081 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1082 cfg->msix.msix_pba_bar); 1083 if (rle == NULL || rle->res == NULL || 1084 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1085 return (ENXIO); 1086 } 1087 cfg->msix.msix_pba_res = rle->res; 1088 1089 if (bootverbose) 1090 device_printf(child, 1091 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1092 *count, cfg->msix.msix_msgnum); 1093 max = min(*count, cfg->msix.msix_msgnum); 1094 for (i = 0; i < max; i++) { 1095 /* Allocate a message. */ 1096 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, i, 1097 &irq); 1098 if (error) 1099 break; 1100 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1101 irq, 1); 1102 } 1103 actual = i; 1104 1105 if (bootverbose) { 1106 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1107 if (actual == 1) 1108 device_printf(child, "using IRQ %lu for MSI-X\n", 1109 rle->start); 1110 else { 1111 int run; 1112 1113 /* 1114 * Be fancy and try to print contiguous runs of 1115 * IRQ values as ranges. 'irq' is the previous IRQ. 1116 * 'run' is true if we are in a range. 1117 */ 1118 device_printf(child, "using IRQs %lu", rle->start); 1119 irq = rle->start; 1120 run = 0; 1121 for (i = 1; i < actual; i++) { 1122 rle = resource_list_find(&dinfo->resources, 1123 SYS_RES_IRQ, i + 1); 1124 1125 /* Still in a run? */ 1126 if (rle->start == irq + 1) { 1127 run = 1; 1128 irq++; 1129 continue; 1130 } 1131 1132 /* Finish previous range. */ 1133 if (run) { 1134 printf("-%d", irq); 1135 run = 0; 1136 } 1137 1138 /* Start new range. */ 1139 printf(",%lu", rle->start); 1140 irq = rle->start; 1141 } 1142 1143 /* Unfinished range? */ 1144 if (run) 1145 printf("%d", irq); 1146 printf(" for MSI-X\n"); 1147 } 1148 } 1149 1150 /* Mask all vectors. */ 1151 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1152 pci_mask_msix(child, i); 1153 1154 /* Update control register to enable MSI-X. */ 1155 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1156 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1157 cfg->msix.msix_ctrl, 2); 1158 1159 /* Update counts of alloc'd messages. */ 1160 cfg->msix.msix_alloc = actual; 1161 *count = actual; 1162 return (0); 1163} 1164 1165/* 1166 * By default, pci_alloc_msix() will assign the allocated IRQ resources to 1167 * the first N messages in the MSI-X table. However, device drivers may 1168 * want to use different layouts in the case that they do not allocate a 1169 * full table. This method allows the driver to specify what layout it 1170 * wants. It must be called after a successful pci_alloc_msix() but 1171 * before any of the associated SYS_RES_IRQ resources are allocated via 1172 * bus_alloc_resource(). The 'indices' array contains N (where N equals 1173 * the 'count' returned from pci_alloc_msix()) message indices. The 1174 * indices are 1-based (meaning the first message is at index 1). On 1175 * successful return, each of the messages in the 'indices' array will 1176 * have an associated SYS_RES_IRQ whose rid is equal to the index. Thus, 1177 * if indices contains { 2, 4 }, then upon successful return, the 'child' 1178 * device will have two SYS_RES_IRQ resources available at rids 2 and 4. 1179 */ 1180int 1181pci_remap_msix_method(device_t dev, device_t child, u_int *indices) 1182{ 1183 struct pci_devinfo *dinfo = device_get_ivars(child); 1184 pcicfgregs *cfg = &dinfo->cfg; 1185 struct resource_list_entry *rle; 1186 int count, error, i, j, *irqs; 1187 1188 /* Sanity check the indices. */ 1189 for (i = 0; i < cfg->msix.msix_alloc; i++) 1190 if (indices[i] == 0 || indices[i] > cfg->msix.msix_msgnum) 1191 return (EINVAL); 1192 1193 /* Check for duplicates. */ 1194 for (i = 0; i < cfg->msix.msix_alloc; i++) 1195 for (j = i + 1; j < cfg->msix.msix_alloc; j++) 1196 if (indices[i] == indices[j]) 1197 return (EINVAL); 1198 1199 /* Make sure none of the resources are allocated. */ 1200 for (i = 1, count = 0; count < cfg->msix.msix_alloc; i++) { 1201 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i); 1202 if (rle == NULL) 1203 continue; 1204 if (rle->res != NULL) 1205 return (EBUSY); 1206 count++; 1207 } 1208 1209 /* Save the IRQ values and free the existing resources. */ 1210 irqs = malloc(sizeof(int) * cfg->msix.msix_alloc, M_TEMP, M_WAITOK); 1211 for (i = 1, count = 0; count < cfg->msix.msix_alloc; i++) { 1212 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i); 1213 if (rle == NULL) 1214 continue; 1215 irqs[count] = rle->start; 1216 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i); 1217 count++; 1218 } 1219 1220 /* Map the IRQ values to the new message indices and rids. */ 1221 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1222 resource_list_add(&dinfo->resources, SYS_RES_IRQ, indices[i], 1223 irqs[i], irqs[i], 1); 1224 error = PCIB_REMAP_MSIX(device_get_parent(dev), child, 1225 indices[i], irqs[i]); 1226 KASSERT(error == 0, ("Failed to remap MSI-X message")); 1227 } 1228 if (bootverbose) { 1229 if (cfg->msix.msix_alloc == 1) 1230 device_printf(child, 1231 "Remapped MSI-X IRQ to index %d\n", indices[0]); 1232 else { 1233 device_printf(child, "Remapped MSI-X IRQs to indices"); 1234 for (i = 0; i < cfg->msix.msix_alloc - 1; i++) 1235 printf(" %d,", indices[i]); 1236 printf(" %d\n", indices[cfg->msix.msix_alloc - 1]); 1237 } 1238 } 1239 free(irqs, M_TEMP); 1240 1241 return (0); 1242} 1243 1244static int 1245pci_release_msix(device_t dev, device_t child) 1246{ 1247 struct pci_devinfo *dinfo = device_get_ivars(child); 1248 pcicfgregs *cfg = &dinfo->cfg; 1249 struct resource_list_entry *rle; 1250 int count, i; 1251 1252 /* Do we have any messages to release? */ 1253 if (cfg->msix.msix_alloc == 0) 1254 return (ENODEV); 1255 1256 /* Make sure none of the resources are allocated. */ 1257 for (i = 1, count = 0; count < cfg->msix.msix_alloc; i++) { 1258 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i); 1259 if (rle == NULL) 1260 continue; 1261 if (rle->res != NULL) 1262 return (EBUSY); 1263 count++; 1264 } 1265 1266 /* Update control register with to disable MSI-X. */ 1267 cfg->msix.msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 1268 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1269 cfg->msix.msix_ctrl, 2); 1270 1271 /* Release the messages. */ 1272 for (i = 1, count = 0; count < cfg->msix.msix_alloc; i++) { 1273 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i); 1274 if (rle == NULL) 1275 continue; 1276 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1277 rle->start); 1278 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i); 1279 count++; 1280 } 1281 1282 /* Update alloc count. */ 1283 cfg->msix.msix_alloc = 0; 1284 return (0); 1285} 1286 1287/* 1288 * Return the max supported MSI-X messages this device supports. 1289 * Basically, assuming the MD code can alloc messages, this function 1290 * should return the maximum value that pci_alloc_msix() can return. 1291 * Thus, it is subject to the tunables, etc. 1292 */ 1293int 1294pci_msix_count_method(device_t dev, device_t child) 1295{ 1296 struct pci_devinfo *dinfo = device_get_ivars(child); 1297 pcicfgregs *cfg = &dinfo->cfg; 1298 1299 if (pci_do_msix && cfg->msix.msix_location != 0) 1300 return (cfg->msix.msix_msgnum); 1301 return (0); 1302} 1303 1304/* 1305 * Support for MSI message signalled interrupts. 1306 */ 1307void 1308pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 1309{ 1310 struct pci_devinfo *dinfo = device_get_ivars(dev); 1311 pcicfgregs *cfg = &dinfo->cfg; 1312 1313 /* Write data and address values. */ 1314 cfg->msi.msi_addr = address; 1315 cfg->msi.msi_data = data; 1316 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR, 1317 address & 0xffffffff, 4); 1318 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) { 1319 pci_write_config(dev, cfg->msi.msi_location + 1320 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1321 pci_write_config(dev, cfg->msi.msi_location + 1322 PCIR_MSI_DATA_64BIT, data, 2); 1323 } else 1324 pci_write_config(dev, cfg->msi.msi_location + 1325 PCIR_MSI_DATA, data, 2); 1326 1327 /* Enable MSI in the control register. */ 1328 cfg->msi.msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 1329 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL, 1330 cfg->msi.msi_ctrl, 2); 1331} 1332 1333/* 1334 * Restore MSI registers during resume. If MSI is enabled then 1335 * restore the data and address registers in addition to the control 1336 * register. 1337 */ 1338static void 1339pci_resume_msi(device_t dev) 1340{ 1341 struct pci_devinfo *dinfo = device_get_ivars(dev); 1342 pcicfgregs *cfg = &dinfo->cfg; 1343 uint64_t address; 1344 uint16_t data; 1345 1346 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 1347 address = cfg->msi.msi_addr; 1348 data = cfg->msi.msi_data; 1349 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR, 1350 address & 0xffffffff, 4); 1351 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) { 1352 pci_write_config(dev, cfg->msi.msi_location + 1353 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1354 pci_write_config(dev, cfg->msi.msi_location + 1355 PCIR_MSI_DATA_64BIT, data, 2); 1356 } else 1357 pci_write_config(dev, cfg->msi.msi_location + 1358 PCIR_MSI_DATA, data, 2); 1359 } 1360 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL, 1361 cfg->msi.msi_ctrl, 2); 1362} 1363 1364/* 1365 * Returns true if the specified device is blacklisted because MSI 1366 * doesn't work. 1367 */ 1368int 1369pci_msi_device_blacklisted(device_t dev) 1370{ 1371 struct pci_quirk *q; 1372 1373 if (!pci_honor_msi_blacklist) 1374 return (0); 1375 1376 for (q = &pci_quirks[0]; q->devid; q++) { 1377 if (q->devid == pci_get_devid(dev) && 1378 q->type == PCI_QUIRK_DISABLE_MSI) 1379 return (1); 1380 } 1381 return (0); 1382} 1383 1384/* 1385 * Determine if MSI is blacklisted globally on this sytem. Currently, 1386 * we just check for blacklisted chipsets as represented by the 1387 * host-PCI bridge at device 0:0:0. In the future, it may become 1388 * necessary to check other system attributes, such as the kenv values 1389 * that give the motherboard manufacturer and model number. 1390 */ 1391static int 1392pci_msi_blacklisted(void) 1393{ 1394 device_t dev; 1395 1396 if (!pci_honor_msi_blacklist) 1397 return (0); 1398 1399 dev = pci_find_bsf(0, 0, 0); 1400 if (dev != NULL) 1401 return (pci_msi_device_blacklisted(dev)); 1402 return (0); 1403} 1404 1405/* 1406 * Attempt to allocate *count MSI messages. The actual number allocated is 1407 * returned in *count. After this function returns, each message will be 1408 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 1409 */ 1410int 1411pci_alloc_msi_method(device_t dev, device_t child, int *count) 1412{ 1413 struct pci_devinfo *dinfo = device_get_ivars(child); 1414 pcicfgregs *cfg = &dinfo->cfg; 1415 struct resource_list_entry *rle; 1416 int actual, error, i, irqs[32]; 1417 uint16_t ctrl; 1418 1419 /* Don't let count == 0 get us into trouble. */ 1420 if (*count == 0) 1421 return (EINVAL); 1422 1423 /* If rid 0 is allocated, then fail. */ 1424 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1425 if (rle != NULL && rle->res != NULL) 1426 return (ENXIO); 1427 1428 /* Already have allocated messages? */ 1429 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1430 return (ENXIO); 1431 1432 /* If MSI is blacklisted for this system, fail. */ 1433 if (pci_msi_blacklisted()) 1434 return (ENXIO); 1435 1436 /* MSI capability present? */ 1437 if (cfg->msi.msi_location == 0 || !pci_do_msi) 1438 return (ENODEV); 1439 1440 if (bootverbose) 1441 device_printf(child, 1442 "attempting to allocate %d MSI vectors (%d supported)\n", 1443 *count, cfg->msi.msi_msgnum); 1444 1445 /* Don't ask for more than the device supports. */ 1446 actual = min(*count, cfg->msi.msi_msgnum); 1447 1448 /* Don't ask for more than 32 messages. */ 1449 actual = min(actual, 32); 1450 1451 /* MSI requires power of 2 number of messages. */ 1452 if (!powerof2(actual)) 1453 return (EINVAL); 1454 1455 for (;;) { 1456 /* Try to allocate N messages. */ 1457 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 1458 cfg->msi.msi_msgnum, irqs); 1459 if (error == 0) 1460 break; 1461 if (actual == 1) 1462 return (error); 1463 1464 /* Try N / 2. */ 1465 actual >>= 1; 1466 } 1467 1468 /* 1469 * We now have N actual messages mapped onto SYS_RES_IRQ 1470 * resources in the irqs[] array, so add new resources 1471 * starting at rid 1. 1472 */ 1473 for (i = 0; i < actual; i++) 1474 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 1475 irqs[i], irqs[i], 1); 1476 1477 if (bootverbose) { 1478 if (actual == 1) 1479 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 1480 else { 1481 int run; 1482 1483 /* 1484 * Be fancy and try to print contiguous runs 1485 * of IRQ values as ranges. 'run' is true if 1486 * we are in a range. 1487 */ 1488 device_printf(child, "using IRQs %d", irqs[0]); 1489 run = 0; 1490 for (i = 1; i < actual; i++) { 1491 1492 /* Still in a run? */ 1493 if (irqs[i] == irqs[i - 1] + 1) { 1494 run = 1; 1495 continue; 1496 } 1497 1498 /* Finish previous range. */ 1499 if (run) { 1500 printf("-%d", irqs[i - 1]); 1501 run = 0; 1502 } 1503 1504 /* Start new range. */ 1505 printf(",%d", irqs[i]); 1506 } 1507 1508 /* Unfinished range? */ 1509 if (run) 1510 printf("%d", irqs[actual - 1]); 1511 printf(" for MSI\n"); 1512 } 1513 } 1514 1515 /* Update control register with actual count and enable MSI. */ 1516 ctrl = cfg->msi.msi_ctrl; 1517 ctrl &= ~PCIM_MSICTRL_MME_MASK; 1518 ctrl |= (ffs(actual) - 1) << 4; 1519 cfg->msi.msi_ctrl = ctrl; 1520 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 1521 1522 /* Update counts of alloc'd messages. */ 1523 cfg->msi.msi_alloc = actual; 1524 *count = actual; 1525 return (0); 1526} 1527 1528/* Release the MSI messages associated with this device. */ 1529int 1530pci_release_msi_method(device_t dev, device_t child) 1531{ 1532 struct pci_devinfo *dinfo = device_get_ivars(child); 1533 pcicfgregs *cfg = &dinfo->cfg; 1534 struct resource_list_entry *rle; 1535 int error, i, irqs[32]; 1536 1537 /* Try MSI-X first. */ 1538 error = pci_release_msix(dev, child); 1539 if (error != ENODEV) 1540 return (error); 1541 1542 /* Do we have any messages to release? */ 1543 if (cfg->msi.msi_alloc == 0) 1544 return (ENODEV); 1545 KASSERT(cfg->msi.msi_alloc <= 32, ("more than 32 alloc'd messages")); 1546 1547 /* Make sure none of the resources are allocated. */ 1548 for (i = 0; i < cfg->msi.msi_alloc; i++) { 1549 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1550 KASSERT(rle != NULL, ("missing MSI resource")); 1551 if (rle->res != NULL) 1552 return (EBUSY); 1553 irqs[i] = rle->start; 1554 } 1555 1556 /* Update control register with 0 count and disable MSI. */ 1557 cfg->msi.msi_ctrl &= ~(PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE); 1558 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 1559 cfg->msi.msi_ctrl, 2); 1560 1561 /* Release the messages. */ 1562 PCIB_RELEASE_MSI(device_get_parent(dev), child, cfg->msi.msi_alloc, 1563 irqs); 1564 for (i = 0; i < cfg->msi.msi_alloc; i++) 1565 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1566 1567 /* Update alloc count. */ 1568 cfg->msi.msi_alloc = 0; 1569 return (0); 1570} 1571 1572/* 1573 * Return the max supported MSI messages this device supports. 1574 * Basically, assuming the MD code can alloc messages, this function 1575 * should return the maximum value that pci_alloc_msi() can return. 1576 * Thus, it is subject to the tunables, etc. 1577 */ 1578int 1579pci_msi_count_method(device_t dev, device_t child) 1580{ 1581 struct pci_devinfo *dinfo = device_get_ivars(child); 1582 pcicfgregs *cfg = &dinfo->cfg; 1583 1584 if (pci_do_msi && cfg->msi.msi_location != 0) 1585 return (cfg->msi.msi_msgnum); 1586 return (0); 1587} 1588 1589/* free pcicfgregs structure and all depending data structures */ 1590 1591int 1592pci_freecfg(struct pci_devinfo *dinfo) 1593{ 1594 struct devlist *devlist_head; 1595 int i; 1596 1597 devlist_head = &pci_devq; 1598 1599 if (dinfo->cfg.vpd.vpd_reg) { 1600 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 1601 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 1602 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 1603 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 1604 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 1605 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 1606 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 1607 } 1608 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 1609 free(dinfo, M_DEVBUF); 1610 1611 /* increment the generation count */ 1612 pci_generation++; 1613 1614 /* we're losing one device */ 1615 pci_numdevs--; 1616 return (0); 1617} 1618 1619/* 1620 * PCI power manangement 1621 */ 1622int 1623pci_set_powerstate_method(device_t dev, device_t child, int state) 1624{ 1625 struct pci_devinfo *dinfo = device_get_ivars(child); 1626 pcicfgregs *cfg = &dinfo->cfg; 1627 uint16_t status; 1628 int result, oldstate, highest, delay; 1629 1630 if (cfg->pp.pp_cap == 0) 1631 return (EOPNOTSUPP); 1632 1633 /* 1634 * Optimize a no state change request away. While it would be OK to 1635 * write to the hardware in theory, some devices have shown odd 1636 * behavior when going from D3 -> D3. 1637 */ 1638 oldstate = pci_get_powerstate(child); 1639 if (oldstate == state) 1640 return (0); 1641 1642 /* 1643 * The PCI power management specification states that after a state 1644 * transition between PCI power states, system software must 1645 * guarantee a minimal delay before the function accesses the device. 1646 * Compute the worst case delay that we need to guarantee before we 1647 * access the device. Many devices will be responsive much more 1648 * quickly than this delay, but there are some that don't respond 1649 * instantly to state changes. Transitions to/from D3 state require 1650 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 1651 * is done below with DELAY rather than a sleeper function because 1652 * this function can be called from contexts where we cannot sleep. 1653 */ 1654 highest = (oldstate > state) ? oldstate : state; 1655 if (highest == PCI_POWERSTATE_D3) 1656 delay = 10000; 1657 else if (highest == PCI_POWERSTATE_D2) 1658 delay = 200; 1659 else 1660 delay = 0; 1661 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 1662 & ~PCIM_PSTAT_DMASK; 1663 result = 0; 1664 switch (state) { 1665 case PCI_POWERSTATE_D0: 1666 status |= PCIM_PSTAT_D0; 1667 break; 1668 case PCI_POWERSTATE_D1: 1669 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 1670 return (EOPNOTSUPP); 1671 status |= PCIM_PSTAT_D1; 1672 break; 1673 case PCI_POWERSTATE_D2: 1674 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 1675 return (EOPNOTSUPP); 1676 status |= PCIM_PSTAT_D2; 1677 break; 1678 case PCI_POWERSTATE_D3: 1679 status |= PCIM_PSTAT_D3; 1680 break; 1681 default: 1682 return (EINVAL); 1683 } 1684 1685 if (bootverbose) 1686 printf( 1687 "pci%d:%d:%d: Transition from D%d to D%d\n", 1688 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1689 oldstate, state); 1690 1691 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 1692 if (delay) 1693 DELAY(delay); 1694 return (0); 1695} 1696 1697int 1698pci_get_powerstate_method(device_t dev, device_t child) 1699{ 1700 struct pci_devinfo *dinfo = device_get_ivars(child); 1701 pcicfgregs *cfg = &dinfo->cfg; 1702 uint16_t status; 1703 int result; 1704 1705 if (cfg->pp.pp_cap != 0) { 1706 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 1707 switch (status & PCIM_PSTAT_DMASK) { 1708 case PCIM_PSTAT_D0: 1709 result = PCI_POWERSTATE_D0; 1710 break; 1711 case PCIM_PSTAT_D1: 1712 result = PCI_POWERSTATE_D1; 1713 break; 1714 case PCIM_PSTAT_D2: 1715 result = PCI_POWERSTATE_D2; 1716 break; 1717 case PCIM_PSTAT_D3: 1718 result = PCI_POWERSTATE_D3; 1719 break; 1720 default: 1721 result = PCI_POWERSTATE_UNKNOWN; 1722 break; 1723 } 1724 } else { 1725 /* No support, device is always at D0 */ 1726 result = PCI_POWERSTATE_D0; 1727 } 1728 return (result); 1729} 1730 1731/* 1732 * Some convenience functions for PCI device drivers. 1733 */ 1734 1735static __inline void 1736pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 1737{ 1738 uint16_t command; 1739 1740 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1741 command |= bit; 1742 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1743} 1744 1745static __inline void 1746pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 1747{ 1748 uint16_t command; 1749 1750 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1751 command &= ~bit; 1752 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1753} 1754 1755int 1756pci_enable_busmaster_method(device_t dev, device_t child) 1757{ 1758 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1759 return (0); 1760} 1761 1762int 1763pci_disable_busmaster_method(device_t dev, device_t child) 1764{ 1765 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1766 return (0); 1767} 1768 1769int 1770pci_enable_io_method(device_t dev, device_t child, int space) 1771{ 1772 uint16_t command; 1773 uint16_t bit; 1774 char *error; 1775 1776 bit = 0; 1777 error = NULL; 1778 1779 switch(space) { 1780 case SYS_RES_IOPORT: 1781 bit = PCIM_CMD_PORTEN; 1782 error = "port"; 1783 break; 1784 case SYS_RES_MEMORY: 1785 bit = PCIM_CMD_MEMEN; 1786 error = "memory"; 1787 break; 1788 default: 1789 return (EINVAL); 1790 } 1791 pci_set_command_bit(dev, child, bit); 1792 /* Some devices seem to need a brief stall here, what do to? */ 1793 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1794 if (command & bit) 1795 return (0); 1796 device_printf(child, "failed to enable %s mapping!\n", error); 1797 return (ENXIO); 1798} 1799 1800int 1801pci_disable_io_method(device_t dev, device_t child, int space) 1802{ 1803 uint16_t command; 1804 uint16_t bit; 1805 char *error; 1806 1807 bit = 0; 1808 error = NULL; 1809 1810 switch(space) { 1811 case SYS_RES_IOPORT: 1812 bit = PCIM_CMD_PORTEN; 1813 error = "port"; 1814 break; 1815 case SYS_RES_MEMORY: 1816 bit = PCIM_CMD_MEMEN; 1817 error = "memory"; 1818 break; 1819 default: 1820 return (EINVAL); 1821 } 1822 pci_clear_command_bit(dev, child, bit); 1823 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1824 if (command & bit) { 1825 device_printf(child, "failed to disable %s mapping!\n", error); 1826 return (ENXIO); 1827 } 1828 return (0); 1829} 1830 1831/* 1832 * New style pci driver. Parent device is either a pci-host-bridge or a 1833 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1834 */ 1835 1836void 1837pci_print_verbose(struct pci_devinfo *dinfo) 1838{ 1839 int i; 1840 1841 if (bootverbose) { 1842 pcicfgregs *cfg = &dinfo->cfg; 1843 1844 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1845 cfg->vendor, cfg->device, cfg->revid); 1846 printf("\tbus=%d, slot=%d, func=%d\n", 1847 cfg->bus, cfg->slot, cfg->func); 1848 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1849 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 1850 cfg->mfdev); 1851 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1852 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1853 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1854 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 1855 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1856 if (cfg->intpin > 0) 1857 printf("\tintpin=%c, irq=%d\n", 1858 cfg->intpin +'a' -1, cfg->intline); 1859 if (cfg->pp.pp_cap) { 1860 uint16_t status; 1861 1862 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 1863 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 1864 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 1865 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 1866 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 1867 status & PCIM_PSTAT_DMASK); 1868 } 1869 if (cfg->vpd.vpd_reg) { 1870 printf("\tVPD Ident: %s\n", cfg->vpd.vpd_ident); 1871 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) { 1872 struct vpd_readonly *vrop; 1873 vrop = &cfg->vpd.vpd_ros[i]; 1874 if (strncmp("CP", vrop->keyword, 2) == 0) 1875 printf("\tCP: id %d, BAR%d, off %#x\n", 1876 vrop->value[0], vrop->value[1], 1877 le16toh( 1878 *(uint16_t *)&vrop->value[2])); 1879 else if (strncmp("RV", vrop->keyword, 2) == 0) 1880 printf("\tRV: %#hhx\n", vrop->value[0]); 1881 else 1882 printf("\t%.2s: %s\n", vrop->keyword, 1883 vrop->value); 1884 } 1885 for (i = 0; i < cfg->vpd.vpd_wcnt; i++) { 1886 struct vpd_write *vwp; 1887 vwp = &cfg->vpd.vpd_w[i]; 1888 if (strncmp("RW", vwp->keyword, 2) != 0) 1889 printf("\t%.2s(%#x-%#x): %s\n", 1890 vwp->keyword, vwp->start, 1891 vwp->start + vwp->len, vwp->value); 1892 } 1893 } 1894 if (cfg->msi.msi_location) { 1895 int ctrl; 1896 1897 ctrl = cfg->msi.msi_ctrl; 1898 printf("\tMSI supports %d message%s%s%s\n", 1899 cfg->msi.msi_msgnum, 1900 (cfg->msi.msi_msgnum == 1) ? "" : "s", 1901 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 1902 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 1903 } 1904 if (cfg->msix.msix_location) { 1905 printf("\tMSI-X supports %d message%s ", 1906 cfg->msix.msix_msgnum, 1907 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 1908 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 1909 printf("in map 0x%x\n", 1910 cfg->msix.msix_table_bar); 1911 else 1912 printf("in maps 0x%x and 0x%x\n", 1913 cfg->msix.msix_table_bar, 1914 cfg->msix.msix_pba_bar); 1915 } 1916 } 1917} 1918 1919static int 1920pci_porten(device_t pcib, int b, int s, int f) 1921{ 1922 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1923 & PCIM_CMD_PORTEN) != 0; 1924} 1925 1926static int 1927pci_memen(device_t pcib, int b, int s, int f) 1928{ 1929 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1930 & PCIM_CMD_MEMEN) != 0; 1931} 1932 1933/* 1934 * Add a resource based on a pci map register. Return 1 if the map 1935 * register is a 32bit map register or 2 if it is a 64bit register. 1936 */ 1937static int 1938pci_add_map(device_t pcib, device_t bus, device_t dev, 1939 int b, int s, int f, int reg, struct resource_list *rl, int force, 1940 int prefetch) 1941{ 1942 uint32_t map; 1943 pci_addr_t base; 1944 pci_addr_t start, end, count; 1945 uint8_t ln2size; 1946 uint8_t ln2range; 1947 uint32_t testval; 1948 uint16_t cmd; 1949 int type; 1950 int barlen; 1951 struct resource *res; 1952 1953 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1954 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1955 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1956 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1957 1958 if (pci_maptype(map) & PCI_MAPMEM) 1959 type = SYS_RES_MEMORY; 1960 else 1961 type = SYS_RES_IOPORT; 1962 ln2size = pci_mapsize(testval); 1963 ln2range = pci_maprange(testval); 1964 base = pci_mapbase(map); 1965 barlen = ln2range == 64 ? 2 : 1; 1966 1967 /* 1968 * For I/O registers, if bottom bit is set, and the next bit up 1969 * isn't clear, we know we have a BAR that doesn't conform to the 1970 * spec, so ignore it. Also, sanity check the size of the data 1971 * areas to the type of memory involved. Memory must be at least 1972 * 16 bytes in size, while I/O ranges must be at least 4. 1973 */ 1974 if ((testval & 0x1) == 0x1 && 1975 (testval & 0x2) != 0) 1976 return (barlen); 1977 if ((type == SYS_RES_MEMORY && ln2size < 4) || 1978 (type == SYS_RES_IOPORT && ln2size < 2)) 1979 return (barlen); 1980 1981 if (ln2range == 64) 1982 /* Read the other half of a 64bit map register */ 1983 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 1984 if (bootverbose) { 1985 printf("\tmap[%02x]: type %x, range %2d, base %#jx, size %2d", 1986 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size); 1987 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1988 printf(", port disabled\n"); 1989 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1990 printf(", memory disabled\n"); 1991 else 1992 printf(", enabled\n"); 1993 } 1994 1995 /* 1996 * If base is 0, then we have problems. It is best to ignore 1997 * such entries for the moment. These will be allocated later if 1998 * the driver specifically requests them. However, some 1999 * removable busses look better when all resources are allocated, 2000 * so allow '0' to be overriden. 2001 * 2002 * Similarly treat maps whose values is the same as the test value 2003 * read back. These maps have had all f's written to them by the 2004 * BIOS in an attempt to disable the resources. 2005 */ 2006 if (!force && (base == 0 || map == testval)) 2007 return (barlen); 2008 if ((u_long)base != base) { 2009 device_printf(bus, 2010 "pci%d:%d:%d bar %#x too many address bits", b, s, f, reg); 2011 return (barlen); 2012 } 2013 2014 /* 2015 * This code theoretically does the right thing, but has 2016 * undesirable side effects in some cases where peripherals 2017 * respond oddly to having these bits enabled. Let the user 2018 * be able to turn them off (since pci_enable_io_modes is 1 by 2019 * default). 2020 */ 2021 if (pci_enable_io_modes) { 2022 /* Turn on resources that have been left off by a lazy BIOS */ 2023 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 2024 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 2025 cmd |= PCIM_CMD_PORTEN; 2026 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 2027 } 2028 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 2029 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 2030 cmd |= PCIM_CMD_MEMEN; 2031 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 2032 } 2033 } else { 2034 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 2035 return (barlen); 2036 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 2037 return (barlen); 2038 } 2039 2040 count = 1 << ln2size; 2041 if (base == 0 || base == pci_mapbase(testval)) { 2042 start = 0; /* Let the parent deside */ 2043 end = ~0ULL; 2044 } else { 2045 start = base; 2046 end = base + (1 << ln2size) - 1; 2047 } 2048 resource_list_add(rl, type, reg, start, end, count); 2049 2050 /* 2051 * Not quite sure what to do on failure of allocating the resource 2052 * since I can postulate several right answers. 2053 */ 2054 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 2055 prefetch ? RF_PREFETCHABLE : 0); 2056 if (res == NULL) 2057 return (barlen); 2058 start = rman_get_start(res); 2059 if ((u_long)start != start) { 2060 /* Wait a minute! this platform can't do this address. */ 2061 device_printf(bus, 2062 "pci%d.%d.%x bar %#x start %#jx, too many bits.", 2063 b, s, f, reg, (uintmax_t)start); 2064 resource_list_release(rl, bus, dev, type, reg, res); 2065 return (barlen); 2066 } 2067 pci_write_config(dev, reg, start, 4); 2068 if (ln2range == 64) 2069 pci_write_config(dev, reg + 4, start >> 32, 4); 2070 return (barlen); 2071} 2072 2073/* 2074 * For ATA devices we need to decide early what addressing mode to use. 2075 * Legacy demands that the primary and secondary ATA ports sits on the 2076 * same addresses that old ISA hardware did. This dictates that we use 2077 * those addresses and ignore the BAR's if we cannot set PCI native 2078 * addressing mode. 2079 */ 2080static void 2081pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 2082 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 2083{ 2084 int rid, type, progif; 2085#if 0 2086 /* if this device supports PCI native addressing use it */ 2087 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2088 if ((progif & 0x8a) == 0x8a) { 2089 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 2090 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 2091 printf("Trying ATA native PCI addressing mode\n"); 2092 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 2093 } 2094 } 2095#endif 2096 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2097 type = SYS_RES_IOPORT; 2098 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 2099 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 2100 prefetchmask & (1 << 0)); 2101 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 2102 prefetchmask & (1 << 1)); 2103 } else { 2104 rid = PCIR_BAR(0); 2105 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 2106 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 2107 0); 2108 rid = PCIR_BAR(1); 2109 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 2110 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 2111 0); 2112 } 2113 if (progif & PCIP_STORAGE_IDE_MODESEC) { 2114 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 2115 prefetchmask & (1 << 2)); 2116 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 2117 prefetchmask & (1 << 3)); 2118 } else { 2119 rid = PCIR_BAR(2); 2120 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 2121 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 2122 0); 2123 rid = PCIR_BAR(3); 2124 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 2125 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 2126 0); 2127 } 2128 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 2129 prefetchmask & (1 << 4)); 2130 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 2131 prefetchmask & (1 << 5)); 2132} 2133 2134static void 2135pci_assign_interrupt(device_t bus, device_t dev, int force_route) 2136{ 2137 struct pci_devinfo *dinfo = device_get_ivars(dev); 2138 pcicfgregs *cfg = &dinfo->cfg; 2139 char tunable_name[64]; 2140 int irq; 2141 2142 /* Has to have an intpin to have an interrupt. */ 2143 if (cfg->intpin == 0) 2144 return; 2145 2146 /* Let the user override the IRQ with a tunable. */ 2147 irq = PCI_INVALID_IRQ; 2148 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 2149 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 2150 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 2151 irq = PCI_INVALID_IRQ; 2152 2153 /* 2154 * If we didn't get an IRQ via the tunable, then we either use the 2155 * IRQ value in the intline register or we ask the bus to route an 2156 * interrupt for us. If force_route is true, then we only use the 2157 * value in the intline register if the bus was unable to assign an 2158 * IRQ. 2159 */ 2160 if (!PCI_INTERRUPT_VALID(irq)) { 2161 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 2162 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 2163 if (!PCI_INTERRUPT_VALID(irq)) 2164 irq = cfg->intline; 2165 } 2166 2167 /* If after all that we don't have an IRQ, just bail. */ 2168 if (!PCI_INTERRUPT_VALID(irq)) 2169 return; 2170 2171 /* Update the config register if it changed. */ 2172 if (irq != cfg->intline) { 2173 cfg->intline = irq; 2174 pci_write_config(dev, PCIR_INTLINE, irq, 1); 2175 } 2176 2177 /* Add this IRQ as rid 0 interrupt resource. */ 2178 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 2179} 2180 2181void 2182pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 2183{ 2184 device_t pcib; 2185 struct pci_devinfo *dinfo = device_get_ivars(dev); 2186 pcicfgregs *cfg = &dinfo->cfg; 2187 struct resource_list *rl = &dinfo->resources; 2188 struct pci_quirk *q; 2189 int b, i, f, s; 2190 2191 pcib = device_get_parent(bus); 2192 2193 b = cfg->bus; 2194 s = cfg->slot; 2195 f = cfg->func; 2196 2197 /* ATA devices needs special map treatment */ 2198 if ((pci_get_class(dev) == PCIC_STORAGE) && 2199 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 2200 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 2201 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 2202 else 2203 for (i = 0; i < cfg->nummaps;) 2204 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 2205 rl, force, prefetchmask & (1 << i)); 2206 2207 /* 2208 * Add additional, quirked resources. 2209 */ 2210 for (q = &pci_quirks[0]; q->devid; q++) { 2211 if (q->devid == ((cfg->device << 16) | cfg->vendor) 2212 && q->type == PCI_QUIRK_MAP_REG) 2213 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 2214 force, 0); 2215 } 2216 2217 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 2218#ifdef __PCI_REROUTE_INTERRUPT 2219 /* 2220 * Try to re-route interrupts. Sometimes the BIOS or 2221 * firmware may leave bogus values in these registers. 2222 * If the re-route fails, then just stick with what we 2223 * have. 2224 */ 2225 pci_assign_interrupt(bus, dev, 1); 2226#else 2227 pci_assign_interrupt(bus, dev, 0); 2228#endif 2229 } 2230} 2231 2232void 2233pci_add_children(device_t dev, int busno, size_t dinfo_size) 2234{ 2235#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 2236 device_t pcib = device_get_parent(dev); 2237 struct pci_devinfo *dinfo; 2238 int maxslots; 2239 int s, f, pcifunchigh; 2240 uint8_t hdrtype; 2241 2242 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 2243 ("dinfo_size too small")); 2244 maxslots = PCIB_MAXSLOTS(pcib); 2245 for (s = 0; s <= maxslots; s++) { 2246 pcifunchigh = 0; 2247 f = 0; 2248 DELAY(1); 2249 hdrtype = REG(PCIR_HDRTYPE, 1); 2250 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 2251 continue; 2252 if (hdrtype & PCIM_MFDEV) 2253 pcifunchigh = PCI_FUNCMAX; 2254 for (f = 0; f <= pcifunchigh; f++) { 2255 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 2256 if (dinfo != NULL) { 2257 pci_add_child(dev, dinfo); 2258 } 2259 } 2260 } 2261#undef REG 2262} 2263 2264void 2265pci_add_child(device_t bus, struct pci_devinfo *dinfo) 2266{ 2267 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 2268 device_set_ivars(dinfo->cfg.dev, dinfo); 2269 resource_list_init(&dinfo->resources); 2270 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 2271 pci_cfg_restore(dinfo->cfg.dev, dinfo); 2272 pci_print_verbose(dinfo); 2273 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 2274} 2275 2276static int 2277pci_probe(device_t dev) 2278{ 2279 2280 device_set_desc(dev, "PCI bus"); 2281 2282 /* Allow other subclasses to override this driver. */ 2283 return (-1000); 2284} 2285 2286static int 2287pci_attach(device_t dev) 2288{ 2289 int busno; 2290 2291 /* 2292 * Since there can be multiple independantly numbered PCI 2293 * busses on systems with multiple PCI domains, we can't use 2294 * the unit number to decide which bus we are probing. We ask 2295 * the parent pcib what our bus number is. 2296 */ 2297 busno = pcib_get_bus(dev); 2298 if (bootverbose) 2299 device_printf(dev, "physical bus=%d\n", busno); 2300 2301 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 2302 2303 return (bus_generic_attach(dev)); 2304} 2305 2306int 2307pci_suspend(device_t dev) 2308{ 2309 int dstate, error, i, numdevs; 2310 device_t acpi_dev, child, *devlist; 2311 struct pci_devinfo *dinfo; 2312 2313 /* 2314 * Save the PCI configuration space for each child and set the 2315 * device in the appropriate power state for this sleep state. 2316 */ 2317 acpi_dev = NULL; 2318 if (pci_do_power_resume) 2319 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2320 device_get_children(dev, &devlist, &numdevs); 2321 for (i = 0; i < numdevs; i++) { 2322 child = devlist[i]; 2323 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2324 pci_cfg_save(child, dinfo, 0); 2325 } 2326 2327 /* Suspend devices before potentially powering them down. */ 2328 error = bus_generic_suspend(dev); 2329 if (error) { 2330 free(devlist, M_TEMP); 2331 return (error); 2332 } 2333 2334 /* 2335 * Always set the device to D3. If ACPI suggests a different 2336 * power state, use it instead. If ACPI is not present, the 2337 * firmware is responsible for managing device power. Skip 2338 * children who aren't attached since they are powered down 2339 * separately. Only manage type 0 devices for now. 2340 */ 2341 for (i = 0; acpi_dev && i < numdevs; i++) { 2342 child = devlist[i]; 2343 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2344 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 2345 dstate = PCI_POWERSTATE_D3; 2346 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 2347 pci_set_powerstate(child, dstate); 2348 } 2349 } 2350 free(devlist, M_TEMP); 2351 return (0); 2352} 2353 2354int 2355pci_resume(device_t dev) 2356{ 2357 int i, numdevs; 2358 device_t acpi_dev, child, *devlist; 2359 struct pci_devinfo *dinfo; 2360 2361 /* 2362 * Set each child to D0 and restore its PCI configuration space. 2363 */ 2364 acpi_dev = NULL; 2365 if (pci_do_power_resume) 2366 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2367 device_get_children(dev, &devlist, &numdevs); 2368 for (i = 0; i < numdevs; i++) { 2369 /* 2370 * Notify ACPI we're going to D0 but ignore the result. If 2371 * ACPI is not present, the firmware is responsible for 2372 * managing device power. Only manage type 0 devices for now. 2373 */ 2374 child = devlist[i]; 2375 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2376 if (acpi_dev && device_is_attached(child) && 2377 dinfo->cfg.hdrtype == 0) { 2378 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 2379 pci_set_powerstate(child, PCI_POWERSTATE_D0); 2380 } 2381 2382 /* Now the device is powered up, restore its config space. */ 2383 pci_cfg_restore(child, dinfo); 2384 } 2385 free(devlist, M_TEMP); 2386 return (bus_generic_resume(dev)); 2387} 2388 2389static void 2390pci_load_vendor_data(void) 2391{ 2392 caddr_t vendordata, info; 2393 2394 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 2395 info = preload_search_info(vendordata, MODINFO_ADDR); 2396 pci_vendordata = *(char **)info; 2397 info = preload_search_info(vendordata, MODINFO_SIZE); 2398 pci_vendordata_size = *(size_t *)info; 2399 /* terminate the database */ 2400 pci_vendordata[pci_vendordata_size] = '\n'; 2401 } 2402} 2403 2404void 2405pci_driver_added(device_t dev, driver_t *driver) 2406{ 2407 int numdevs; 2408 device_t *devlist; 2409 device_t child; 2410 struct pci_devinfo *dinfo; 2411 int i; 2412 2413 if (bootverbose) 2414 device_printf(dev, "driver added\n"); 2415 DEVICE_IDENTIFY(driver, dev); 2416 device_get_children(dev, &devlist, &numdevs); 2417 for (i = 0; i < numdevs; i++) { 2418 child = devlist[i]; 2419 if (device_get_state(child) != DS_NOTPRESENT) 2420 continue; 2421 dinfo = device_get_ivars(child); 2422 pci_print_verbose(dinfo); 2423 if (bootverbose) 2424 printf("pci%d:%d:%d: reprobing on driver added\n", 2425 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 2426 pci_cfg_restore(child, dinfo); 2427 if (device_probe_and_attach(child) != 0) 2428 pci_cfg_save(child, dinfo, 1); 2429 } 2430 free(devlist, M_TEMP); 2431} 2432 2433int 2434pci_print_child(device_t dev, device_t child) 2435{ 2436 struct pci_devinfo *dinfo; 2437 struct resource_list *rl; 2438 int retval = 0; 2439 2440 dinfo = device_get_ivars(child); 2441 rl = &dinfo->resources; 2442 2443 retval += bus_print_child_header(dev, child); 2444 2445 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 2446 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 2447 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 2448 if (device_get_flags(dev)) 2449 retval += printf(" flags %#x", device_get_flags(dev)); 2450 2451 retval += printf(" at device %d.%d", pci_get_slot(child), 2452 pci_get_function(child)); 2453 2454 retval += bus_print_child_footer(dev, child); 2455 2456 return (retval); 2457} 2458 2459static struct 2460{ 2461 int class; 2462 int subclass; 2463 char *desc; 2464} pci_nomatch_tab[] = { 2465 {PCIC_OLD, -1, "old"}, 2466 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 2467 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 2468 {PCIC_STORAGE, -1, "mass storage"}, 2469 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 2470 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 2471 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 2472 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 2473 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 2474 {PCIC_NETWORK, -1, "network"}, 2475 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 2476 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 2477 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 2478 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 2479 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 2480 {PCIC_DISPLAY, -1, "display"}, 2481 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 2482 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 2483 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 2484 {PCIC_MULTIMEDIA, -1, "multimedia"}, 2485 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 2486 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 2487 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 2488 {PCIC_MEMORY, -1, "memory"}, 2489 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 2490 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 2491 {PCIC_BRIDGE, -1, "bridge"}, 2492 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 2493 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 2494 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 2495 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 2496 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 2497 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 2498 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 2499 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 2500 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 2501 {PCIC_SIMPLECOMM, -1, "simple comms"}, 2502 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 2503 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 2504 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 2505 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 2506 {PCIC_BASEPERIPH, -1, "base peripheral"}, 2507 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 2508 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 2509 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 2510 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 2511 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 2512 {PCIC_INPUTDEV, -1, "input device"}, 2513 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 2514 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 2515 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 2516 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 2517 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 2518 {PCIC_DOCKING, -1, "docking station"}, 2519 {PCIC_PROCESSOR, -1, "processor"}, 2520 {PCIC_SERIALBUS, -1, "serial bus"}, 2521 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 2522 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 2523 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 2524 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 2525 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 2526 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 2527 {PCIC_WIRELESS, -1, "wireless controller"}, 2528 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 2529 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 2530 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 2531 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 2532 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 2533 {PCIC_SATCOM, -1, "satellite communication"}, 2534 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 2535 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 2536 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 2537 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 2538 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 2539 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 2540 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 2541 {PCIC_DASP, -1, "dasp"}, 2542 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 2543 {0, 0, NULL} 2544}; 2545 2546void 2547pci_probe_nomatch(device_t dev, device_t child) 2548{ 2549 int i; 2550 char *cp, *scp, *device; 2551 2552 /* 2553 * Look for a listing for this device in a loaded device database. 2554 */ 2555 if ((device = pci_describe_device(child)) != NULL) { 2556 device_printf(dev, "<%s>", device); 2557 free(device, M_DEVBUF); 2558 } else { 2559 /* 2560 * Scan the class/subclass descriptions for a general 2561 * description. 2562 */ 2563 cp = "unknown"; 2564 scp = NULL; 2565 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 2566 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 2567 if (pci_nomatch_tab[i].subclass == -1) { 2568 cp = pci_nomatch_tab[i].desc; 2569 } else if (pci_nomatch_tab[i].subclass == 2570 pci_get_subclass(child)) { 2571 scp = pci_nomatch_tab[i].desc; 2572 } 2573 } 2574 } 2575 device_printf(dev, "<%s%s%s>", 2576 cp ? cp : "", 2577 ((cp != NULL) && (scp != NULL)) ? ", " : "", 2578 scp ? scp : ""); 2579 } 2580 printf(" at device %d.%d (no driver attached)\n", 2581 pci_get_slot(child), pci_get_function(child)); 2582 if (pci_do_power_nodriver) 2583 pci_cfg_save(child, 2584 (struct pci_devinfo *) device_get_ivars(child), 1); 2585 return; 2586} 2587 2588/* 2589 * Parse the PCI device database, if loaded, and return a pointer to a 2590 * description of the device. 2591 * 2592 * The database is flat text formatted as follows: 2593 * 2594 * Any line not in a valid format is ignored. 2595 * Lines are terminated with newline '\n' characters. 2596 * 2597 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 2598 * the vendor name. 2599 * 2600 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 2601 * - devices cannot be listed without a corresponding VENDOR line. 2602 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 2603 * another TAB, then the device name. 2604 */ 2605 2606/* 2607 * Assuming (ptr) points to the beginning of a line in the database, 2608 * return the vendor or device and description of the next entry. 2609 * The value of (vendor) or (device) inappropriate for the entry type 2610 * is set to -1. Returns nonzero at the end of the database. 2611 * 2612 * Note that this is slightly unrobust in the face of corrupt data; 2613 * we attempt to safeguard against this by spamming the end of the 2614 * database with a newline when we initialise. 2615 */ 2616static int 2617pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 2618{ 2619 char *cp = *ptr; 2620 int left; 2621 2622 *device = -1; 2623 *vendor = -1; 2624 **desc = '\0'; 2625 for (;;) { 2626 left = pci_vendordata_size - (cp - pci_vendordata); 2627 if (left <= 0) { 2628 *ptr = cp; 2629 return(1); 2630 } 2631 2632 /* vendor entry? */ 2633 if (*cp != '\t' && 2634 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 2635 break; 2636 /* device entry? */ 2637 if (*cp == '\t' && 2638 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 2639 break; 2640 2641 /* skip to next line */ 2642 while (*cp != '\n' && left > 0) { 2643 cp++; 2644 left--; 2645 } 2646 if (*cp == '\n') { 2647 cp++; 2648 left--; 2649 } 2650 } 2651 /* skip to next line */ 2652 while (*cp != '\n' && left > 0) { 2653 cp++; 2654 left--; 2655 } 2656 if (*cp == '\n' && left > 0) 2657 cp++; 2658 *ptr = cp; 2659 return(0); 2660} 2661 2662static char * 2663pci_describe_device(device_t dev) 2664{ 2665 int vendor, device; 2666 char *desc, *vp, *dp, *line; 2667 2668 desc = vp = dp = NULL; 2669 2670 /* 2671 * If we have no vendor data, we can't do anything. 2672 */ 2673 if (pci_vendordata == NULL) 2674 goto out; 2675 2676 /* 2677 * Scan the vendor data looking for this device 2678 */ 2679 line = pci_vendordata; 2680 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 2681 goto out; 2682 for (;;) { 2683 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 2684 goto out; 2685 if (vendor == pci_get_vendor(dev)) 2686 break; 2687 } 2688 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 2689 goto out; 2690 for (;;) { 2691 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 2692 *dp = 0; 2693 break; 2694 } 2695 if (vendor != -1) { 2696 *dp = 0; 2697 break; 2698 } 2699 if (device == pci_get_device(dev)) 2700 break; 2701 } 2702 if (dp[0] == '\0') 2703 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 2704 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 2705 NULL) 2706 sprintf(desc, "%s, %s", vp, dp); 2707 out: 2708 if (vp != NULL) 2709 free(vp, M_DEVBUF); 2710 if (dp != NULL) 2711 free(dp, M_DEVBUF); 2712 return(desc); 2713} 2714 2715int 2716pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 2717{ 2718 struct pci_devinfo *dinfo; 2719 pcicfgregs *cfg; 2720 2721 dinfo = device_get_ivars(child); 2722 cfg = &dinfo->cfg; 2723 2724 switch (which) { 2725 case PCI_IVAR_ETHADDR: 2726 /* 2727 * The generic accessor doesn't deal with failure, so 2728 * we set the return value, then return an error. 2729 */ 2730 *((uint8_t **) result) = NULL; 2731 return (EINVAL); 2732 case PCI_IVAR_SUBVENDOR: 2733 *result = cfg->subvendor; 2734 break; 2735 case PCI_IVAR_SUBDEVICE: 2736 *result = cfg->subdevice; 2737 break; 2738 case PCI_IVAR_VENDOR: 2739 *result = cfg->vendor; 2740 break; 2741 case PCI_IVAR_DEVICE: 2742 *result = cfg->device; 2743 break; 2744 case PCI_IVAR_DEVID: 2745 *result = (cfg->device << 16) | cfg->vendor; 2746 break; 2747 case PCI_IVAR_CLASS: 2748 *result = cfg->baseclass; 2749 break; 2750 case PCI_IVAR_SUBCLASS: 2751 *result = cfg->subclass; 2752 break; 2753 case PCI_IVAR_PROGIF: 2754 *result = cfg->progif; 2755 break; 2756 case PCI_IVAR_REVID: 2757 *result = cfg->revid; 2758 break; 2759 case PCI_IVAR_INTPIN: 2760 *result = cfg->intpin; 2761 break; 2762 case PCI_IVAR_IRQ: 2763 *result = cfg->intline; 2764 break; 2765 case PCI_IVAR_BUS: 2766 *result = cfg->bus; 2767 break; 2768 case PCI_IVAR_SLOT: 2769 *result = cfg->slot; 2770 break; 2771 case PCI_IVAR_FUNCTION: 2772 *result = cfg->func; 2773 break; 2774 case PCI_IVAR_CMDREG: 2775 *result = cfg->cmdreg; 2776 break; 2777 case PCI_IVAR_CACHELNSZ: 2778 *result = cfg->cachelnsz; 2779 break; 2780 case PCI_IVAR_MINGNT: 2781 *result = cfg->mingnt; 2782 break; 2783 case PCI_IVAR_MAXLAT: 2784 *result = cfg->maxlat; 2785 break; 2786 case PCI_IVAR_LATTIMER: 2787 *result = cfg->lattimer; 2788 break; 2789 default: 2790 return (ENOENT); 2791 } 2792 return (0); 2793} 2794 2795int 2796pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 2797{ 2798 struct pci_devinfo *dinfo; 2799 2800 dinfo = device_get_ivars(child); 2801 2802 switch (which) { 2803 case PCI_IVAR_INTPIN: 2804 dinfo->cfg.intpin = value; 2805 return (0); 2806 case PCI_IVAR_ETHADDR: 2807 case PCI_IVAR_SUBVENDOR: 2808 case PCI_IVAR_SUBDEVICE: 2809 case PCI_IVAR_VENDOR: 2810 case PCI_IVAR_DEVICE: 2811 case PCI_IVAR_DEVID: 2812 case PCI_IVAR_CLASS: 2813 case PCI_IVAR_SUBCLASS: 2814 case PCI_IVAR_PROGIF: 2815 case PCI_IVAR_REVID: 2816 case PCI_IVAR_IRQ: 2817 case PCI_IVAR_BUS: 2818 case PCI_IVAR_SLOT: 2819 case PCI_IVAR_FUNCTION: 2820 return (EINVAL); /* disallow for now */ 2821 2822 default: 2823 return (ENOENT); 2824 } 2825} 2826 2827 2828#include "opt_ddb.h" 2829#ifdef DDB 2830#include <ddb/ddb.h> 2831#include <sys/cons.h> 2832 2833/* 2834 * List resources based on pci map registers, used for within ddb 2835 */ 2836 2837DB_SHOW_COMMAND(pciregs, db_pci_dump) 2838{ 2839 struct pci_devinfo *dinfo; 2840 struct devlist *devlist_head; 2841 struct pci_conf *p; 2842 const char *name; 2843 int i, error, none_count; 2844 2845 none_count = 0; 2846 /* get the head of the device queue */ 2847 devlist_head = &pci_devq; 2848 2849 /* 2850 * Go through the list of devices and print out devices 2851 */ 2852 for (error = 0, i = 0, 2853 dinfo = STAILQ_FIRST(devlist_head); 2854 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 2855 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 2856 2857 /* Populate pd_name and pd_unit */ 2858 name = NULL; 2859 if (dinfo->cfg.dev) 2860 name = device_get_name(dinfo->cfg.dev); 2861 2862 p = &dinfo->conf; 2863 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 2864 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 2865 (name && *name) ? name : "none", 2866 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 2867 none_count++, 2868 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 2869 p->pc_sel.pc_func, (p->pc_class << 16) | 2870 (p->pc_subclass << 8) | p->pc_progif, 2871 (p->pc_subdevice << 16) | p->pc_subvendor, 2872 (p->pc_device << 16) | p->pc_vendor, 2873 p->pc_revid, p->pc_hdr); 2874 } 2875} 2876#endif /* DDB */ 2877 2878static struct resource * 2879pci_alloc_map(device_t dev, device_t child, int type, int *rid, 2880 u_long start, u_long end, u_long count, u_int flags) 2881{ 2882 struct pci_devinfo *dinfo = device_get_ivars(child); 2883 struct resource_list *rl = &dinfo->resources; 2884 struct resource_list_entry *rle; 2885 struct resource *res; 2886 pci_addr_t map, testval; 2887 int mapsize; 2888 2889 /* 2890 * Weed out the bogons, and figure out how large the BAR/map 2891 * is. Bars that read back 0 here are bogus and unimplemented. 2892 * Note: atapci in legacy mode are special and handled elsewhere 2893 * in the code. If you have a atapci device in legacy mode and 2894 * it fails here, that other code is broken. 2895 */ 2896 res = NULL; 2897 map = pci_read_config(child, *rid, 4); 2898 pci_write_config(child, *rid, 0xffffffff, 4); 2899 testval = pci_read_config(child, *rid, 4); 2900 if (pci_maprange(testval) == 64) 2901 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32; 2902 if (pci_mapbase(testval) == 0) 2903 goto out; 2904 if (pci_maptype(testval) & PCI_MAPMEM) { 2905 if (type != SYS_RES_MEMORY) { 2906 if (bootverbose) 2907 device_printf(dev, 2908 "child %s requested type %d for rid %#x," 2909 " but the BAR says it is an memio\n", 2910 device_get_nameunit(child), type, *rid); 2911 goto out; 2912 } 2913 } else { 2914 if (type != SYS_RES_IOPORT) { 2915 if (bootverbose) 2916 device_printf(dev, 2917 "child %s requested type %d for rid %#x," 2918 " but the BAR says it is an ioport\n", 2919 device_get_nameunit(child), type, *rid); 2920 goto out; 2921 } 2922 } 2923 /* 2924 * For real BARs, we need to override the size that 2925 * the driver requests, because that's what the BAR 2926 * actually uses and we would otherwise have a 2927 * situation where we might allocate the excess to 2928 * another driver, which won't work. 2929 */ 2930 mapsize = pci_mapsize(testval); 2931 count = 1UL << mapsize; 2932 if (RF_ALIGNMENT(flags) < mapsize) 2933 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 2934 2935 /* 2936 * Allocate enough resource, and then write back the 2937 * appropriate bar for that resource. 2938 */ 2939 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2940 start, end, count, flags); 2941 if (res == NULL) { 2942 device_printf(child, 2943 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 2944 count, *rid, type, start, end); 2945 goto out; 2946 } 2947 resource_list_add(rl, type, *rid, start, end, count); 2948 rle = resource_list_find(rl, type, *rid); 2949 if (rle == NULL) 2950 panic("pci_alloc_map: unexpectedly can't find resource."); 2951 rle->res = res; 2952 rle->start = rman_get_start(res); 2953 rle->end = rman_get_end(res); 2954 rle->count = count; 2955 if (bootverbose) 2956 device_printf(child, 2957 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 2958 count, *rid, type, rman_get_start(res)); 2959 map = rman_get_start(res); 2960out:; 2961 pci_write_config(child, *rid, map, 4); 2962 if (pci_maprange(testval) == 64) 2963 pci_write_config(child, *rid + 4, map >> 32, 4); 2964 return (res); 2965} 2966 2967 2968struct resource * 2969pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2970 u_long start, u_long end, u_long count, u_int flags) 2971{ 2972 struct pci_devinfo *dinfo = device_get_ivars(child); 2973 struct resource_list *rl = &dinfo->resources; 2974 struct resource_list_entry *rle; 2975 pcicfgregs *cfg = &dinfo->cfg; 2976 2977 /* 2978 * Perform lazy resource allocation 2979 */ 2980 if (device_get_parent(child) == dev) { 2981 switch (type) { 2982 case SYS_RES_IRQ: 2983 /* 2984 * Can't alloc legacy interrupt once MSI messages 2985 * have been allocated. 2986 */ 2987 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 2988 cfg->msix.msix_alloc > 0)) 2989 return (NULL); 2990 /* 2991 * If the child device doesn't have an 2992 * interrupt routed and is deserving of an 2993 * interrupt, try to assign it one. 2994 */ 2995 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 2996 (cfg->intpin != 0)) 2997 pci_assign_interrupt(dev, child, 0); 2998 break; 2999 case SYS_RES_IOPORT: 3000 case SYS_RES_MEMORY: 3001 if (*rid < PCIR_BAR(cfg->nummaps)) { 3002 /* 3003 * Enable the I/O mode. We should 3004 * also be assigning resources too 3005 * when none are present. The 3006 * resource_list_alloc kind of sorta does 3007 * this... 3008 */ 3009 if (PCI_ENABLE_IO(dev, child, type)) 3010 return (NULL); 3011 } 3012 rle = resource_list_find(rl, type, *rid); 3013 if (rle == NULL) 3014 return (pci_alloc_map(dev, child, type, rid, 3015 start, end, count, flags)); 3016 break; 3017 } 3018 /* 3019 * If we've already allocated the resource, then 3020 * return it now. But first we may need to activate 3021 * it, since we don't allocate the resource as active 3022 * above. Normally this would be done down in the 3023 * nexus, but since we short-circuit that path we have 3024 * to do its job here. Not sure if we should free the 3025 * resource if it fails to activate. 3026 */ 3027 rle = resource_list_find(rl, type, *rid); 3028 if (rle != NULL && rle->res != NULL) { 3029 if (bootverbose) 3030 device_printf(child, 3031 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 3032 rman_get_size(rle->res), *rid, type, 3033 rman_get_start(rle->res)); 3034 if ((flags & RF_ACTIVE) && 3035 bus_generic_activate_resource(dev, child, type, 3036 *rid, rle->res) != 0) 3037 return NULL; 3038 return (rle->res); 3039 } 3040 } 3041 return (resource_list_alloc(rl, dev, child, type, rid, 3042 start, end, count, flags)); 3043} 3044 3045void 3046pci_delete_resource(device_t dev, device_t child, int type, int rid) 3047{ 3048 struct pci_devinfo *dinfo; 3049 struct resource_list *rl; 3050 struct resource_list_entry *rle; 3051 3052 if (device_get_parent(child) != dev) 3053 return; 3054 3055 dinfo = device_get_ivars(child); 3056 rl = &dinfo->resources; 3057 rle = resource_list_find(rl, type, rid); 3058 if (rle) { 3059 if (rle->res) { 3060 if (rman_get_device(rle->res) != dev || 3061 rman_get_flags(rle->res) & RF_ACTIVE) { 3062 device_printf(dev, "delete_resource: " 3063 "Resource still owned by child, oops. " 3064 "(type=%d, rid=%d, addr=%lx)\n", 3065 rle->type, rle->rid, 3066 rman_get_start(rle->res)); 3067 return; 3068 } 3069 bus_release_resource(dev, type, rid, rle->res); 3070 } 3071 resource_list_delete(rl, type, rid); 3072 } 3073 /* 3074 * Why do we turn off the PCI configuration BAR when we delete a 3075 * resource? -- imp 3076 */ 3077 pci_write_config(child, rid, 0, 4); 3078 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 3079} 3080 3081struct resource_list * 3082pci_get_resource_list (device_t dev, device_t child) 3083{ 3084 struct pci_devinfo *dinfo = device_get_ivars(child); 3085 3086 return (&dinfo->resources); 3087} 3088 3089uint32_t 3090pci_read_config_method(device_t dev, device_t child, int reg, int width) 3091{ 3092 struct pci_devinfo *dinfo = device_get_ivars(child); 3093 pcicfgregs *cfg = &dinfo->cfg; 3094 3095 return (PCIB_READ_CONFIG(device_get_parent(dev), 3096 cfg->bus, cfg->slot, cfg->func, reg, width)); 3097} 3098 3099void 3100pci_write_config_method(device_t dev, device_t child, int reg, 3101 uint32_t val, int width) 3102{ 3103 struct pci_devinfo *dinfo = device_get_ivars(child); 3104 pcicfgregs *cfg = &dinfo->cfg; 3105 3106 PCIB_WRITE_CONFIG(device_get_parent(dev), 3107 cfg->bus, cfg->slot, cfg->func, reg, val, width); 3108} 3109 3110int 3111pci_child_location_str_method(device_t dev, device_t child, char *buf, 3112 size_t buflen) 3113{ 3114 3115 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 3116 pci_get_function(child)); 3117 return (0); 3118} 3119 3120int 3121pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 3122 size_t buflen) 3123{ 3124 struct pci_devinfo *dinfo; 3125 pcicfgregs *cfg; 3126 3127 dinfo = device_get_ivars(child); 3128 cfg = &dinfo->cfg; 3129 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 3130 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 3131 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 3132 cfg->progif); 3133 return (0); 3134} 3135 3136int 3137pci_assign_interrupt_method(device_t dev, device_t child) 3138{ 3139 struct pci_devinfo *dinfo = device_get_ivars(child); 3140 pcicfgregs *cfg = &dinfo->cfg; 3141 3142 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 3143 cfg->intpin)); 3144} 3145 3146static int 3147pci_modevent(module_t mod, int what, void *arg) 3148{ 3149 static struct cdev *pci_cdev; 3150 3151 switch (what) { 3152 case MOD_LOAD: 3153 STAILQ_INIT(&pci_devq); 3154 pci_generation = 0; 3155 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 3156 "pci"); 3157 pci_load_vendor_data(); 3158 break; 3159 3160 case MOD_UNLOAD: 3161 destroy_dev(pci_cdev); 3162 break; 3163 } 3164 3165 return (0); 3166} 3167 3168void 3169pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 3170{ 3171 int i; 3172 3173 /* 3174 * Only do header type 0 devices. Type 1 devices are bridges, 3175 * which we know need special treatment. Type 2 devices are 3176 * cardbus bridges which also require special treatment. 3177 * Other types are unknown, and we err on the side of safety 3178 * by ignoring them. 3179 */ 3180 if (dinfo->cfg.hdrtype != 0) 3181 return; 3182 3183 /* 3184 * Restore the device to full power mode. We must do this 3185 * before we restore the registers because moving from D3 to 3186 * D0 will cause the chip's BARs and some other registers to 3187 * be reset to some unknown power on reset values. Cut down 3188 * the noise on boot by doing nothing if we are already in 3189 * state D0. 3190 */ 3191 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 3192 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 3193 } 3194 for (i = 0; i < dinfo->cfg.nummaps; i++) 3195 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 3196 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 3197 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 3198 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 3199 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 3200 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 3201 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 3202 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 3203 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 3204 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 3205 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 3206 3207 /* 3208 * Restore MSI configuration if it is present. If MSI is enabled, 3209 * then restore the data and addr registers. 3210 */ 3211 if (dinfo->cfg.msi.msi_location != 0) 3212 pci_resume_msi(dev); 3213} 3214 3215void 3216pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 3217{ 3218 int i; 3219 uint32_t cls; 3220 int ps; 3221 3222 /* 3223 * Only do header type 0 devices. Type 1 devices are bridges, which 3224 * we know need special treatment. Type 2 devices are cardbus bridges 3225 * which also require special treatment. Other types are unknown, and 3226 * we err on the side of safety by ignoring them. Powering down 3227 * bridges should not be undertaken lightly. 3228 */ 3229 if (dinfo->cfg.hdrtype != 0) 3230 return; 3231 for (i = 0; i < dinfo->cfg.nummaps; i++) 3232 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 3233 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 3234 3235 /* 3236 * Some drivers apparently write to these registers w/o updating our 3237 * cached copy. No harm happens if we update the copy, so do so here 3238 * so we can restore them. The COMMAND register is modified by the 3239 * bus w/o updating the cache. This should represent the normally 3240 * writable portion of the 'defined' part of type 0 headers. In 3241 * theory we also need to save/restore the PCI capability structures 3242 * we know about, but apart from power we don't know any that are 3243 * writable. 3244 */ 3245 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 3246 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 3247 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 3248 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 3249 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 3250 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 3251 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 3252 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 3253 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 3254 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3255 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3256 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 3257 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 3258 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 3259 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 3260 3261 /* 3262 * don't set the state for display devices, base peripherals and 3263 * memory devices since bad things happen when they are powered down. 3264 * We should (a) have drivers that can easily detach and (b) use 3265 * generic drivers for these devices so that some device actually 3266 * attaches. We need to make sure that when we implement (a) we don't 3267 * power the device down on a reattach. 3268 */ 3269 cls = pci_get_class(dev); 3270 if (!setstate) 3271 return; 3272 switch (pci_do_power_nodriver) 3273 { 3274 case 0: /* NO powerdown at all */ 3275 return; 3276 case 1: /* Conservative about what to power down */ 3277 if (cls == PCIC_STORAGE) 3278 return; 3279 /*FALLTHROUGH*/ 3280 case 2: /* Agressive about what to power down */ 3281 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 3282 cls == PCIC_BASEPERIPH) 3283 return; 3284 /*FALLTHROUGH*/ 3285 case 3: /* Power down everything */ 3286 break; 3287 } 3288 /* 3289 * PCI spec says we can only go into D3 state from D0 state. 3290 * Transition from D[12] into D0 before going to D3 state. 3291 */ 3292 ps = pci_get_powerstate(dev); 3293 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 3294 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 3295 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 3296 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 3297} 3298