pci.c revision 165130
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 165130 2006-12-12 19:30:40Z jhb $"); 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/endian.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63#ifdef __HAVE_ACPI 64#include <contrib/dev/acpica/acpi.h> 65#include "acpi_if.h" 66#else 67#define ACPI_PWR_FOR_SLEEP(x, y, z) 68#endif 69 70static uint32_t pci_mapbase(unsigned mapreg); 71static int pci_maptype(unsigned mapreg); 72static int pci_mapsize(unsigned testval); 73static int pci_maprange(unsigned mapreg); 74static void pci_fixancient(pcicfgregs *cfg); 75 76static int pci_porten(device_t pcib, int b, int s, int f); 77static int pci_memen(device_t pcib, int b, int s, int f); 78static void pci_assign_interrupt(device_t bus, device_t dev, 79 int force_route); 80static int pci_add_map(device_t pcib, device_t bus, device_t dev, 81 int b, int s, int f, int reg, 82 struct resource_list *rl, int force, int prefetch); 83static int pci_probe(device_t dev); 84static int pci_attach(device_t dev); 85static void pci_load_vendor_data(void); 86static int pci_describe_parse_line(char **ptr, int *vendor, 87 int *device, char **desc); 88static char *pci_describe_device(device_t dev); 89static int pci_modevent(module_t mod, int what, void *arg); 90static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 91 pcicfgregs *cfg); 92static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 93static uint32_t pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 94 int reg); 95#if 0 96static void pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 97 int reg, uint32_t data); 98#endif 99static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 100 101static device_method_t pci_methods[] = { 102 /* Device interface */ 103 DEVMETHOD(device_probe, pci_probe), 104 DEVMETHOD(device_attach, pci_attach), 105 DEVMETHOD(device_detach, bus_generic_detach), 106 DEVMETHOD(device_shutdown, bus_generic_shutdown), 107 DEVMETHOD(device_suspend, pci_suspend), 108 DEVMETHOD(device_resume, pci_resume), 109 110 /* Bus interface */ 111 DEVMETHOD(bus_print_child, pci_print_child), 112 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 113 DEVMETHOD(bus_read_ivar, pci_read_ivar), 114 DEVMETHOD(bus_write_ivar, pci_write_ivar), 115 DEVMETHOD(bus_driver_added, pci_driver_added), 116 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 117 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 118 119 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 120 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 121 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 122 DEVMETHOD(bus_delete_resource, pci_delete_resource), 123 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 124 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 125 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 126 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 127 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 128 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 129 130 /* PCI interface */ 131 DEVMETHOD(pci_read_config, pci_read_config_method), 132 DEVMETHOD(pci_write_config, pci_write_config_method), 133 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 134 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 135 DEVMETHOD(pci_enable_io, pci_enable_io_method), 136 DEVMETHOD(pci_disable_io, pci_disable_io_method), 137 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 138 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 139 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 140 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 141 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 142 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 143 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 144 DEVMETHOD(pci_release_msi, pci_release_msi_method), 145 DEVMETHOD(pci_msi_count, pci_msi_count_method), 146 147 { 0, 0 } 148}; 149 150DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 151 152static devclass_t pci_devclass; 153DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 154MODULE_VERSION(pci, 1); 155 156static char *pci_vendordata; 157static size_t pci_vendordata_size; 158 159 160struct pci_quirk { 161 uint32_t devid; /* Vendor/device of the card */ 162 int type; 163#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 164 int arg1; 165 int arg2; 166}; 167 168struct pci_quirk pci_quirks[] = { 169 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 170 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 171 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 172 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 173 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 174 175 { 0 } 176}; 177 178/* map register information */ 179#define PCI_MAPMEM 0x01 /* memory map */ 180#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 181#define PCI_MAPPORT 0x04 /* port map */ 182 183struct devlist pci_devq; 184uint32_t pci_generation; 185uint32_t pci_numdevs = 0; 186 187/* sysctl vars */ 188SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 189 190static int pci_enable_io_modes = 1; 191TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 192SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 193 &pci_enable_io_modes, 1, 194 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 195enable these bits correctly. We'd like to do this all the time, but there\n\ 196are some peripherals that this causes problems with."); 197 198static int pci_do_power_nodriver = 0; 199TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 200SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 201 &pci_do_power_nodriver, 0, 202 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 203disable. 1 means conservatively place devices into D3 state. 2 means\n\ 204agressively place devices into D3 state. 3 means put absolutely everything\n\ 205in D3 state."); 206 207static int pci_do_power_resume = 1; 208TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 209SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 210 &pci_do_power_resume, 1, 211 "Transition from D3 -> D0 on resume."); 212 213static int pci_do_msi = 1; 214TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi); 215SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1, 216 "Enable support for MSI interrupts"); 217 218static int pci_do_msix = 1; 219TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix); 220SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1, 221 "Enable support for MSI-X interrupts"); 222 223/* Find a device_t by bus/slot/function */ 224 225device_t 226pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 227{ 228 struct pci_devinfo *dinfo; 229 230 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 231 if ((dinfo->cfg.bus == bus) && 232 (dinfo->cfg.slot == slot) && 233 (dinfo->cfg.func == func)) { 234 return (dinfo->cfg.dev); 235 } 236 } 237 238 return (NULL); 239} 240 241/* Find a device_t by vendor/device ID */ 242 243device_t 244pci_find_device(uint16_t vendor, uint16_t device) 245{ 246 struct pci_devinfo *dinfo; 247 248 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 249 if ((dinfo->cfg.vendor == vendor) && 250 (dinfo->cfg.device == device)) { 251 return (dinfo->cfg.dev); 252 } 253 } 254 255 return (NULL); 256} 257 258/* return base address of memory or port map */ 259 260static uint32_t 261pci_mapbase(uint32_t mapreg) 262{ 263 int mask = 0x03; 264 if ((mapreg & 0x01) == 0) 265 mask = 0x0f; 266 return (mapreg & ~mask); 267} 268 269/* return map type of memory or port map */ 270 271static int 272pci_maptype(unsigned mapreg) 273{ 274 static uint8_t maptype[0x10] = { 275 PCI_MAPMEM, PCI_MAPPORT, 276 PCI_MAPMEM, 0, 277 PCI_MAPMEM, PCI_MAPPORT, 278 0, 0, 279 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 280 PCI_MAPMEM|PCI_MAPMEMP, 0, 281 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 282 0, 0, 283 }; 284 285 return maptype[mapreg & 0x0f]; 286} 287 288/* return log2 of map size decoded for memory or port map */ 289 290static int 291pci_mapsize(uint32_t testval) 292{ 293 int ln2size; 294 295 testval = pci_mapbase(testval); 296 ln2size = 0; 297 if (testval != 0) { 298 while ((testval & 1) == 0) 299 { 300 ln2size++; 301 testval >>= 1; 302 } 303 } 304 return (ln2size); 305} 306 307/* return log2 of address range supported by map register */ 308 309static int 310pci_maprange(unsigned mapreg) 311{ 312 int ln2range = 0; 313 switch (mapreg & 0x07) { 314 case 0x00: 315 case 0x01: 316 case 0x05: 317 ln2range = 32; 318 break; 319 case 0x02: 320 ln2range = 20; 321 break; 322 case 0x04: 323 ln2range = 64; 324 break; 325 } 326 return (ln2range); 327} 328 329/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 330 331static void 332pci_fixancient(pcicfgregs *cfg) 333{ 334 if (cfg->hdrtype != 0) 335 return; 336 337 /* PCI to PCI bridges use header type 1 */ 338 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 339 cfg->hdrtype = 1; 340} 341 342/* extract header type specific config data */ 343 344static void 345pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 346{ 347#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 348 switch (cfg->hdrtype) { 349 case 0: 350 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 351 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 352 cfg->nummaps = PCI_MAXMAPS_0; 353 break; 354 case 1: 355 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 356 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 357 cfg->nummaps = PCI_MAXMAPS_1; 358 break; 359 case 2: 360 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 361 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 362 cfg->nummaps = PCI_MAXMAPS_2; 363 break; 364 } 365#undef REG 366} 367 368/* read configuration header into pcicfgregs structure */ 369struct pci_devinfo * 370pci_read_device(device_t pcib, int b, int s, int f, size_t size) 371{ 372#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 373 pcicfgregs *cfg = NULL; 374 struct pci_devinfo *devlist_entry; 375 struct devlist *devlist_head; 376 377 devlist_head = &pci_devq; 378 379 devlist_entry = NULL; 380 381 if (REG(PCIR_DEVVENDOR, 4) != -1) { 382 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 383 if (devlist_entry == NULL) 384 return (NULL); 385 386 cfg = &devlist_entry->cfg; 387 388 cfg->bus = b; 389 cfg->slot = s; 390 cfg->func = f; 391 cfg->vendor = REG(PCIR_VENDOR, 2); 392 cfg->device = REG(PCIR_DEVICE, 2); 393 cfg->cmdreg = REG(PCIR_COMMAND, 2); 394 cfg->statreg = REG(PCIR_STATUS, 2); 395 cfg->baseclass = REG(PCIR_CLASS, 1); 396 cfg->subclass = REG(PCIR_SUBCLASS, 1); 397 cfg->progif = REG(PCIR_PROGIF, 1); 398 cfg->revid = REG(PCIR_REVID, 1); 399 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 400 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 401 cfg->lattimer = REG(PCIR_LATTIMER, 1); 402 cfg->intpin = REG(PCIR_INTPIN, 1); 403 cfg->intline = REG(PCIR_INTLINE, 1); 404 405 cfg->mingnt = REG(PCIR_MINGNT, 1); 406 cfg->maxlat = REG(PCIR_MAXLAT, 1); 407 408 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 409 cfg->hdrtype &= ~PCIM_MFDEV; 410 411 pci_fixancient(cfg); 412 pci_hdrtypedata(pcib, b, s, f, cfg); 413 414 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 415 pci_read_extcap(pcib, cfg); 416 417 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 418 419 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 420 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 421 devlist_entry->conf.pc_sel.pc_func = cfg->func; 422 devlist_entry->conf.pc_hdr = cfg->hdrtype; 423 424 devlist_entry->conf.pc_subvendor = cfg->subvendor; 425 devlist_entry->conf.pc_subdevice = cfg->subdevice; 426 devlist_entry->conf.pc_vendor = cfg->vendor; 427 devlist_entry->conf.pc_device = cfg->device; 428 429 devlist_entry->conf.pc_class = cfg->baseclass; 430 devlist_entry->conf.pc_subclass = cfg->subclass; 431 devlist_entry->conf.pc_progif = cfg->progif; 432 devlist_entry->conf.pc_revid = cfg->revid; 433 434 pci_numdevs++; 435 pci_generation++; 436 } 437 return (devlist_entry); 438#undef REG 439} 440 441static void 442pci_read_extcap(device_t pcib, pcicfgregs *cfg) 443{ 444#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 445#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 446 uint32_t val; 447 int ptr, nextptr, ptrptr; 448 449 switch (cfg->hdrtype & PCIM_HDRTYPE) { 450 case 0: 451 case 1: 452 ptrptr = PCIR_CAP_PTR; 453 break; 454 case 2: 455 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 456 break; 457 default: 458 return; /* no extended capabilities support */ 459 } 460 nextptr = REG(ptrptr, 1); /* sanity check? */ 461 462 /* 463 * Read capability entries. 464 */ 465 while (nextptr != 0) { 466 /* Sanity check */ 467 if (nextptr > 255) { 468 printf("illegal PCI extended capability offset %d\n", 469 nextptr); 470 return; 471 } 472 /* Find the next entry */ 473 ptr = nextptr; 474 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 475 476 /* Process this entry */ 477 switch (REG(ptr + PCICAP_ID, 1)) { 478 case PCIY_PMG: /* PCI power management */ 479 if (cfg->pp.pp_cap == 0) { 480 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 481 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 482 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 483 if ((nextptr - ptr) > PCIR_POWER_DATA) 484 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 485 } 486 break; 487 case PCIY_MSI: /* PCI MSI */ 488 cfg->msi.msi_location = ptr; 489 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 490 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 491 PCIM_MSICTRL_MMC_MASK)>>1); 492 break; 493 case PCIY_MSIX: /* PCI MSI-X */ 494 cfg->msix.msix_location = ptr; 495 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 496 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 497 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 498 val = REG(ptr + PCIR_MSIX_TABLE, 4); 499 cfg->msix.msix_table_bar = PCIR_BAR(val & 500 PCIM_MSIX_BIR_MASK); 501 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 502 val = REG(ptr + PCIR_MSIX_PBA, 4); 503 cfg->msix.msix_pba_bar = PCIR_BAR(val & 504 PCIM_MSIX_BIR_MASK); 505 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 506 break; 507 case PCIY_VPD: /* PCI Vital Product Data */ 508 cfg->vpd.vpd_reg = ptr; 509 pci_read_vpd(pcib, cfg); 510 break; 511 default: 512 break; 513 } 514 } 515/* REG and WREG use carry through to next functions */ 516} 517 518/* 519 * PCI Vital Product Data 520 */ 521static uint32_t 522pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg) 523{ 524 525 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 526 527 WREG(cfg->vpd.vpd_reg + 2, reg, 2); 528 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) != 0x8000) 529 DELAY(1); /* limit looping */ 530 531 return REG(cfg->vpd.vpd_reg + 4, 4); 532} 533 534#if 0 535static void 536pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 537{ 538 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 539 540 WREG(cfg->vpd.vpd_reg + 4, data, 4); 541 WREG(cfg->vpd.vpd_reg + 2, reg | 0x8000, 2); 542 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) == 0x8000) 543 DELAY(1); /* limit looping */ 544 545 return; 546} 547#endif 548 549struct vpd_readstate { 550 device_t pcib; 551 pcicfgregs *cfg; 552 uint32_t val; 553 int bytesinval; 554 int off; 555 uint8_t cksum; 556}; 557 558static uint8_t 559vpd_nextbyte(struct vpd_readstate *vrs) 560{ 561 uint8_t byte; 562 563 if (vrs->bytesinval == 0) { 564 vrs->val = le32toh(pci_read_vpd_reg(vrs->pcib, vrs->cfg, 565 vrs->off)); 566 vrs->off += 4; 567 byte = vrs->val & 0xff; 568 vrs->bytesinval = 3; 569 } else { 570 vrs->val = vrs->val >> 8; 571 byte = vrs->val & 0xff; 572 vrs->bytesinval--; 573 } 574 575 vrs->cksum += byte; 576 return byte; 577} 578 579static void 580pci_read_vpd(device_t pcib, pcicfgregs *cfg) 581{ 582 struct vpd_readstate vrs; 583 int state; 584 int name; 585 int remain; 586 int end; 587 int i; 588 uint8_t byte; 589 int alloc, off; /* alloc/off for RO/W arrays */ 590 int cksumvalid; 591 int dflen; 592 593 /* init vpd reader */ 594 vrs.bytesinval = 0; 595 vrs.off = 0; 596 vrs.pcib = pcib; 597 vrs.cfg = cfg; 598 vrs.cksum = 0; 599 600 state = 0; 601 name = remain = i = 0; /* shut up stupid gcc */ 602 alloc = off = 0; /* shut up stupid gcc */ 603 dflen = 0; /* shut up stupid gcc */ 604 end = 0; 605 cksumvalid = -1; 606 for (; !end;) { 607 byte = vpd_nextbyte(&vrs); 608#if 0 609 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 610 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 611 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 612#endif 613 switch (state) { 614 case 0: /* item name */ 615 if (byte & 0x80) { 616 remain = vpd_nextbyte(&vrs); 617 remain |= vpd_nextbyte(&vrs) << 8; 618 if (remain > (0x7f*4 - vrs.off)) { 619 end = 1; 620 printf( 621 "pci%d:%d:%d: invalid vpd data, remain %#x\n", 622 cfg->bus, cfg->slot, cfg->func, 623 remain); 624 } 625 name = byte & 0x7f; 626 } else { 627 remain = byte & 0x7; 628 name = (byte >> 3) & 0xf; 629 } 630 switch (name) { 631 case 0x2: /* String */ 632 cfg->vpd.vpd_ident = malloc(remain + 1, 633 M_DEVBUF, M_WAITOK); 634 i = 0; 635 state = 1; 636 break; 637 case 0xf: /* End */ 638 end = 1; 639 state = -1; 640 break; 641 case 0x10: /* VPD-R */ 642 alloc = 8; 643 off = 0; 644 cfg->vpd.vpd_ros = malloc(alloc * 645 sizeof *cfg->vpd.vpd_ros, M_DEVBUF, 646 M_WAITOK); 647 state = 2; 648 break; 649 case 0x11: /* VPD-W */ 650 alloc = 8; 651 off = 0; 652 cfg->vpd.vpd_w = malloc(alloc * 653 sizeof *cfg->vpd.vpd_w, M_DEVBUF, 654 M_WAITOK); 655 state = 5; 656 break; 657 default: /* Invalid data, abort */ 658 end = 1; 659 continue; 660 } 661 break; 662 663 case 1: /* Identifier String */ 664 cfg->vpd.vpd_ident[i++] = byte; 665 remain--; 666 if (remain == 0) { 667 cfg->vpd.vpd_ident[i] = '\0'; 668 state = 0; 669 } 670 break; 671 672 case 2: /* VPD-R Keyword Header */ 673 if (off == alloc) { 674 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 675 (alloc *= 2) * sizeof *cfg->vpd.vpd_ros, 676 M_DEVBUF, M_WAITOK); 677 } 678 cfg->vpd.vpd_ros[off].keyword[0] = byte; 679 cfg->vpd.vpd_ros[off].keyword[1] = vpd_nextbyte(&vrs); 680 dflen = vpd_nextbyte(&vrs); 681 if (dflen == 0 && 682 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 683 2) == 0) { 684 /* 685 * if this happens, we can't trust the rest 686 * of the VPD. 687 */ 688 printf("pci%d:%d:%d: bad keyword length: %d\n", 689 cfg->bus, cfg->slot, cfg->func, dflen); 690 cksumvalid = 0; 691 end = 1; 692 break; 693 } else if (dflen == 0) { 694 cfg->vpd.vpd_ros[off].value = malloc(1 * 695 sizeof *cfg->vpd.vpd_ros[off].value, 696 M_DEVBUF, M_WAITOK); 697 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 698 } else 699 cfg->vpd.vpd_ros[off].value = malloc( 700 (dflen + 1) * 701 sizeof *cfg->vpd.vpd_ros[off].value, 702 M_DEVBUF, M_WAITOK); 703 remain -= 3; 704 i = 0; 705 /* keep in sync w/ state 3's transistions */ 706 if (dflen == 0 && remain == 0) 707 state = 0; 708 else if (dflen == 0) 709 state = 2; 710 else 711 state = 3; 712 break; 713 714 case 3: /* VPD-R Keyword Value */ 715 cfg->vpd.vpd_ros[off].value[i++] = byte; 716 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 717 "RV", 2) == 0 && cksumvalid == -1) { 718 if (vrs.cksum == 0) 719 cksumvalid = 1; 720 else { 721 printf( 722 "pci%d:%d:%d: bad VPD cksum, remain %hhu\n", 723 cfg->bus, cfg->slot, cfg->func, 724 vrs.cksum); 725 cksumvalid = 0; 726 end = 1; 727 break; 728 } 729 } 730 dflen--; 731 remain--; 732 /* keep in sync w/ state 2's transistions */ 733 if (dflen == 0) 734 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 735 if (dflen == 0 && remain == 0) { 736 cfg->vpd.vpd_rocnt = off; 737 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 738 off * sizeof *cfg->vpd.vpd_ros, 739 M_DEVBUF, M_WAITOK); 740 state = 0; 741 } else if (dflen == 0) 742 state = 2; 743 break; 744 745 case 4: 746 remain--; 747 if (remain == 0) 748 state = 0; 749 break; 750 751 case 5: /* VPD-W Keyword Header */ 752 if (off == alloc) { 753 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 754 (alloc *= 2) * sizeof *cfg->vpd.vpd_w, 755 M_DEVBUF, M_WAITOK); 756 } 757 cfg->vpd.vpd_w[off].keyword[0] = byte; 758 cfg->vpd.vpd_w[off].keyword[1] = vpd_nextbyte(&vrs); 759 cfg->vpd.vpd_w[off].len = dflen = vpd_nextbyte(&vrs); 760 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 761 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 762 sizeof *cfg->vpd.vpd_w[off].value, 763 M_DEVBUF, M_WAITOK); 764 remain -= 3; 765 i = 0; 766 /* keep in sync w/ state 6's transistions */ 767 if (dflen == 0 && remain == 0) 768 state = 0; 769 else if (dflen == 0) 770 state = 5; 771 else 772 state = 6; 773 break; 774 775 case 6: /* VPD-W Keyword Value */ 776 cfg->vpd.vpd_w[off].value[i++] = byte; 777 dflen--; 778 remain--; 779 /* keep in sync w/ state 5's transistions */ 780 if (dflen == 0) 781 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 782 if (dflen == 0 && remain == 0) { 783 cfg->vpd.vpd_wcnt = off; 784 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 785 off * sizeof *cfg->vpd.vpd_w, 786 M_DEVBUF, M_WAITOK); 787 state = 0; 788 } else if (dflen == 0) 789 state = 5; 790 break; 791 792 default: 793 printf("pci%d:%d:%d: invalid state: %d\n", 794 cfg->bus, cfg->slot, cfg->func, state); 795 end = 1; 796 break; 797 } 798 } 799 800 if (cksumvalid == 0) { 801 /* read-only data bad, clean up */ 802 for (; off; off--) 803 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 804 805 free(cfg->vpd.vpd_ros, M_DEVBUF); 806 cfg->vpd.vpd_ros = NULL; 807 } 808#undef REG 809#undef WREG 810} 811 812int 813pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 814{ 815 struct pci_devinfo *dinfo = device_get_ivars(child); 816 pcicfgregs *cfg = &dinfo->cfg; 817 818 *identptr = cfg->vpd.vpd_ident; 819 820 if (*identptr == NULL) 821 return ENXIO; 822 823 return 0; 824} 825 826int 827pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 828 const char **vptr) 829{ 830 struct pci_devinfo *dinfo = device_get_ivars(child); 831 pcicfgregs *cfg = &dinfo->cfg; 832 int i; 833 834 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 835 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 836 sizeof cfg->vpd.vpd_ros[i].keyword) == 0) { 837 *vptr = cfg->vpd.vpd_ros[i].value; 838 } 839 840 if (i != cfg->vpd.vpd_rocnt) 841 return 0; 842 843 *vptr = NULL; 844 return ENXIO; 845} 846 847/* 848 * Return the offset in configuration space of the requested extended 849 * capability entry or 0 if the specified capability was not found. 850 */ 851int 852pci_find_extcap_method(device_t dev, device_t child, int capability, 853 int *capreg) 854{ 855 struct pci_devinfo *dinfo = device_get_ivars(child); 856 pcicfgregs *cfg = &dinfo->cfg; 857 u_int32_t status; 858 u_int8_t ptr; 859 860 /* 861 * Check the CAP_LIST bit of the PCI status register first. 862 */ 863 status = pci_read_config(child, PCIR_STATUS, 2); 864 if (!(status & PCIM_STATUS_CAPPRESENT)) 865 return (ENXIO); 866 867 /* 868 * Determine the start pointer of the capabilities list. 869 */ 870 switch (cfg->hdrtype & PCIM_HDRTYPE) { 871 case 0: 872 case 1: 873 ptr = PCIR_CAP_PTR; 874 break; 875 case 2: 876 ptr = PCIR_CAP_PTR_2; 877 break; 878 default: 879 /* XXX: panic? */ 880 return (ENXIO); /* no extended capabilities support */ 881 } 882 ptr = pci_read_config(child, ptr, 1); 883 884 /* 885 * Traverse the capabilities list. 886 */ 887 while (ptr != 0) { 888 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 889 if (capreg != NULL) 890 *capreg = ptr; 891 return (0); 892 } 893 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 894 } 895 896 return (ENOENT); 897} 898 899/* 900 * Support for MSI-X message interrupts. 901 */ 902void 903pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 904{ 905 struct pci_devinfo *dinfo = device_get_ivars(dev); 906 pcicfgregs *cfg = &dinfo->cfg; 907 uint32_t offset; 908 909 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 910 offset = cfg->msix.msix_table_offset + index * 16; 911 bus_write_4(cfg->msix.msix_table_res, offset, address & 0xffffffff); 912 bus_write_4(cfg->msix.msix_table_res, offset + 4, address >> 32); 913 bus_write_4(cfg->msix.msix_table_res, offset + 8, data); 914} 915 916void 917pci_mask_msix(device_t dev, u_int index) 918{ 919 struct pci_devinfo *dinfo = device_get_ivars(dev); 920 pcicfgregs *cfg = &dinfo->cfg; 921 uint32_t offset, val; 922 923 KASSERT(cfg->msix.msix_msgnum > index, ("bogus index")); 924 offset = cfg->msix.msix_table_offset + index * 16 + 12; 925 val = bus_read_4(cfg->msix.msix_table_res, offset); 926 if (!(val & PCIM_MSIX_VCTRL_MASK)) { 927 val |= PCIM_MSIX_VCTRL_MASK; 928 bus_write_4(cfg->msix.msix_table_res, offset, val); 929 } 930} 931 932void 933pci_unmask_msix(device_t dev, u_int index) 934{ 935 struct pci_devinfo *dinfo = device_get_ivars(dev); 936 pcicfgregs *cfg = &dinfo->cfg; 937 uint32_t offset, val; 938 939 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 940 offset = cfg->msix.msix_table_offset + index * 16 + 12; 941 val = bus_read_4(cfg->msix.msix_table_res, offset); 942 if (val & PCIM_MSIX_VCTRL_MASK) { 943 val &= ~PCIM_MSIX_VCTRL_MASK; 944 bus_write_4(cfg->msix.msix_table_res, offset, val); 945 } 946} 947 948int 949pci_pending_msix(device_t dev, u_int index) 950{ 951 struct pci_devinfo *dinfo = device_get_ivars(dev); 952 pcicfgregs *cfg = &dinfo->cfg; 953 uint32_t offset, bit; 954 955 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 956 offset = cfg->msix.msix_pba_offset + (index / 4) * 4; 957 bit = 1 << index % 32; 958 return (bus_read_4(cfg->msix.msix_pba_res, offset) & bit); 959} 960 961static int 962pci_alloc_msix(device_t dev, device_t child, int *count) 963{ 964 struct pci_devinfo *dinfo = device_get_ivars(child); 965 pcicfgregs *cfg = &dinfo->cfg; 966 struct resource_list_entry *rle; 967 int actual, error, i, irq, max; 968 969 /* MSI-X capability present? */ 970 if (cfg->msix.msix_location == 0 || !pci_do_msix) 971 return (ENODEV); 972 973 /* Make sure the appropriate BARs are mapped. */ 974 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 975 cfg->msix.msix_table_bar); 976 if (rle == NULL || rle->res == NULL || 977 !(rman_get_flags(rle->res) & RF_ACTIVE)) 978 return (ENXIO); 979 cfg->msix.msix_table_res = rle->res; 980 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 981 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 982 cfg->msix.msix_pba_bar); 983 if (rle == NULL || rle->res == NULL || 984 !(rman_get_flags(rle->res) & RF_ACTIVE)) 985 return (ENXIO); 986 } 987 cfg->msix.msix_pba_res = rle->res; 988 989 /* Already have allocated messages? */ 990 if (cfg->msix.msix_alloc != 0) 991 return (ENXIO); 992 993 if (bootverbose) 994 device_printf(child, 995 "attempting to allocate %d MSI-X vectors (%d supported)\n", 996 *count, cfg->msix.msix_msgnum); 997 max = min(*count, cfg->msix.msix_msgnum); 998 for (i = 0; i < max; i++) { 999 /* Allocate a message. */ 1000 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, i, 1001 &irq); 1002 if (error) 1003 break; 1004 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1005 irq, 1); 1006 } 1007 actual = i; 1008 1009 if (bootverbose) { 1010 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1011 if (actual == 1) 1012 device_printf(child, "using IRQ %lu for MSI-X\n", 1013 rle->start); 1014 else { 1015 int run; 1016 1017 /* 1018 * Be fancy and try to print contiguous runs of 1019 * IRQ values as ranges. 'irq' is the previous IRQ. 1020 * 'run' is true if we are in a range. 1021 */ 1022 device_printf(child, "using IRQs %lu", rle->start); 1023 irq = rle->start; 1024 run = 0; 1025 for (i = 1; i < actual; i++) { 1026 rle = resource_list_find(&dinfo->resources, 1027 SYS_RES_IRQ, i + 1); 1028 1029 /* Still in a run? */ 1030 if (rle->start == irq + 1) { 1031 run = 1; 1032 irq++; 1033 continue; 1034 } 1035 1036 /* Finish previous range. */ 1037 if (run) { 1038 printf("-%d", irq); 1039 run = 0; 1040 } 1041 1042 /* Start new range. */ 1043 printf(",%lu", rle->start); 1044 irq = rle->start; 1045 } 1046 1047 /* Unfinished range? */ 1048 if (run) 1049 printf("%d", irq); 1050 printf(" for MSI-X\n"); 1051 } 1052 } 1053 1054 /* Mask all vectors. */ 1055 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1056 pci_mask_msix(child, i); 1057 1058 /* Update control register to enable MSI-X. */ 1059 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1060 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1061 cfg->msix.msix_ctrl, 2); 1062 1063 /* Update counts of alloc'd messages. */ 1064 cfg->msix.msix_alloc = actual; 1065 *count = actual; 1066 return (0); 1067} 1068 1069static int 1070pci_release_msix(device_t dev, device_t child) 1071{ 1072 struct pci_devinfo *dinfo = device_get_ivars(child); 1073 pcicfgregs *cfg = &dinfo->cfg; 1074 struct resource_list_entry *rle; 1075 int i; 1076 1077 /* Do we have any messages to release? */ 1078 if (cfg->msix.msix_alloc == 0) 1079 return (ENODEV); 1080 1081 /* Make sure none of the resources are allocated. */ 1082 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1083 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1084 KASSERT(rle != NULL, ("missing MSI resource")); 1085 if (rle->res != NULL) 1086 return (EBUSY); 1087 } 1088 1089 /* Update control register with to disable MSI-X. */ 1090 cfg->msix.msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 1091 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1092 cfg->msix.msix_ctrl, 2); 1093 1094 /* Release the messages. */ 1095 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1096 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1097 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1098 rle->start); 1099 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1100 } 1101 1102 /* Update alloc count. */ 1103 cfg->msix.msix_alloc = 0; 1104 return (0); 1105} 1106 1107/* 1108 * Support for MSI message signalled interrupts. 1109 */ 1110void 1111pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 1112{ 1113 struct pci_devinfo *dinfo = device_get_ivars(dev); 1114 pcicfgregs *cfg = &dinfo->cfg; 1115 1116 /* Write data and address values. */ 1117 cfg->msi.msi_addr = address; 1118 cfg->msi.msi_data = data; 1119 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR, 1120 address & 0xffffffff, 4); 1121 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) { 1122 pci_write_config(dev, cfg->msi.msi_location + 1123 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1124 pci_write_config(dev, cfg->msi.msi_location + 1125 PCIR_MSI_DATA_64BIT, data, 2); 1126 } else 1127 pci_write_config(dev, cfg->msi.msi_location + 1128 PCIR_MSI_DATA, data, 2); 1129 1130 /* Enable MSI in the control register. */ 1131 cfg->msi.msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 1132 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL, 1133 cfg->msi.msi_ctrl, 2); 1134} 1135 1136/* 1137 * Restore MSI registers during resume. If MSI is enabled then 1138 * restore the data and address registers in addition to the control 1139 * register. 1140 */ 1141static void 1142pci_resume_msi(device_t dev) 1143{ 1144 struct pci_devinfo *dinfo = device_get_ivars(dev); 1145 pcicfgregs *cfg = &dinfo->cfg; 1146 uint64_t address; 1147 uint16_t data; 1148 1149 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 1150 address = cfg->msi.msi_addr; 1151 data = cfg->msi.msi_data; 1152 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR, 1153 address & 0xffffffff, 4); 1154 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) { 1155 pci_write_config(dev, cfg->msi.msi_location + 1156 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1157 pci_write_config(dev, cfg->msi.msi_location + 1158 PCIR_MSI_DATA_64BIT, data, 2); 1159 } else 1160 pci_write_config(dev, cfg->msi.msi_location + 1161 PCIR_MSI_DATA, data, 2); 1162 } 1163 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL, 1164 cfg->msi.msi_ctrl, 2); 1165} 1166 1167/* 1168 * Attempt to allocate *count MSI messages. The actual number allocated is 1169 * returned in *count. After this function returns, each message will be 1170 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 1171 */ 1172int 1173pci_alloc_msi_method(device_t dev, device_t child, int *count) 1174{ 1175 struct pci_devinfo *dinfo = device_get_ivars(child); 1176 pcicfgregs *cfg = &dinfo->cfg; 1177 struct resource_list_entry *rle; 1178 int actual, error, i, irqs[32]; 1179 uint16_t ctrl; 1180 1181 /* Don't let count == 0 get us into trouble. */ 1182 if (*count == 0) 1183 return (EINVAL); 1184 1185 /* If rid 0 is allocated, then fail. */ 1186 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1187 if (rle != NULL && rle->res != NULL) 1188 return (ENXIO); 1189 1190 /* Try MSI-X first. */ 1191 error = pci_alloc_msix(dev, child, count); 1192 if (error != ENODEV) 1193 return (error); 1194 1195 /* MSI capability present? */ 1196 if (cfg->msi.msi_location == 0 || !pci_do_msi) 1197 return (ENODEV); 1198 1199 /* Already have allocated messages? */ 1200 if (cfg->msi.msi_alloc != 0) 1201 return (ENXIO); 1202 1203 if (bootverbose) 1204 device_printf(child, 1205 "attempting to allocate %d MSI vectors (%d supported)\n", 1206 *count, cfg->msi.msi_msgnum); 1207 1208 /* Don't ask for more than the device supports. */ 1209 actual = min(*count, cfg->msi.msi_msgnum); 1210 1211 /* Don't ask for more than 32 messages. */ 1212 actual = min(actual, 32); 1213 1214 /* MSI requires power of 2 number of messages. */ 1215 if (!powerof2(actual)) 1216 return (EINVAL); 1217 1218 for (;;) { 1219 /* Try to allocate N messages. */ 1220 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 1221 cfg->msi.msi_msgnum, irqs); 1222 if (error == 0) 1223 break; 1224 if (actual == 1) 1225 return (error); 1226 1227 /* Try N / 2. */ 1228 actual >>= 1; 1229 } 1230 1231 /* 1232 * We now have N actual messages mapped onto SYS_RES_IRQ 1233 * resources in the irqs[] array, so add new resources 1234 * starting at rid 1. 1235 */ 1236 for (i = 0; i < actual; i++) 1237 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 1238 irqs[i], irqs[i], 1); 1239 1240 if (bootverbose) { 1241 if (actual == 1) 1242 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 1243 else { 1244 int run; 1245 1246 /* 1247 * Be fancy and try to print contiguous runs 1248 * of IRQ values as ranges. 'run' is true if 1249 * we are in a range. 1250 */ 1251 device_printf(child, "using IRQs %d", irqs[0]); 1252 run = 0; 1253 for (i = 1; i < actual; i++) { 1254 1255 /* Still in a run? */ 1256 if (irqs[i] == irqs[i - 1] + 1) { 1257 run = 1; 1258 continue; 1259 } 1260 1261 /* Finish previous range. */ 1262 if (run) { 1263 printf("-%d", irqs[i - 1]); 1264 run = 0; 1265 } 1266 1267 /* Start new range. */ 1268 printf(",%d", irqs[i]); 1269 } 1270 1271 /* Unfinished range? */ 1272 if (run) 1273 printf("%d", irqs[actual - 1]); 1274 printf(" for MSI\n"); 1275 } 1276 } 1277 1278 /* Update control register with actual count and enable MSI. */ 1279 ctrl = cfg->msi.msi_ctrl; 1280 ctrl &= ~PCIM_MSICTRL_MME_MASK; 1281 ctrl |= (ffs(actual) - 1) << 4; 1282 cfg->msi.msi_ctrl = ctrl; 1283 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 1284 1285 /* Update counts of alloc'd messages. */ 1286 cfg->msi.msi_alloc = actual; 1287 *count = actual; 1288 return (0); 1289} 1290 1291/* Release the MSI messages associated with this device. */ 1292int 1293pci_release_msi_method(device_t dev, device_t child) 1294{ 1295 struct pci_devinfo *dinfo = device_get_ivars(child); 1296 pcicfgregs *cfg = &dinfo->cfg; 1297 struct resource_list_entry *rle; 1298 int error, i, irqs[32]; 1299 1300 /* Try MSI-X first. */ 1301 error = pci_release_msix(dev, child); 1302 if (error != ENODEV) 1303 return (error); 1304 1305 /* Do we have any messages to release? */ 1306 if (cfg->msi.msi_alloc == 0) 1307 return (ENODEV); 1308 KASSERT(cfg->msi.msi_alloc <= 32, ("more than 32 alloc'd messages")); 1309 1310 /* Make sure none of the resources are allocated. */ 1311 for (i = 0; i < cfg->msi.msi_alloc; i++) { 1312 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1313 KASSERT(rle != NULL, ("missing MSI resource")); 1314 if (rle->res != NULL) 1315 return (EBUSY); 1316 irqs[i] = rle->start; 1317 } 1318 1319 /* Update control register with 0 count and disable MSI. */ 1320 cfg->msi.msi_ctrl &= ~(PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE); 1321 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 1322 cfg->msi.msi_ctrl, 2); 1323 1324 /* Release the messages. */ 1325 PCIB_RELEASE_MSI(device_get_parent(dev), child, cfg->msi.msi_alloc, 1326 irqs); 1327 for (i = 0; i < cfg->msi.msi_alloc; i++) 1328 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1329 1330 /* Update alloc count. */ 1331 cfg->msi.msi_alloc = 0; 1332 return (0); 1333} 1334 1335/* 1336 * Return the max supported MSI or MSI-X messages this device supports. 1337 * Basically, assuming the MD code can alloc messages, this function 1338 * should return the maximum value that pci_alloc_msi() can return. Thus, 1339 * it is subject to the tunables, etc. 1340 */ 1341int 1342pci_msi_count_method(device_t dev, device_t child) 1343{ 1344 struct pci_devinfo *dinfo = device_get_ivars(child); 1345 pcicfgregs *cfg = &dinfo->cfg; 1346 1347 if (pci_do_msix && cfg->msix.msix_location != 0) 1348 return (cfg->msix.msix_msgnum); 1349 if (pci_do_msi && cfg->msi.msi_location != 0) 1350 return (cfg->msi.msi_msgnum); 1351 return (0); 1352} 1353 1354/* free pcicfgregs structure and all depending data structures */ 1355 1356int 1357pci_freecfg(struct pci_devinfo *dinfo) 1358{ 1359 struct devlist *devlist_head; 1360 int i; 1361 1362 devlist_head = &pci_devq; 1363 1364 if (dinfo->cfg.vpd.vpd_reg) { 1365 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 1366 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 1367 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 1368 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 1369 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 1370 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 1371 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 1372 } 1373 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 1374 free(dinfo, M_DEVBUF); 1375 1376 /* increment the generation count */ 1377 pci_generation++; 1378 1379 /* we're losing one device */ 1380 pci_numdevs--; 1381 return (0); 1382} 1383 1384/* 1385 * PCI power manangement 1386 */ 1387int 1388pci_set_powerstate_method(device_t dev, device_t child, int state) 1389{ 1390 struct pci_devinfo *dinfo = device_get_ivars(child); 1391 pcicfgregs *cfg = &dinfo->cfg; 1392 uint16_t status; 1393 int result, oldstate, highest, delay; 1394 1395 if (cfg->pp.pp_cap == 0) 1396 return (EOPNOTSUPP); 1397 1398 /* 1399 * Optimize a no state change request away. While it would be OK to 1400 * write to the hardware in theory, some devices have shown odd 1401 * behavior when going from D3 -> D3. 1402 */ 1403 oldstate = pci_get_powerstate(child); 1404 if (oldstate == state) 1405 return (0); 1406 1407 /* 1408 * The PCI power management specification states that after a state 1409 * transition between PCI power states, system software must 1410 * guarantee a minimal delay before the function accesses the device. 1411 * Compute the worst case delay that we need to guarantee before we 1412 * access the device. Many devices will be responsive much more 1413 * quickly than this delay, but there are some that don't respond 1414 * instantly to state changes. Transitions to/from D3 state require 1415 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 1416 * is done below with DELAY rather than a sleeper function because 1417 * this function can be called from contexts where we cannot sleep. 1418 */ 1419 highest = (oldstate > state) ? oldstate : state; 1420 if (highest == PCI_POWERSTATE_D3) 1421 delay = 10000; 1422 else if (highest == PCI_POWERSTATE_D2) 1423 delay = 200; 1424 else 1425 delay = 0; 1426 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 1427 & ~PCIM_PSTAT_DMASK; 1428 result = 0; 1429 switch (state) { 1430 case PCI_POWERSTATE_D0: 1431 status |= PCIM_PSTAT_D0; 1432 break; 1433 case PCI_POWERSTATE_D1: 1434 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 1435 return (EOPNOTSUPP); 1436 status |= PCIM_PSTAT_D1; 1437 break; 1438 case PCI_POWERSTATE_D2: 1439 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 1440 return (EOPNOTSUPP); 1441 status |= PCIM_PSTAT_D2; 1442 break; 1443 case PCI_POWERSTATE_D3: 1444 status |= PCIM_PSTAT_D3; 1445 break; 1446 default: 1447 return (EINVAL); 1448 } 1449 1450 if (bootverbose) 1451 printf( 1452 "pci%d:%d:%d: Transition from D%d to D%d\n", 1453 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1454 oldstate, state); 1455 1456 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 1457 if (delay) 1458 DELAY(delay); 1459 return (0); 1460} 1461 1462int 1463pci_get_powerstate_method(device_t dev, device_t child) 1464{ 1465 struct pci_devinfo *dinfo = device_get_ivars(child); 1466 pcicfgregs *cfg = &dinfo->cfg; 1467 uint16_t status; 1468 int result; 1469 1470 if (cfg->pp.pp_cap != 0) { 1471 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 1472 switch (status & PCIM_PSTAT_DMASK) { 1473 case PCIM_PSTAT_D0: 1474 result = PCI_POWERSTATE_D0; 1475 break; 1476 case PCIM_PSTAT_D1: 1477 result = PCI_POWERSTATE_D1; 1478 break; 1479 case PCIM_PSTAT_D2: 1480 result = PCI_POWERSTATE_D2; 1481 break; 1482 case PCIM_PSTAT_D3: 1483 result = PCI_POWERSTATE_D3; 1484 break; 1485 default: 1486 result = PCI_POWERSTATE_UNKNOWN; 1487 break; 1488 } 1489 } else { 1490 /* No support, device is always at D0 */ 1491 result = PCI_POWERSTATE_D0; 1492 } 1493 return (result); 1494} 1495 1496/* 1497 * Some convenience functions for PCI device drivers. 1498 */ 1499 1500static __inline void 1501pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 1502{ 1503 uint16_t command; 1504 1505 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1506 command |= bit; 1507 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1508} 1509 1510static __inline void 1511pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 1512{ 1513 uint16_t command; 1514 1515 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1516 command &= ~bit; 1517 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1518} 1519 1520int 1521pci_enable_busmaster_method(device_t dev, device_t child) 1522{ 1523 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1524 return (0); 1525} 1526 1527int 1528pci_disable_busmaster_method(device_t dev, device_t child) 1529{ 1530 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1531 return (0); 1532} 1533 1534int 1535pci_enable_io_method(device_t dev, device_t child, int space) 1536{ 1537 uint16_t command; 1538 uint16_t bit; 1539 char *error; 1540 1541 bit = 0; 1542 error = NULL; 1543 1544 switch(space) { 1545 case SYS_RES_IOPORT: 1546 bit = PCIM_CMD_PORTEN; 1547 error = "port"; 1548 break; 1549 case SYS_RES_MEMORY: 1550 bit = PCIM_CMD_MEMEN; 1551 error = "memory"; 1552 break; 1553 default: 1554 return (EINVAL); 1555 } 1556 pci_set_command_bit(dev, child, bit); 1557 /* Some devices seem to need a brief stall here, what do to? */ 1558 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1559 if (command & bit) 1560 return (0); 1561 device_printf(child, "failed to enable %s mapping!\n", error); 1562 return (ENXIO); 1563} 1564 1565int 1566pci_disable_io_method(device_t dev, device_t child, int space) 1567{ 1568 uint16_t command; 1569 uint16_t bit; 1570 char *error; 1571 1572 bit = 0; 1573 error = NULL; 1574 1575 switch(space) { 1576 case SYS_RES_IOPORT: 1577 bit = PCIM_CMD_PORTEN; 1578 error = "port"; 1579 break; 1580 case SYS_RES_MEMORY: 1581 bit = PCIM_CMD_MEMEN; 1582 error = "memory"; 1583 break; 1584 default: 1585 return (EINVAL); 1586 } 1587 pci_clear_command_bit(dev, child, bit); 1588 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1589 if (command & bit) { 1590 device_printf(child, "failed to disable %s mapping!\n", error); 1591 return (ENXIO); 1592 } 1593 return (0); 1594} 1595 1596/* 1597 * New style pci driver. Parent device is either a pci-host-bridge or a 1598 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1599 */ 1600 1601void 1602pci_print_verbose(struct pci_devinfo *dinfo) 1603{ 1604 int i; 1605 1606 if (bootverbose) { 1607 pcicfgregs *cfg = &dinfo->cfg; 1608 1609 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1610 cfg->vendor, cfg->device, cfg->revid); 1611 printf("\tbus=%d, slot=%d, func=%d\n", 1612 cfg->bus, cfg->slot, cfg->func); 1613 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1614 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 1615 cfg->mfdev); 1616 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1617 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1618 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1619 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 1620 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1621 if (cfg->intpin > 0) 1622 printf("\tintpin=%c, irq=%d\n", 1623 cfg->intpin +'a' -1, cfg->intline); 1624 if (cfg->pp.pp_cap) { 1625 uint16_t status; 1626 1627 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 1628 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 1629 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 1630 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 1631 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 1632 status & PCIM_PSTAT_DMASK); 1633 } 1634 if (cfg->vpd.vpd_reg) { 1635 printf("\tVPD Ident: %s\n", cfg->vpd.vpd_ident); 1636 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) { 1637 struct vpd_readonly *vrop; 1638 vrop = &cfg->vpd.vpd_ros[i]; 1639 if (strncmp("CP", vrop->keyword, 2) == 0) 1640 printf("\tCP: id %d, BAR%d, off %#x\n", 1641 vrop->value[0], vrop->value[1], 1642 le16toh( 1643 *(uint16_t *)&vrop->value[2])); 1644 else if (strncmp("RV", vrop->keyword, 2) == 0) 1645 printf("\tRV: %#hhx\n", vrop->value[0]); 1646 else 1647 printf("\t%.2s: %s\n", vrop->keyword, 1648 vrop->value); 1649 } 1650 for (i = 0; i < cfg->vpd.vpd_wcnt; i++) { 1651 struct vpd_write *vwp; 1652 vwp = &cfg->vpd.vpd_w[i]; 1653 if (strncmp("RW", vwp->keyword, 2) != 0) 1654 printf("\t%.2s(%#x-%#x): %s\n", 1655 vwp->keyword, vwp->start, 1656 vwp->start + vwp->len, vwp->value); 1657 } 1658 } 1659 if (cfg->msi.msi_location) { 1660 int ctrl; 1661 1662 ctrl = cfg->msi.msi_ctrl; 1663 printf("\tMSI supports %d message%s%s%s\n", 1664 cfg->msi.msi_msgnum, 1665 (cfg->msi.msi_msgnum == 1) ? "" : "s", 1666 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 1667 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 1668 } 1669 if (cfg->msix.msix_location) { 1670 printf("\tMSI-X supports %d message%s ", 1671 cfg->msix.msix_msgnum, 1672 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 1673 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 1674 printf("in map 0x%x\n", 1675 cfg->msix.msix_table_bar); 1676 else 1677 printf("in maps 0x%x and 0x%x\n", 1678 cfg->msix.msix_table_bar, 1679 cfg->msix.msix_pba_bar); 1680 } 1681 } 1682} 1683 1684static int 1685pci_porten(device_t pcib, int b, int s, int f) 1686{ 1687 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1688 & PCIM_CMD_PORTEN) != 0; 1689} 1690 1691static int 1692pci_memen(device_t pcib, int b, int s, int f) 1693{ 1694 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1695 & PCIM_CMD_MEMEN) != 0; 1696} 1697 1698/* 1699 * Add a resource based on a pci map register. Return 1 if the map 1700 * register is a 32bit map register or 2 if it is a 64bit register. 1701 */ 1702static int 1703pci_add_map(device_t pcib, device_t bus, device_t dev, 1704 int b, int s, int f, int reg, struct resource_list *rl, int force, 1705 int prefetch) 1706{ 1707 uint32_t map; 1708 pci_addr_t base; 1709 pci_addr_t start, end, count; 1710 uint8_t ln2size; 1711 uint8_t ln2range; 1712 uint32_t testval; 1713 uint16_t cmd; 1714 int type; 1715 int barlen; 1716 struct resource *res; 1717 1718 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1719 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1720 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1721 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1722 1723 if (pci_maptype(map) & PCI_MAPMEM) 1724 type = SYS_RES_MEMORY; 1725 else 1726 type = SYS_RES_IOPORT; 1727 ln2size = pci_mapsize(testval); 1728 ln2range = pci_maprange(testval); 1729 base = pci_mapbase(map); 1730 barlen = ln2range == 64 ? 2 : 1; 1731 1732 /* 1733 * For I/O registers, if bottom bit is set, and the next bit up 1734 * isn't clear, we know we have a BAR that doesn't conform to the 1735 * spec, so ignore it. Also, sanity check the size of the data 1736 * areas to the type of memory involved. Memory must be at least 1737 * 16 bytes in size, while I/O ranges must be at least 4. 1738 */ 1739 if ((testval & 0x1) == 0x1 && 1740 (testval & 0x2) != 0) 1741 return (barlen); 1742 if ((type == SYS_RES_MEMORY && ln2size < 4) || 1743 (type == SYS_RES_IOPORT && ln2size < 2)) 1744 return (barlen); 1745 1746 if (ln2range == 64) 1747 /* Read the other half of a 64bit map register */ 1748 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 1749 if (bootverbose) { 1750 printf("\tmap[%02x]: type %x, range %2d, base %#jx, size %2d", 1751 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size); 1752 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1753 printf(", port disabled\n"); 1754 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1755 printf(", memory disabled\n"); 1756 else 1757 printf(", enabled\n"); 1758 } 1759 1760 /* 1761 * If base is 0, then we have problems. It is best to ignore 1762 * such entries for the moment. These will be allocated later if 1763 * the driver specifically requests them. However, some 1764 * removable busses look better when all resources are allocated, 1765 * so allow '0' to be overriden. 1766 * 1767 * Similarly treat maps whose values is the same as the test value 1768 * read back. These maps have had all f's written to them by the 1769 * BIOS in an attempt to disable the resources. 1770 */ 1771 if (!force && (base == 0 || map == testval)) 1772 return (barlen); 1773 if ((u_long)base != base) { 1774 device_printf(bus, 1775 "pci%d:%d:%d bar %#x too many address bits", b, s, f, reg); 1776 return (barlen); 1777 } 1778 1779 /* 1780 * This code theoretically does the right thing, but has 1781 * undesirable side effects in some cases where peripherals 1782 * respond oddly to having these bits enabled. Let the user 1783 * be able to turn them off (since pci_enable_io_modes is 1 by 1784 * default). 1785 */ 1786 if (pci_enable_io_modes) { 1787 /* Turn on resources that have been left off by a lazy BIOS */ 1788 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1789 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1790 cmd |= PCIM_CMD_PORTEN; 1791 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1792 } 1793 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1794 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1795 cmd |= PCIM_CMD_MEMEN; 1796 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1797 } 1798 } else { 1799 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1800 return (barlen); 1801 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1802 return (barlen); 1803 } 1804 1805 count = 1 << ln2size; 1806 if (base == 0 || base == pci_mapbase(testval)) { 1807 start = 0; /* Let the parent deside */ 1808 end = ~0ULL; 1809 } else { 1810 start = base; 1811 end = base + (1 << ln2size) - 1; 1812 } 1813 resource_list_add(rl, type, reg, start, end, count); 1814 1815 /* 1816 * Not quite sure what to do on failure of allocating the resource 1817 * since I can postulate several right answers. 1818 */ 1819 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 1820 prefetch ? RF_PREFETCHABLE : 0); 1821 if (res == NULL) 1822 return (barlen); 1823 start = rman_get_start(res); 1824 if ((u_long)start != start) { 1825 /* Wait a minute! this platform can't do this address. */ 1826 device_printf(bus, 1827 "pci%d.%d.%x bar %#x start %#jx, too many bits.", 1828 b, s, f, reg, (uintmax_t)start); 1829 resource_list_release(rl, bus, dev, type, reg, res); 1830 return (barlen); 1831 } 1832 pci_write_config(dev, reg, start, 4); 1833 if (ln2range == 64) 1834 pci_write_config(dev, reg + 4, start >> 32, 4); 1835 return (barlen); 1836} 1837 1838/* 1839 * For ATA devices we need to decide early what addressing mode to use. 1840 * Legacy demands that the primary and secondary ATA ports sits on the 1841 * same addresses that old ISA hardware did. This dictates that we use 1842 * those addresses and ignore the BAR's if we cannot set PCI native 1843 * addressing mode. 1844 */ 1845static void 1846pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 1847 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 1848{ 1849 int rid, type, progif; 1850#if 0 1851 /* if this device supports PCI native addressing use it */ 1852 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1853 if ((progif & 0x8a) == 0x8a) { 1854 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1855 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1856 printf("Trying ATA native PCI addressing mode\n"); 1857 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1858 } 1859 } 1860#endif 1861 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1862 type = SYS_RES_IOPORT; 1863 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1864 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 1865 prefetchmask & (1 << 0)); 1866 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 1867 prefetchmask & (1 << 1)); 1868 } else { 1869 rid = PCIR_BAR(0); 1870 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1871 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1872 0); 1873 rid = PCIR_BAR(1); 1874 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1875 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1876 0); 1877 } 1878 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1879 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 1880 prefetchmask & (1 << 2)); 1881 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 1882 prefetchmask & (1 << 3)); 1883 } else { 1884 rid = PCIR_BAR(2); 1885 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1886 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1887 0); 1888 rid = PCIR_BAR(3); 1889 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1890 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1891 0); 1892 } 1893 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 1894 prefetchmask & (1 << 4)); 1895 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 1896 prefetchmask & (1 << 5)); 1897} 1898 1899static void 1900pci_assign_interrupt(device_t bus, device_t dev, int force_route) 1901{ 1902 struct pci_devinfo *dinfo = device_get_ivars(dev); 1903 pcicfgregs *cfg = &dinfo->cfg; 1904 char tunable_name[64]; 1905 int irq; 1906 1907 /* Has to have an intpin to have an interrupt. */ 1908 if (cfg->intpin == 0) 1909 return; 1910 1911 /* Let the user override the IRQ with a tunable. */ 1912 irq = PCI_INVALID_IRQ; 1913 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 1914 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 1915 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 1916 irq = PCI_INVALID_IRQ; 1917 1918 /* 1919 * If we didn't get an IRQ via the tunable, then we either use the 1920 * IRQ value in the intline register or we ask the bus to route an 1921 * interrupt for us. If force_route is true, then we only use the 1922 * value in the intline register if the bus was unable to assign an 1923 * IRQ. 1924 */ 1925 if (!PCI_INTERRUPT_VALID(irq)) { 1926 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 1927 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 1928 if (!PCI_INTERRUPT_VALID(irq)) 1929 irq = cfg->intline; 1930 } 1931 1932 /* If after all that we don't have an IRQ, just bail. */ 1933 if (!PCI_INTERRUPT_VALID(irq)) 1934 return; 1935 1936 /* Update the config register if it changed. */ 1937 if (irq != cfg->intline) { 1938 cfg->intline = irq; 1939 pci_write_config(dev, PCIR_INTLINE, irq, 1); 1940 } 1941 1942 /* Add this IRQ as rid 0 interrupt resource. */ 1943 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 1944} 1945 1946void 1947pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 1948{ 1949 device_t pcib; 1950 struct pci_devinfo *dinfo = device_get_ivars(dev); 1951 pcicfgregs *cfg = &dinfo->cfg; 1952 struct resource_list *rl = &dinfo->resources; 1953 struct pci_quirk *q; 1954 int b, i, f, s; 1955 1956 pcib = device_get_parent(bus); 1957 1958 b = cfg->bus; 1959 s = cfg->slot; 1960 f = cfg->func; 1961 1962 /* ATA devices needs special map treatment */ 1963 if ((pci_get_class(dev) == PCIC_STORAGE) && 1964 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1965 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1966 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 1967 else 1968 for (i = 0; i < cfg->nummaps;) 1969 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1970 rl, force, prefetchmask & (1 << i)); 1971 1972 /* 1973 * Add additional, quirked resources. 1974 */ 1975 for (q = &pci_quirks[0]; q->devid; q++) { 1976 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1977 && q->type == PCI_QUIRK_MAP_REG) 1978 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 1979 force, 0); 1980 } 1981 1982 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1983#ifdef __PCI_REROUTE_INTERRUPT 1984 /* 1985 * Try to re-route interrupts. Sometimes the BIOS or 1986 * firmware may leave bogus values in these registers. 1987 * If the re-route fails, then just stick with what we 1988 * have. 1989 */ 1990 pci_assign_interrupt(bus, dev, 1); 1991#else 1992 pci_assign_interrupt(bus, dev, 0); 1993#endif 1994 } 1995} 1996 1997void 1998pci_add_children(device_t dev, int busno, size_t dinfo_size) 1999{ 2000#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 2001 device_t pcib = device_get_parent(dev); 2002 struct pci_devinfo *dinfo; 2003 int maxslots; 2004 int s, f, pcifunchigh; 2005 uint8_t hdrtype; 2006 2007 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 2008 ("dinfo_size too small")); 2009 maxslots = PCIB_MAXSLOTS(pcib); 2010 for (s = 0; s <= maxslots; s++) { 2011 pcifunchigh = 0; 2012 f = 0; 2013 DELAY(1); 2014 hdrtype = REG(PCIR_HDRTYPE, 1); 2015 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 2016 continue; 2017 if (hdrtype & PCIM_MFDEV) 2018 pcifunchigh = PCI_FUNCMAX; 2019 for (f = 0; f <= pcifunchigh; f++) { 2020 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 2021 if (dinfo != NULL) { 2022 pci_add_child(dev, dinfo); 2023 } 2024 } 2025 } 2026#undef REG 2027} 2028 2029void 2030pci_add_child(device_t bus, struct pci_devinfo *dinfo) 2031{ 2032 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 2033 device_set_ivars(dinfo->cfg.dev, dinfo); 2034 resource_list_init(&dinfo->resources); 2035 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 2036 pci_cfg_restore(dinfo->cfg.dev, dinfo); 2037 pci_print_verbose(dinfo); 2038 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 2039} 2040 2041static int 2042pci_probe(device_t dev) 2043{ 2044 2045 device_set_desc(dev, "PCI bus"); 2046 2047 /* Allow other subclasses to override this driver. */ 2048 return (-1000); 2049} 2050 2051static int 2052pci_attach(device_t dev) 2053{ 2054 int busno; 2055 2056 /* 2057 * Since there can be multiple independantly numbered PCI 2058 * busses on systems with multiple PCI domains, we can't use 2059 * the unit number to decide which bus we are probing. We ask 2060 * the parent pcib what our bus number is. 2061 */ 2062 busno = pcib_get_bus(dev); 2063 if (bootverbose) 2064 device_printf(dev, "physical bus=%d\n", busno); 2065 2066 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 2067 2068 return (bus_generic_attach(dev)); 2069} 2070 2071int 2072pci_suspend(device_t dev) 2073{ 2074 int dstate, error, i, numdevs; 2075 device_t acpi_dev, child, *devlist; 2076 struct pci_devinfo *dinfo; 2077 2078 /* 2079 * Save the PCI configuration space for each child and set the 2080 * device in the appropriate power state for this sleep state. 2081 */ 2082 acpi_dev = NULL; 2083 if (pci_do_power_resume) 2084 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2085 device_get_children(dev, &devlist, &numdevs); 2086 for (i = 0; i < numdevs; i++) { 2087 child = devlist[i]; 2088 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2089 pci_cfg_save(child, dinfo, 0); 2090 } 2091 2092 /* Suspend devices before potentially powering them down. */ 2093 error = bus_generic_suspend(dev); 2094 if (error) { 2095 free(devlist, M_TEMP); 2096 return (error); 2097 } 2098 2099 /* 2100 * Always set the device to D3. If ACPI suggests a different 2101 * power state, use it instead. If ACPI is not present, the 2102 * firmware is responsible for managing device power. Skip 2103 * children who aren't attached since they are powered down 2104 * separately. Only manage type 0 devices for now. 2105 */ 2106 for (i = 0; acpi_dev && i < numdevs; i++) { 2107 child = devlist[i]; 2108 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2109 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 2110 dstate = PCI_POWERSTATE_D3; 2111 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 2112 pci_set_powerstate(child, dstate); 2113 } 2114 } 2115 free(devlist, M_TEMP); 2116 return (0); 2117} 2118 2119int 2120pci_resume(device_t dev) 2121{ 2122 int i, numdevs; 2123 device_t acpi_dev, child, *devlist; 2124 struct pci_devinfo *dinfo; 2125 2126 /* 2127 * Set each child to D0 and restore its PCI configuration space. 2128 */ 2129 acpi_dev = NULL; 2130 if (pci_do_power_resume) 2131 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2132 device_get_children(dev, &devlist, &numdevs); 2133 for (i = 0; i < numdevs; i++) { 2134 /* 2135 * Notify ACPI we're going to D0 but ignore the result. If 2136 * ACPI is not present, the firmware is responsible for 2137 * managing device power. Only manage type 0 devices for now. 2138 */ 2139 child = devlist[i]; 2140 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2141 if (acpi_dev && device_is_attached(child) && 2142 dinfo->cfg.hdrtype == 0) { 2143 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 2144 pci_set_powerstate(child, PCI_POWERSTATE_D0); 2145 } 2146 2147 /* Now the device is powered up, restore its config space. */ 2148 pci_cfg_restore(child, dinfo); 2149 } 2150 free(devlist, M_TEMP); 2151 return (bus_generic_resume(dev)); 2152} 2153 2154static void 2155pci_load_vendor_data(void) 2156{ 2157 caddr_t vendordata, info; 2158 2159 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 2160 info = preload_search_info(vendordata, MODINFO_ADDR); 2161 pci_vendordata = *(char **)info; 2162 info = preload_search_info(vendordata, MODINFO_SIZE); 2163 pci_vendordata_size = *(size_t *)info; 2164 /* terminate the database */ 2165 pci_vendordata[pci_vendordata_size] = '\n'; 2166 } 2167} 2168 2169void 2170pci_driver_added(device_t dev, driver_t *driver) 2171{ 2172 int numdevs; 2173 device_t *devlist; 2174 device_t child; 2175 struct pci_devinfo *dinfo; 2176 int i; 2177 2178 if (bootverbose) 2179 device_printf(dev, "driver added\n"); 2180 DEVICE_IDENTIFY(driver, dev); 2181 device_get_children(dev, &devlist, &numdevs); 2182 for (i = 0; i < numdevs; i++) { 2183 child = devlist[i]; 2184 if (device_get_state(child) != DS_NOTPRESENT) 2185 continue; 2186 dinfo = device_get_ivars(child); 2187 pci_print_verbose(dinfo); 2188 if (bootverbose) 2189 printf("pci%d:%d:%d: reprobing on driver added\n", 2190 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 2191 pci_cfg_restore(child, dinfo); 2192 if (device_probe_and_attach(child) != 0) 2193 pci_cfg_save(child, dinfo, 1); 2194 } 2195 free(devlist, M_TEMP); 2196} 2197 2198int 2199pci_print_child(device_t dev, device_t child) 2200{ 2201 struct pci_devinfo *dinfo; 2202 struct resource_list *rl; 2203 int retval = 0; 2204 2205 dinfo = device_get_ivars(child); 2206 rl = &dinfo->resources; 2207 2208 retval += bus_print_child_header(dev, child); 2209 2210 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 2211 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 2212 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 2213 if (device_get_flags(dev)) 2214 retval += printf(" flags %#x", device_get_flags(dev)); 2215 2216 retval += printf(" at device %d.%d", pci_get_slot(child), 2217 pci_get_function(child)); 2218 2219 retval += bus_print_child_footer(dev, child); 2220 2221 return (retval); 2222} 2223 2224static struct 2225{ 2226 int class; 2227 int subclass; 2228 char *desc; 2229} pci_nomatch_tab[] = { 2230 {PCIC_OLD, -1, "old"}, 2231 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 2232 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 2233 {PCIC_STORAGE, -1, "mass storage"}, 2234 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 2235 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 2236 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 2237 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 2238 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 2239 {PCIC_NETWORK, -1, "network"}, 2240 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 2241 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 2242 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 2243 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 2244 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 2245 {PCIC_DISPLAY, -1, "display"}, 2246 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 2247 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 2248 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 2249 {PCIC_MULTIMEDIA, -1, "multimedia"}, 2250 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 2251 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 2252 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 2253 {PCIC_MEMORY, -1, "memory"}, 2254 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 2255 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 2256 {PCIC_BRIDGE, -1, "bridge"}, 2257 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 2258 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 2259 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 2260 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 2261 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 2262 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 2263 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 2264 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 2265 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 2266 {PCIC_SIMPLECOMM, -1, "simple comms"}, 2267 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 2268 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 2269 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 2270 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 2271 {PCIC_BASEPERIPH, -1, "base peripheral"}, 2272 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 2273 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 2274 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 2275 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 2276 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 2277 {PCIC_INPUTDEV, -1, "input device"}, 2278 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 2279 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 2280 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 2281 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 2282 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 2283 {PCIC_DOCKING, -1, "docking station"}, 2284 {PCIC_PROCESSOR, -1, "processor"}, 2285 {PCIC_SERIALBUS, -1, "serial bus"}, 2286 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 2287 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 2288 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 2289 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 2290 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 2291 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 2292 {PCIC_WIRELESS, -1, "wireless controller"}, 2293 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 2294 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 2295 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 2296 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 2297 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 2298 {PCIC_SATCOM, -1, "satellite communication"}, 2299 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 2300 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 2301 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 2302 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 2303 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 2304 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 2305 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 2306 {PCIC_DASP, -1, "dasp"}, 2307 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 2308 {0, 0, NULL} 2309}; 2310 2311void 2312pci_probe_nomatch(device_t dev, device_t child) 2313{ 2314 int i; 2315 char *cp, *scp, *device; 2316 2317 /* 2318 * Look for a listing for this device in a loaded device database. 2319 */ 2320 if ((device = pci_describe_device(child)) != NULL) { 2321 device_printf(dev, "<%s>", device); 2322 free(device, M_DEVBUF); 2323 } else { 2324 /* 2325 * Scan the class/subclass descriptions for a general 2326 * description. 2327 */ 2328 cp = "unknown"; 2329 scp = NULL; 2330 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 2331 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 2332 if (pci_nomatch_tab[i].subclass == -1) { 2333 cp = pci_nomatch_tab[i].desc; 2334 } else if (pci_nomatch_tab[i].subclass == 2335 pci_get_subclass(child)) { 2336 scp = pci_nomatch_tab[i].desc; 2337 } 2338 } 2339 } 2340 device_printf(dev, "<%s%s%s>", 2341 cp ? cp : "", 2342 ((cp != NULL) && (scp != NULL)) ? ", " : "", 2343 scp ? scp : ""); 2344 } 2345 printf(" at device %d.%d (no driver attached)\n", 2346 pci_get_slot(child), pci_get_function(child)); 2347 if (pci_do_power_nodriver) 2348 pci_cfg_save(child, 2349 (struct pci_devinfo *) device_get_ivars(child), 1); 2350 return; 2351} 2352 2353/* 2354 * Parse the PCI device database, if loaded, and return a pointer to a 2355 * description of the device. 2356 * 2357 * The database is flat text formatted as follows: 2358 * 2359 * Any line not in a valid format is ignored. 2360 * Lines are terminated with newline '\n' characters. 2361 * 2362 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 2363 * the vendor name. 2364 * 2365 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 2366 * - devices cannot be listed without a corresponding VENDOR line. 2367 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 2368 * another TAB, then the device name. 2369 */ 2370 2371/* 2372 * Assuming (ptr) points to the beginning of a line in the database, 2373 * return the vendor or device and description of the next entry. 2374 * The value of (vendor) or (device) inappropriate for the entry type 2375 * is set to -1. Returns nonzero at the end of the database. 2376 * 2377 * Note that this is slightly unrobust in the face of corrupt data; 2378 * we attempt to safeguard against this by spamming the end of the 2379 * database with a newline when we initialise. 2380 */ 2381static int 2382pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 2383{ 2384 char *cp = *ptr; 2385 int left; 2386 2387 *device = -1; 2388 *vendor = -1; 2389 **desc = '\0'; 2390 for (;;) { 2391 left = pci_vendordata_size - (cp - pci_vendordata); 2392 if (left <= 0) { 2393 *ptr = cp; 2394 return(1); 2395 } 2396 2397 /* vendor entry? */ 2398 if (*cp != '\t' && 2399 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 2400 break; 2401 /* device entry? */ 2402 if (*cp == '\t' && 2403 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 2404 break; 2405 2406 /* skip to next line */ 2407 while (*cp != '\n' && left > 0) { 2408 cp++; 2409 left--; 2410 } 2411 if (*cp == '\n') { 2412 cp++; 2413 left--; 2414 } 2415 } 2416 /* skip to next line */ 2417 while (*cp != '\n' && left > 0) { 2418 cp++; 2419 left--; 2420 } 2421 if (*cp == '\n' && left > 0) 2422 cp++; 2423 *ptr = cp; 2424 return(0); 2425} 2426 2427static char * 2428pci_describe_device(device_t dev) 2429{ 2430 int vendor, device; 2431 char *desc, *vp, *dp, *line; 2432 2433 desc = vp = dp = NULL; 2434 2435 /* 2436 * If we have no vendor data, we can't do anything. 2437 */ 2438 if (pci_vendordata == NULL) 2439 goto out; 2440 2441 /* 2442 * Scan the vendor data looking for this device 2443 */ 2444 line = pci_vendordata; 2445 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 2446 goto out; 2447 for (;;) { 2448 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 2449 goto out; 2450 if (vendor == pci_get_vendor(dev)) 2451 break; 2452 } 2453 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 2454 goto out; 2455 for (;;) { 2456 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 2457 *dp = 0; 2458 break; 2459 } 2460 if (vendor != -1) { 2461 *dp = 0; 2462 break; 2463 } 2464 if (device == pci_get_device(dev)) 2465 break; 2466 } 2467 if (dp[0] == '\0') 2468 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 2469 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 2470 NULL) 2471 sprintf(desc, "%s, %s", vp, dp); 2472 out: 2473 if (vp != NULL) 2474 free(vp, M_DEVBUF); 2475 if (dp != NULL) 2476 free(dp, M_DEVBUF); 2477 return(desc); 2478} 2479 2480int 2481pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 2482{ 2483 struct pci_devinfo *dinfo; 2484 pcicfgregs *cfg; 2485 2486 dinfo = device_get_ivars(child); 2487 cfg = &dinfo->cfg; 2488 2489 switch (which) { 2490 case PCI_IVAR_ETHADDR: 2491 /* 2492 * The generic accessor doesn't deal with failure, so 2493 * we set the return value, then return an error. 2494 */ 2495 *((uint8_t **) result) = NULL; 2496 return (EINVAL); 2497 case PCI_IVAR_SUBVENDOR: 2498 *result = cfg->subvendor; 2499 break; 2500 case PCI_IVAR_SUBDEVICE: 2501 *result = cfg->subdevice; 2502 break; 2503 case PCI_IVAR_VENDOR: 2504 *result = cfg->vendor; 2505 break; 2506 case PCI_IVAR_DEVICE: 2507 *result = cfg->device; 2508 break; 2509 case PCI_IVAR_DEVID: 2510 *result = (cfg->device << 16) | cfg->vendor; 2511 break; 2512 case PCI_IVAR_CLASS: 2513 *result = cfg->baseclass; 2514 break; 2515 case PCI_IVAR_SUBCLASS: 2516 *result = cfg->subclass; 2517 break; 2518 case PCI_IVAR_PROGIF: 2519 *result = cfg->progif; 2520 break; 2521 case PCI_IVAR_REVID: 2522 *result = cfg->revid; 2523 break; 2524 case PCI_IVAR_INTPIN: 2525 *result = cfg->intpin; 2526 break; 2527 case PCI_IVAR_IRQ: 2528 *result = cfg->intline; 2529 break; 2530 case PCI_IVAR_BUS: 2531 *result = cfg->bus; 2532 break; 2533 case PCI_IVAR_SLOT: 2534 *result = cfg->slot; 2535 break; 2536 case PCI_IVAR_FUNCTION: 2537 *result = cfg->func; 2538 break; 2539 case PCI_IVAR_CMDREG: 2540 *result = cfg->cmdreg; 2541 break; 2542 case PCI_IVAR_CACHELNSZ: 2543 *result = cfg->cachelnsz; 2544 break; 2545 case PCI_IVAR_MINGNT: 2546 *result = cfg->mingnt; 2547 break; 2548 case PCI_IVAR_MAXLAT: 2549 *result = cfg->maxlat; 2550 break; 2551 case PCI_IVAR_LATTIMER: 2552 *result = cfg->lattimer; 2553 break; 2554 default: 2555 return (ENOENT); 2556 } 2557 return (0); 2558} 2559 2560int 2561pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 2562{ 2563 struct pci_devinfo *dinfo; 2564 2565 dinfo = device_get_ivars(child); 2566 2567 switch (which) { 2568 case PCI_IVAR_INTPIN: 2569 dinfo->cfg.intpin = value; 2570 return (0); 2571 case PCI_IVAR_ETHADDR: 2572 case PCI_IVAR_SUBVENDOR: 2573 case PCI_IVAR_SUBDEVICE: 2574 case PCI_IVAR_VENDOR: 2575 case PCI_IVAR_DEVICE: 2576 case PCI_IVAR_DEVID: 2577 case PCI_IVAR_CLASS: 2578 case PCI_IVAR_SUBCLASS: 2579 case PCI_IVAR_PROGIF: 2580 case PCI_IVAR_REVID: 2581 case PCI_IVAR_IRQ: 2582 case PCI_IVAR_BUS: 2583 case PCI_IVAR_SLOT: 2584 case PCI_IVAR_FUNCTION: 2585 return (EINVAL); /* disallow for now */ 2586 2587 default: 2588 return (ENOENT); 2589 } 2590} 2591 2592 2593#include "opt_ddb.h" 2594#ifdef DDB 2595#include <ddb/ddb.h> 2596#include <sys/cons.h> 2597 2598/* 2599 * List resources based on pci map registers, used for within ddb 2600 */ 2601 2602DB_SHOW_COMMAND(pciregs, db_pci_dump) 2603{ 2604 struct pci_devinfo *dinfo; 2605 struct devlist *devlist_head; 2606 struct pci_conf *p; 2607 const char *name; 2608 int i, error, none_count; 2609 2610 none_count = 0; 2611 /* get the head of the device queue */ 2612 devlist_head = &pci_devq; 2613 2614 /* 2615 * Go through the list of devices and print out devices 2616 */ 2617 for (error = 0, i = 0, 2618 dinfo = STAILQ_FIRST(devlist_head); 2619 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 2620 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 2621 2622 /* Populate pd_name and pd_unit */ 2623 name = NULL; 2624 if (dinfo->cfg.dev) 2625 name = device_get_name(dinfo->cfg.dev); 2626 2627 p = &dinfo->conf; 2628 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 2629 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 2630 (name && *name) ? name : "none", 2631 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 2632 none_count++, 2633 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 2634 p->pc_sel.pc_func, (p->pc_class << 16) | 2635 (p->pc_subclass << 8) | p->pc_progif, 2636 (p->pc_subdevice << 16) | p->pc_subvendor, 2637 (p->pc_device << 16) | p->pc_vendor, 2638 p->pc_revid, p->pc_hdr); 2639 } 2640} 2641#endif /* DDB */ 2642 2643static struct resource * 2644pci_alloc_map(device_t dev, device_t child, int type, int *rid, 2645 u_long start, u_long end, u_long count, u_int flags) 2646{ 2647 struct pci_devinfo *dinfo = device_get_ivars(child); 2648 struct resource_list *rl = &dinfo->resources; 2649 struct resource_list_entry *rle; 2650 struct resource *res; 2651 pci_addr_t map, testval; 2652 int mapsize; 2653 2654 /* 2655 * Weed out the bogons, and figure out how large the BAR/map 2656 * is. Bars that read back 0 here are bogus and unimplemented. 2657 * Note: atapci in legacy mode are special and handled elsewhere 2658 * in the code. If you have a atapci device in legacy mode and 2659 * it fails here, that other code is broken. 2660 */ 2661 res = NULL; 2662 map = pci_read_config(child, *rid, 4); 2663 pci_write_config(child, *rid, 0xffffffff, 4); 2664 testval = pci_read_config(child, *rid, 4); 2665 if (pci_maprange(testval) == 64) 2666 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32; 2667 if (pci_mapbase(testval) == 0) 2668 goto out; 2669 if (pci_maptype(testval) & PCI_MAPMEM) { 2670 if (type != SYS_RES_MEMORY) { 2671 if (bootverbose) 2672 device_printf(dev, 2673 "child %s requested type %d for rid %#x," 2674 " but the BAR says it is an memio\n", 2675 device_get_nameunit(child), type, *rid); 2676 goto out; 2677 } 2678 } else { 2679 if (type != SYS_RES_IOPORT) { 2680 if (bootverbose) 2681 device_printf(dev, 2682 "child %s requested type %d for rid %#x," 2683 " but the BAR says it is an ioport\n", 2684 device_get_nameunit(child), type, *rid); 2685 goto out; 2686 } 2687 } 2688 /* 2689 * For real BARs, we need to override the size that 2690 * the driver requests, because that's what the BAR 2691 * actually uses and we would otherwise have a 2692 * situation where we might allocate the excess to 2693 * another driver, which won't work. 2694 */ 2695 mapsize = pci_mapsize(testval); 2696 count = 1UL << mapsize; 2697 if (RF_ALIGNMENT(flags) < mapsize) 2698 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 2699 2700 /* 2701 * Allocate enough resource, and then write back the 2702 * appropriate bar for that resource. 2703 */ 2704 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2705 start, end, count, flags); 2706 if (res == NULL) { 2707 device_printf(child, 2708 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 2709 count, *rid, type, start, end); 2710 goto out; 2711 } 2712 resource_list_add(rl, type, *rid, start, end, count); 2713 rle = resource_list_find(rl, type, *rid); 2714 if (rle == NULL) 2715 panic("pci_alloc_map: unexpectedly can't find resource."); 2716 rle->res = res; 2717 rle->start = rman_get_start(res); 2718 rle->end = rman_get_end(res); 2719 rle->count = count; 2720 if (bootverbose) 2721 device_printf(child, 2722 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 2723 count, *rid, type, rman_get_start(res)); 2724 map = rman_get_start(res); 2725out:; 2726 pci_write_config(child, *rid, map, 4); 2727 if (pci_maprange(testval) == 64) 2728 pci_write_config(child, *rid + 4, map >> 32, 4); 2729 return (res); 2730} 2731 2732 2733struct resource * 2734pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2735 u_long start, u_long end, u_long count, u_int flags) 2736{ 2737 struct pci_devinfo *dinfo = device_get_ivars(child); 2738 struct resource_list *rl = &dinfo->resources; 2739 struct resource_list_entry *rle; 2740 pcicfgregs *cfg = &dinfo->cfg; 2741 2742 /* 2743 * Perform lazy resource allocation 2744 */ 2745 if (device_get_parent(child) == dev) { 2746 switch (type) { 2747 case SYS_RES_IRQ: 2748 /* 2749 * Can't alloc legacy interrupt once MSI messages 2750 * have been allocated. 2751 */ 2752 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 2753 cfg->msix.msix_alloc > 0)) 2754 return (NULL); 2755 /* 2756 * If the child device doesn't have an 2757 * interrupt routed and is deserving of an 2758 * interrupt, try to assign it one. 2759 */ 2760 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 2761 (cfg->intpin != 0)) 2762 pci_assign_interrupt(dev, child, 0); 2763 break; 2764 case SYS_RES_IOPORT: 2765 case SYS_RES_MEMORY: 2766 if (*rid < PCIR_BAR(cfg->nummaps)) { 2767 /* 2768 * Enable the I/O mode. We should 2769 * also be assigning resources too 2770 * when none are present. The 2771 * resource_list_alloc kind of sorta does 2772 * this... 2773 */ 2774 if (PCI_ENABLE_IO(dev, child, type)) 2775 return (NULL); 2776 } 2777 rle = resource_list_find(rl, type, *rid); 2778 if (rle == NULL) 2779 return (pci_alloc_map(dev, child, type, rid, 2780 start, end, count, flags)); 2781 break; 2782 } 2783 /* 2784 * If we've already allocated the resource, then 2785 * return it now. But first we may need to activate 2786 * it, since we don't allocate the resource as active 2787 * above. Normally this would be done down in the 2788 * nexus, but since we short-circuit that path we have 2789 * to do its job here. Not sure if we should free the 2790 * resource if it fails to activate. 2791 */ 2792 rle = resource_list_find(rl, type, *rid); 2793 if (rle != NULL && rle->res != NULL) { 2794 if (bootverbose) 2795 device_printf(child, 2796 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 2797 rman_get_size(rle->res), *rid, type, 2798 rman_get_start(rle->res)); 2799 if ((flags & RF_ACTIVE) && 2800 bus_generic_activate_resource(dev, child, type, 2801 *rid, rle->res) != 0) 2802 return NULL; 2803 return (rle->res); 2804 } 2805 } 2806 return (resource_list_alloc(rl, dev, child, type, rid, 2807 start, end, count, flags)); 2808} 2809 2810void 2811pci_delete_resource(device_t dev, device_t child, int type, int rid) 2812{ 2813 struct pci_devinfo *dinfo; 2814 struct resource_list *rl; 2815 struct resource_list_entry *rle; 2816 2817 if (device_get_parent(child) != dev) 2818 return; 2819 2820 dinfo = device_get_ivars(child); 2821 rl = &dinfo->resources; 2822 rle = resource_list_find(rl, type, rid); 2823 if (rle) { 2824 if (rle->res) { 2825 if (rman_get_device(rle->res) != dev || 2826 rman_get_flags(rle->res) & RF_ACTIVE) { 2827 device_printf(dev, "delete_resource: " 2828 "Resource still owned by child, oops. " 2829 "(type=%d, rid=%d, addr=%lx)\n", 2830 rle->type, rle->rid, 2831 rman_get_start(rle->res)); 2832 return; 2833 } 2834 bus_release_resource(dev, type, rid, rle->res); 2835 } 2836 resource_list_delete(rl, type, rid); 2837 } 2838 /* 2839 * Why do we turn off the PCI configuration BAR when we delete a 2840 * resource? -- imp 2841 */ 2842 pci_write_config(child, rid, 0, 4); 2843 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 2844} 2845 2846struct resource_list * 2847pci_get_resource_list (device_t dev, device_t child) 2848{ 2849 struct pci_devinfo *dinfo = device_get_ivars(child); 2850 2851 return (&dinfo->resources); 2852} 2853 2854uint32_t 2855pci_read_config_method(device_t dev, device_t child, int reg, int width) 2856{ 2857 struct pci_devinfo *dinfo = device_get_ivars(child); 2858 pcicfgregs *cfg = &dinfo->cfg; 2859 2860 return (PCIB_READ_CONFIG(device_get_parent(dev), 2861 cfg->bus, cfg->slot, cfg->func, reg, width)); 2862} 2863 2864void 2865pci_write_config_method(device_t dev, device_t child, int reg, 2866 uint32_t val, int width) 2867{ 2868 struct pci_devinfo *dinfo = device_get_ivars(child); 2869 pcicfgregs *cfg = &dinfo->cfg; 2870 2871 PCIB_WRITE_CONFIG(device_get_parent(dev), 2872 cfg->bus, cfg->slot, cfg->func, reg, val, width); 2873} 2874 2875int 2876pci_child_location_str_method(device_t dev, device_t child, char *buf, 2877 size_t buflen) 2878{ 2879 2880 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2881 pci_get_function(child)); 2882 return (0); 2883} 2884 2885int 2886pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 2887 size_t buflen) 2888{ 2889 struct pci_devinfo *dinfo; 2890 pcicfgregs *cfg; 2891 2892 dinfo = device_get_ivars(child); 2893 cfg = &dinfo->cfg; 2894 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2895 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2896 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2897 cfg->progif); 2898 return (0); 2899} 2900 2901int 2902pci_assign_interrupt_method(device_t dev, device_t child) 2903{ 2904 struct pci_devinfo *dinfo = device_get_ivars(child); 2905 pcicfgregs *cfg = &dinfo->cfg; 2906 2907 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2908 cfg->intpin)); 2909} 2910 2911static int 2912pci_modevent(module_t mod, int what, void *arg) 2913{ 2914 static struct cdev *pci_cdev; 2915 2916 switch (what) { 2917 case MOD_LOAD: 2918 STAILQ_INIT(&pci_devq); 2919 pci_generation = 0; 2920 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 2921 "pci"); 2922 pci_load_vendor_data(); 2923 break; 2924 2925 case MOD_UNLOAD: 2926 destroy_dev(pci_cdev); 2927 break; 2928 } 2929 2930 return (0); 2931} 2932 2933void 2934pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 2935{ 2936 int i; 2937 2938 /* 2939 * Only do header type 0 devices. Type 1 devices are bridges, 2940 * which we know need special treatment. Type 2 devices are 2941 * cardbus bridges which also require special treatment. 2942 * Other types are unknown, and we err on the side of safety 2943 * by ignoring them. 2944 */ 2945 if (dinfo->cfg.hdrtype != 0) 2946 return; 2947 2948 /* 2949 * Restore the device to full power mode. We must do this 2950 * before we restore the registers because moving from D3 to 2951 * D0 will cause the chip's BARs and some other registers to 2952 * be reset to some unknown power on reset values. Cut down 2953 * the noise on boot by doing nothing if we are already in 2954 * state D0. 2955 */ 2956 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2957 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2958 } 2959 for (i = 0; i < dinfo->cfg.nummaps; i++) 2960 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2961 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2962 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2963 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2964 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2965 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2966 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2967 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2968 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2969 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2970 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2971 2972 /* 2973 * Restore MSI configuration if it is present. If MSI is enabled, 2974 * then restore the data and addr registers. 2975 */ 2976 if (dinfo->cfg.msi.msi_location != 0) 2977 pci_resume_msi(dev); 2978} 2979 2980void 2981pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2982{ 2983 int i; 2984 uint32_t cls; 2985 int ps; 2986 2987 /* 2988 * Only do header type 0 devices. Type 1 devices are bridges, which 2989 * we know need special treatment. Type 2 devices are cardbus bridges 2990 * which also require special treatment. Other types are unknown, and 2991 * we err on the side of safety by ignoring them. Powering down 2992 * bridges should not be undertaken lightly. 2993 */ 2994 if (dinfo->cfg.hdrtype != 0) 2995 return; 2996 for (i = 0; i < dinfo->cfg.nummaps; i++) 2997 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2998 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2999 3000 /* 3001 * Some drivers apparently write to these registers w/o updating our 3002 * cached copy. No harm happens if we update the copy, so do so here 3003 * so we can restore them. The COMMAND register is modified by the 3004 * bus w/o updating the cache. This should represent the normally 3005 * writable portion of the 'defined' part of type 0 headers. In 3006 * theory we also need to save/restore the PCI capability structures 3007 * we know about, but apart from power we don't know any that are 3008 * writable. 3009 */ 3010 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 3011 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 3012 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 3013 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 3014 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 3015 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 3016 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 3017 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 3018 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 3019 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3020 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3021 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 3022 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 3023 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 3024 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 3025 3026 /* 3027 * don't set the state for display devices, base peripherals and 3028 * memory devices since bad things happen when they are powered down. 3029 * We should (a) have drivers that can easily detach and (b) use 3030 * generic drivers for these devices so that some device actually 3031 * attaches. We need to make sure that when we implement (a) we don't 3032 * power the device down on a reattach. 3033 */ 3034 cls = pci_get_class(dev); 3035 if (!setstate) 3036 return; 3037 switch (pci_do_power_nodriver) 3038 { 3039 case 0: /* NO powerdown at all */ 3040 return; 3041 case 1: /* Conservative about what to power down */ 3042 if (cls == PCIC_STORAGE) 3043 return; 3044 /*FALLTHROUGH*/ 3045 case 2: /* Agressive about what to power down */ 3046 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 3047 cls == PCIC_BASEPERIPH) 3048 return; 3049 /*FALLTHROUGH*/ 3050 case 3: /* Power down everything */ 3051 break; 3052 } 3053 /* 3054 * PCI spec says we can only go into D3 state from D0 state. 3055 * Transition from D[12] into D0 before going to D3 state. 3056 */ 3057 ps = pci_get_powerstate(dev); 3058 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 3059 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 3060 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 3061 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 3062} 3063