pci.c revision 164467
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 164467 2006-11-21 05:46:09Z jmg $"); 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/endian.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63#ifdef __HAVE_ACPI 64#include <contrib/dev/acpica/acpi.h> 65#include "acpi_if.h" 66#else 67#define ACPI_PWR_FOR_SLEEP(x, y, z) 68#endif 69 70static uint32_t pci_mapbase(unsigned mapreg); 71static int pci_maptype(unsigned mapreg); 72static int pci_mapsize(unsigned testval); 73static int pci_maprange(unsigned mapreg); 74static void pci_fixancient(pcicfgregs *cfg); 75 76static int pci_porten(device_t pcib, int b, int s, int f); 77static int pci_memen(device_t pcib, int b, int s, int f); 78static void pci_assign_interrupt(device_t bus, device_t dev, 79 int force_route); 80static int pci_add_map(device_t pcib, device_t bus, device_t dev, 81 int b, int s, int f, int reg, 82 struct resource_list *rl, int force, int prefetch); 83static int pci_probe(device_t dev); 84static int pci_attach(device_t dev); 85static void pci_load_vendor_data(void); 86static int pci_describe_parse_line(char **ptr, int *vendor, 87 int *device, char **desc); 88static char *pci_describe_device(device_t dev); 89static int pci_modevent(module_t mod, int what, void *arg); 90static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 91 pcicfgregs *cfg); 92static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 93static uint32_t pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 94 int reg); 95#if 0 96static void pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 97 int reg, uint32_t data); 98#endif 99static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 100 101static device_method_t pci_methods[] = { 102 /* Device interface */ 103 DEVMETHOD(device_probe, pci_probe), 104 DEVMETHOD(device_attach, pci_attach), 105 DEVMETHOD(device_detach, bus_generic_detach), 106 DEVMETHOD(device_shutdown, bus_generic_shutdown), 107 DEVMETHOD(device_suspend, pci_suspend), 108 DEVMETHOD(device_resume, pci_resume), 109 110 /* Bus interface */ 111 DEVMETHOD(bus_print_child, pci_print_child), 112 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 113 DEVMETHOD(bus_read_ivar, pci_read_ivar), 114 DEVMETHOD(bus_write_ivar, pci_write_ivar), 115 DEVMETHOD(bus_driver_added, pci_driver_added), 116 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 117 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 118 119 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 120 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 121 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 122 DEVMETHOD(bus_delete_resource, pci_delete_resource), 123 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 124 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 125 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 126 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 127 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 128 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 129 130 /* PCI interface */ 131 DEVMETHOD(pci_read_config, pci_read_config_method), 132 DEVMETHOD(pci_write_config, pci_write_config_method), 133 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 134 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 135 DEVMETHOD(pci_enable_io, pci_enable_io_method), 136 DEVMETHOD(pci_disable_io, pci_disable_io_method), 137 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 138 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 139 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 140 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 141 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 142 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 143 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 144 DEVMETHOD(pci_release_msi, pci_release_msi_method), 145 DEVMETHOD(pci_msi_count, pci_msi_count_method), 146 147 { 0, 0 } 148}; 149 150DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 151 152static devclass_t pci_devclass; 153DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 154MODULE_VERSION(pci, 1); 155 156static char *pci_vendordata; 157static size_t pci_vendordata_size; 158 159 160struct pci_quirk { 161 uint32_t devid; /* Vendor/device of the card */ 162 int type; 163#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 164 int arg1; 165 int arg2; 166}; 167 168struct pci_quirk pci_quirks[] = { 169 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 170 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 171 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 172 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 173 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 174 175 { 0 } 176}; 177 178/* map register information */ 179#define PCI_MAPMEM 0x01 /* memory map */ 180#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 181#define PCI_MAPPORT 0x04 /* port map */ 182 183struct devlist pci_devq; 184uint32_t pci_generation; 185uint32_t pci_numdevs = 0; 186 187/* sysctl vars */ 188SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 189 190static int pci_enable_io_modes = 1; 191TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 192SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 193 &pci_enable_io_modes, 1, 194 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 195enable these bits correctly. We'd like to do this all the time, but there\n\ 196are some peripherals that this causes problems with."); 197 198static int pci_do_power_nodriver = 0; 199TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 200SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 201 &pci_do_power_nodriver, 0, 202 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 203disable. 1 means conservatively place devices into D3 state. 2 means\n\ 204agressively place devices into D3 state. 3 means put absolutely everything\n\ 205in D3 state."); 206 207static int pci_do_power_resume = 1; 208TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 209SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 210 &pci_do_power_resume, 1, 211 "Transition from D3 -> D0 on resume."); 212 213static int pci_do_msi = 1; 214TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi); 215SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1, 216 "Enable support for MSI interrupts"); 217 218static int pci_do_msix = 1; 219TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix); 220SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1, 221 "Enable support for MSI-X interrupts"); 222 223/* Find a device_t by bus/slot/function */ 224 225device_t 226pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 227{ 228 struct pci_devinfo *dinfo; 229 230 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 231 if ((dinfo->cfg.bus == bus) && 232 (dinfo->cfg.slot == slot) && 233 (dinfo->cfg.func == func)) { 234 return (dinfo->cfg.dev); 235 } 236 } 237 238 return (NULL); 239} 240 241/* Find a device_t by vendor/device ID */ 242 243device_t 244pci_find_device(uint16_t vendor, uint16_t device) 245{ 246 struct pci_devinfo *dinfo; 247 248 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 249 if ((dinfo->cfg.vendor == vendor) && 250 (dinfo->cfg.device == device)) { 251 return (dinfo->cfg.dev); 252 } 253 } 254 255 return (NULL); 256} 257 258/* return base address of memory or port map */ 259 260static uint32_t 261pci_mapbase(uint32_t mapreg) 262{ 263 int mask = 0x03; 264 if ((mapreg & 0x01) == 0) 265 mask = 0x0f; 266 return (mapreg & ~mask); 267} 268 269/* return map type of memory or port map */ 270 271static int 272pci_maptype(unsigned mapreg) 273{ 274 static uint8_t maptype[0x10] = { 275 PCI_MAPMEM, PCI_MAPPORT, 276 PCI_MAPMEM, 0, 277 PCI_MAPMEM, PCI_MAPPORT, 278 0, 0, 279 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 280 PCI_MAPMEM|PCI_MAPMEMP, 0, 281 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 282 0, 0, 283 }; 284 285 return maptype[mapreg & 0x0f]; 286} 287 288/* return log2 of map size decoded for memory or port map */ 289 290static int 291pci_mapsize(uint32_t testval) 292{ 293 int ln2size; 294 295 testval = pci_mapbase(testval); 296 ln2size = 0; 297 if (testval != 0) { 298 while ((testval & 1) == 0) 299 { 300 ln2size++; 301 testval >>= 1; 302 } 303 } 304 return (ln2size); 305} 306 307/* return log2 of address range supported by map register */ 308 309static int 310pci_maprange(unsigned mapreg) 311{ 312 int ln2range = 0; 313 switch (mapreg & 0x07) { 314 case 0x00: 315 case 0x01: 316 case 0x05: 317 ln2range = 32; 318 break; 319 case 0x02: 320 ln2range = 20; 321 break; 322 case 0x04: 323 ln2range = 64; 324 break; 325 } 326 return (ln2range); 327} 328 329/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 330 331static void 332pci_fixancient(pcicfgregs *cfg) 333{ 334 if (cfg->hdrtype != 0) 335 return; 336 337 /* PCI to PCI bridges use header type 1 */ 338 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 339 cfg->hdrtype = 1; 340} 341 342/* extract header type specific config data */ 343 344static void 345pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 346{ 347#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 348 switch (cfg->hdrtype) { 349 case 0: 350 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 351 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 352 cfg->nummaps = PCI_MAXMAPS_0; 353 break; 354 case 1: 355 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 356 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 357 cfg->nummaps = PCI_MAXMAPS_1; 358 break; 359 case 2: 360 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 361 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 362 cfg->nummaps = PCI_MAXMAPS_2; 363 break; 364 } 365#undef REG 366} 367 368/* read configuration header into pcicfgregs structure */ 369struct pci_devinfo * 370pci_read_device(device_t pcib, int b, int s, int f, size_t size) 371{ 372#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 373 pcicfgregs *cfg = NULL; 374 struct pci_devinfo *devlist_entry; 375 struct devlist *devlist_head; 376 377 devlist_head = &pci_devq; 378 379 devlist_entry = NULL; 380 381 if (REG(PCIR_DEVVENDOR, 4) != -1) { 382 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 383 if (devlist_entry == NULL) 384 return (NULL); 385 386 cfg = &devlist_entry->cfg; 387 388 cfg->bus = b; 389 cfg->slot = s; 390 cfg->func = f; 391 cfg->vendor = REG(PCIR_VENDOR, 2); 392 cfg->device = REG(PCIR_DEVICE, 2); 393 cfg->cmdreg = REG(PCIR_COMMAND, 2); 394 cfg->statreg = REG(PCIR_STATUS, 2); 395 cfg->baseclass = REG(PCIR_CLASS, 1); 396 cfg->subclass = REG(PCIR_SUBCLASS, 1); 397 cfg->progif = REG(PCIR_PROGIF, 1); 398 cfg->revid = REG(PCIR_REVID, 1); 399 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 400 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 401 cfg->lattimer = REG(PCIR_LATTIMER, 1); 402 cfg->intpin = REG(PCIR_INTPIN, 1); 403 cfg->intline = REG(PCIR_INTLINE, 1); 404 405 cfg->mingnt = REG(PCIR_MINGNT, 1); 406 cfg->maxlat = REG(PCIR_MAXLAT, 1); 407 408 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 409 cfg->hdrtype &= ~PCIM_MFDEV; 410 411 pci_fixancient(cfg); 412 pci_hdrtypedata(pcib, b, s, f, cfg); 413 414 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 415 pci_read_extcap(pcib, cfg); 416 417 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 418 419 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 420 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 421 devlist_entry->conf.pc_sel.pc_func = cfg->func; 422 devlist_entry->conf.pc_hdr = cfg->hdrtype; 423 424 devlist_entry->conf.pc_subvendor = cfg->subvendor; 425 devlist_entry->conf.pc_subdevice = cfg->subdevice; 426 devlist_entry->conf.pc_vendor = cfg->vendor; 427 devlist_entry->conf.pc_device = cfg->device; 428 429 devlist_entry->conf.pc_class = cfg->baseclass; 430 devlist_entry->conf.pc_subclass = cfg->subclass; 431 devlist_entry->conf.pc_progif = cfg->progif; 432 devlist_entry->conf.pc_revid = cfg->revid; 433 434 pci_numdevs++; 435 pci_generation++; 436 } 437 return (devlist_entry); 438#undef REG 439} 440 441static void 442pci_read_extcap(device_t pcib, pcicfgregs *cfg) 443{ 444#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 445 uint32_t val; 446 int ptr, nextptr, ptrptr; 447 448 switch (cfg->hdrtype & PCIM_HDRTYPE) { 449 case 0: 450 case 1: 451 ptrptr = PCIR_CAP_PTR; 452 break; 453 case 2: 454 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 455 break; 456 default: 457 return; /* no extended capabilities support */ 458 } 459 nextptr = REG(ptrptr, 1); /* sanity check? */ 460 461 /* 462 * Read capability entries. 463 */ 464 while (nextptr != 0) { 465 /* Sanity check */ 466 if (nextptr > 255) { 467 printf("illegal PCI extended capability offset %d\n", 468 nextptr); 469 return; 470 } 471 /* Find the next entry */ 472 ptr = nextptr; 473 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 474 475 /* Process this entry */ 476 switch (REG(ptr + PCICAP_ID, 1)) { 477 case PCIY_PMG: /* PCI power management */ 478 if (cfg->pp.pp_cap == 0) { 479 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 480 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 481 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 482 if ((nextptr - ptr) > PCIR_POWER_DATA) 483 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 484 } 485 break; 486 case PCIY_MSI: /* PCI MSI */ 487 cfg->msi.msi_location = ptr; 488 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 489 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 490 PCIM_MSICTRL_MMC_MASK)>>1); 491 break; 492 case PCIY_MSIX: /* PCI MSI-X */ 493 cfg->msix.msix_location = ptr; 494 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 495 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 496 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 497 val = REG(ptr + PCIR_MSIX_TABLE, 4); 498 cfg->msix.msix_table_bar = PCIR_BAR(val & 499 PCIM_MSIX_BIR_MASK); 500 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 501 val = REG(ptr + PCIR_MSIX_PBA, 4); 502 cfg->msix.msix_pba_bar = PCIR_BAR(val & 503 PCIM_MSIX_BIR_MASK); 504 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 505 break; 506 case PCIY_VPD: /* PCI Vital Product Data */ 507 cfg->vpd.vpd_reg = ptr; 508 pci_read_vpd(pcib, cfg); 509 break; 510 default: 511 break; 512 } 513 } 514/* REG use carry through to next functions */ 515} 516 517/* 518 * PCI Vital Product Data 519 */ 520static uint32_t 521pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg) 522{ 523#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 524 525 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 526 527 WREG(cfg->vpd.vpd_reg + 2, reg, 2); 528 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) != 0x8000) 529 DELAY(1); /* limit looping */ 530 531 return REG(cfg->vpd.vpd_reg + 4, 4); 532} 533 534#if 0 535static void 536pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 537{ 538 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 539 540 WREG(cfg->vpd.vpd_reg + 4, data, 4); 541 WREG(cfg->vpd.vpd_reg + 2, reg | 0x8000, 2); 542 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) == 0x8000) 543 DELAY(1); /* limit looping */ 544 545 return; 546} 547#endif 548#undef WREG 549 550struct vpd_readstate { 551 device_t pcib; 552 pcicfgregs *cfg; 553 uint32_t val; 554 int bytesinval; 555 int off; 556 uint8_t cksum; 557}; 558 559static uint8_t 560vpd_nextbyte(struct vpd_readstate *vrs) 561{ 562 uint8_t byte; 563 564 if (vrs->bytesinval == 0) { 565 vrs->val = le32toh(pci_read_vpd_reg(vrs->pcib, vrs->cfg, 566 vrs->off)); 567 vrs->off += 4; 568 byte = vrs->val & 0xff; 569 vrs->bytesinval = 3; 570 } else { 571 vrs->val = vrs->val >> 8; 572 byte = vrs->val & 0xff; 573 vrs->bytesinval--; 574 } 575 576 vrs->cksum += byte; 577 return byte; 578} 579 580static void 581pci_read_vpd(device_t pcib, pcicfgregs *cfg) 582{ 583 struct vpd_readstate vrs; 584 int state; 585 int name; 586 int remain; 587 int end; 588 int i; 589 uint8_t byte; 590 int alloc, off; /* alloc/off for RO/W arrays */ 591 int cksumvalid; 592 int dflen; 593 594 /* init vpd reader */ 595 vrs.bytesinval = 0; 596 vrs.off = 0; 597 vrs.pcib = pcib; 598 vrs.cfg = cfg; 599 vrs.cksum = 0; 600 601 state = 0; 602 name = remain = i = 0; /* shut up stupid gcc */ 603 alloc = off = 0; /* shut up stupid gcc */ 604 dflen = 0; /* shut up stupid gcc */ 605 end = 0; 606 cksumvalid = -1; 607 for (; !end;) { 608 byte = vpd_nextbyte(&vrs); 609#if 0 610 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 611 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 612 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 613#endif 614 switch (state) { 615 case 0: /* item name */ 616 if (byte & 0x80) { 617 remain = vpd_nextbyte(&vrs); 618 remain |= vpd_nextbyte(&vrs) << 8; 619 if (remain > (0x7f*4 - vrs.off)) { 620 end = 1; 621 printf( 622 "pci%d:%d:%d: invalid vpd data, remain %#x\n", 623 cfg->bus, cfg->slot, cfg->func, 624 remain); 625 } 626 name = byte & 0x7f; 627 } else { 628 remain = byte & 0x7; 629 name = (byte >> 3) & 0xf; 630 } 631 switch (name) { 632 case 0x2: /* String */ 633 cfg->vpd.vpd_ident = malloc(remain + 1, 634 M_DEVBUF, M_WAITOK); 635 i = 0; 636 state = 1; 637 break; 638 case 0xf: /* End */ 639 end = 1; 640 state = -1; 641 break; 642 case 0x10: /* VPD-R */ 643 alloc = 8; 644 off = 0; 645 cfg->vpd.vpd_ros = malloc(alloc * 646 sizeof *cfg->vpd.vpd_ros, M_DEVBUF, 647 M_WAITOK); 648 state = 2; 649 break; 650 case 0x11: /* VPD-W */ 651 alloc = 8; 652 off = 0; 653 cfg->vpd.vpd_w = malloc(alloc * 654 sizeof *cfg->vpd.vpd_w, M_DEVBUF, 655 M_WAITOK); 656 state = 5; 657 break; 658 default: /* Invalid data, abort */ 659 end = 1; 660 continue; 661 } 662 break; 663 664 case 1: /* Identifier String */ 665 cfg->vpd.vpd_ident[i++] = byte; 666 remain--; 667 if (remain == 0) { 668 cfg->vpd.vpd_ident[i] = '\0'; 669 state = 0; 670 } 671 break; 672 673 case 2: /* VPD-R Keyword Header */ 674 if (off == alloc) { 675 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 676 (alloc *= 2) * sizeof *cfg->vpd.vpd_ros, 677 M_DEVBUF, M_WAITOK); 678 } 679 cfg->vpd.vpd_ros[off].keyword[0] = byte; 680 cfg->vpd.vpd_ros[off].keyword[1] = vpd_nextbyte(&vrs); 681 dflen = vpd_nextbyte(&vrs); 682 if (dflen == 0 && 683 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 684 2) == 0) { 685 /* 686 * if this happens, we can't trust the rest 687 * of the VPD. 688 */ 689 printf("pci%d:%d:%d: bad keyword length: %d\n", 690 cfg->bus, cfg->slot, cfg->func, dflen); 691 cksumvalid = 0; 692 end = 1; 693 break; 694 } else if (dflen == 0) { 695 cfg->vpd.vpd_ros[off].value = malloc(1 * 696 sizeof *cfg->vpd.vpd_ros[off].value, 697 M_DEVBUF, M_WAITOK); 698 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 699 } else 700 cfg->vpd.vpd_ros[off].value = malloc( 701 (dflen + 1) * 702 sizeof *cfg->vpd.vpd_ros[off].value, 703 M_DEVBUF, M_WAITOK); 704 remain -= 3; 705 i = 0; 706 /* keep in sync w/ state 3's transistions */ 707 if (dflen == 0 && remain == 0) 708 state = 0; 709 else if (dflen == 0) 710 state = 2; 711 else 712 state = 3; 713 break; 714 715 case 3: /* VPD-R Keyword Value */ 716 cfg->vpd.vpd_ros[off].value[i++] = byte; 717 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 718 "RV", 2) == 0 && cksumvalid == -1) { 719 if (vrs.cksum == 0) 720 cksumvalid = 1; 721 else { 722 printf( 723 "pci%d:%d:%d: bad VPD cksum, remain %hhu\n", 724 cfg->bus, cfg->slot, cfg->func, 725 vrs.cksum); 726 cksumvalid = 0; 727 end = 1; 728 break; 729 } 730 } 731 dflen--; 732 remain--; 733 /* keep in sync w/ state 2's transistions */ 734 if (dflen == 0) 735 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 736 if (dflen == 0 && remain == 0) { 737 cfg->vpd.vpd_rocnt = off; 738 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 739 off * sizeof *cfg->vpd.vpd_ros, 740 M_DEVBUF, M_WAITOK); 741 state = 0; 742 } else if (dflen == 0) 743 state = 2; 744 break; 745 746 case 4: 747 remain--; 748 if (remain == 0) 749 state = 0; 750 break; 751 752 case 5: /* VPD-W Keyword Header */ 753 if (off == alloc) { 754 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 755 (alloc *= 2) * sizeof *cfg->vpd.vpd_w, 756 M_DEVBUF, M_WAITOK); 757 } 758 cfg->vpd.vpd_w[off].keyword[0] = byte; 759 cfg->vpd.vpd_w[off].keyword[1] = vpd_nextbyte(&vrs); 760 cfg->vpd.vpd_w[off].len = dflen = vpd_nextbyte(&vrs); 761 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 762 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 763 sizeof *cfg->vpd.vpd_w[off].value, 764 M_DEVBUF, M_WAITOK); 765 remain -= 3; 766 i = 0; 767 /* keep in sync w/ state 6's transistions */ 768 if (dflen == 0 && remain == 0) 769 state = 0; 770 else if (dflen == 0) 771 state = 5; 772 else 773 state = 6; 774 break; 775 776 case 6: /* VPD-W Keyword Value */ 777 cfg->vpd.vpd_w[off].value[i++] = byte; 778 dflen--; 779 remain--; 780 /* keep in sync w/ state 5's transistions */ 781 if (dflen == 0) 782 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 783 if (dflen == 0 && remain == 0) { 784 cfg->vpd.vpd_wcnt = off; 785 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 786 off * sizeof *cfg->vpd.vpd_w, 787 M_DEVBUF, M_WAITOK); 788 state = 0; 789 } else if (dflen == 0) 790 state = 5; 791 break; 792 793 default: 794 printf("pci%d:%d:%d: invalid state: %d\n", 795 cfg->bus, cfg->slot, cfg->func, state); 796 end = 1; 797 break; 798 } 799 } 800 801 if (cksumvalid == 0) { 802 /* read-only data bad, clean up */ 803 for (; off; off--) 804 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 805 806 free(cfg->vpd.vpd_ros, M_DEVBUF); 807 cfg->vpd.vpd_ros = NULL; 808 } 809#undef REG 810} 811 812int 813pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 814{ 815 struct pci_devinfo *dinfo = device_get_ivars(child); 816 pcicfgregs *cfg = &dinfo->cfg; 817 818 *identptr = cfg->vpd.vpd_ident; 819 820 if (*identptr == NULL) 821 return ENXIO; 822 823 return 0; 824} 825 826int 827pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 828 const char **vptr) 829{ 830 struct pci_devinfo *dinfo = device_get_ivars(child); 831 pcicfgregs *cfg = &dinfo->cfg; 832 int i; 833 834 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 835 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 836 sizeof cfg->vpd.vpd_ros[i].keyword) == 0) { 837 *vptr = cfg->vpd.vpd_ros[i].value; 838 } 839 840 if (i != cfg->vpd.vpd_rocnt) 841 return 0; 842 843 *vptr = NULL; 844 return ENXIO; 845} 846 847/* 848 * Return the offset in configuration space of the requested extended 849 * capability entry or 0 if the specified capability was not found. 850 */ 851int 852pci_find_extcap_method(device_t dev, device_t child, int capability, 853 int *capreg) 854{ 855 struct pci_devinfo *dinfo = device_get_ivars(child); 856 pcicfgregs *cfg = &dinfo->cfg; 857 u_int32_t status; 858 u_int8_t ptr; 859 860 /* 861 * Check the CAP_LIST bit of the PCI status register first. 862 */ 863 status = pci_read_config(child, PCIR_STATUS, 2); 864 if (!(status & PCIM_STATUS_CAPPRESENT)) 865 return (ENXIO); 866 867 /* 868 * Determine the start pointer of the capabilities list. 869 */ 870 switch (cfg->hdrtype & PCIM_HDRTYPE) { 871 case 0: 872 case 1: 873 ptr = PCIR_CAP_PTR; 874 break; 875 case 2: 876 ptr = PCIR_CAP_PTR_2; 877 break; 878 default: 879 /* XXX: panic? */ 880 return (ENXIO); /* no extended capabilities support */ 881 } 882 ptr = pci_read_config(child, ptr, 1); 883 884 /* 885 * Traverse the capabilities list. 886 */ 887 while (ptr != 0) { 888 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 889 if (capreg != NULL) 890 *capreg = ptr; 891 return (0); 892 } 893 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 894 } 895 896 return (ENOENT); 897} 898 899/* 900 * Support for MSI-X message interrupts. 901 */ 902void 903pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 904{ 905 struct pci_devinfo *dinfo = device_get_ivars(dev); 906 pcicfgregs *cfg = &dinfo->cfg; 907 uint32_t offset; 908 909 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 910 offset = cfg->msix.msix_table_offset + index * 16; 911 bus_write_4(cfg->msix.msix_table_res, offset, address & 0xffffffff); 912 bus_write_4(cfg->msix.msix_table_res, offset + 4, address >> 32); 913 bus_write_4(cfg->msix.msix_table_res, offset + 8, data); 914} 915 916void 917pci_mask_msix(device_t dev, u_int index) 918{ 919 struct pci_devinfo *dinfo = device_get_ivars(dev); 920 pcicfgregs *cfg = &dinfo->cfg; 921 uint32_t offset, val; 922 923 KASSERT(cfg->msix.msix_msgnum > index, ("bogus index")); 924 offset = cfg->msix.msix_table_offset + index * 16 + 12; 925 val = bus_read_4(cfg->msix.msix_table_res, offset); 926 if (!(val & PCIM_MSIX_VCTRL_MASK)) { 927 val |= PCIM_MSIX_VCTRL_MASK; 928 bus_write_4(cfg->msix.msix_table_res, offset, val); 929 } 930} 931 932void 933pci_unmask_msix(device_t dev, u_int index) 934{ 935 struct pci_devinfo *dinfo = device_get_ivars(dev); 936 pcicfgregs *cfg = &dinfo->cfg; 937 uint32_t offset, val; 938 939 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 940 offset = cfg->msix.msix_table_offset + index * 16 + 12; 941 val = bus_read_4(cfg->msix.msix_table_res, offset); 942 if (val & PCIM_MSIX_VCTRL_MASK) { 943 val &= ~PCIM_MSIX_VCTRL_MASK; 944 bus_write_4(cfg->msix.msix_table_res, offset, val); 945 } 946} 947 948int 949pci_pending_msix(device_t dev, u_int index) 950{ 951 struct pci_devinfo *dinfo = device_get_ivars(dev); 952 pcicfgregs *cfg = &dinfo->cfg; 953 uint32_t offset, bit; 954 955 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 956 offset = cfg->msix.msix_pba_offset + (index / 4) * 4; 957 bit = 1 << index % 32; 958 return (bus_read_4(cfg->msix.msix_pba_res, offset) & bit); 959} 960 961static int 962pci_alloc_msix(device_t dev, device_t child, int *count) 963{ 964 struct pci_devinfo *dinfo = device_get_ivars(child); 965 pcicfgregs *cfg = &dinfo->cfg; 966 struct resource_list_entry *rle; 967 int actual, error, i, irq, max; 968 969 /* MSI-X capability present? */ 970 if (cfg->msix.msix_location == 0 || !pci_do_msix) 971 return (ENODEV); 972 973 /* Make sure the appropriate BARs are mapped. */ 974 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 975 cfg->msix.msix_table_bar); 976 if (rle == NULL || rle->res == NULL || 977 !(rman_get_flags(rle->res) & RF_ACTIVE)) 978 return (ENXIO); 979 cfg->msix.msix_table_res = rle->res; 980 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 981 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 982 cfg->msix.msix_pba_bar); 983 if (rle == NULL || rle->res == NULL || 984 !(rman_get_flags(rle->res) & RF_ACTIVE)) 985 return (ENXIO); 986 } 987 cfg->msix.msix_pba_res = rle->res; 988 989 /* Already have allocated messages? */ 990 if (cfg->msix.msix_alloc != 0) 991 return (ENXIO); 992 993 max = min(*count, cfg->msix.msix_msgnum); 994 for (i = 0; i < max; i++) { 995 /* Allocate a message. */ 996 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, i, 997 &irq); 998 if (error) 999 break; 1000 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1001 irq, 1); 1002 } 1003 actual = i; 1004 1005 /* Mask all vectors. */ 1006 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1007 pci_mask_msix(child, i); 1008 1009 /* Update control register to enable MSI-X. */ 1010 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1011 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1012 cfg->msix.msix_ctrl, 2); 1013 1014 /* Update counts of alloc'd messages. */ 1015 cfg->msix.msix_alloc = actual; 1016 *count = actual; 1017 return (0); 1018} 1019 1020static int 1021pci_release_msix(device_t dev, device_t child) 1022{ 1023 struct pci_devinfo *dinfo = device_get_ivars(child); 1024 pcicfgregs *cfg = &dinfo->cfg; 1025 struct resource_list_entry *rle; 1026 int i; 1027 1028 /* Do we have any messages to release? */ 1029 if (cfg->msix.msix_alloc == 0) 1030 return (ENODEV); 1031 1032 /* Make sure none of the resources are allocated. */ 1033 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1034 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1035 KASSERT(rle != NULL, ("missing MSI resource")); 1036 if (rle->res != NULL) 1037 return (EBUSY); 1038 } 1039 1040 /* Update control register with to disable MSI-X. */ 1041 cfg->msix.msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 1042 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1043 cfg->msix.msix_ctrl, 2); 1044 1045 /* Release the messages. */ 1046 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1047 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1048 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1049 rle->start); 1050 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1051 } 1052 1053 /* Update alloc count. */ 1054 cfg->msix.msix_alloc = 0; 1055 return (0); 1056} 1057 1058/* 1059 * Support for MSI message signalled interrupts. 1060 */ 1061void 1062pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 1063{ 1064 struct pci_devinfo *dinfo = device_get_ivars(dev); 1065 pcicfgregs *cfg = &dinfo->cfg; 1066 1067 /* Write data and address values. */ 1068 cfg->msi.msi_addr = address; 1069 cfg->msi.msi_data = data; 1070 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR, 1071 address & 0xffffffff, 4); 1072 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) { 1073 pci_write_config(dev, cfg->msi.msi_location + 1074 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1075 pci_write_config(dev, cfg->msi.msi_location + 1076 PCIR_MSI_DATA_64BIT, data, 2); 1077 } else 1078 pci_write_config(dev, cfg->msi.msi_location + 1079 PCIR_MSI_DATA, data, 2); 1080 1081 /* Enable MSI in the control register. */ 1082 cfg->msi.msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 1083 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL, 1084 cfg->msi.msi_ctrl, 2); 1085} 1086 1087/* 1088 * Restore MSI registers during resume. If MSI is enabled then 1089 * restore the data and address registers in addition to the control 1090 * register. 1091 */ 1092static void 1093pci_resume_msi(device_t dev) 1094{ 1095 struct pci_devinfo *dinfo = device_get_ivars(dev); 1096 pcicfgregs *cfg = &dinfo->cfg; 1097 uint64_t address; 1098 uint16_t data; 1099 1100 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 1101 address = cfg->msi.msi_addr; 1102 data = cfg->msi.msi_data; 1103 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR, 1104 address & 0xffffffff, 4); 1105 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) { 1106 pci_write_config(dev, cfg->msi.msi_location + 1107 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1108 pci_write_config(dev, cfg->msi.msi_location + 1109 PCIR_MSI_DATA_64BIT, data, 2); 1110 } else 1111 pci_write_config(dev, cfg->msi.msi_location + 1112 PCIR_MSI_DATA, data, 2); 1113 } 1114 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL, 1115 cfg->msi.msi_ctrl, 2); 1116} 1117 1118/* 1119 * Attempt to allocate *count MSI messages. The actual number allocated is 1120 * returned in *count. After this function returns, each message will be 1121 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 1122 */ 1123int 1124pci_alloc_msi_method(device_t dev, device_t child, int *count) 1125{ 1126 struct pci_devinfo *dinfo = device_get_ivars(child); 1127 pcicfgregs *cfg = &dinfo->cfg; 1128 struct resource_list_entry *rle; 1129 int actual, error, i, irqs[32]; 1130 uint16_t ctrl; 1131 1132 /* Don't let count == 0 get us into trouble. */ 1133 if (*count == 0) 1134 return (EINVAL); 1135 1136 /* If rid 0 is allocated, then fail. */ 1137 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1138 if (rle != NULL && rle->res != NULL) 1139 return (ENXIO); 1140 1141 /* Try MSI-X first. */ 1142 error = pci_alloc_msix(dev, child, count); 1143 if (error != ENODEV) 1144 return (error); 1145 1146 /* MSI capability present? */ 1147 if (cfg->msi.msi_location == 0 || !pci_do_msi) 1148 return (ENODEV); 1149 1150 /* Already have allocated messages? */ 1151 if (cfg->msi.msi_alloc != 0) 1152 return (ENXIO); 1153 1154 /* Don't ask for more than the device supports. */ 1155 actual = min(*count, cfg->msi.msi_msgnum); 1156 1157 /* Don't ask for more than 32 messages. */ 1158 actual = min(actual, 32); 1159 1160 /* MSI requires power of 2 number of messages. */ 1161 if (!powerof2(actual)) 1162 return (EINVAL); 1163 1164 for (;;) { 1165 /* Try to allocate N messages. */ 1166 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 1167 cfg->msi.msi_msgnum, irqs); 1168 if (error == 0) 1169 break; 1170 if (actual == 1) 1171 return (error); 1172 1173 /* Try N / 2. */ 1174 actual >>= 1; 1175 } 1176 1177 /* 1178 * We now have N actual messages mapped onto SYS_RES_IRQ 1179 * resources in the irqs[] array, so add new resources 1180 * starting at rid 1. 1181 */ 1182 for (i = 0; i < actual; i++) 1183 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 1184 irqs[i], irqs[i], 1); 1185 1186 /* Update control register with actual count and enable MSI. */ 1187 ctrl = cfg->msi.msi_ctrl; 1188 ctrl &= ~PCIM_MSICTRL_MME_MASK; 1189 ctrl |= (ffs(actual) - 1) << 4; 1190 cfg->msi.msi_ctrl = ctrl; 1191 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 1192 1193 /* Update counts of alloc'd messages. */ 1194 cfg->msi.msi_alloc = actual; 1195 *count = actual; 1196 return (0); 1197} 1198 1199/* Release the MSI messages associated with this device. */ 1200int 1201pci_release_msi_method(device_t dev, device_t child) 1202{ 1203 struct pci_devinfo *dinfo = device_get_ivars(child); 1204 pcicfgregs *cfg = &dinfo->cfg; 1205 struct resource_list_entry *rle; 1206 int error, i, irqs[32]; 1207 1208 /* Try MSI-X first. */ 1209 error = pci_release_msix(dev, child); 1210 if (error != ENODEV) 1211 return (error); 1212 1213 /* Do we have any messages to release? */ 1214 if (cfg->msi.msi_alloc == 0) 1215 return (ENODEV); 1216 KASSERT(cfg->msi.msi_alloc <= 32, ("more than 32 alloc'd messages")); 1217 1218 /* Make sure none of the resources are allocated. */ 1219 for (i = 0; i < cfg->msi.msi_alloc; i++) { 1220 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1221 KASSERT(rle != NULL, ("missing MSI resource")); 1222 if (rle->res != NULL) 1223 return (EBUSY); 1224 irqs[i] = rle->start; 1225 } 1226 1227 /* Update control register with 0 count and disable MSI. */ 1228 cfg->msi.msi_ctrl &= ~(PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE); 1229 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 1230 cfg->msi.msi_ctrl, 2); 1231 1232 /* Release the messages. */ 1233 PCIB_RELEASE_MSI(device_get_parent(dev), child, cfg->msi.msi_alloc, 1234 irqs); 1235 for (i = 0; i < cfg->msi.msi_alloc; i++) 1236 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1237 1238 /* Update alloc count. */ 1239 cfg->msi.msi_alloc = 0; 1240 return (0); 1241} 1242 1243/* 1244 * Return the max supported MSI or MSI-X messages this device supports. 1245 * Basically, assuming the MD code can alloc messages, this function 1246 * should return the maximum value that pci_alloc_msi() can return. Thus, 1247 * it is subject to the tunables, etc. 1248 */ 1249int 1250pci_msi_count_method(device_t dev, device_t child) 1251{ 1252 struct pci_devinfo *dinfo = device_get_ivars(child); 1253 pcicfgregs *cfg = &dinfo->cfg; 1254 1255 if (pci_do_msix && cfg->msix.msix_location != 0) 1256 return (cfg->msix.msix_msgnum); 1257 if (pci_do_msi && cfg->msi.msi_location != 0) 1258 return (cfg->msi.msi_msgnum); 1259 return (0); 1260} 1261 1262/* free pcicfgregs structure and all depending data structures */ 1263 1264int 1265pci_freecfg(struct pci_devinfo *dinfo) 1266{ 1267 struct devlist *devlist_head; 1268 int i; 1269 1270 devlist_head = &pci_devq; 1271 1272 if (dinfo->cfg.vpd.vpd_reg) { 1273 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 1274 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 1275 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 1276 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 1277 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 1278 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 1279 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 1280 } 1281 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 1282 free(dinfo, M_DEVBUF); 1283 1284 /* increment the generation count */ 1285 pci_generation++; 1286 1287 /* we're losing one device */ 1288 pci_numdevs--; 1289 return (0); 1290} 1291 1292/* 1293 * PCI power manangement 1294 */ 1295int 1296pci_set_powerstate_method(device_t dev, device_t child, int state) 1297{ 1298 struct pci_devinfo *dinfo = device_get_ivars(child); 1299 pcicfgregs *cfg = &dinfo->cfg; 1300 uint16_t status; 1301 int result, oldstate, highest, delay; 1302 1303 if (cfg->pp.pp_cap == 0) 1304 return (EOPNOTSUPP); 1305 1306 /* 1307 * Optimize a no state change request away. While it would be OK to 1308 * write to the hardware in theory, some devices have shown odd 1309 * behavior when going from D3 -> D3. 1310 */ 1311 oldstate = pci_get_powerstate(child); 1312 if (oldstate == state) 1313 return (0); 1314 1315 /* 1316 * The PCI power management specification states that after a state 1317 * transition between PCI power states, system software must 1318 * guarantee a minimal delay before the function accesses the device. 1319 * Compute the worst case delay that we need to guarantee before we 1320 * access the device. Many devices will be responsive much more 1321 * quickly than this delay, but there are some that don't respond 1322 * instantly to state changes. Transitions to/from D3 state require 1323 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 1324 * is done below with DELAY rather than a sleeper function because 1325 * this function can be called from contexts where we cannot sleep. 1326 */ 1327 highest = (oldstate > state) ? oldstate : state; 1328 if (highest == PCI_POWERSTATE_D3) 1329 delay = 10000; 1330 else if (highest == PCI_POWERSTATE_D2) 1331 delay = 200; 1332 else 1333 delay = 0; 1334 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 1335 & ~PCIM_PSTAT_DMASK; 1336 result = 0; 1337 switch (state) { 1338 case PCI_POWERSTATE_D0: 1339 status |= PCIM_PSTAT_D0; 1340 break; 1341 case PCI_POWERSTATE_D1: 1342 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 1343 return (EOPNOTSUPP); 1344 status |= PCIM_PSTAT_D1; 1345 break; 1346 case PCI_POWERSTATE_D2: 1347 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 1348 return (EOPNOTSUPP); 1349 status |= PCIM_PSTAT_D2; 1350 break; 1351 case PCI_POWERSTATE_D3: 1352 status |= PCIM_PSTAT_D3; 1353 break; 1354 default: 1355 return (EINVAL); 1356 } 1357 1358 if (bootverbose) 1359 printf( 1360 "pci%d:%d:%d: Transition from D%d to D%d\n", 1361 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1362 oldstate, state); 1363 1364 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 1365 if (delay) 1366 DELAY(delay); 1367 return (0); 1368} 1369 1370int 1371pci_get_powerstate_method(device_t dev, device_t child) 1372{ 1373 struct pci_devinfo *dinfo = device_get_ivars(child); 1374 pcicfgregs *cfg = &dinfo->cfg; 1375 uint16_t status; 1376 int result; 1377 1378 if (cfg->pp.pp_cap != 0) { 1379 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 1380 switch (status & PCIM_PSTAT_DMASK) { 1381 case PCIM_PSTAT_D0: 1382 result = PCI_POWERSTATE_D0; 1383 break; 1384 case PCIM_PSTAT_D1: 1385 result = PCI_POWERSTATE_D1; 1386 break; 1387 case PCIM_PSTAT_D2: 1388 result = PCI_POWERSTATE_D2; 1389 break; 1390 case PCIM_PSTAT_D3: 1391 result = PCI_POWERSTATE_D3; 1392 break; 1393 default: 1394 result = PCI_POWERSTATE_UNKNOWN; 1395 break; 1396 } 1397 } else { 1398 /* No support, device is always at D0 */ 1399 result = PCI_POWERSTATE_D0; 1400 } 1401 return (result); 1402} 1403 1404/* 1405 * Some convenience functions for PCI device drivers. 1406 */ 1407 1408static __inline void 1409pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 1410{ 1411 uint16_t command; 1412 1413 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1414 command |= bit; 1415 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1416} 1417 1418static __inline void 1419pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 1420{ 1421 uint16_t command; 1422 1423 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1424 command &= ~bit; 1425 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1426} 1427 1428int 1429pci_enable_busmaster_method(device_t dev, device_t child) 1430{ 1431 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1432 return (0); 1433} 1434 1435int 1436pci_disable_busmaster_method(device_t dev, device_t child) 1437{ 1438 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1439 return (0); 1440} 1441 1442int 1443pci_enable_io_method(device_t dev, device_t child, int space) 1444{ 1445 uint16_t command; 1446 uint16_t bit; 1447 char *error; 1448 1449 bit = 0; 1450 error = NULL; 1451 1452 switch(space) { 1453 case SYS_RES_IOPORT: 1454 bit = PCIM_CMD_PORTEN; 1455 error = "port"; 1456 break; 1457 case SYS_RES_MEMORY: 1458 bit = PCIM_CMD_MEMEN; 1459 error = "memory"; 1460 break; 1461 default: 1462 return (EINVAL); 1463 } 1464 pci_set_command_bit(dev, child, bit); 1465 /* Some devices seem to need a brief stall here, what do to? */ 1466 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1467 if (command & bit) 1468 return (0); 1469 device_printf(child, "failed to enable %s mapping!\n", error); 1470 return (ENXIO); 1471} 1472 1473int 1474pci_disable_io_method(device_t dev, device_t child, int space) 1475{ 1476 uint16_t command; 1477 uint16_t bit; 1478 char *error; 1479 1480 bit = 0; 1481 error = NULL; 1482 1483 switch(space) { 1484 case SYS_RES_IOPORT: 1485 bit = PCIM_CMD_PORTEN; 1486 error = "port"; 1487 break; 1488 case SYS_RES_MEMORY: 1489 bit = PCIM_CMD_MEMEN; 1490 error = "memory"; 1491 break; 1492 default: 1493 return (EINVAL); 1494 } 1495 pci_clear_command_bit(dev, child, bit); 1496 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1497 if (command & bit) { 1498 device_printf(child, "failed to disable %s mapping!\n", error); 1499 return (ENXIO); 1500 } 1501 return (0); 1502} 1503 1504/* 1505 * New style pci driver. Parent device is either a pci-host-bridge or a 1506 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1507 */ 1508 1509void 1510pci_print_verbose(struct pci_devinfo *dinfo) 1511{ 1512 int i; 1513 1514 if (bootverbose) { 1515 pcicfgregs *cfg = &dinfo->cfg; 1516 1517 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1518 cfg->vendor, cfg->device, cfg->revid); 1519 printf("\tbus=%d, slot=%d, func=%d\n", 1520 cfg->bus, cfg->slot, cfg->func); 1521 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1522 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 1523 cfg->mfdev); 1524 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1525 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1526 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1527 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 1528 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1529 if (cfg->intpin > 0) 1530 printf("\tintpin=%c, irq=%d\n", 1531 cfg->intpin +'a' -1, cfg->intline); 1532 if (cfg->pp.pp_cap) { 1533 uint16_t status; 1534 1535 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 1536 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 1537 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 1538 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 1539 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 1540 status & PCIM_PSTAT_DMASK); 1541 } 1542 if (cfg->vpd.vpd_reg) { 1543 printf("\tVPD Ident: %s\n", cfg->vpd.vpd_ident); 1544 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) { 1545 struct vpd_readonly *vrop; 1546 vrop = &cfg->vpd.vpd_ros[i]; 1547 if (strncmp("CP", vrop->keyword, 2) == 0) 1548 printf("\tCP: id %d, BAR%d, off %#x\n", 1549 vrop->value[0], vrop->value[1], 1550 le16toh( 1551 *(uint16_t *)&vrop->value[2])); 1552 else if (strncmp("RV", vrop->keyword, 2) == 0) 1553 printf("\tRV: %#hhx\n", vrop->value[0]); 1554 else 1555 printf("\t%.2s: %s\n", vrop->keyword, 1556 vrop->value); 1557 } 1558 for (i = 0; i < cfg->vpd.vpd_wcnt; i++) { 1559 struct vpd_write *vwp; 1560 vwp = &cfg->vpd.vpd_w[i]; 1561 if (strncmp("RW", vwp->keyword, 2) != 0) 1562 printf("\t%.2s(%#x-%#x): %s\n", 1563 vwp->keyword, vwp->start, 1564 vwp->start + vwp->len, vwp->value); 1565 } 1566 } 1567 if (cfg->msi.msi_location) { 1568 int ctrl; 1569 1570 ctrl = cfg->msi.msi_ctrl; 1571 printf("\tMSI supports %d message%s%s%s\n", 1572 cfg->msi.msi_msgnum, 1573 (cfg->msi.msi_msgnum == 1) ? "" : "s", 1574 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 1575 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 1576 } 1577 if (cfg->msix.msix_location) { 1578 printf("\tMSI-X supports %d message%s ", 1579 cfg->msix.msix_msgnum, 1580 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 1581 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 1582 printf("in map 0x%x\n", 1583 cfg->msix.msix_table_bar); 1584 else 1585 printf("in maps 0x%x and 0x%x\n", 1586 cfg->msix.msix_table_bar, 1587 cfg->msix.msix_pba_bar); 1588 } 1589 } 1590} 1591 1592static int 1593pci_porten(device_t pcib, int b, int s, int f) 1594{ 1595 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1596 & PCIM_CMD_PORTEN) != 0; 1597} 1598 1599static int 1600pci_memen(device_t pcib, int b, int s, int f) 1601{ 1602 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1603 & PCIM_CMD_MEMEN) != 0; 1604} 1605 1606/* 1607 * Add a resource based on a pci map register. Return 1 if the map 1608 * register is a 32bit map register or 2 if it is a 64bit register. 1609 */ 1610static int 1611pci_add_map(device_t pcib, device_t bus, device_t dev, 1612 int b, int s, int f, int reg, struct resource_list *rl, int force, 1613 int prefetch) 1614{ 1615 uint32_t map; 1616 pci_addr_t base; 1617 pci_addr_t start, end, count; 1618 uint8_t ln2size; 1619 uint8_t ln2range; 1620 uint32_t testval; 1621 uint16_t cmd; 1622 int type; 1623 int barlen; 1624 struct resource *res; 1625 1626 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1627 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1628 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1629 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1630 1631 if (pci_maptype(map) & PCI_MAPMEM) 1632 type = SYS_RES_MEMORY; 1633 else 1634 type = SYS_RES_IOPORT; 1635 ln2size = pci_mapsize(testval); 1636 ln2range = pci_maprange(testval); 1637 base = pci_mapbase(map); 1638 barlen = ln2range == 64 ? 2 : 1; 1639 1640 /* 1641 * For I/O registers, if bottom bit is set, and the next bit up 1642 * isn't clear, we know we have a BAR that doesn't conform to the 1643 * spec, so ignore it. Also, sanity check the size of the data 1644 * areas to the type of memory involved. Memory must be at least 1645 * 16 bytes in size, while I/O ranges must be at least 4. 1646 */ 1647 if ((testval & 0x1) == 0x1 && 1648 (testval & 0x2) != 0) 1649 return (barlen); 1650 if ((type == SYS_RES_MEMORY && ln2size < 4) || 1651 (type == SYS_RES_IOPORT && ln2size < 2)) 1652 return (barlen); 1653 1654 if (ln2range == 64) 1655 /* Read the other half of a 64bit map register */ 1656 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 1657 if (bootverbose) { 1658 printf("\tmap[%02x]: type %x, range %2d, base %#jx, size %2d", 1659 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size); 1660 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1661 printf(", port disabled\n"); 1662 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1663 printf(", memory disabled\n"); 1664 else 1665 printf(", enabled\n"); 1666 } 1667 1668 /* 1669 * If base is 0, then we have problems. It is best to ignore 1670 * such entries for the moment. These will be allocated later if 1671 * the driver specifically requests them. However, some 1672 * removable busses look better when all resources are allocated, 1673 * so allow '0' to be overriden. 1674 * 1675 * Similarly treat maps whose values is the same as the test value 1676 * read back. These maps have had all f's written to them by the 1677 * BIOS in an attempt to disable the resources. 1678 */ 1679 if (!force && (base == 0 || map == testval)) 1680 return (barlen); 1681 if ((u_long)base != base) { 1682 device_printf(bus, 1683 "pci%d:%d:%d bar %#x too many address bits", b, s, f, reg); 1684 return (barlen); 1685 } 1686 1687 /* 1688 * This code theoretically does the right thing, but has 1689 * undesirable side effects in some cases where peripherals 1690 * respond oddly to having these bits enabled. Let the user 1691 * be able to turn them off (since pci_enable_io_modes is 1 by 1692 * default). 1693 */ 1694 if (pci_enable_io_modes) { 1695 /* Turn on resources that have been left off by a lazy BIOS */ 1696 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1697 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1698 cmd |= PCIM_CMD_PORTEN; 1699 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1700 } 1701 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1702 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1703 cmd |= PCIM_CMD_MEMEN; 1704 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1705 } 1706 } else { 1707 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1708 return (barlen); 1709 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1710 return (barlen); 1711 } 1712 1713 count = 1 << ln2size; 1714 if (base == 0 || base == pci_mapbase(testval)) { 1715 start = 0; /* Let the parent deside */ 1716 end = ~0ULL; 1717 } else { 1718 start = base; 1719 end = base + (1 << ln2size) - 1; 1720 } 1721 resource_list_add(rl, type, reg, start, end, count); 1722 1723 /* 1724 * Not quite sure what to do on failure of allocating the resource 1725 * since I can postulate several right answers. 1726 */ 1727 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 1728 prefetch ? RF_PREFETCHABLE : 0); 1729 if (res == NULL) 1730 return (barlen); 1731 start = rman_get_start(res); 1732 if ((u_long)start != start) { 1733 /* Wait a minute! this platform can't do this address. */ 1734 device_printf(bus, 1735 "pci%d.%d.%x bar %#x start %#jx, too many bits.", 1736 b, s, f, reg, (uintmax_t)start); 1737 resource_list_release(rl, bus, dev, type, reg, res); 1738 return (barlen); 1739 } 1740 pci_write_config(dev, reg, start, 4); 1741 if (ln2range == 64) 1742 pci_write_config(dev, reg + 4, start >> 32, 4); 1743 return (barlen); 1744} 1745 1746/* 1747 * For ATA devices we need to decide early what addressing mode to use. 1748 * Legacy demands that the primary and secondary ATA ports sits on the 1749 * same addresses that old ISA hardware did. This dictates that we use 1750 * those addresses and ignore the BAR's if we cannot set PCI native 1751 * addressing mode. 1752 */ 1753static void 1754pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 1755 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 1756{ 1757 int rid, type, progif; 1758#if 0 1759 /* if this device supports PCI native addressing use it */ 1760 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1761 if ((progif & 0x8a) == 0x8a) { 1762 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1763 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1764 printf("Trying ATA native PCI addressing mode\n"); 1765 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1766 } 1767 } 1768#endif 1769 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1770 type = SYS_RES_IOPORT; 1771 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1772 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 1773 prefetchmask & (1 << 0)); 1774 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 1775 prefetchmask & (1 << 1)); 1776 } else { 1777 rid = PCIR_BAR(0); 1778 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1779 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1780 0); 1781 rid = PCIR_BAR(1); 1782 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1783 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1784 0); 1785 } 1786 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1787 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 1788 prefetchmask & (1 << 2)); 1789 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 1790 prefetchmask & (1 << 3)); 1791 } else { 1792 rid = PCIR_BAR(2); 1793 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1794 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1795 0); 1796 rid = PCIR_BAR(3); 1797 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1798 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1799 0); 1800 } 1801 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 1802 prefetchmask & (1 << 4)); 1803 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 1804 prefetchmask & (1 << 5)); 1805} 1806 1807static void 1808pci_assign_interrupt(device_t bus, device_t dev, int force_route) 1809{ 1810 struct pci_devinfo *dinfo = device_get_ivars(dev); 1811 pcicfgregs *cfg = &dinfo->cfg; 1812 char tunable_name[64]; 1813 int irq; 1814 1815 /* Has to have an intpin to have an interrupt. */ 1816 if (cfg->intpin == 0) 1817 return; 1818 1819 /* Let the user override the IRQ with a tunable. */ 1820 irq = PCI_INVALID_IRQ; 1821 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 1822 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 1823 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 1824 irq = PCI_INVALID_IRQ; 1825 1826 /* 1827 * If we didn't get an IRQ via the tunable, then we either use the 1828 * IRQ value in the intline register or we ask the bus to route an 1829 * interrupt for us. If force_route is true, then we only use the 1830 * value in the intline register if the bus was unable to assign an 1831 * IRQ. 1832 */ 1833 if (!PCI_INTERRUPT_VALID(irq)) { 1834 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 1835 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 1836 if (!PCI_INTERRUPT_VALID(irq)) 1837 irq = cfg->intline; 1838 } 1839 1840 /* If after all that we don't have an IRQ, just bail. */ 1841 if (!PCI_INTERRUPT_VALID(irq)) 1842 return; 1843 1844 /* Update the config register if it changed. */ 1845 if (irq != cfg->intline) { 1846 cfg->intline = irq; 1847 pci_write_config(dev, PCIR_INTLINE, irq, 1); 1848 } 1849 1850 /* Add this IRQ as rid 0 interrupt resource. */ 1851 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 1852} 1853 1854void 1855pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 1856{ 1857 device_t pcib; 1858 struct pci_devinfo *dinfo = device_get_ivars(dev); 1859 pcicfgregs *cfg = &dinfo->cfg; 1860 struct resource_list *rl = &dinfo->resources; 1861 struct pci_quirk *q; 1862 int b, i, f, s; 1863 1864 pcib = device_get_parent(bus); 1865 1866 b = cfg->bus; 1867 s = cfg->slot; 1868 f = cfg->func; 1869 1870 /* ATA devices needs special map treatment */ 1871 if ((pci_get_class(dev) == PCIC_STORAGE) && 1872 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1873 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1874 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 1875 else 1876 for (i = 0; i < cfg->nummaps;) 1877 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1878 rl, force, prefetchmask & (1 << i)); 1879 1880 /* 1881 * Add additional, quirked resources. 1882 */ 1883 for (q = &pci_quirks[0]; q->devid; q++) { 1884 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1885 && q->type == PCI_QUIRK_MAP_REG) 1886 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 1887 force, 0); 1888 } 1889 1890 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1891#ifdef __PCI_REROUTE_INTERRUPT 1892 /* 1893 * Try to re-route interrupts. Sometimes the BIOS or 1894 * firmware may leave bogus values in these registers. 1895 * If the re-route fails, then just stick with what we 1896 * have. 1897 */ 1898 pci_assign_interrupt(bus, dev, 1); 1899#else 1900 pci_assign_interrupt(bus, dev, 0); 1901#endif 1902 } 1903} 1904 1905void 1906pci_add_children(device_t dev, int busno, size_t dinfo_size) 1907{ 1908#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1909 device_t pcib = device_get_parent(dev); 1910 struct pci_devinfo *dinfo; 1911 int maxslots; 1912 int s, f, pcifunchigh; 1913 uint8_t hdrtype; 1914 1915 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 1916 ("dinfo_size too small")); 1917 maxslots = PCIB_MAXSLOTS(pcib); 1918 for (s = 0; s <= maxslots; s++) { 1919 pcifunchigh = 0; 1920 f = 0; 1921 DELAY(1); 1922 hdrtype = REG(PCIR_HDRTYPE, 1); 1923 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1924 continue; 1925 if (hdrtype & PCIM_MFDEV) 1926 pcifunchigh = PCI_FUNCMAX; 1927 for (f = 0; f <= pcifunchigh; f++) { 1928 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1929 if (dinfo != NULL) { 1930 pci_add_child(dev, dinfo); 1931 } 1932 } 1933 } 1934#undef REG 1935} 1936 1937void 1938pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1939{ 1940 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1941 device_set_ivars(dinfo->cfg.dev, dinfo); 1942 resource_list_init(&dinfo->resources); 1943 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1944 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1945 pci_print_verbose(dinfo); 1946 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 1947} 1948 1949static int 1950pci_probe(device_t dev) 1951{ 1952 1953 device_set_desc(dev, "PCI bus"); 1954 1955 /* Allow other subclasses to override this driver. */ 1956 return (-1000); 1957} 1958 1959static int 1960pci_attach(device_t dev) 1961{ 1962 int busno; 1963 1964 /* 1965 * Since there can be multiple independantly numbered PCI 1966 * busses on systems with multiple PCI domains, we can't use 1967 * the unit number to decide which bus we are probing. We ask 1968 * the parent pcib what our bus number is. 1969 */ 1970 busno = pcib_get_bus(dev); 1971 if (bootverbose) 1972 device_printf(dev, "physical bus=%d\n", busno); 1973 1974 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1975 1976 return (bus_generic_attach(dev)); 1977} 1978 1979int 1980pci_suspend(device_t dev) 1981{ 1982 int dstate, error, i, numdevs; 1983 device_t acpi_dev, child, *devlist; 1984 struct pci_devinfo *dinfo; 1985 1986 /* 1987 * Save the PCI configuration space for each child and set the 1988 * device in the appropriate power state for this sleep state. 1989 */ 1990 acpi_dev = NULL; 1991 if (pci_do_power_resume) 1992 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1993 device_get_children(dev, &devlist, &numdevs); 1994 for (i = 0; i < numdevs; i++) { 1995 child = devlist[i]; 1996 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1997 pci_cfg_save(child, dinfo, 0); 1998 } 1999 2000 /* Suspend devices before potentially powering them down. */ 2001 error = bus_generic_suspend(dev); 2002 if (error) { 2003 free(devlist, M_TEMP); 2004 return (error); 2005 } 2006 2007 /* 2008 * Always set the device to D3. If ACPI suggests a different 2009 * power state, use it instead. If ACPI is not present, the 2010 * firmware is responsible for managing device power. Skip 2011 * children who aren't attached since they are powered down 2012 * separately. Only manage type 0 devices for now. 2013 */ 2014 for (i = 0; acpi_dev && i < numdevs; i++) { 2015 child = devlist[i]; 2016 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2017 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 2018 dstate = PCI_POWERSTATE_D3; 2019 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 2020 pci_set_powerstate(child, dstate); 2021 } 2022 } 2023 free(devlist, M_TEMP); 2024 return (0); 2025} 2026 2027int 2028pci_resume(device_t dev) 2029{ 2030 int i, numdevs; 2031 device_t acpi_dev, child, *devlist; 2032 struct pci_devinfo *dinfo; 2033 2034 /* 2035 * Set each child to D0 and restore its PCI configuration space. 2036 */ 2037 acpi_dev = NULL; 2038 if (pci_do_power_resume) 2039 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2040 device_get_children(dev, &devlist, &numdevs); 2041 for (i = 0; i < numdevs; i++) { 2042 /* 2043 * Notify ACPI we're going to D0 but ignore the result. If 2044 * ACPI is not present, the firmware is responsible for 2045 * managing device power. Only manage type 0 devices for now. 2046 */ 2047 child = devlist[i]; 2048 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2049 if (acpi_dev && device_is_attached(child) && 2050 dinfo->cfg.hdrtype == 0) { 2051 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 2052 pci_set_powerstate(child, PCI_POWERSTATE_D0); 2053 } 2054 2055 /* Now the device is powered up, restore its config space. */ 2056 pci_cfg_restore(child, dinfo); 2057 } 2058 free(devlist, M_TEMP); 2059 return (bus_generic_resume(dev)); 2060} 2061 2062static void 2063pci_load_vendor_data(void) 2064{ 2065 caddr_t vendordata, info; 2066 2067 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 2068 info = preload_search_info(vendordata, MODINFO_ADDR); 2069 pci_vendordata = *(char **)info; 2070 info = preload_search_info(vendordata, MODINFO_SIZE); 2071 pci_vendordata_size = *(size_t *)info; 2072 /* terminate the database */ 2073 pci_vendordata[pci_vendordata_size] = '\n'; 2074 } 2075} 2076 2077void 2078pci_driver_added(device_t dev, driver_t *driver) 2079{ 2080 int numdevs; 2081 device_t *devlist; 2082 device_t child; 2083 struct pci_devinfo *dinfo; 2084 int i; 2085 2086 if (bootverbose) 2087 device_printf(dev, "driver added\n"); 2088 DEVICE_IDENTIFY(driver, dev); 2089 device_get_children(dev, &devlist, &numdevs); 2090 for (i = 0; i < numdevs; i++) { 2091 child = devlist[i]; 2092 if (device_get_state(child) != DS_NOTPRESENT) 2093 continue; 2094 dinfo = device_get_ivars(child); 2095 pci_print_verbose(dinfo); 2096 if (bootverbose) 2097 printf("pci%d:%d:%d: reprobing on driver added\n", 2098 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 2099 pci_cfg_restore(child, dinfo); 2100 if (device_probe_and_attach(child) != 0) 2101 pci_cfg_save(child, dinfo, 1); 2102 } 2103 free(devlist, M_TEMP); 2104} 2105 2106int 2107pci_print_child(device_t dev, device_t child) 2108{ 2109 struct pci_devinfo *dinfo; 2110 struct resource_list *rl; 2111 int retval = 0; 2112 2113 dinfo = device_get_ivars(child); 2114 rl = &dinfo->resources; 2115 2116 retval += bus_print_child_header(dev, child); 2117 2118 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 2119 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 2120 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 2121 if (device_get_flags(dev)) 2122 retval += printf(" flags %#x", device_get_flags(dev)); 2123 2124 retval += printf(" at device %d.%d", pci_get_slot(child), 2125 pci_get_function(child)); 2126 2127 retval += bus_print_child_footer(dev, child); 2128 2129 return (retval); 2130} 2131 2132static struct 2133{ 2134 int class; 2135 int subclass; 2136 char *desc; 2137} pci_nomatch_tab[] = { 2138 {PCIC_OLD, -1, "old"}, 2139 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 2140 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 2141 {PCIC_STORAGE, -1, "mass storage"}, 2142 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 2143 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 2144 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 2145 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 2146 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 2147 {PCIC_NETWORK, -1, "network"}, 2148 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 2149 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 2150 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 2151 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 2152 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 2153 {PCIC_DISPLAY, -1, "display"}, 2154 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 2155 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 2156 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 2157 {PCIC_MULTIMEDIA, -1, "multimedia"}, 2158 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 2159 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 2160 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 2161 {PCIC_MEMORY, -1, "memory"}, 2162 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 2163 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 2164 {PCIC_BRIDGE, -1, "bridge"}, 2165 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 2166 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 2167 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 2168 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 2169 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 2170 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 2171 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 2172 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 2173 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 2174 {PCIC_SIMPLECOMM, -1, "simple comms"}, 2175 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 2176 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 2177 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 2178 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 2179 {PCIC_BASEPERIPH, -1, "base peripheral"}, 2180 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 2181 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 2182 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 2183 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 2184 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 2185 {PCIC_INPUTDEV, -1, "input device"}, 2186 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 2187 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 2188 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 2189 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 2190 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 2191 {PCIC_DOCKING, -1, "docking station"}, 2192 {PCIC_PROCESSOR, -1, "processor"}, 2193 {PCIC_SERIALBUS, -1, "serial bus"}, 2194 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 2195 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 2196 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 2197 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 2198 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 2199 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 2200 {PCIC_WIRELESS, -1, "wireless controller"}, 2201 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 2202 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 2203 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 2204 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 2205 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 2206 {PCIC_SATCOM, -1, "satellite communication"}, 2207 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 2208 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 2209 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 2210 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 2211 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 2212 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 2213 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 2214 {PCIC_DASP, -1, "dasp"}, 2215 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 2216 {0, 0, NULL} 2217}; 2218 2219void 2220pci_probe_nomatch(device_t dev, device_t child) 2221{ 2222 int i; 2223 char *cp, *scp, *device; 2224 2225 /* 2226 * Look for a listing for this device in a loaded device database. 2227 */ 2228 if ((device = pci_describe_device(child)) != NULL) { 2229 device_printf(dev, "<%s>", device); 2230 free(device, M_DEVBUF); 2231 } else { 2232 /* 2233 * Scan the class/subclass descriptions for a general 2234 * description. 2235 */ 2236 cp = "unknown"; 2237 scp = NULL; 2238 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 2239 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 2240 if (pci_nomatch_tab[i].subclass == -1) { 2241 cp = pci_nomatch_tab[i].desc; 2242 } else if (pci_nomatch_tab[i].subclass == 2243 pci_get_subclass(child)) { 2244 scp = pci_nomatch_tab[i].desc; 2245 } 2246 } 2247 } 2248 device_printf(dev, "<%s%s%s>", 2249 cp ? cp : "", 2250 ((cp != NULL) && (scp != NULL)) ? ", " : "", 2251 scp ? scp : ""); 2252 } 2253 printf(" at device %d.%d (no driver attached)\n", 2254 pci_get_slot(child), pci_get_function(child)); 2255 if (pci_do_power_nodriver) 2256 pci_cfg_save(child, 2257 (struct pci_devinfo *) device_get_ivars(child), 1); 2258 return; 2259} 2260 2261/* 2262 * Parse the PCI device database, if loaded, and return a pointer to a 2263 * description of the device. 2264 * 2265 * The database is flat text formatted as follows: 2266 * 2267 * Any line not in a valid format is ignored. 2268 * Lines are terminated with newline '\n' characters. 2269 * 2270 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 2271 * the vendor name. 2272 * 2273 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 2274 * - devices cannot be listed without a corresponding VENDOR line. 2275 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 2276 * another TAB, then the device name. 2277 */ 2278 2279/* 2280 * Assuming (ptr) points to the beginning of a line in the database, 2281 * return the vendor or device and description of the next entry. 2282 * The value of (vendor) or (device) inappropriate for the entry type 2283 * is set to -1. Returns nonzero at the end of the database. 2284 * 2285 * Note that this is slightly unrobust in the face of corrupt data; 2286 * we attempt to safeguard against this by spamming the end of the 2287 * database with a newline when we initialise. 2288 */ 2289static int 2290pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 2291{ 2292 char *cp = *ptr; 2293 int left; 2294 2295 *device = -1; 2296 *vendor = -1; 2297 **desc = '\0'; 2298 for (;;) { 2299 left = pci_vendordata_size - (cp - pci_vendordata); 2300 if (left <= 0) { 2301 *ptr = cp; 2302 return(1); 2303 } 2304 2305 /* vendor entry? */ 2306 if (*cp != '\t' && 2307 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 2308 break; 2309 /* device entry? */ 2310 if (*cp == '\t' && 2311 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 2312 break; 2313 2314 /* skip to next line */ 2315 while (*cp != '\n' && left > 0) { 2316 cp++; 2317 left--; 2318 } 2319 if (*cp == '\n') { 2320 cp++; 2321 left--; 2322 } 2323 } 2324 /* skip to next line */ 2325 while (*cp != '\n' && left > 0) { 2326 cp++; 2327 left--; 2328 } 2329 if (*cp == '\n' && left > 0) 2330 cp++; 2331 *ptr = cp; 2332 return(0); 2333} 2334 2335static char * 2336pci_describe_device(device_t dev) 2337{ 2338 int vendor, device; 2339 char *desc, *vp, *dp, *line; 2340 2341 desc = vp = dp = NULL; 2342 2343 /* 2344 * If we have no vendor data, we can't do anything. 2345 */ 2346 if (pci_vendordata == NULL) 2347 goto out; 2348 2349 /* 2350 * Scan the vendor data looking for this device 2351 */ 2352 line = pci_vendordata; 2353 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 2354 goto out; 2355 for (;;) { 2356 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 2357 goto out; 2358 if (vendor == pci_get_vendor(dev)) 2359 break; 2360 } 2361 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 2362 goto out; 2363 for (;;) { 2364 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 2365 *dp = 0; 2366 break; 2367 } 2368 if (vendor != -1) { 2369 *dp = 0; 2370 break; 2371 } 2372 if (device == pci_get_device(dev)) 2373 break; 2374 } 2375 if (dp[0] == '\0') 2376 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 2377 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 2378 NULL) 2379 sprintf(desc, "%s, %s", vp, dp); 2380 out: 2381 if (vp != NULL) 2382 free(vp, M_DEVBUF); 2383 if (dp != NULL) 2384 free(dp, M_DEVBUF); 2385 return(desc); 2386} 2387 2388int 2389pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 2390{ 2391 struct pci_devinfo *dinfo; 2392 pcicfgregs *cfg; 2393 2394 dinfo = device_get_ivars(child); 2395 cfg = &dinfo->cfg; 2396 2397 switch (which) { 2398 case PCI_IVAR_ETHADDR: 2399 /* 2400 * The generic accessor doesn't deal with failure, so 2401 * we set the return value, then return an error. 2402 */ 2403 *((uint8_t **) result) = NULL; 2404 return (EINVAL); 2405 case PCI_IVAR_SUBVENDOR: 2406 *result = cfg->subvendor; 2407 break; 2408 case PCI_IVAR_SUBDEVICE: 2409 *result = cfg->subdevice; 2410 break; 2411 case PCI_IVAR_VENDOR: 2412 *result = cfg->vendor; 2413 break; 2414 case PCI_IVAR_DEVICE: 2415 *result = cfg->device; 2416 break; 2417 case PCI_IVAR_DEVID: 2418 *result = (cfg->device << 16) | cfg->vendor; 2419 break; 2420 case PCI_IVAR_CLASS: 2421 *result = cfg->baseclass; 2422 break; 2423 case PCI_IVAR_SUBCLASS: 2424 *result = cfg->subclass; 2425 break; 2426 case PCI_IVAR_PROGIF: 2427 *result = cfg->progif; 2428 break; 2429 case PCI_IVAR_REVID: 2430 *result = cfg->revid; 2431 break; 2432 case PCI_IVAR_INTPIN: 2433 *result = cfg->intpin; 2434 break; 2435 case PCI_IVAR_IRQ: 2436 *result = cfg->intline; 2437 break; 2438 case PCI_IVAR_BUS: 2439 *result = cfg->bus; 2440 break; 2441 case PCI_IVAR_SLOT: 2442 *result = cfg->slot; 2443 break; 2444 case PCI_IVAR_FUNCTION: 2445 *result = cfg->func; 2446 break; 2447 case PCI_IVAR_CMDREG: 2448 *result = cfg->cmdreg; 2449 break; 2450 case PCI_IVAR_CACHELNSZ: 2451 *result = cfg->cachelnsz; 2452 break; 2453 case PCI_IVAR_MINGNT: 2454 *result = cfg->mingnt; 2455 break; 2456 case PCI_IVAR_MAXLAT: 2457 *result = cfg->maxlat; 2458 break; 2459 case PCI_IVAR_LATTIMER: 2460 *result = cfg->lattimer; 2461 break; 2462 default: 2463 return (ENOENT); 2464 } 2465 return (0); 2466} 2467 2468int 2469pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 2470{ 2471 struct pci_devinfo *dinfo; 2472 2473 dinfo = device_get_ivars(child); 2474 2475 switch (which) { 2476 case PCI_IVAR_INTPIN: 2477 dinfo->cfg.intpin = value; 2478 return (0); 2479 case PCI_IVAR_ETHADDR: 2480 case PCI_IVAR_SUBVENDOR: 2481 case PCI_IVAR_SUBDEVICE: 2482 case PCI_IVAR_VENDOR: 2483 case PCI_IVAR_DEVICE: 2484 case PCI_IVAR_DEVID: 2485 case PCI_IVAR_CLASS: 2486 case PCI_IVAR_SUBCLASS: 2487 case PCI_IVAR_PROGIF: 2488 case PCI_IVAR_REVID: 2489 case PCI_IVAR_IRQ: 2490 case PCI_IVAR_BUS: 2491 case PCI_IVAR_SLOT: 2492 case PCI_IVAR_FUNCTION: 2493 return (EINVAL); /* disallow for now */ 2494 2495 default: 2496 return (ENOENT); 2497 } 2498} 2499 2500 2501#include "opt_ddb.h" 2502#ifdef DDB 2503#include <ddb/ddb.h> 2504#include <sys/cons.h> 2505 2506/* 2507 * List resources based on pci map registers, used for within ddb 2508 */ 2509 2510DB_SHOW_COMMAND(pciregs, db_pci_dump) 2511{ 2512 struct pci_devinfo *dinfo; 2513 struct devlist *devlist_head; 2514 struct pci_conf *p; 2515 const char *name; 2516 int i, error, none_count; 2517 2518 none_count = 0; 2519 /* get the head of the device queue */ 2520 devlist_head = &pci_devq; 2521 2522 /* 2523 * Go through the list of devices and print out devices 2524 */ 2525 for (error = 0, i = 0, 2526 dinfo = STAILQ_FIRST(devlist_head); 2527 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 2528 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 2529 2530 /* Populate pd_name and pd_unit */ 2531 name = NULL; 2532 if (dinfo->cfg.dev) 2533 name = device_get_name(dinfo->cfg.dev); 2534 2535 p = &dinfo->conf; 2536 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 2537 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 2538 (name && *name) ? name : "none", 2539 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 2540 none_count++, 2541 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 2542 p->pc_sel.pc_func, (p->pc_class << 16) | 2543 (p->pc_subclass << 8) | p->pc_progif, 2544 (p->pc_subdevice << 16) | p->pc_subvendor, 2545 (p->pc_device << 16) | p->pc_vendor, 2546 p->pc_revid, p->pc_hdr); 2547 } 2548} 2549#endif /* DDB */ 2550 2551static struct resource * 2552pci_alloc_map(device_t dev, device_t child, int type, int *rid, 2553 u_long start, u_long end, u_long count, u_int flags) 2554{ 2555 struct pci_devinfo *dinfo = device_get_ivars(child); 2556 struct resource_list *rl = &dinfo->resources; 2557 struct resource_list_entry *rle; 2558 struct resource *res; 2559 pci_addr_t map, testval; 2560 int mapsize; 2561 2562 /* 2563 * Weed out the bogons, and figure out how large the BAR/map 2564 * is. Bars that read back 0 here are bogus and unimplemented. 2565 * Note: atapci in legacy mode are special and handled elsewhere 2566 * in the code. If you have a atapci device in legacy mode and 2567 * it fails here, that other code is broken. 2568 */ 2569 res = NULL; 2570 map = pci_read_config(child, *rid, 4); 2571 pci_write_config(child, *rid, 0xffffffff, 4); 2572 testval = pci_read_config(child, *rid, 4); 2573 if (pci_maprange(testval) == 64) 2574 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32; 2575 if (pci_mapbase(testval) == 0) 2576 goto out; 2577 if (pci_maptype(testval) & PCI_MAPMEM) { 2578 if (type != SYS_RES_MEMORY) { 2579 if (bootverbose) 2580 device_printf(dev, 2581 "child %s requested type %d for rid %#x," 2582 " but the BAR says it is an memio\n", 2583 device_get_nameunit(child), type, *rid); 2584 goto out; 2585 } 2586 } else { 2587 if (type != SYS_RES_IOPORT) { 2588 if (bootverbose) 2589 device_printf(dev, 2590 "child %s requested type %d for rid %#x," 2591 " but the BAR says it is an ioport\n", 2592 device_get_nameunit(child), type, *rid); 2593 goto out; 2594 } 2595 } 2596 /* 2597 * For real BARs, we need to override the size that 2598 * the driver requests, because that's what the BAR 2599 * actually uses and we would otherwise have a 2600 * situation where we might allocate the excess to 2601 * another driver, which won't work. 2602 */ 2603 mapsize = pci_mapsize(testval); 2604 count = 1UL << mapsize; 2605 if (RF_ALIGNMENT(flags) < mapsize) 2606 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 2607 2608 /* 2609 * Allocate enough resource, and then write back the 2610 * appropriate bar for that resource. 2611 */ 2612 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2613 start, end, count, flags); 2614 if (res == NULL) { 2615 device_printf(child, 2616 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 2617 count, *rid, type, start, end); 2618 goto out; 2619 } 2620 resource_list_add(rl, type, *rid, start, end, count); 2621 rle = resource_list_find(rl, type, *rid); 2622 if (rle == NULL) 2623 panic("pci_alloc_map: unexpectedly can't find resource."); 2624 rle->res = res; 2625 rle->start = rman_get_start(res); 2626 rle->end = rman_get_end(res); 2627 rle->count = count; 2628 if (bootverbose) 2629 device_printf(child, 2630 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 2631 count, *rid, type, rman_get_start(res)); 2632 map = rman_get_start(res); 2633out:; 2634 pci_write_config(child, *rid, map, 4); 2635 if (pci_maprange(testval) == 64) 2636 pci_write_config(child, *rid + 4, map >> 32, 4); 2637 return (res); 2638} 2639 2640 2641struct resource * 2642pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2643 u_long start, u_long end, u_long count, u_int flags) 2644{ 2645 struct pci_devinfo *dinfo = device_get_ivars(child); 2646 struct resource_list *rl = &dinfo->resources; 2647 struct resource_list_entry *rle; 2648 pcicfgregs *cfg = &dinfo->cfg; 2649 2650 /* 2651 * Perform lazy resource allocation 2652 */ 2653 if (device_get_parent(child) == dev) { 2654 switch (type) { 2655 case SYS_RES_IRQ: 2656 /* 2657 * Can't alloc legacy interrupt once MSI messages 2658 * have been allocated. 2659 */ 2660 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 2661 cfg->msix.msix_alloc > 0)) 2662 return (NULL); 2663 /* 2664 * If the child device doesn't have an 2665 * interrupt routed and is deserving of an 2666 * interrupt, try to assign it one. 2667 */ 2668 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 2669 (cfg->intpin != 0)) 2670 pci_assign_interrupt(dev, child, 0); 2671 break; 2672 case SYS_RES_IOPORT: 2673 case SYS_RES_MEMORY: 2674 if (*rid < PCIR_BAR(cfg->nummaps)) { 2675 /* 2676 * Enable the I/O mode. We should 2677 * also be assigning resources too 2678 * when none are present. The 2679 * resource_list_alloc kind of sorta does 2680 * this... 2681 */ 2682 if (PCI_ENABLE_IO(dev, child, type)) 2683 return (NULL); 2684 } 2685 rle = resource_list_find(rl, type, *rid); 2686 if (rle == NULL) 2687 return (pci_alloc_map(dev, child, type, rid, 2688 start, end, count, flags)); 2689 break; 2690 } 2691 /* 2692 * If we've already allocated the resource, then 2693 * return it now. But first we may need to activate 2694 * it, since we don't allocate the resource as active 2695 * above. Normally this would be done down in the 2696 * nexus, but since we short-circuit that path we have 2697 * to do its job here. Not sure if we should free the 2698 * resource if it fails to activate. 2699 */ 2700 rle = resource_list_find(rl, type, *rid); 2701 if (rle != NULL && rle->res != NULL) { 2702 if (bootverbose) 2703 device_printf(child, 2704 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 2705 rman_get_size(rle->res), *rid, type, 2706 rman_get_start(rle->res)); 2707 if ((flags & RF_ACTIVE) && 2708 bus_generic_activate_resource(dev, child, type, 2709 *rid, rle->res) != 0) 2710 return NULL; 2711 return (rle->res); 2712 } 2713 } 2714 return (resource_list_alloc(rl, dev, child, type, rid, 2715 start, end, count, flags)); 2716} 2717 2718void 2719pci_delete_resource(device_t dev, device_t child, int type, int rid) 2720{ 2721 struct pci_devinfo *dinfo; 2722 struct resource_list *rl; 2723 struct resource_list_entry *rle; 2724 2725 if (device_get_parent(child) != dev) 2726 return; 2727 2728 dinfo = device_get_ivars(child); 2729 rl = &dinfo->resources; 2730 rle = resource_list_find(rl, type, rid); 2731 if (rle) { 2732 if (rle->res) { 2733 if (rman_get_device(rle->res) != dev || 2734 rman_get_flags(rle->res) & RF_ACTIVE) { 2735 device_printf(dev, "delete_resource: " 2736 "Resource still owned by child, oops. " 2737 "(type=%d, rid=%d, addr=%lx)\n", 2738 rle->type, rle->rid, 2739 rman_get_start(rle->res)); 2740 return; 2741 } 2742 bus_release_resource(dev, type, rid, rle->res); 2743 } 2744 resource_list_delete(rl, type, rid); 2745 } 2746 /* 2747 * Why do we turn off the PCI configuration BAR when we delete a 2748 * resource? -- imp 2749 */ 2750 pci_write_config(child, rid, 0, 4); 2751 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 2752} 2753 2754struct resource_list * 2755pci_get_resource_list (device_t dev, device_t child) 2756{ 2757 struct pci_devinfo *dinfo = device_get_ivars(child); 2758 2759 return (&dinfo->resources); 2760} 2761 2762uint32_t 2763pci_read_config_method(device_t dev, device_t child, int reg, int width) 2764{ 2765 struct pci_devinfo *dinfo = device_get_ivars(child); 2766 pcicfgregs *cfg = &dinfo->cfg; 2767 2768 return (PCIB_READ_CONFIG(device_get_parent(dev), 2769 cfg->bus, cfg->slot, cfg->func, reg, width)); 2770} 2771 2772void 2773pci_write_config_method(device_t dev, device_t child, int reg, 2774 uint32_t val, int width) 2775{ 2776 struct pci_devinfo *dinfo = device_get_ivars(child); 2777 pcicfgregs *cfg = &dinfo->cfg; 2778 2779 PCIB_WRITE_CONFIG(device_get_parent(dev), 2780 cfg->bus, cfg->slot, cfg->func, reg, val, width); 2781} 2782 2783int 2784pci_child_location_str_method(device_t dev, device_t child, char *buf, 2785 size_t buflen) 2786{ 2787 2788 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2789 pci_get_function(child)); 2790 return (0); 2791} 2792 2793int 2794pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 2795 size_t buflen) 2796{ 2797 struct pci_devinfo *dinfo; 2798 pcicfgregs *cfg; 2799 2800 dinfo = device_get_ivars(child); 2801 cfg = &dinfo->cfg; 2802 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2803 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2804 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2805 cfg->progif); 2806 return (0); 2807} 2808 2809int 2810pci_assign_interrupt_method(device_t dev, device_t child) 2811{ 2812 struct pci_devinfo *dinfo = device_get_ivars(child); 2813 pcicfgregs *cfg = &dinfo->cfg; 2814 2815 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2816 cfg->intpin)); 2817} 2818 2819static int 2820pci_modevent(module_t mod, int what, void *arg) 2821{ 2822 static struct cdev *pci_cdev; 2823 2824 switch (what) { 2825 case MOD_LOAD: 2826 STAILQ_INIT(&pci_devq); 2827 pci_generation = 0; 2828 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 2829 "pci"); 2830 pci_load_vendor_data(); 2831 break; 2832 2833 case MOD_UNLOAD: 2834 destroy_dev(pci_cdev); 2835 break; 2836 } 2837 2838 return (0); 2839} 2840 2841void 2842pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 2843{ 2844 int i; 2845 2846 /* 2847 * Only do header type 0 devices. Type 1 devices are bridges, 2848 * which we know need special treatment. Type 2 devices are 2849 * cardbus bridges which also require special treatment. 2850 * Other types are unknown, and we err on the side of safety 2851 * by ignoring them. 2852 */ 2853 if (dinfo->cfg.hdrtype != 0) 2854 return; 2855 2856 /* 2857 * Restore the device to full power mode. We must do this 2858 * before we restore the registers because moving from D3 to 2859 * D0 will cause the chip's BARs and some other registers to 2860 * be reset to some unknown power on reset values. Cut down 2861 * the noise on boot by doing nothing if we are already in 2862 * state D0. 2863 */ 2864 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2865 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2866 } 2867 for (i = 0; i < dinfo->cfg.nummaps; i++) 2868 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2869 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2870 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2871 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2872 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2873 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2874 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2875 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2876 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2877 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2878 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2879 2880 /* 2881 * Restore MSI configuration if it is present. If MSI is enabled, 2882 * then restore the data and addr registers. 2883 */ 2884 if (dinfo->cfg.msi.msi_location != 0) 2885 pci_resume_msi(dev); 2886} 2887 2888void 2889pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2890{ 2891 int i; 2892 uint32_t cls; 2893 int ps; 2894 2895 /* 2896 * Only do header type 0 devices. Type 1 devices are bridges, which 2897 * we know need special treatment. Type 2 devices are cardbus bridges 2898 * which also require special treatment. Other types are unknown, and 2899 * we err on the side of safety by ignoring them. Powering down 2900 * bridges should not be undertaken lightly. 2901 */ 2902 if (dinfo->cfg.hdrtype != 0) 2903 return; 2904 for (i = 0; i < dinfo->cfg.nummaps; i++) 2905 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2906 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2907 2908 /* 2909 * Some drivers apparently write to these registers w/o updating our 2910 * cached copy. No harm happens if we update the copy, so do so here 2911 * so we can restore them. The COMMAND register is modified by the 2912 * bus w/o updating the cache. This should represent the normally 2913 * writable portion of the 'defined' part of type 0 headers. In 2914 * theory we also need to save/restore the PCI capability structures 2915 * we know about, but apart from power we don't know any that are 2916 * writable. 2917 */ 2918 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2919 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2920 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2921 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2922 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2923 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2924 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2925 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2926 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2927 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2928 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2929 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2930 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2931 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2932 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2933 2934 /* 2935 * don't set the state for display devices, base peripherals and 2936 * memory devices since bad things happen when they are powered down. 2937 * We should (a) have drivers that can easily detach and (b) use 2938 * generic drivers for these devices so that some device actually 2939 * attaches. We need to make sure that when we implement (a) we don't 2940 * power the device down on a reattach. 2941 */ 2942 cls = pci_get_class(dev); 2943 if (!setstate) 2944 return; 2945 switch (pci_do_power_nodriver) 2946 { 2947 case 0: /* NO powerdown at all */ 2948 return; 2949 case 1: /* Conservative about what to power down */ 2950 if (cls == PCIC_STORAGE) 2951 return; 2952 /*FALLTHROUGH*/ 2953 case 2: /* Agressive about what to power down */ 2954 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2955 cls == PCIC_BASEPERIPH) 2956 return; 2957 /*FALLTHROUGH*/ 2958 case 3: /* Power down everything */ 2959 break; 2960 } 2961 /* 2962 * PCI spec says we can only go into D3 state from D0 state. 2963 * Transition from D[12] into D0 before going to D3 state. 2964 */ 2965 ps = pci_get_powerstate(dev); 2966 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2967 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2968 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2969 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2970} 2971