pci.c revision 163975
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 163975 2006-11-04 06:56:51Z imp $"); 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/endian.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63#ifdef __HAVE_ACPI 64#include <contrib/dev/acpica/acpi.h> 65#include "acpi_if.h" 66#else 67#define ACPI_PWR_FOR_SLEEP(x, y, z) 68#endif 69 70static uint32_t pci_mapbase(unsigned mapreg); 71static int pci_maptype(unsigned mapreg); 72static int pci_mapsize(unsigned testval); 73static int pci_maprange(unsigned mapreg); 74static void pci_fixancient(pcicfgregs *cfg); 75 76static int pci_porten(device_t pcib, int b, int s, int f); 77static int pci_memen(device_t pcib, int b, int s, int f); 78static void pci_assign_interrupt(device_t bus, device_t dev, 79 int force_route); 80static int pci_add_map(device_t pcib, device_t bus, device_t dev, 81 int b, int s, int f, int reg, 82 struct resource_list *rl, int force, int prefetch); 83static int pci_probe(device_t dev); 84static int pci_attach(device_t dev); 85static void pci_load_vendor_data(void); 86static int pci_describe_parse_line(char **ptr, int *vendor, 87 int *device, char **desc); 88static char *pci_describe_device(device_t dev); 89static int pci_modevent(module_t mod, int what, void *arg); 90static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 91 pcicfgregs *cfg); 92static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 93static uint32_t pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 94 int reg); 95#if 0 96static void pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 97 int reg, uint32_t data); 98#endif 99static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 100 101static device_method_t pci_methods[] = { 102 /* Device interface */ 103 DEVMETHOD(device_probe, pci_probe), 104 DEVMETHOD(device_attach, pci_attach), 105 DEVMETHOD(device_detach, bus_generic_detach), 106 DEVMETHOD(device_shutdown, bus_generic_shutdown), 107 DEVMETHOD(device_suspend, pci_suspend), 108 DEVMETHOD(device_resume, pci_resume), 109 110 /* Bus interface */ 111 DEVMETHOD(bus_print_child, pci_print_child), 112 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 113 DEVMETHOD(bus_read_ivar, pci_read_ivar), 114 DEVMETHOD(bus_write_ivar, pci_write_ivar), 115 DEVMETHOD(bus_driver_added, pci_driver_added), 116 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 117 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 118 119 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 120 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 121 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 122 DEVMETHOD(bus_delete_resource, pci_delete_resource), 123 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 124 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 125 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 126 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 127 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 128 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 129 130 /* PCI interface */ 131 DEVMETHOD(pci_read_config, pci_read_config_method), 132 DEVMETHOD(pci_write_config, pci_write_config_method), 133 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 134 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 135 DEVMETHOD(pci_enable_io, pci_enable_io_method), 136 DEVMETHOD(pci_disable_io, pci_disable_io_method), 137 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 138 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 139 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 140 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 141 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 142 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 143 144 { 0, 0 } 145}; 146 147DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 148 149static devclass_t pci_devclass; 150DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 151MODULE_VERSION(pci, 1); 152 153static char *pci_vendordata; 154static size_t pci_vendordata_size; 155 156 157struct pci_quirk { 158 uint32_t devid; /* Vendor/device of the card */ 159 int type; 160#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 161 int arg1; 162 int arg2; 163}; 164 165struct pci_quirk pci_quirks[] = { 166 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 167 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 168 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 169 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 170 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 171 172 { 0 } 173}; 174 175/* map register information */ 176#define PCI_MAPMEM 0x01 /* memory map */ 177#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 178#define PCI_MAPPORT 0x04 /* port map */ 179 180struct devlist pci_devq; 181uint32_t pci_generation; 182uint32_t pci_numdevs = 0; 183 184/* sysctl vars */ 185SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 186 187static int pci_enable_io_modes = 1; 188TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 189SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 190 &pci_enable_io_modes, 1, 191 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 192enable these bits correctly. We'd like to do this all the time, but there\n\ 193are some peripherals that this causes problems with."); 194 195static int pci_do_power_nodriver = 0; 196TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 197SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 198 &pci_do_power_nodriver, 0, 199 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 200disable. 1 means conservatively place devices into D3 state. 2 means\n\ 201agressively place devices into D3 state. 3 means put absolutely everything\n\ 202in D3 state."); 203 204static int pci_do_power_resume = 1; 205TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 206SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 207 &pci_do_power_resume, 1, 208 "Transition from D3 -> D0 on resume."); 209 210/* Find a device_t by bus/slot/function */ 211 212device_t 213pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 214{ 215 struct pci_devinfo *dinfo; 216 217 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 218 if ((dinfo->cfg.bus == bus) && 219 (dinfo->cfg.slot == slot) && 220 (dinfo->cfg.func == func)) { 221 return (dinfo->cfg.dev); 222 } 223 } 224 225 return (NULL); 226} 227 228/* Find a device_t by vendor/device ID */ 229 230device_t 231pci_find_device(uint16_t vendor, uint16_t device) 232{ 233 struct pci_devinfo *dinfo; 234 235 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 236 if ((dinfo->cfg.vendor == vendor) && 237 (dinfo->cfg.device == device)) { 238 return (dinfo->cfg.dev); 239 } 240 } 241 242 return (NULL); 243} 244 245/* return base address of memory or port map */ 246 247static uint32_t 248pci_mapbase(uint32_t mapreg) 249{ 250 int mask = 0x03; 251 if ((mapreg & 0x01) == 0) 252 mask = 0x0f; 253 return (mapreg & ~mask); 254} 255 256/* return map type of memory or port map */ 257 258static int 259pci_maptype(unsigned mapreg) 260{ 261 static uint8_t maptype[0x10] = { 262 PCI_MAPMEM, PCI_MAPPORT, 263 PCI_MAPMEM, 0, 264 PCI_MAPMEM, PCI_MAPPORT, 265 0, 0, 266 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 267 PCI_MAPMEM|PCI_MAPMEMP, 0, 268 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 269 0, 0, 270 }; 271 272 return maptype[mapreg & 0x0f]; 273} 274 275/* return log2 of map size decoded for memory or port map */ 276 277static int 278pci_mapsize(uint32_t testval) 279{ 280 int ln2size; 281 282 testval = pci_mapbase(testval); 283 ln2size = 0; 284 if (testval != 0) { 285 while ((testval & 1) == 0) 286 { 287 ln2size++; 288 testval >>= 1; 289 } 290 } 291 return (ln2size); 292} 293 294/* return log2 of address range supported by map register */ 295 296static int 297pci_maprange(unsigned mapreg) 298{ 299 int ln2range = 0; 300 switch (mapreg & 0x07) { 301 case 0x00: 302 case 0x01: 303 case 0x05: 304 ln2range = 32; 305 break; 306 case 0x02: 307 ln2range = 20; 308 break; 309 case 0x04: 310 ln2range = 64; 311 break; 312 } 313 return (ln2range); 314} 315 316/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 317 318static void 319pci_fixancient(pcicfgregs *cfg) 320{ 321 if (cfg->hdrtype != 0) 322 return; 323 324 /* PCI to PCI bridges use header type 1 */ 325 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 326 cfg->hdrtype = 1; 327} 328 329/* extract header type specific config data */ 330 331static void 332pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 333{ 334#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 335 switch (cfg->hdrtype) { 336 case 0: 337 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 338 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 339 cfg->nummaps = PCI_MAXMAPS_0; 340 break; 341 case 1: 342 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 343 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 344 cfg->nummaps = PCI_MAXMAPS_1; 345 break; 346 case 2: 347 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 348 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 349 cfg->nummaps = PCI_MAXMAPS_2; 350 break; 351 } 352#undef REG 353} 354 355/* read configuration header into pcicfgregs structure */ 356struct pci_devinfo * 357pci_read_device(device_t pcib, int b, int s, int f, size_t size) 358{ 359#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 360 pcicfgregs *cfg = NULL; 361 struct pci_devinfo *devlist_entry; 362 struct devlist *devlist_head; 363 364 devlist_head = &pci_devq; 365 366 devlist_entry = NULL; 367 368 if (REG(PCIR_DEVVENDOR, 4) != -1) { 369 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 370 if (devlist_entry == NULL) 371 return (NULL); 372 373 cfg = &devlist_entry->cfg; 374 375 cfg->bus = b; 376 cfg->slot = s; 377 cfg->func = f; 378 cfg->vendor = REG(PCIR_VENDOR, 2); 379 cfg->device = REG(PCIR_DEVICE, 2); 380 cfg->cmdreg = REG(PCIR_COMMAND, 2); 381 cfg->statreg = REG(PCIR_STATUS, 2); 382 cfg->baseclass = REG(PCIR_CLASS, 1); 383 cfg->subclass = REG(PCIR_SUBCLASS, 1); 384 cfg->progif = REG(PCIR_PROGIF, 1); 385 cfg->revid = REG(PCIR_REVID, 1); 386 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 387 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 388 cfg->lattimer = REG(PCIR_LATTIMER, 1); 389 cfg->intpin = REG(PCIR_INTPIN, 1); 390 cfg->intline = REG(PCIR_INTLINE, 1); 391 392 cfg->mingnt = REG(PCIR_MINGNT, 1); 393 cfg->maxlat = REG(PCIR_MAXLAT, 1); 394 395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 396 cfg->hdrtype &= ~PCIM_MFDEV; 397 398 pci_fixancient(cfg); 399 pci_hdrtypedata(pcib, b, s, f, cfg); 400 401 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 402 pci_read_extcap(pcib, cfg); 403 404 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 405 406 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 407 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 408 devlist_entry->conf.pc_sel.pc_func = cfg->func; 409 devlist_entry->conf.pc_hdr = cfg->hdrtype; 410 411 devlist_entry->conf.pc_subvendor = cfg->subvendor; 412 devlist_entry->conf.pc_subdevice = cfg->subdevice; 413 devlist_entry->conf.pc_vendor = cfg->vendor; 414 devlist_entry->conf.pc_device = cfg->device; 415 416 devlist_entry->conf.pc_class = cfg->baseclass; 417 devlist_entry->conf.pc_subclass = cfg->subclass; 418 devlist_entry->conf.pc_progif = cfg->progif; 419 devlist_entry->conf.pc_revid = cfg->revid; 420 421 pci_numdevs++; 422 pci_generation++; 423 } 424 return (devlist_entry); 425#undef REG 426} 427 428static void 429pci_read_extcap(device_t pcib, pcicfgregs *cfg) 430{ 431#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 432 int ptr, nextptr, ptrptr; 433 434 switch (cfg->hdrtype & PCIM_HDRTYPE) { 435 case 0: 436 ptrptr = PCIR_CAP_PTR; 437 break; 438 case 2: 439 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 440 break; 441 default: 442 return; /* no extended capabilities support */ 443 } 444 nextptr = REG(ptrptr, 1); /* sanity check? */ 445 446 /* 447 * Read capability entries. 448 */ 449 while (nextptr != 0) { 450 /* Sanity check */ 451 if (nextptr > 255) { 452 printf("illegal PCI extended capability offset %d\n", 453 nextptr); 454 return; 455 } 456 /* Find the next entry */ 457 ptr = nextptr; 458 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 459 460 /* Process this entry */ 461 switch (REG(ptr + PCICAP_ID, 1)) { 462 case PCIY_PMG: /* PCI power management */ 463 if (cfg->pp.pp_cap == 0) { 464 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 465 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 466 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 467 if ((nextptr - ptr) > PCIR_POWER_DATA) 468 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 469 } 470 break; 471 case PCIY_MSI: /* PCI MSI */ 472 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 473 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 474 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 475 else 476 cfg->msi.msi_data = PCIR_MSI_DATA; 477 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 478 PCIM_MSICTRL_MMC_MASK)>>1); 479 break; 480 case PCIY_VPD: /* PCI Vital Product Data */ 481 cfg->vpd.vpd_reg = ptr; 482 pci_read_vpd(pcib, cfg); 483 break; 484 default: 485 break; 486 } 487 } 488/* REG use carry through to next functions */ 489} 490 491/* 492 * PCI Vital Product Data 493 */ 494static uint32_t 495pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg) 496{ 497#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 498 499 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 500 501 WREG(cfg->vpd.vpd_reg + 2, reg, 2); 502 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) != 0x8000) 503 DELAY(1); /* limit looping */ 504 505 return REG(cfg->vpd.vpd_reg + 4, 4); 506} 507 508#if 0 509static void 510pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 511{ 512 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 513 514 WREG(cfg->vpd.vpd_reg + 4, data, 4); 515 WREG(cfg->vpd.vpd_reg + 2, reg | 0x8000, 2); 516 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) == 0x8000) 517 DELAY(1); /* limit looping */ 518 519 return; 520} 521#endif 522#undef WREG 523 524struct vpd_readstate { 525 device_t pcib; 526 pcicfgregs *cfg; 527 uint32_t val; 528 int bytesinval; 529 int off; 530 uint8_t cksum; 531}; 532 533static uint8_t 534vpd_nextbyte(struct vpd_readstate *vrs) 535{ 536 uint8_t byte; 537 538 if (vrs->bytesinval == 0) { 539 vrs->val = le32toh(pci_read_vpd_reg(vrs->pcib, vrs->cfg, 540 vrs->off)); 541 vrs->off += 4; 542 byte = vrs->val & 0xff; 543 vrs->bytesinval = 3; 544 } else { 545 vrs->val = vrs->val >> 8; 546 byte = vrs->val & 0xff; 547 vrs->bytesinval--; 548 } 549 550 vrs->cksum += byte; 551 return byte; 552} 553 554static void 555pci_read_vpd(device_t pcib, pcicfgregs *cfg) 556{ 557 struct vpd_readstate vrs; 558 int state; 559 int name; 560 int remain; 561 int end; 562 int i; 563 uint8_t byte; 564 int alloc, off; /* alloc/off for RO/W arrays */ 565 int cksumvalid; 566 int dflen; 567 568 /* init vpd reader */ 569 vrs.bytesinval = 0; 570 vrs.off = 0; 571 vrs.pcib = pcib; 572 vrs.cfg = cfg; 573 vrs.cksum = 0; 574 575 state = 0; 576 name = remain = i = 0; /* shut up stupid gcc */ 577 alloc = off = 0; /* shut up stupid gcc */ 578 dflen = 0; /* shut up stupid gcc */ 579 end = 0; 580 cksumvalid = -1; 581 for (; !end;) { 582 byte = vpd_nextbyte(&vrs); 583#if 0 584 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 585 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 586 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 587#endif 588 switch (state) { 589 case 0: /* item name */ 590 if (byte & 0x80) { 591 remain = vpd_nextbyte(&vrs); 592 remain |= vpd_nextbyte(&vrs) << 8; 593 if (remain > (0x7f*4 - vrs.off)) { 594 end = 1; 595 printf( 596 "pci%d:%d:%d: invalid vpd data, remain %#x\n", 597 cfg->bus, cfg->slot, cfg->func, 598 remain); 599 } 600 name = byte & 0x7f; 601 } else { 602 remain = byte & 0x7; 603 name = (byte >> 3) & 0xf; 604 } 605 switch (name) { 606 case 0x2: /* String */ 607 cfg->vpd.vpd_ident = malloc(remain + 1, 608 M_DEVBUF, M_WAITOK); 609 i = 0; 610 state = 1; 611 break; 612 case 0xf: /* End */ 613 end = 1; 614 state = -1; 615 break; 616 case 0x10: /* VPD-R */ 617 alloc = 8; 618 off = 0; 619 cfg->vpd.vpd_ros = malloc(alloc * 620 sizeof *cfg->vpd.vpd_ros, M_DEVBUF, 621 M_WAITOK); 622 state = 2; 623 break; 624 case 0x11: /* VPD-W */ 625 alloc = 8; 626 off = 0; 627 cfg->vpd.vpd_w = malloc(alloc * 628 sizeof *cfg->vpd.vpd_w, M_DEVBUF, 629 M_WAITOK); 630 state = 5; 631 break; 632 default: /* XXX - unimplemented */ 633 state = 4; 634 break; 635 } 636 break; 637 638 case 1: /* Identifier String */ 639 cfg->vpd.vpd_ident[i++] = byte; 640 remain--; 641 if (remain == 0) { 642 cfg->vpd.vpd_ident[i] = '\0'; 643 state = 0; 644 } 645 break; 646 647 case 2: /* VPD-R Keyword Header */ 648 if (off == alloc) { 649 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 650 (alloc *= 2) * sizeof *cfg->vpd.vpd_ros, 651 M_DEVBUF, M_WAITOK); 652 } 653 cfg->vpd.vpd_ros[off].keyword[0] = byte; 654 cfg->vpd.vpd_ros[off].keyword[1] = vpd_nextbyte(&vrs); 655 dflen = vpd_nextbyte(&vrs); 656 if (dflen == 0 && 657 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 658 2) == 0) { 659 /* 660 * if this happens, we can't trust the rest 661 * of the VPD. 662 */ 663 printf("pci%d:%d:%d: bad keyword length: %d\n", 664 cfg->bus, cfg->slot, cfg->func, dflen); 665 cksumvalid = 0; 666 end = 1; 667 break; 668 } else if (dflen == 0) { 669 cfg->vpd.vpd_ros[off].value = malloc(1 * 670 sizeof *cfg->vpd.vpd_ros[off].value, 671 M_DEVBUF, M_WAITOK); 672 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 673 } else 674 cfg->vpd.vpd_ros[off].value = malloc( 675 (dflen + 1) * 676 sizeof *cfg->vpd.vpd_ros[off].value, 677 M_DEVBUF, M_WAITOK); 678 remain -= 3; 679 i = 0; 680 /* keep in sync w/ state 3's transistions */ 681 if (dflen == 0 && remain == 0) 682 state = 0; 683 else if (dflen == 0) 684 state = 2; 685 else 686 state = 3; 687 break; 688 689 case 3: /* VPD-R Keyword Value */ 690 cfg->vpd.vpd_ros[off].value[i++] = byte; 691 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 692 "RV", 2) == 0 && cksumvalid == -1) { 693 if (vrs.cksum == 0) 694 cksumvalid = 1; 695 else { 696 printf( 697 "pci%d:%d:%d: bad VPD cksum, remain %hhu\n", 698 cfg->bus, cfg->slot, cfg->func, 699 vrs.cksum); 700 cksumvalid = 0; 701 end = 1; 702 break; 703 } 704 } 705 dflen--; 706 remain--; 707 /* keep in sync w/ state 2's transistions */ 708 if (dflen == 0) 709 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 710 if (dflen == 0 && remain == 0) { 711 cfg->vpd.vpd_rocnt = off; 712 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 713 off * sizeof *cfg->vpd.vpd_ros, 714 M_DEVBUF, M_WAITOK); 715 state = 0; 716 } else if (dflen == 0) 717 state = 2; 718 break; 719 720 case 4: 721 remain--; 722 if (remain == 0) 723 state = 0; 724 break; 725 726 case 5: /* VPD-W Keyword Header */ 727 if (off == alloc) { 728 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 729 (alloc *= 2) * sizeof *cfg->vpd.vpd_w, 730 M_DEVBUF, M_WAITOK); 731 } 732 cfg->vpd.vpd_w[off].keyword[0] = byte; 733 cfg->vpd.vpd_w[off].keyword[1] = vpd_nextbyte(&vrs); 734 cfg->vpd.vpd_w[off].len = dflen = vpd_nextbyte(&vrs); 735 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 736 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 737 sizeof *cfg->vpd.vpd_w[off].value, 738 M_DEVBUF, M_WAITOK); 739 remain -= 3; 740 i = 0; 741 /* keep in sync w/ state 6's transistions */ 742 if (dflen == 0 && remain == 0) 743 state = 0; 744 else if (dflen == 0) 745 state = 5; 746 else 747 state = 6; 748 break; 749 750 case 6: /* VPD-W Keyword Value */ 751 cfg->vpd.vpd_w[off].value[i++] = byte; 752 dflen--; 753 remain--; 754 /* keep in sync w/ state 5's transistions */ 755 if (dflen == 0) 756 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 757 if (dflen == 0 && remain == 0) { 758 cfg->vpd.vpd_wcnt = off; 759 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 760 off * sizeof *cfg->vpd.vpd_w, 761 M_DEVBUF, M_WAITOK); 762 state = 0; 763 } else if (dflen == 0) 764 state = 5; 765 break; 766 767 default: 768 printf("pci%d:%d:%d: invalid state: %d\n", 769 cfg->bus, cfg->slot, cfg->func, state); 770 end = 1; 771 break; 772 } 773 } 774 775 if (cksumvalid == 0) { 776 /* read-only data bad, clean up */ 777 for (; off; off--) 778 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 779 780 free(cfg->vpd.vpd_ros, M_DEVBUF); 781 cfg->vpd.vpd_ros = NULL; 782 } 783#undef REG 784} 785 786int 787pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 788{ 789 struct pci_devinfo *dinfo = device_get_ivars(child); 790 pcicfgregs *cfg = &dinfo->cfg; 791 792 *identptr = cfg->vpd.vpd_ident; 793 794 if (*identptr == NULL) 795 return ENXIO; 796 797 return 0; 798} 799 800int 801pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 802 const char **vptr) 803{ 804 struct pci_devinfo *dinfo = device_get_ivars(child); 805 pcicfgregs *cfg = &dinfo->cfg; 806 int i; 807 808 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 809 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 810 sizeof cfg->vpd.vpd_ros[i].keyword) == 0) { 811 *vptr = cfg->vpd.vpd_ros[i].value; 812 } 813 814 if (i != cfg->vpd.vpd_rocnt) 815 return 0; 816 817 *vptr = NULL; 818 return ENXIO; 819} 820 821/* 822 * Return the offset in configuration space of the requested extended 823 * capability entry or 0 if the specified capability was not found. 824 */ 825int 826pci_find_extcap_method(device_t dev, device_t child, int capability, 827 int *capreg) 828{ 829 struct pci_devinfo *dinfo = device_get_ivars(child); 830 pcicfgregs *cfg = &dinfo->cfg; 831 u_int32_t status; 832 u_int8_t ptr; 833 834 /* 835 * Check the CAP_LIST bit of the PCI status register first. 836 */ 837 status = pci_read_config(child, PCIR_STATUS, 2); 838 if (!(status & PCIM_STATUS_CAPPRESENT)) 839 return (ENXIO); 840 841 /* 842 * Determine the start pointer of the capabilities list. 843 */ 844 switch (cfg->hdrtype & PCIM_HDRTYPE) { 845 case 0: 846 ptr = PCIR_CAP_PTR; 847 break; 848 case 2: 849 ptr = PCIR_CAP_PTR_2; 850 break; 851 default: 852 /* XXX: panic? */ 853 return (ENXIO); /* no extended capabilities support */ 854 } 855 ptr = pci_read_config(child, ptr, 1); 856 857 /* 858 * Traverse the capabilities list. 859 */ 860 while (ptr != 0) { 861 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 862 if (capreg != NULL) 863 *capreg = ptr; 864 return (0); 865 } 866 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 867 } 868 869 return (ENOENT); 870} 871 872/* free pcicfgregs structure and all depending data structures */ 873 874int 875pci_freecfg(struct pci_devinfo *dinfo) 876{ 877 struct devlist *devlist_head; 878 int i; 879 880 devlist_head = &pci_devq; 881 882 if (dinfo->cfg.vpd.vpd_reg) { 883 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 884 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 885 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 886 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 887 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 888 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 889 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 890 } 891 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 892 free(dinfo, M_DEVBUF); 893 894 /* increment the generation count */ 895 pci_generation++; 896 897 /* we're losing one device */ 898 pci_numdevs--; 899 return (0); 900} 901 902/* 903 * PCI power manangement 904 */ 905int 906pci_set_powerstate_method(device_t dev, device_t child, int state) 907{ 908 struct pci_devinfo *dinfo = device_get_ivars(child); 909 pcicfgregs *cfg = &dinfo->cfg; 910 uint16_t status; 911 int result, oldstate, highest, delay; 912 913 if (cfg->pp.pp_cap == 0) 914 return (EOPNOTSUPP); 915 916 /* 917 * Optimize a no state change request away. While it would be OK to 918 * write to the hardware in theory, some devices have shown odd 919 * behavior when going from D3 -> D3. 920 */ 921 oldstate = pci_get_powerstate(child); 922 if (oldstate == state) 923 return (0); 924 925 /* 926 * The PCI power management specification states that after a state 927 * transition between PCI power states, system software must 928 * guarantee a minimal delay before the function accesses the device. 929 * Compute the worst case delay that we need to guarantee before we 930 * access the device. Many devices will be responsive much more 931 * quickly than this delay, but there are some that don't respond 932 * instantly to state changes. Transitions to/from D3 state require 933 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 934 * is done below with DELAY rather than a sleeper function because 935 * this function can be called from contexts where we cannot sleep. 936 */ 937 highest = (oldstate > state) ? oldstate : state; 938 if (highest == PCI_POWERSTATE_D3) 939 delay = 10000; 940 else if (highest == PCI_POWERSTATE_D2) 941 delay = 200; 942 else 943 delay = 0; 944 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 945 & ~PCIM_PSTAT_DMASK; 946 result = 0; 947 switch (state) { 948 case PCI_POWERSTATE_D0: 949 status |= PCIM_PSTAT_D0; 950 break; 951 case PCI_POWERSTATE_D1: 952 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 953 return (EOPNOTSUPP); 954 status |= PCIM_PSTAT_D1; 955 break; 956 case PCI_POWERSTATE_D2: 957 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 958 return (EOPNOTSUPP); 959 status |= PCIM_PSTAT_D2; 960 break; 961 case PCI_POWERSTATE_D3: 962 status |= PCIM_PSTAT_D3; 963 break; 964 default: 965 return (EINVAL); 966 } 967 968 if (bootverbose) 969 printf( 970 "pci%d:%d:%d: Transition from D%d to D%d\n", 971 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 972 oldstate, state); 973 974 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 975 if (delay) 976 DELAY(delay); 977 return (0); 978} 979 980int 981pci_get_powerstate_method(device_t dev, device_t child) 982{ 983 struct pci_devinfo *dinfo = device_get_ivars(child); 984 pcicfgregs *cfg = &dinfo->cfg; 985 uint16_t status; 986 int result; 987 988 if (cfg->pp.pp_cap != 0) { 989 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 990 switch (status & PCIM_PSTAT_DMASK) { 991 case PCIM_PSTAT_D0: 992 result = PCI_POWERSTATE_D0; 993 break; 994 case PCIM_PSTAT_D1: 995 result = PCI_POWERSTATE_D1; 996 break; 997 case PCIM_PSTAT_D2: 998 result = PCI_POWERSTATE_D2; 999 break; 1000 case PCIM_PSTAT_D3: 1001 result = PCI_POWERSTATE_D3; 1002 break; 1003 default: 1004 result = PCI_POWERSTATE_UNKNOWN; 1005 break; 1006 } 1007 } else { 1008 /* No support, device is always at D0 */ 1009 result = PCI_POWERSTATE_D0; 1010 } 1011 return (result); 1012} 1013 1014/* 1015 * Some convenience functions for PCI device drivers. 1016 */ 1017 1018static __inline void 1019pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 1020{ 1021 uint16_t command; 1022 1023 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1024 command |= bit; 1025 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1026} 1027 1028static __inline void 1029pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 1030{ 1031 uint16_t command; 1032 1033 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1034 command &= ~bit; 1035 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1036} 1037 1038int 1039pci_enable_busmaster_method(device_t dev, device_t child) 1040{ 1041 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1042 return (0); 1043} 1044 1045int 1046pci_disable_busmaster_method(device_t dev, device_t child) 1047{ 1048 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1049 return (0); 1050} 1051 1052int 1053pci_enable_io_method(device_t dev, device_t child, int space) 1054{ 1055 uint16_t command; 1056 uint16_t bit; 1057 char *error; 1058 1059 bit = 0; 1060 error = NULL; 1061 1062 switch(space) { 1063 case SYS_RES_IOPORT: 1064 bit = PCIM_CMD_PORTEN; 1065 error = "port"; 1066 break; 1067 case SYS_RES_MEMORY: 1068 bit = PCIM_CMD_MEMEN; 1069 error = "memory"; 1070 break; 1071 default: 1072 return (EINVAL); 1073 } 1074 pci_set_command_bit(dev, child, bit); 1075 /* Some devices seem to need a brief stall here, what do to? */ 1076 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1077 if (command & bit) 1078 return (0); 1079 device_printf(child, "failed to enable %s mapping!\n", error); 1080 return (ENXIO); 1081} 1082 1083int 1084pci_disable_io_method(device_t dev, device_t child, int space) 1085{ 1086 uint16_t command; 1087 uint16_t bit; 1088 char *error; 1089 1090 bit = 0; 1091 error = NULL; 1092 1093 switch(space) { 1094 case SYS_RES_IOPORT: 1095 bit = PCIM_CMD_PORTEN; 1096 error = "port"; 1097 break; 1098 case SYS_RES_MEMORY: 1099 bit = PCIM_CMD_MEMEN; 1100 error = "memory"; 1101 break; 1102 default: 1103 return (EINVAL); 1104 } 1105 pci_clear_command_bit(dev, child, bit); 1106 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1107 if (command & bit) { 1108 device_printf(child, "failed to disable %s mapping!\n", error); 1109 return (ENXIO); 1110 } 1111 return (0); 1112} 1113 1114/* 1115 * New style pci driver. Parent device is either a pci-host-bridge or a 1116 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1117 */ 1118 1119void 1120pci_print_verbose(struct pci_devinfo *dinfo) 1121{ 1122 int i; 1123 1124 if (bootverbose) { 1125 pcicfgregs *cfg = &dinfo->cfg; 1126 1127 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1128 cfg->vendor, cfg->device, cfg->revid); 1129 printf("\tbus=%d, slot=%d, func=%d\n", 1130 cfg->bus, cfg->slot, cfg->func); 1131 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1132 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 1133 cfg->mfdev); 1134 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1135 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1136 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1137 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 1138 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1139 if (cfg->intpin > 0) 1140 printf("\tintpin=%c, irq=%d\n", 1141 cfg->intpin +'a' -1, cfg->intline); 1142 if (cfg->pp.pp_cap) { 1143 uint16_t status; 1144 1145 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 1146 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 1147 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 1148 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 1149 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 1150 status & PCIM_PSTAT_DMASK); 1151 } 1152 if (cfg->vpd.vpd_reg) { 1153 printf("\tVPD Ident: %s\n", cfg->vpd.vpd_ident); 1154 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) { 1155 struct vpd_readonly *vrop; 1156 vrop = &cfg->vpd.vpd_ros[i]; 1157 if (strncmp("CP", vrop->keyword, 2) == 0) 1158 printf("\tCP: id %d, BAR%d, off %#x\n", 1159 vrop->value[0], vrop->value[1], 1160 le16toh( 1161 *(uint16_t *)&vrop->value[2])); 1162 else if (strncmp("RV", vrop->keyword, 2) == 0) 1163 printf("\tRV: %#hhx\n", vrop->value[0]); 1164 else 1165 printf("\t%.2s: %s\n", vrop->keyword, 1166 vrop->value); 1167 } 1168 for (i = 0; i < cfg->vpd.vpd_wcnt; i++) { 1169 struct vpd_write *vwp; 1170 vwp = &cfg->vpd.vpd_w[i]; 1171 if (strncmp("RW", vwp->keyword, 2) != 0) 1172 printf("\t%.2s(%#x-%#x): %s\n", 1173 vwp->keyword, vwp->start, 1174 vwp->start + vwp->len, vwp->value); 1175 } 1176 } 1177 if (cfg->msi.msi_data) { 1178 int ctrl; 1179 1180 ctrl = cfg->msi.msi_ctrl; 1181 printf("\tMSI supports %d message%s%s%s\n", 1182 cfg->msi.msi_msgnum, 1183 (cfg->msi.msi_msgnum == 1) ? "" : "s", 1184 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 1185 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 1186 } 1187 } 1188} 1189 1190static int 1191pci_porten(device_t pcib, int b, int s, int f) 1192{ 1193 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1194 & PCIM_CMD_PORTEN) != 0; 1195} 1196 1197static int 1198pci_memen(device_t pcib, int b, int s, int f) 1199{ 1200 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1201 & PCIM_CMD_MEMEN) != 0; 1202} 1203 1204/* 1205 * Add a resource based on a pci map register. Return 1 if the map 1206 * register is a 32bit map register or 2 if it is a 64bit register. 1207 */ 1208static int 1209pci_add_map(device_t pcib, device_t bus, device_t dev, 1210 int b, int s, int f, int reg, struct resource_list *rl, int force, 1211 int prefetch) 1212{ 1213 uint32_t map; 1214 pci_addr_t base; 1215 pci_addr_t start, end, count; 1216 uint8_t ln2size; 1217 uint8_t ln2range; 1218 uint32_t testval; 1219 uint16_t cmd; 1220 int type; 1221 int barlen; 1222 struct resource *res; 1223 1224 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1225 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1226 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1227 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1228 1229 if (pci_maptype(map) & PCI_MAPMEM) 1230 type = SYS_RES_MEMORY; 1231 else 1232 type = SYS_RES_IOPORT; 1233 ln2size = pci_mapsize(testval); 1234 ln2range = pci_maprange(testval); 1235 base = pci_mapbase(map); 1236 barlen = ln2range == 64 ? 2 : 1; 1237 1238 /* 1239 * For I/O registers, if bottom bit is set, and the next bit up 1240 * isn't clear, we know we have a BAR that doesn't conform to the 1241 * spec, so ignore it. Also, sanity check the size of the data 1242 * areas to the type of memory involved. Memory must be at least 1243 * 16 bytes in size, while I/O ranges must be at least 4. 1244 */ 1245 if ((testval & 0x1) == 0x1 && 1246 (testval & 0x2) != 0) 1247 return (barlen); 1248 if ((type == SYS_RES_MEMORY && ln2size < 4) || 1249 (type == SYS_RES_IOPORT && ln2size < 2)) 1250 return (barlen); 1251 1252 if (ln2range == 64) 1253 /* Read the other half of a 64bit map register */ 1254 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 1255 if (bootverbose) { 1256 printf("\tmap[%02x]: type %x, range %2d, base %#jx, size %2d", 1257 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size); 1258 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1259 printf(", port disabled\n"); 1260 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1261 printf(", memory disabled\n"); 1262 else 1263 printf(", enabled\n"); 1264 } 1265 1266 /* 1267 * If base is 0, then we have problems. It is best to ignore 1268 * such entries for the moment. These will be allocated later if 1269 * the driver specifically requests them. However, some 1270 * removable busses look better when all resources are allocated, 1271 * so allow '0' to be overriden. 1272 * 1273 * Similarly treat maps whose values is the same as the test value 1274 * read back. These maps have had all f's written to them by the 1275 * BIOS in an attempt to disable the resources. 1276 */ 1277 if (!force && (base == 0 || map == testval)) 1278 return (barlen); 1279 if ((u_long)base != base) { 1280 device_printf(bus, 1281 "pci%d:%d:%d bar %#x too many address bits", b, s, f, reg); 1282 return (barlen); 1283 } 1284 /* 1285 * This code theoretically does the right thing, but has 1286 * undesirable side effects in some cases where peripherals 1287 * respond oddly to having these bits enabled. Let the user 1288 * be able to turn them off (since pci_enable_io_modes is 1 by 1289 * default). 1290 */ 1291 if (pci_enable_io_modes) { 1292 /* Turn on resources that have been left off by a lazy BIOS */ 1293 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1294 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1295 cmd |= PCIM_CMD_PORTEN; 1296 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1297 } 1298 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1299 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1300 cmd |= PCIM_CMD_MEMEN; 1301 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1302 } 1303 } else { 1304 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1305 return (barlen); 1306 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1307 return (barlen); 1308 } 1309 1310 count = 1 << ln2size; 1311 if (base == 0 || base == pci_mapbase(testval)) { 1312 start = 0; /* Let the parent deside */ 1313 end = ~0ULL; 1314 } else { 1315 start = base; 1316 end = base + (1 << ln2size) - 1; 1317 } 1318 resource_list_add(rl, type, reg, start, end, count); 1319 1320 /* 1321 * Not quite sure what to do on failure of allocating the resource 1322 * since I can postulate several right answers. 1323 */ 1324 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 1325 prefetch ? RF_PREFETCHABLE : 0); 1326 if (res == NULL) 1327 return (barlen); 1328 start = rman_get_start(res); 1329 if ((u_long)start != start) { 1330 /* Wait a minute! this platform can't do this address. */ 1331 device_printf(bus, 1332 "pci%d.%d.%x bar %#x start %#jx, too many bits.", 1333 b, s, f, reg, (uintmax_t)start); 1334 resource_list_release(rl, bus, dev, type, reg, res); 1335 return (barlen); 1336 } 1337 pci_write_config(dev, reg, start, 4); 1338 if (ln2range == 64) 1339 pci_write_config(dev, reg + 4, start >> 32, 4); 1340 return (barlen); 1341} 1342 1343/* 1344 * For ATA devices we need to decide early what addressing mode to use. 1345 * Legacy demands that the primary and secondary ATA ports sits on the 1346 * same addresses that old ISA hardware did. This dictates that we use 1347 * those addresses and ignore the BAR's if we cannot set PCI native 1348 * addressing mode. 1349 */ 1350static void 1351pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 1352 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 1353{ 1354 int rid, type, progif; 1355#if 0 1356 /* if this device supports PCI native addressing use it */ 1357 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1358 if ((progif & 0x8a) == 0x8a) { 1359 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1360 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1361 printf("Trying ATA native PCI addressing mode\n"); 1362 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1363 } 1364 } 1365#endif 1366 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1367 type = SYS_RES_IOPORT; 1368 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1369 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 1370 prefetchmask & (1 << 0)); 1371 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 1372 prefetchmask & (1 << 1)); 1373 } else { 1374 rid = PCIR_BAR(0); 1375 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1376 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1377 0); 1378 rid = PCIR_BAR(1); 1379 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1380 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1381 0); 1382 } 1383 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1384 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 1385 prefetchmask & (1 << 2)); 1386 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 1387 prefetchmask & (1 << 3)); 1388 } else { 1389 rid = PCIR_BAR(2); 1390 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1391 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1392 0); 1393 rid = PCIR_BAR(3); 1394 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1395 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1396 0); 1397 } 1398 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 1399 prefetchmask & (1 << 4)); 1400 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 1401 prefetchmask & (1 << 5)); 1402} 1403 1404static void 1405pci_assign_interrupt(device_t bus, device_t dev, int force_route) 1406{ 1407 struct pci_devinfo *dinfo = device_get_ivars(dev); 1408 pcicfgregs *cfg = &dinfo->cfg; 1409 char tunable_name[64]; 1410 int irq; 1411 1412 /* Has to have an intpin to have an interrupt. */ 1413 if (cfg->intpin == 0) 1414 return; 1415 1416 /* Let the user override the IRQ with a tunable. */ 1417 irq = PCI_INVALID_IRQ; 1418 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 1419 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 1420 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 1421 irq = PCI_INVALID_IRQ; 1422 1423 /* 1424 * If we didn't get an IRQ via the tunable, then we either use the 1425 * IRQ value in the intline register or we ask the bus to route an 1426 * interrupt for us. If force_route is true, then we only use the 1427 * value in the intline register if the bus was unable to assign an 1428 * IRQ. 1429 */ 1430 if (!PCI_INTERRUPT_VALID(irq)) { 1431 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 1432 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 1433 if (!PCI_INTERRUPT_VALID(irq)) 1434 irq = cfg->intline; 1435 } 1436 1437 /* If after all that we don't have an IRQ, just bail. */ 1438 if (!PCI_INTERRUPT_VALID(irq)) 1439 return; 1440 1441 /* Update the config register if it changed. */ 1442 if (irq != cfg->intline) { 1443 cfg->intline = irq; 1444 pci_write_config(dev, PCIR_INTLINE, irq, 1); 1445 } 1446 1447 /* Add this IRQ as rid 0 interrupt resource. */ 1448 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 1449} 1450 1451void 1452pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 1453{ 1454 device_t pcib; 1455 struct pci_devinfo *dinfo = device_get_ivars(dev); 1456 pcicfgregs *cfg = &dinfo->cfg; 1457 struct resource_list *rl = &dinfo->resources; 1458 struct pci_quirk *q; 1459 int b, i, f, s; 1460 1461 pcib = device_get_parent(bus); 1462 1463 b = cfg->bus; 1464 s = cfg->slot; 1465 f = cfg->func; 1466 1467 /* ATA devices needs special map treatment */ 1468 if ((pci_get_class(dev) == PCIC_STORAGE) && 1469 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1470 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1471 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 1472 else 1473 for (i = 0; i < cfg->nummaps;) 1474 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1475 rl, force, prefetchmask & (1 << i)); 1476 1477 /* 1478 * Add additional, quirked resources. 1479 */ 1480 for (q = &pci_quirks[0]; q->devid; q++) { 1481 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1482 && q->type == PCI_QUIRK_MAP_REG) 1483 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 1484 force, 0); 1485 } 1486 1487 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1488#ifdef __PCI_REROUTE_INTERRUPT 1489 /* 1490 * Try to re-route interrupts. Sometimes the BIOS or 1491 * firmware may leave bogus values in these registers. 1492 * If the re-route fails, then just stick with what we 1493 * have. 1494 */ 1495 pci_assign_interrupt(bus, dev, 1); 1496#else 1497 pci_assign_interrupt(bus, dev, 0); 1498#endif 1499 } 1500} 1501 1502void 1503pci_add_children(device_t dev, int busno, size_t dinfo_size) 1504{ 1505#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1506 device_t pcib = device_get_parent(dev); 1507 struct pci_devinfo *dinfo; 1508 int maxslots; 1509 int s, f, pcifunchigh; 1510 uint8_t hdrtype; 1511 1512 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 1513 ("dinfo_size too small")); 1514 maxslots = PCIB_MAXSLOTS(pcib); 1515 for (s = 0; s <= maxslots; s++) { 1516 pcifunchigh = 0; 1517 f = 0; 1518 DELAY(1); 1519 hdrtype = REG(PCIR_HDRTYPE, 1); 1520 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1521 continue; 1522 if (hdrtype & PCIM_MFDEV) 1523 pcifunchigh = PCI_FUNCMAX; 1524 for (f = 0; f <= pcifunchigh; f++) { 1525 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1526 if (dinfo != NULL) { 1527 pci_add_child(dev, dinfo); 1528 } 1529 } 1530 } 1531#undef REG 1532} 1533 1534void 1535pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1536{ 1537 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1538 device_set_ivars(dinfo->cfg.dev, dinfo); 1539 resource_list_init(&dinfo->resources); 1540 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1541 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1542 pci_print_verbose(dinfo); 1543 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 1544} 1545 1546static int 1547pci_probe(device_t dev) 1548{ 1549 1550 device_set_desc(dev, "PCI bus"); 1551 1552 /* Allow other subclasses to override this driver. */ 1553 return (-1000); 1554} 1555 1556static int 1557pci_attach(device_t dev) 1558{ 1559 int busno; 1560 1561 /* 1562 * Since there can be multiple independantly numbered PCI 1563 * busses on systems with multiple PCI domains, we can't use 1564 * the unit number to decide which bus we are probing. We ask 1565 * the parent pcib what our bus number is. 1566 */ 1567 busno = pcib_get_bus(dev); 1568 if (bootverbose) 1569 device_printf(dev, "physical bus=%d\n", busno); 1570 1571 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1572 1573 return (bus_generic_attach(dev)); 1574} 1575 1576int 1577pci_suspend(device_t dev) 1578{ 1579 int dstate, error, i, numdevs; 1580 device_t acpi_dev, child, *devlist; 1581 struct pci_devinfo *dinfo; 1582 1583 /* 1584 * Save the PCI configuration space for each child and set the 1585 * device in the appropriate power state for this sleep state. 1586 */ 1587 acpi_dev = NULL; 1588 if (pci_do_power_resume) 1589 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1590 device_get_children(dev, &devlist, &numdevs); 1591 for (i = 0; i < numdevs; i++) { 1592 child = devlist[i]; 1593 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1594 pci_cfg_save(child, dinfo, 0); 1595 } 1596 1597 /* Suspend devices before potentially powering them down. */ 1598 error = bus_generic_suspend(dev); 1599 if (error) { 1600 free(devlist, M_TEMP); 1601 return (error); 1602 } 1603 1604 /* 1605 * Always set the device to D3. If ACPI suggests a different 1606 * power state, use it instead. If ACPI is not present, the 1607 * firmware is responsible for managing device power. Skip 1608 * children who aren't attached since they are powered down 1609 * separately. Only manage type 0 devices for now. 1610 */ 1611 for (i = 0; acpi_dev && i < numdevs; i++) { 1612 child = devlist[i]; 1613 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1614 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1615 dstate = PCI_POWERSTATE_D3; 1616 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1617 pci_set_powerstate(child, dstate); 1618 } 1619 } 1620 free(devlist, M_TEMP); 1621 return (0); 1622} 1623 1624int 1625pci_resume(device_t dev) 1626{ 1627 int i, numdevs; 1628 device_t acpi_dev, child, *devlist; 1629 struct pci_devinfo *dinfo; 1630 1631 /* 1632 * Set each child to D0 and restore its PCI configuration space. 1633 */ 1634 acpi_dev = NULL; 1635 if (pci_do_power_resume) 1636 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1637 device_get_children(dev, &devlist, &numdevs); 1638 for (i = 0; i < numdevs; i++) { 1639 /* 1640 * Notify ACPI we're going to D0 but ignore the result. If 1641 * ACPI is not present, the firmware is responsible for 1642 * managing device power. Only manage type 0 devices for now. 1643 */ 1644 child = devlist[i]; 1645 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1646 if (acpi_dev && device_is_attached(child) && 1647 dinfo->cfg.hdrtype == 0) { 1648 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1649 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1650 } 1651 1652 /* Now the device is powered up, restore its config space. */ 1653 pci_cfg_restore(child, dinfo); 1654 } 1655 free(devlist, M_TEMP); 1656 return (bus_generic_resume(dev)); 1657} 1658 1659static void 1660pci_load_vendor_data(void) 1661{ 1662 caddr_t vendordata, info; 1663 1664 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1665 info = preload_search_info(vendordata, MODINFO_ADDR); 1666 pci_vendordata = *(char **)info; 1667 info = preload_search_info(vendordata, MODINFO_SIZE); 1668 pci_vendordata_size = *(size_t *)info; 1669 /* terminate the database */ 1670 pci_vendordata[pci_vendordata_size] = '\n'; 1671 } 1672} 1673 1674void 1675pci_driver_added(device_t dev, driver_t *driver) 1676{ 1677 int numdevs; 1678 device_t *devlist; 1679 device_t child; 1680 struct pci_devinfo *dinfo; 1681 int i; 1682 1683 if (bootverbose) 1684 device_printf(dev, "driver added\n"); 1685 DEVICE_IDENTIFY(driver, dev); 1686 device_get_children(dev, &devlist, &numdevs); 1687 for (i = 0; i < numdevs; i++) { 1688 child = devlist[i]; 1689 if (device_get_state(child) != DS_NOTPRESENT) 1690 continue; 1691 dinfo = device_get_ivars(child); 1692 pci_print_verbose(dinfo); 1693 if (bootverbose) 1694 printf("pci%d:%d:%d: reprobing on driver added\n", 1695 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1696 pci_cfg_restore(child, dinfo); 1697 if (device_probe_and_attach(child) != 0) 1698 pci_cfg_save(child, dinfo, 1); 1699 } 1700 free(devlist, M_TEMP); 1701} 1702 1703int 1704pci_print_child(device_t dev, device_t child) 1705{ 1706 struct pci_devinfo *dinfo; 1707 struct resource_list *rl; 1708 int retval = 0; 1709 1710 dinfo = device_get_ivars(child); 1711 rl = &dinfo->resources; 1712 1713 retval += bus_print_child_header(dev, child); 1714 1715 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1716 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1717 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1718 if (device_get_flags(dev)) 1719 retval += printf(" flags %#x", device_get_flags(dev)); 1720 1721 retval += printf(" at device %d.%d", pci_get_slot(child), 1722 pci_get_function(child)); 1723 1724 retval += bus_print_child_footer(dev, child); 1725 1726 return (retval); 1727} 1728 1729static struct 1730{ 1731 int class; 1732 int subclass; 1733 char *desc; 1734} pci_nomatch_tab[] = { 1735 {PCIC_OLD, -1, "old"}, 1736 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1737 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1738 {PCIC_STORAGE, -1, "mass storage"}, 1739 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1740 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1741 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1742 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1743 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1744 {PCIC_NETWORK, -1, "network"}, 1745 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1746 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1747 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1748 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1749 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1750 {PCIC_DISPLAY, -1, "display"}, 1751 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1752 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1753 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1754 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1755 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1756 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1757 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1758 {PCIC_MEMORY, -1, "memory"}, 1759 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1760 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1761 {PCIC_BRIDGE, -1, "bridge"}, 1762 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1763 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1764 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1765 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1766 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1767 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1768 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1769 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1770 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1771 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1772 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1773 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1774 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1775 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1776 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1777 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1778 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1779 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1780 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1781 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1782 {PCIC_INPUTDEV, -1, "input device"}, 1783 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1784 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1785 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1786 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1787 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1788 {PCIC_DOCKING, -1, "docking station"}, 1789 {PCIC_PROCESSOR, -1, "processor"}, 1790 {PCIC_SERIALBUS, -1, "serial bus"}, 1791 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1792 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1793 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1794 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1795 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1796 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1797 {PCIC_WIRELESS, -1, "wireless controller"}, 1798 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1799 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1800 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1801 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1802 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1803 {PCIC_SATCOM, -1, "satellite communication"}, 1804 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1805 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1806 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1807 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1808 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1809 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1810 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 1811 {PCIC_DASP, -1, "dasp"}, 1812 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1813 {0, 0, NULL} 1814}; 1815 1816void 1817pci_probe_nomatch(device_t dev, device_t child) 1818{ 1819 int i; 1820 char *cp, *scp, *device; 1821 1822 /* 1823 * Look for a listing for this device in a loaded device database. 1824 */ 1825 if ((device = pci_describe_device(child)) != NULL) { 1826 device_printf(dev, "<%s>", device); 1827 free(device, M_DEVBUF); 1828 } else { 1829 /* 1830 * Scan the class/subclass descriptions for a general 1831 * description. 1832 */ 1833 cp = "unknown"; 1834 scp = NULL; 1835 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1836 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1837 if (pci_nomatch_tab[i].subclass == -1) { 1838 cp = pci_nomatch_tab[i].desc; 1839 } else if (pci_nomatch_tab[i].subclass == 1840 pci_get_subclass(child)) { 1841 scp = pci_nomatch_tab[i].desc; 1842 } 1843 } 1844 } 1845 device_printf(dev, "<%s%s%s>", 1846 cp ? cp : "", 1847 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1848 scp ? scp : ""); 1849 } 1850 printf(" at device %d.%d (no driver attached)\n", 1851 pci_get_slot(child), pci_get_function(child)); 1852 if (pci_do_power_nodriver) 1853 pci_cfg_save(child, 1854 (struct pci_devinfo *) device_get_ivars(child), 1); 1855 return; 1856} 1857 1858/* 1859 * Parse the PCI device database, if loaded, and return a pointer to a 1860 * description of the device. 1861 * 1862 * The database is flat text formatted as follows: 1863 * 1864 * Any line not in a valid format is ignored. 1865 * Lines are terminated with newline '\n' characters. 1866 * 1867 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1868 * the vendor name. 1869 * 1870 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1871 * - devices cannot be listed without a corresponding VENDOR line. 1872 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1873 * another TAB, then the device name. 1874 */ 1875 1876/* 1877 * Assuming (ptr) points to the beginning of a line in the database, 1878 * return the vendor or device and description of the next entry. 1879 * The value of (vendor) or (device) inappropriate for the entry type 1880 * is set to -1. Returns nonzero at the end of the database. 1881 * 1882 * Note that this is slightly unrobust in the face of corrupt data; 1883 * we attempt to safeguard against this by spamming the end of the 1884 * database with a newline when we initialise. 1885 */ 1886static int 1887pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1888{ 1889 char *cp = *ptr; 1890 int left; 1891 1892 *device = -1; 1893 *vendor = -1; 1894 **desc = '\0'; 1895 for (;;) { 1896 left = pci_vendordata_size - (cp - pci_vendordata); 1897 if (left <= 0) { 1898 *ptr = cp; 1899 return(1); 1900 } 1901 1902 /* vendor entry? */ 1903 if (*cp != '\t' && 1904 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1905 break; 1906 /* device entry? */ 1907 if (*cp == '\t' && 1908 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1909 break; 1910 1911 /* skip to next line */ 1912 while (*cp != '\n' && left > 0) { 1913 cp++; 1914 left--; 1915 } 1916 if (*cp == '\n') { 1917 cp++; 1918 left--; 1919 } 1920 } 1921 /* skip to next line */ 1922 while (*cp != '\n' && left > 0) { 1923 cp++; 1924 left--; 1925 } 1926 if (*cp == '\n' && left > 0) 1927 cp++; 1928 *ptr = cp; 1929 return(0); 1930} 1931 1932static char * 1933pci_describe_device(device_t dev) 1934{ 1935 int vendor, device; 1936 char *desc, *vp, *dp, *line; 1937 1938 desc = vp = dp = NULL; 1939 1940 /* 1941 * If we have no vendor data, we can't do anything. 1942 */ 1943 if (pci_vendordata == NULL) 1944 goto out; 1945 1946 /* 1947 * Scan the vendor data looking for this device 1948 */ 1949 line = pci_vendordata; 1950 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1951 goto out; 1952 for (;;) { 1953 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1954 goto out; 1955 if (vendor == pci_get_vendor(dev)) 1956 break; 1957 } 1958 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1959 goto out; 1960 for (;;) { 1961 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1962 *dp = 0; 1963 break; 1964 } 1965 if (vendor != -1) { 1966 *dp = 0; 1967 break; 1968 } 1969 if (device == pci_get_device(dev)) 1970 break; 1971 } 1972 if (dp[0] == '\0') 1973 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1974 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1975 NULL) 1976 sprintf(desc, "%s, %s", vp, dp); 1977 out: 1978 if (vp != NULL) 1979 free(vp, M_DEVBUF); 1980 if (dp != NULL) 1981 free(dp, M_DEVBUF); 1982 return(desc); 1983} 1984 1985int 1986pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1987{ 1988 struct pci_devinfo *dinfo; 1989 pcicfgregs *cfg; 1990 1991 dinfo = device_get_ivars(child); 1992 cfg = &dinfo->cfg; 1993 1994 switch (which) { 1995 case PCI_IVAR_ETHADDR: 1996 /* 1997 * The generic accessor doesn't deal with failure, so 1998 * we set the return value, then return an error. 1999 */ 2000 *((uint8_t **) result) = NULL; 2001 return (EINVAL); 2002 case PCI_IVAR_SUBVENDOR: 2003 *result = cfg->subvendor; 2004 break; 2005 case PCI_IVAR_SUBDEVICE: 2006 *result = cfg->subdevice; 2007 break; 2008 case PCI_IVAR_VENDOR: 2009 *result = cfg->vendor; 2010 break; 2011 case PCI_IVAR_DEVICE: 2012 *result = cfg->device; 2013 break; 2014 case PCI_IVAR_DEVID: 2015 *result = (cfg->device << 16) | cfg->vendor; 2016 break; 2017 case PCI_IVAR_CLASS: 2018 *result = cfg->baseclass; 2019 break; 2020 case PCI_IVAR_SUBCLASS: 2021 *result = cfg->subclass; 2022 break; 2023 case PCI_IVAR_PROGIF: 2024 *result = cfg->progif; 2025 break; 2026 case PCI_IVAR_REVID: 2027 *result = cfg->revid; 2028 break; 2029 case PCI_IVAR_INTPIN: 2030 *result = cfg->intpin; 2031 break; 2032 case PCI_IVAR_IRQ: 2033 *result = cfg->intline; 2034 break; 2035 case PCI_IVAR_BUS: 2036 *result = cfg->bus; 2037 break; 2038 case PCI_IVAR_SLOT: 2039 *result = cfg->slot; 2040 break; 2041 case PCI_IVAR_FUNCTION: 2042 *result = cfg->func; 2043 break; 2044 case PCI_IVAR_CMDREG: 2045 *result = cfg->cmdreg; 2046 break; 2047 case PCI_IVAR_CACHELNSZ: 2048 *result = cfg->cachelnsz; 2049 break; 2050 case PCI_IVAR_MINGNT: 2051 *result = cfg->mingnt; 2052 break; 2053 case PCI_IVAR_MAXLAT: 2054 *result = cfg->maxlat; 2055 break; 2056 case PCI_IVAR_LATTIMER: 2057 *result = cfg->lattimer; 2058 break; 2059 default: 2060 return (ENOENT); 2061 } 2062 return (0); 2063} 2064 2065int 2066pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 2067{ 2068 struct pci_devinfo *dinfo; 2069 2070 dinfo = device_get_ivars(child); 2071 2072 switch (which) { 2073 case PCI_IVAR_INTPIN: 2074 dinfo->cfg.intpin = value; 2075 return (0); 2076 case PCI_IVAR_ETHADDR: 2077 case PCI_IVAR_SUBVENDOR: 2078 case PCI_IVAR_SUBDEVICE: 2079 case PCI_IVAR_VENDOR: 2080 case PCI_IVAR_DEVICE: 2081 case PCI_IVAR_DEVID: 2082 case PCI_IVAR_CLASS: 2083 case PCI_IVAR_SUBCLASS: 2084 case PCI_IVAR_PROGIF: 2085 case PCI_IVAR_REVID: 2086 case PCI_IVAR_IRQ: 2087 case PCI_IVAR_BUS: 2088 case PCI_IVAR_SLOT: 2089 case PCI_IVAR_FUNCTION: 2090 return (EINVAL); /* disallow for now */ 2091 2092 default: 2093 return (ENOENT); 2094 } 2095} 2096 2097 2098#include "opt_ddb.h" 2099#ifdef DDB 2100#include <ddb/ddb.h> 2101#include <sys/cons.h> 2102 2103/* 2104 * List resources based on pci map registers, used for within ddb 2105 */ 2106 2107DB_SHOW_COMMAND(pciregs, db_pci_dump) 2108{ 2109 struct pci_devinfo *dinfo; 2110 struct devlist *devlist_head; 2111 struct pci_conf *p; 2112 const char *name; 2113 int i, error, none_count; 2114 2115 none_count = 0; 2116 /* get the head of the device queue */ 2117 devlist_head = &pci_devq; 2118 2119 /* 2120 * Go through the list of devices and print out devices 2121 */ 2122 for (error = 0, i = 0, 2123 dinfo = STAILQ_FIRST(devlist_head); 2124 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 2125 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 2126 2127 /* Populate pd_name and pd_unit */ 2128 name = NULL; 2129 if (dinfo->cfg.dev) 2130 name = device_get_name(dinfo->cfg.dev); 2131 2132 p = &dinfo->conf; 2133 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 2134 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 2135 (name && *name) ? name : "none", 2136 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 2137 none_count++, 2138 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 2139 p->pc_sel.pc_func, (p->pc_class << 16) | 2140 (p->pc_subclass << 8) | p->pc_progif, 2141 (p->pc_subdevice << 16) | p->pc_subvendor, 2142 (p->pc_device << 16) | p->pc_vendor, 2143 p->pc_revid, p->pc_hdr); 2144 } 2145} 2146#endif /* DDB */ 2147 2148static struct resource * 2149pci_alloc_map(device_t dev, device_t child, int type, int *rid, 2150 u_long start, u_long end, u_long count, u_int flags) 2151{ 2152 struct pci_devinfo *dinfo = device_get_ivars(child); 2153 struct resource_list *rl = &dinfo->resources; 2154 struct resource_list_entry *rle; 2155 struct resource *res; 2156 pci_addr_t map, testval; 2157 int mapsize; 2158 2159 /* 2160 * Weed out the bogons, and figure out how large the BAR/map 2161 * is. Bars that read back 0 here are bogus and unimplemented. 2162 * Note: atapci in legacy mode are special and handled elsewhere 2163 * in the code. If you have a atapci device in legacy mode and 2164 * it fails here, that other code is broken. 2165 */ 2166 res = NULL; 2167 map = pci_read_config(child, *rid, 4); 2168 pci_write_config(child, *rid, 0xffffffff, 4); 2169 testval = pci_read_config(child, *rid, 4); 2170 if (pci_maprange(testval) == 64) 2171 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32; 2172 if (pci_mapbase(testval) == 0) 2173 goto out; 2174 if (pci_maptype(testval) & PCI_MAPMEM) { 2175 if (type != SYS_RES_MEMORY) { 2176 if (bootverbose) 2177 device_printf(dev, 2178 "child %s requested type %d for rid %#x," 2179 " but the BAR says it is an memio\n", 2180 device_get_nameunit(child), type, *rid); 2181 goto out; 2182 } 2183 } else { 2184 if (type != SYS_RES_IOPORT) { 2185 if (bootverbose) 2186 device_printf(dev, 2187 "child %s requested type %d for rid %#x," 2188 " but the BAR says it is an ioport\n", 2189 device_get_nameunit(child), type, *rid); 2190 goto out; 2191 } 2192 } 2193 /* 2194 * For real BARs, we need to override the size that 2195 * the driver requests, because that's what the BAR 2196 * actually uses and we would otherwise have a 2197 * situation where we might allocate the excess to 2198 * another driver, which won't work. 2199 */ 2200 mapsize = pci_mapsize(testval); 2201 count = 1UL << mapsize; 2202 if (RF_ALIGNMENT(flags) < mapsize) 2203 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 2204 2205 /* 2206 * Allocate enough resource, and then write back the 2207 * appropriate bar for that resource. 2208 */ 2209 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2210 start, end, count, flags); 2211 if (res == NULL) { 2212 device_printf(child, 2213 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 2214 count, *rid, type, start, end); 2215 goto out; 2216 } 2217 resource_list_add(rl, type, *rid, start, end, count); 2218 rle = resource_list_find(rl, type, *rid); 2219 if (rle == NULL) 2220 panic("pci_alloc_map: unexpectedly can't find resource."); 2221 rle->res = res; 2222 rle->start = rman_get_start(res); 2223 rle->end = rman_get_end(res); 2224 rle->count = count; 2225 if (bootverbose) 2226 device_printf(child, 2227 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 2228 count, *rid, type, rman_get_start(res)); 2229 map = rman_get_start(res); 2230out:; 2231 pci_write_config(child, *rid, map, 4); 2232 if (pci_maprange(testval) == 64) 2233 pci_write_config(child, *rid + 4, map >> 32, 4); 2234 return (res); 2235} 2236 2237 2238struct resource * 2239pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2240 u_long start, u_long end, u_long count, u_int flags) 2241{ 2242 struct pci_devinfo *dinfo = device_get_ivars(child); 2243 struct resource_list *rl = &dinfo->resources; 2244 struct resource_list_entry *rle; 2245 pcicfgregs *cfg = &dinfo->cfg; 2246 2247 /* 2248 * Perform lazy resource allocation 2249 */ 2250 if (device_get_parent(child) == dev) { 2251 switch (type) { 2252 case SYS_RES_IRQ: 2253 /* 2254 * If the child device doesn't have an 2255 * interrupt routed and is deserving of an 2256 * interrupt, try to assign it one. 2257 */ 2258 if (!PCI_INTERRUPT_VALID(cfg->intline) && 2259 (cfg->intpin != 0)) 2260 pci_assign_interrupt(dev, child, 0); 2261 break; 2262 case SYS_RES_IOPORT: 2263 case SYS_RES_MEMORY: 2264 if (*rid < PCIR_BAR(cfg->nummaps)) { 2265 /* 2266 * Enable the I/O mode. We should 2267 * also be assigning resources too 2268 * when none are present. The 2269 * resource_list_alloc kind of sorta does 2270 * this... 2271 */ 2272 if (PCI_ENABLE_IO(dev, child, type)) 2273 return (NULL); 2274 } 2275 rle = resource_list_find(rl, type, *rid); 2276 if (rle == NULL) 2277 return (pci_alloc_map(dev, child, type, rid, 2278 start, end, count, flags)); 2279 break; 2280 } 2281 /* 2282 * If we've already allocated the resource, then 2283 * return it now. But first we may need to activate 2284 * it, since we don't allocate the resource as active 2285 * above. Normally this would be done down in the 2286 * nexus, but since we short-circuit that path we have 2287 * to do its job here. Not sure if we should free the 2288 * resource if it fails to activate. 2289 */ 2290 rle = resource_list_find(rl, type, *rid); 2291 if (rle != NULL && rle->res != NULL) { 2292 if (bootverbose) 2293 device_printf(child, 2294 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 2295 rman_get_size(rle->res), *rid, type, 2296 rman_get_start(rle->res)); 2297 if ((flags & RF_ACTIVE) && 2298 bus_generic_activate_resource(dev, child, type, 2299 *rid, rle->res) != 0) 2300 return NULL; 2301 return (rle->res); 2302 } 2303 } 2304 return (resource_list_alloc(rl, dev, child, type, rid, 2305 start, end, count, flags)); 2306} 2307 2308void 2309pci_delete_resource(device_t dev, device_t child, int type, int rid) 2310{ 2311 struct pci_devinfo *dinfo; 2312 struct resource_list *rl; 2313 struct resource_list_entry *rle; 2314 2315 if (device_get_parent(child) != dev) 2316 return; 2317 2318 dinfo = device_get_ivars(child); 2319 rl = &dinfo->resources; 2320 rle = resource_list_find(rl, type, rid); 2321 if (rle) { 2322 if (rle->res) { 2323 if (rman_get_device(rle->res) != dev || 2324 rman_get_flags(rle->res) & RF_ACTIVE) { 2325 device_printf(dev, "delete_resource: " 2326 "Resource still owned by child, oops. " 2327 "(type=%d, rid=%d, addr=%lx)\n", 2328 rle->type, rle->rid, 2329 rman_get_start(rle->res)); 2330 return; 2331 } 2332 bus_release_resource(dev, type, rid, rle->res); 2333 } 2334 resource_list_delete(rl, type, rid); 2335 } 2336 /* 2337 * Why do we turn off the PCI configuration BAR when we delete a 2338 * resource? -- imp 2339 */ 2340 pci_write_config(child, rid, 0, 4); 2341 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 2342} 2343 2344struct resource_list * 2345pci_get_resource_list (device_t dev, device_t child) 2346{ 2347 struct pci_devinfo *dinfo = device_get_ivars(child); 2348 2349 return (&dinfo->resources); 2350} 2351 2352uint32_t 2353pci_read_config_method(device_t dev, device_t child, int reg, int width) 2354{ 2355 struct pci_devinfo *dinfo = device_get_ivars(child); 2356 pcicfgregs *cfg = &dinfo->cfg; 2357 2358 return (PCIB_READ_CONFIG(device_get_parent(dev), 2359 cfg->bus, cfg->slot, cfg->func, reg, width)); 2360} 2361 2362void 2363pci_write_config_method(device_t dev, device_t child, int reg, 2364 uint32_t val, int width) 2365{ 2366 struct pci_devinfo *dinfo = device_get_ivars(child); 2367 pcicfgregs *cfg = &dinfo->cfg; 2368 2369 PCIB_WRITE_CONFIG(device_get_parent(dev), 2370 cfg->bus, cfg->slot, cfg->func, reg, val, width); 2371} 2372 2373int 2374pci_child_location_str_method(device_t dev, device_t child, char *buf, 2375 size_t buflen) 2376{ 2377 2378 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2379 pci_get_function(child)); 2380 return (0); 2381} 2382 2383int 2384pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 2385 size_t buflen) 2386{ 2387 struct pci_devinfo *dinfo; 2388 pcicfgregs *cfg; 2389 2390 dinfo = device_get_ivars(child); 2391 cfg = &dinfo->cfg; 2392 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2393 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2394 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2395 cfg->progif); 2396 return (0); 2397} 2398 2399int 2400pci_assign_interrupt_method(device_t dev, device_t child) 2401{ 2402 struct pci_devinfo *dinfo = device_get_ivars(child); 2403 pcicfgregs *cfg = &dinfo->cfg; 2404 2405 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2406 cfg->intpin)); 2407} 2408 2409static int 2410pci_modevent(module_t mod, int what, void *arg) 2411{ 2412 static struct cdev *pci_cdev; 2413 2414 switch (what) { 2415 case MOD_LOAD: 2416 STAILQ_INIT(&pci_devq); 2417 pci_generation = 0; 2418 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 2419 "pci"); 2420 pci_load_vendor_data(); 2421 break; 2422 2423 case MOD_UNLOAD: 2424 destroy_dev(pci_cdev); 2425 break; 2426 } 2427 2428 return (0); 2429} 2430 2431void 2432pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 2433{ 2434 int i; 2435 2436 /* 2437 * Only do header type 0 devices. Type 1 devices are bridges, 2438 * which we know need special treatment. Type 2 devices are 2439 * cardbus bridges which also require special treatment. 2440 * Other types are unknown, and we err on the side of safety 2441 * by ignoring them. 2442 */ 2443 if (dinfo->cfg.hdrtype != 0) 2444 return; 2445 2446 /* 2447 * Restore the device to full power mode. We must do this 2448 * before we restore the registers because moving from D3 to 2449 * D0 will cause the chip's BARs and some other registers to 2450 * be reset to some unknown power on reset values. Cut down 2451 * the noise on boot by doing nothing if we are already in 2452 * state D0. 2453 */ 2454 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2455 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2456 } 2457 for (i = 0; i < dinfo->cfg.nummaps; i++) 2458 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2459 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2460 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2461 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2462 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2463 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2464 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2465 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2466 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2467 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2468 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2469} 2470 2471void 2472pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2473{ 2474 int i; 2475 uint32_t cls; 2476 int ps; 2477 2478 /* 2479 * Only do header type 0 devices. Type 1 devices are bridges, which 2480 * we know need special treatment. Type 2 devices are cardbus bridges 2481 * which also require special treatment. Other types are unknown, and 2482 * we err on the side of safety by ignoring them. Powering down 2483 * bridges should not be undertaken lightly. 2484 */ 2485 if (dinfo->cfg.hdrtype != 0) 2486 return; 2487 for (i = 0; i < dinfo->cfg.nummaps; i++) 2488 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2489 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2490 2491 /* 2492 * Some drivers apparently write to these registers w/o updating our 2493 * cached copy. No harm happens if we update the copy, so do so here 2494 * so we can restore them. The COMMAND register is modified by the 2495 * bus w/o updating the cache. This should represent the normally 2496 * writable portion of the 'defined' part of type 0 headers. In 2497 * theory we also need to save/restore the PCI capability structures 2498 * we know about, but apart from power we don't know any that are 2499 * writable. 2500 */ 2501 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2502 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2503 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2504 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2505 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2506 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2507 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2508 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2509 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2510 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2511 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2512 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2513 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2514 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2515 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2516 2517 /* 2518 * don't set the state for display devices, base peripherals and 2519 * memory devices since bad things happen when they are powered down. 2520 * We should (a) have drivers that can easily detach and (b) use 2521 * generic drivers for these devices so that some device actually 2522 * attaches. We need to make sure that when we implement (a) we don't 2523 * power the device down on a reattach. 2524 */ 2525 cls = pci_get_class(dev); 2526 if (!setstate) 2527 return; 2528 switch (pci_do_power_nodriver) 2529 { 2530 case 0: /* NO powerdown at all */ 2531 return; 2532 case 1: /* Conservative about what to power down */ 2533 if (cls == PCIC_STORAGE) 2534 return; 2535 /*FALLTHROUGH*/ 2536 case 2: /* Agressive about what to power down */ 2537 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2538 cls == PCIC_BASEPERIPH) 2539 return; 2540 /*FALLTHROUGH*/ 2541 case 3: /* Power down everything */ 2542 break; 2543 } 2544 /* 2545 * PCI spec says we can only go into D3 state from D0 state. 2546 * Transition from D[12] into D0 before going to D3 state. 2547 */ 2548 ps = pci_get_powerstate(dev); 2549 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2550 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2551 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2552 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2553} 2554