pci.c revision 153898
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 153898 2005-12-30 19:28:26Z imp $"); 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63#if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65#include <contrib/dev/acpica/acpi.h> 66#include "acpi_if.h" 67#else 68#define ACPI_PWR_FOR_SLEEP(x, y, z) 69#endif 70 71static uint32_t pci_mapbase(unsigned mapreg); 72static int pci_maptype(unsigned mapreg); 73static int pci_mapsize(unsigned testval); 74static int pci_maprange(unsigned mapreg); 75static void pci_fixancient(pcicfgregs *cfg); 76 77static int pci_porten(device_t pcib, int b, int s, int f); 78static int pci_memen(device_t pcib, int b, int s, int f); 79static void pci_assign_interrupt(device_t bus, device_t dev, 80 int force_route); 81static int pci_add_map(device_t pcib, device_t bus, device_t dev, 82 int b, int s, int f, int reg, 83 struct resource_list *rl, int force, int prefetch); 84static int pci_probe(device_t dev); 85static int pci_attach(device_t dev); 86static void pci_load_vendor_data(void); 87static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89static char *pci_describe_device(device_t dev); 90static int pci_modevent(module_t mod, int what, void *arg); 91static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 95static device_method_t pci_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pci_probe), 98 DEVMETHOD(device_attach, pci_attach), 99 DEVMETHOD(device_detach, bus_generic_detach), 100 DEVMETHOD(device_shutdown, bus_generic_shutdown), 101 DEVMETHOD(device_suspend, pci_suspend), 102 DEVMETHOD(device_resume, pci_resume), 103 104 /* Bus interface */ 105 DEVMETHOD(bus_print_child, pci_print_child), 106 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 107 DEVMETHOD(bus_read_ivar, pci_read_ivar), 108 DEVMETHOD(bus_write_ivar, pci_write_ivar), 109 DEVMETHOD(bus_driver_added, pci_driver_added), 110 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 111 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 112 113 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 114 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 115 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 116 DEVMETHOD(bus_delete_resource, pci_delete_resource), 117 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 118 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 119 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 120 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 121 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 122 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 123 124 /* PCI interface */ 125 DEVMETHOD(pci_read_config, pci_read_config_method), 126 DEVMETHOD(pci_write_config, pci_write_config_method), 127 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 128 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 129 DEVMETHOD(pci_enable_io, pci_enable_io_method), 130 DEVMETHOD(pci_disable_io, pci_disable_io_method), 131 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 132 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 133 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 134 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 135 136 { 0, 0 } 137}; 138 139DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 140 141devclass_t pci_devclass; 142DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 143MODULE_VERSION(pci, 1); 144 145static char *pci_vendordata; 146static size_t pci_vendordata_size; 147 148 149struct pci_quirk { 150 uint32_t devid; /* Vendor/device of the card */ 151 int type; 152#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 153 int arg1; 154 int arg2; 155}; 156 157struct pci_quirk pci_quirks[] = { 158 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 159 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 160 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 161 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 162 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 163 164 { 0 } 165}; 166 167/* map register information */ 168#define PCI_MAPMEM 0x01 /* memory map */ 169#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 170#define PCI_MAPPORT 0x04 /* port map */ 171 172struct devlist pci_devq; 173uint32_t pci_generation; 174uint32_t pci_numdevs = 0; 175 176/* sysctl vars */ 177SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 178 179static int pci_enable_io_modes = 1; 180TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 181SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 182 &pci_enable_io_modes, 1, 183 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 184enable these bits correctly. We'd like to do this all the time, but there\n\ 185are some peripherals that this causes problems with."); 186 187static int pci_do_power_nodriver = 0; 188TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 189SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 190 &pci_do_power_nodriver, 0, 191 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 192disable. 1 means conservatively place devices into D3 state. 2 means\n\ 193agressively place devices into D3 state. 3 means put absolutely everything\n\ 194in D3 state."); 195 196static int pci_do_power_resume = 1; 197TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 198SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 199 &pci_do_power_resume, 1, 200 "Transition from D3 -> D0 on resume."); 201 202/* Find a device_t by bus/slot/function */ 203 204device_t 205pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 206{ 207 struct pci_devinfo *dinfo; 208 209 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 210 if ((dinfo->cfg.bus == bus) && 211 (dinfo->cfg.slot == slot) && 212 (dinfo->cfg.func == func)) { 213 return (dinfo->cfg.dev); 214 } 215 } 216 217 return (NULL); 218} 219 220/* Find a device_t by vendor/device ID */ 221 222device_t 223pci_find_device(uint16_t vendor, uint16_t device) 224{ 225 struct pci_devinfo *dinfo; 226 227 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 228 if ((dinfo->cfg.vendor == vendor) && 229 (dinfo->cfg.device == device)) { 230 return (dinfo->cfg.dev); 231 } 232 } 233 234 return (NULL); 235} 236 237/* return base address of memory or port map */ 238 239static uint32_t 240pci_mapbase(unsigned mapreg) 241{ 242 int mask = 0x03; 243 if ((mapreg & 0x01) == 0) 244 mask = 0x0f; 245 return (mapreg & ~mask); 246} 247 248/* return map type of memory or port map */ 249 250static int 251pci_maptype(unsigned mapreg) 252{ 253 static uint8_t maptype[0x10] = { 254 PCI_MAPMEM, PCI_MAPPORT, 255 PCI_MAPMEM, 0, 256 PCI_MAPMEM, PCI_MAPPORT, 257 0, 0, 258 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 259 PCI_MAPMEM|PCI_MAPMEMP, 0, 260 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 261 0, 0, 262 }; 263 264 return maptype[mapreg & 0x0f]; 265} 266 267/* return log2 of map size decoded for memory or port map */ 268 269static int 270pci_mapsize(unsigned testval) 271{ 272 int ln2size; 273 274 testval = pci_mapbase(testval); 275 ln2size = 0; 276 if (testval != 0) { 277 while ((testval & 1) == 0) 278 { 279 ln2size++; 280 testval >>= 1; 281 } 282 } 283 return (ln2size); 284} 285 286/* return log2 of address range supported by map register */ 287 288static int 289pci_maprange(unsigned mapreg) 290{ 291 int ln2range = 0; 292 switch (mapreg & 0x07) { 293 case 0x00: 294 case 0x01: 295 case 0x05: 296 ln2range = 32; 297 break; 298 case 0x02: 299 ln2range = 20; 300 break; 301 case 0x04: 302 ln2range = 64; 303 break; 304 } 305 return (ln2range); 306} 307 308/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 309 310static void 311pci_fixancient(pcicfgregs *cfg) 312{ 313 if (cfg->hdrtype != 0) 314 return; 315 316 /* PCI to PCI bridges use header type 1 */ 317 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 318 cfg->hdrtype = 1; 319} 320 321/* extract header type specific config data */ 322 323static void 324pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 325{ 326#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 327 switch (cfg->hdrtype) { 328 case 0: 329 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 330 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 331 cfg->nummaps = PCI_MAXMAPS_0; 332 break; 333 case 1: 334 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 335 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 336 cfg->nummaps = PCI_MAXMAPS_1; 337 break; 338 case 2: 339 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 340 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 341 cfg->nummaps = PCI_MAXMAPS_2; 342 break; 343 } 344#undef REG 345} 346 347/* read configuration header into pcicfgregs structure */ 348 349struct pci_devinfo * 350pci_read_device(device_t pcib, int b, int s, int f, size_t size) 351{ 352#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 353 pcicfgregs *cfg = NULL; 354 struct pci_devinfo *devlist_entry; 355 struct devlist *devlist_head; 356 357 devlist_head = &pci_devq; 358 359 devlist_entry = NULL; 360 361 if (REG(PCIR_DEVVENDOR, 4) != -1) { 362 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 363 if (devlist_entry == NULL) 364 return (NULL); 365 366 cfg = &devlist_entry->cfg; 367 368 cfg->bus = b; 369 cfg->slot = s; 370 cfg->func = f; 371 cfg->vendor = REG(PCIR_VENDOR, 2); 372 cfg->device = REG(PCIR_DEVICE, 2); 373 cfg->cmdreg = REG(PCIR_COMMAND, 2); 374 cfg->statreg = REG(PCIR_STATUS, 2); 375 cfg->baseclass = REG(PCIR_CLASS, 1); 376 cfg->subclass = REG(PCIR_SUBCLASS, 1); 377 cfg->progif = REG(PCIR_PROGIF, 1); 378 cfg->revid = REG(PCIR_REVID, 1); 379 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 380 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 381 cfg->lattimer = REG(PCIR_LATTIMER, 1); 382 cfg->intpin = REG(PCIR_INTPIN, 1); 383 cfg->intline = REG(PCIR_INTLINE, 1); 384 385 cfg->mingnt = REG(PCIR_MINGNT, 1); 386 cfg->maxlat = REG(PCIR_MAXLAT, 1); 387 388 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 389 cfg->hdrtype &= ~PCIM_MFDEV; 390 391 pci_fixancient(cfg); 392 pci_hdrtypedata(pcib, b, s, f, cfg); 393 394 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 395 pci_read_extcap(pcib, cfg); 396 397 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 398 399 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 400 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 401 devlist_entry->conf.pc_sel.pc_func = cfg->func; 402 devlist_entry->conf.pc_hdr = cfg->hdrtype; 403 404 devlist_entry->conf.pc_subvendor = cfg->subvendor; 405 devlist_entry->conf.pc_subdevice = cfg->subdevice; 406 devlist_entry->conf.pc_vendor = cfg->vendor; 407 devlist_entry->conf.pc_device = cfg->device; 408 409 devlist_entry->conf.pc_class = cfg->baseclass; 410 devlist_entry->conf.pc_subclass = cfg->subclass; 411 devlist_entry->conf.pc_progif = cfg->progif; 412 devlist_entry->conf.pc_revid = cfg->revid; 413 414 pci_numdevs++; 415 pci_generation++; 416 } 417 return (devlist_entry); 418#undef REG 419} 420 421static void 422pci_read_extcap(device_t pcib, pcicfgregs *cfg) 423{ 424#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 425 int ptr, nextptr, ptrptr; 426 427 switch (cfg->hdrtype & PCIM_HDRTYPE) { 428 case 0: 429 ptrptr = PCIR_CAP_PTR; 430 break; 431 case 2: 432 ptrptr = PCIR_CAP_PTR_2; 433 break; 434 default: 435 return; /* no extended capabilities support */ 436 } 437 nextptr = REG(ptrptr, 1); /* sanity check? */ 438 439 /* 440 * Read capability entries. 441 */ 442 while (nextptr != 0) { 443 /* Sanity check */ 444 if (nextptr > 255) { 445 printf("illegal PCI extended capability offset %d\n", 446 nextptr); 447 return; 448 } 449 /* Find the next entry */ 450 ptr = nextptr; 451 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 452 453 /* Process this entry */ 454 switch (REG(ptr + PCICAP_ID, 1)) { 455 case PCIY_PMG: /* PCI power management */ 456 if (cfg->pp.pp_cap == 0) { 457 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 458 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 459 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 460 if ((nextptr - ptr) > PCIR_POWER_DATA) 461 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 462 } 463 break; 464 case PCIY_MSI: /* PCI MSI */ 465 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 466 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 467 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 468 else 469 cfg->msi.msi_data = PCIR_MSI_DATA; 470 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 471 PCIM_MSICTRL_MMC_MASK)>>1); 472 default: 473 break; 474 } 475 } 476#undef REG 477} 478 479/* 480 * Return the offset in configuration space of the requested extended 481 * capability entry or 0 if the specified capability was not found. 482 */ 483int 484pci_find_extcap_method(device_t dev, device_t child, int capability, 485 int *capreg) 486{ 487 struct pci_devinfo *dinfo = device_get_ivars(child); 488 pcicfgregs *cfg = &dinfo->cfg; 489 u_int32_t status; 490 u_int8_t ptr; 491 492 /* 493 * Check the CAP_LIST bit of the PCI status register first. 494 */ 495 status = pci_read_config(child, PCIR_STATUS, 2); 496 if (!(status & PCIM_STATUS_CAPPRESENT)) 497 return (ENXIO); 498 499 /* 500 * Determine the start pointer of the capabilities list. 501 */ 502 switch (cfg->hdrtype & PCIM_HDRTYPE) { 503 case 0: 504 ptr = PCIR_CAP_PTR; 505 break; 506 case 2: 507 ptr = PCIR_CAP_PTR_2; 508 break; 509 default: 510 /* XXX: panic? */ 511 return (ENXIO); /* no extended capabilities support */ 512 } 513 ptr = pci_read_config(child, ptr, 1); 514 515 /* 516 * Traverse the capabilities list. 517 */ 518 while (ptr != 0) { 519 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 520 if (capreg != NULL) 521 *capreg = ptr; 522 return (0); 523 } 524 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 525 } 526 527 return (ENOENT); 528} 529 530/* free pcicfgregs structure and all depending data structures */ 531 532int 533pci_freecfg(struct pci_devinfo *dinfo) 534{ 535 struct devlist *devlist_head; 536 537 devlist_head = &pci_devq; 538 539 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 540 free(dinfo, M_DEVBUF); 541 542 /* increment the generation count */ 543 pci_generation++; 544 545 /* we're losing one device */ 546 pci_numdevs--; 547 return (0); 548} 549 550/* 551 * PCI power manangement 552 */ 553int 554pci_set_powerstate_method(device_t dev, device_t child, int state) 555{ 556 struct pci_devinfo *dinfo = device_get_ivars(child); 557 pcicfgregs *cfg = &dinfo->cfg; 558 uint16_t status; 559 int result, oldstate, highest, delay; 560 561 if (cfg->pp.pp_cap == 0) 562 return (EOPNOTSUPP); 563 564 /* 565 * Optimize a no state change request away. While it would be OK to 566 * write to the hardware in theory, some devices have shown odd 567 * behavior when going from D3 -> D3. 568 */ 569 oldstate = pci_get_powerstate(child); 570 if (oldstate == state) 571 return (0); 572 573 /* 574 * The PCI power management specification states that after a state 575 * transition between PCI power states, system software must 576 * guarantee a minimal delay before the function accesses the device. 577 * Compute the worst case delay that we need to guarantee before we 578 * access the device. Many devices will be responsive much more 579 * quickly than this delay, but there are some that don't respond 580 * instantly to state changes. Transitions to/from D3 state require 581 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 582 * is done below with DELAY rather than a sleeper function because 583 * this function can be called from contexts where we cannot sleep. 584 */ 585 highest = (oldstate > state) ? oldstate : state; 586 if (highest == PCI_POWERSTATE_D3) 587 delay = 10000; 588 else if (highest == PCI_POWERSTATE_D2) 589 delay = 200; 590 else 591 delay = 0; 592 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 593 & ~PCIM_PSTAT_DMASK; 594 result = 0; 595 switch (state) { 596 case PCI_POWERSTATE_D0: 597 status |= PCIM_PSTAT_D0; 598 break; 599 case PCI_POWERSTATE_D1: 600 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 601 return (EOPNOTSUPP); 602 status |= PCIM_PSTAT_D1; 603 break; 604 case PCI_POWERSTATE_D2: 605 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 606 return (EOPNOTSUPP); 607 status |= PCIM_PSTAT_D2; 608 break; 609 case PCI_POWERSTATE_D3: 610 status |= PCIM_PSTAT_D3; 611 break; 612 default: 613 return (EINVAL); 614 } 615 616 if (bootverbose) 617 printf( 618 "pci%d:%d:%d: Transition from D%d to D%d\n", 619 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 620 oldstate, state); 621 622 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 623 if (delay) 624 DELAY(delay); 625 return (0); 626} 627 628int 629pci_get_powerstate_method(device_t dev, device_t child) 630{ 631 struct pci_devinfo *dinfo = device_get_ivars(child); 632 pcicfgregs *cfg = &dinfo->cfg; 633 uint16_t status; 634 int result; 635 636 if (cfg->pp.pp_cap != 0) { 637 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 638 switch (status & PCIM_PSTAT_DMASK) { 639 case PCIM_PSTAT_D0: 640 result = PCI_POWERSTATE_D0; 641 break; 642 case PCIM_PSTAT_D1: 643 result = PCI_POWERSTATE_D1; 644 break; 645 case PCIM_PSTAT_D2: 646 result = PCI_POWERSTATE_D2; 647 break; 648 case PCIM_PSTAT_D3: 649 result = PCI_POWERSTATE_D3; 650 break; 651 default: 652 result = PCI_POWERSTATE_UNKNOWN; 653 break; 654 } 655 } else { 656 /* No support, device is always at D0 */ 657 result = PCI_POWERSTATE_D0; 658 } 659 return (result); 660} 661 662/* 663 * Some convenience functions for PCI device drivers. 664 */ 665 666static __inline void 667pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 668{ 669 uint16_t command; 670 671 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 672 command |= bit; 673 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 674} 675 676static __inline void 677pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 678{ 679 uint16_t command; 680 681 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 682 command &= ~bit; 683 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 684} 685 686int 687pci_enable_busmaster_method(device_t dev, device_t child) 688{ 689 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 690 return (0); 691} 692 693int 694pci_disable_busmaster_method(device_t dev, device_t child) 695{ 696 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 697 return (0); 698} 699 700int 701pci_enable_io_method(device_t dev, device_t child, int space) 702{ 703 uint16_t command; 704 uint16_t bit; 705 char *error; 706 707 bit = 0; 708 error = NULL; 709 710 switch(space) { 711 case SYS_RES_IOPORT: 712 bit = PCIM_CMD_PORTEN; 713 error = "port"; 714 break; 715 case SYS_RES_MEMORY: 716 bit = PCIM_CMD_MEMEN; 717 error = "memory"; 718 break; 719 default: 720 return (EINVAL); 721 } 722 pci_set_command_bit(dev, child, bit); 723 /* Some devices seem to need a brief stall here, what do to? */ 724 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 725 if (command & bit) 726 return (0); 727 device_printf(child, "failed to enable %s mapping!\n", error); 728 return (ENXIO); 729} 730 731int 732pci_disable_io_method(device_t dev, device_t child, int space) 733{ 734 uint16_t command; 735 uint16_t bit; 736 char *error; 737 738 bit = 0; 739 error = NULL; 740 741 switch(space) { 742 case SYS_RES_IOPORT: 743 bit = PCIM_CMD_PORTEN; 744 error = "port"; 745 break; 746 case SYS_RES_MEMORY: 747 bit = PCIM_CMD_MEMEN; 748 error = "memory"; 749 break; 750 default: 751 return (EINVAL); 752 } 753 pci_clear_command_bit(dev, child, bit); 754 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 755 if (command & bit) { 756 device_printf(child, "failed to disable %s mapping!\n", error); 757 return (ENXIO); 758 } 759 return (0); 760} 761 762/* 763 * New style pci driver. Parent device is either a pci-host-bridge or a 764 * pci-pci-bridge. Both kinds are represented by instances of pcib. 765 */ 766 767void 768pci_print_verbose(struct pci_devinfo *dinfo) 769{ 770 if (bootverbose) { 771 pcicfgregs *cfg = &dinfo->cfg; 772 773 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 774 cfg->vendor, cfg->device, cfg->revid); 775 printf("\tbus=%d, slot=%d, func=%d\n", 776 cfg->bus, cfg->slot, cfg->func); 777 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 778 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 779 cfg->mfdev); 780 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 781 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 782 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 783 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 784 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 785 if (cfg->intpin > 0) 786 printf("\tintpin=%c, irq=%d\n", 787 cfg->intpin +'a' -1, cfg->intline); 788 if (cfg->pp.pp_cap) { 789 uint16_t status; 790 791 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 792 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 793 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 794 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 795 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 796 status & PCIM_PSTAT_DMASK); 797 } 798 if (cfg->msi.msi_data) { 799 int ctrl; 800 801 ctrl = cfg->msi.msi_ctrl; 802 printf("\tMSI supports %d message%s%s%s\n", 803 cfg->msi.msi_msgnum, 804 (cfg->msi.msi_msgnum == 1) ? "" : "s", 805 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 806 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 807 } 808 } 809} 810 811static int 812pci_porten(device_t pcib, int b, int s, int f) 813{ 814 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 815 & PCIM_CMD_PORTEN) != 0; 816} 817 818static int 819pci_memen(device_t pcib, int b, int s, int f) 820{ 821 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 822 & PCIM_CMD_MEMEN) != 0; 823} 824 825/* 826 * Add a resource based on a pci map register. Return 1 if the map 827 * register is a 32bit map register or 2 if it is a 64bit register. 828 */ 829static int 830pci_add_map(device_t pcib, device_t bus, device_t dev, 831 int b, int s, int f, int reg, struct resource_list *rl, int force, 832 int prefetch) 833{ 834 uint32_t map; 835 uint64_t base; 836 uint64_t start, end, count; 837 uint8_t ln2size; 838 uint8_t ln2range; 839 uint32_t testval; 840 uint16_t cmd; 841 int type; 842 int barlen; 843 struct resource *res; 844 845 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 846 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 847 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 848 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 849 850 if (pci_maptype(map) & PCI_MAPMEM) 851 type = SYS_RES_MEMORY; 852 else 853 type = SYS_RES_IOPORT; 854 ln2size = pci_mapsize(testval); 855 ln2range = pci_maprange(testval); 856 base = pci_mapbase(map); 857 barlen = ln2range == 64 ? 2 : 1; 858 859 /* 860 * For I/O registers, if bottom bit is set, and the next bit up 861 * isn't clear, we know we have a BAR that doesn't conform to the 862 * spec, so ignore it. Also, sanity check the size of the data 863 * areas to the type of memory involved. Memory must be at least 864 * 32 bytes in size, while I/O ranges must be at least 4. 865 */ 866 if ((testval & 0x1) == 0x1 && 867 (testval & 0x2) != 0) 868 return (barlen); 869 if ((type == SYS_RES_MEMORY && ln2size < 5) || 870 (type == SYS_RES_IOPORT && ln2size < 2)) 871 return (barlen); 872 873 if (ln2range == 64) 874 /* Read the other half of a 64bit map register */ 875 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 876 877 if (bootverbose) { 878 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 879 reg, pci_maptype(map), ln2range, 880 (unsigned int) base, ln2size); 881 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 882 printf(", port disabled\n"); 883 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 884 printf(", memory disabled\n"); 885 else 886 printf(", enabled\n"); 887 } 888 889 /* 890 * If base is 0, then we have problems. It is best to ignore 891 * such entries for the moment. These will be allocated later if 892 * the driver specifically requests them. However, some 893 * removable busses look better when all resources are allocated, 894 * so allow '0' to be overriden. 895 * 896 * Similarly treat maps whose values is the same as the test value 897 * read back. These maps have had all f's written to them by the 898 * BIOS in an attempt to disable the resources. 899 */ 900 if (!force && (base == 0 || map == testval)) { 901 if (bootverbose) 902 printf("ignored rid %#x: base %#llx map %#x testval %#x\n", 903 reg, base, map, testval); 904 return (barlen); 905 } 906 907 /* 908 * This code theoretically does the right thing, but has 909 * undesirable side effects in some cases where peripherals 910 * respond oddly to having these bits enabled. Let the user 911 * be able to turn them off (since pci_enable_io_modes is 1 by 912 * default). 913 */ 914 if (pci_enable_io_modes) { 915 /* Turn on resources that have been left off by a lazy BIOS */ 916 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 917 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 918 cmd |= PCIM_CMD_PORTEN; 919 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 920 } 921 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 922 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 923 cmd |= PCIM_CMD_MEMEN; 924 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 925 } 926 } else { 927 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 928 return (barlen); 929 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 930 return (barlen); 931 } 932 933 count = 1 << ln2size; 934 if (base == 0 || base == pci_mapbase(testval)) { 935 start = 0; /* Let the parent deside */ 936 end = ~0ULL; 937 } else { 938 start = base; 939 end = base + (1 << ln2size) - 1; 940 } 941 resource_list_add(rl, type, reg, start, end, count); 942 943 /* 944 * Not quite sure what to do on failure of allocating the resource 945 * since I can postulate several right answers. 946 */ 947 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 948 prefetch ? RF_PREFETCHABLE : 0); 949 if (res == NULL) 950 printf("alloc failed\n"); 951 else 952 printf("Allocated for %#x: start %#lx end %#lx\n", reg, rman_get_start(res), rman_get_end(res)); 953 if (res != NULL) 954 pci_write_config(dev, reg, rman_get_start(res), 4); 955 return (barlen); 956} 957 958/* 959 * For ATA devices we need to decide early what addressing mode to use. 960 * Legacy demands that the primary and secondary ATA ports sits on the 961 * same addresses that old ISA hardware did. This dictates that we use 962 * those addresses and ignore the BAR's if we cannot set PCI native 963 * addressing mode. 964 */ 965static void 966pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 967 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 968{ 969 int rid, type, progif; 970#if 0 971 /* if this device supports PCI native addressing use it */ 972 progif = pci_read_config(dev, PCIR_PROGIF, 1); 973 if ((progif & 0x8a) == 0x8a) { 974 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 975 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 976 printf("Trying ATA native PCI addressing mode\n"); 977 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 978 } 979 } 980#endif 981 progif = pci_read_config(dev, PCIR_PROGIF, 1); 982 type = SYS_RES_IOPORT; 983 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 984 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 985 prefetchmask & (1 << 0)); 986 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 987 prefetchmask & (1 << 1)); 988 } else { 989 rid = PCIR_BAR(0); 990 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 991 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 992 0); 993 rid = PCIR_BAR(1); 994 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 995 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 996 0); 997 } 998 if (progif & PCIP_STORAGE_IDE_MODESEC) { 999 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 1000 prefetchmask & (1 << 2)); 1001 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 1002 prefetchmask & (1 << 3)); 1003 } else { 1004 rid = PCIR_BAR(2); 1005 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1006 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1007 0); 1008 rid = PCIR_BAR(3); 1009 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1010 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1011 0); 1012 } 1013 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 1014 prefetchmask & (1 << 4)); 1015 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 1016 prefetchmask & (1 << 5)); 1017} 1018 1019static void 1020pci_assign_interrupt(device_t bus, device_t dev, int force_route) 1021{ 1022 struct pci_devinfo *dinfo = device_get_ivars(dev); 1023 pcicfgregs *cfg = &dinfo->cfg; 1024 char tunable_name[64]; 1025 int irq; 1026 1027 /* Has to have an intpin to have an interrupt. */ 1028 if (cfg->intpin == 0) 1029 return; 1030 1031 /* Let the user override the IRQ with a tunable. */ 1032 irq = PCI_INVALID_IRQ; 1033 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 1034 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 1035 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 1036 irq = PCI_INVALID_IRQ; 1037 1038 /* 1039 * If we didn't get an IRQ via the tunable, then we either use the 1040 * IRQ value in the intline register or we ask the bus to route an 1041 * interrupt for us. If force_route is true, then we only use the 1042 * value in the intline register if the bus was unable to assign an 1043 * IRQ. 1044 */ 1045 if (!PCI_INTERRUPT_VALID(irq)) { 1046 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 1047 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 1048 if (!PCI_INTERRUPT_VALID(irq)) 1049 irq = cfg->intline; 1050 } 1051 1052 /* If after all that we don't have an IRQ, just bail. */ 1053 if (!PCI_INTERRUPT_VALID(irq)) 1054 return; 1055 1056 /* Update the config register if it changed. */ 1057 if (irq != cfg->intline) { 1058 cfg->intline = irq; 1059 pci_write_config(dev, PCIR_INTLINE, irq, 1); 1060 } 1061 1062 /* Add this IRQ as rid 0 interrupt resource. */ 1063 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 1064} 1065 1066void 1067pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 1068{ 1069 device_t pcib; 1070 struct pci_devinfo *dinfo = device_get_ivars(dev); 1071 pcicfgregs *cfg = &dinfo->cfg; 1072 struct resource_list *rl = &dinfo->resources; 1073 struct pci_quirk *q; 1074 int b, i, f, s; 1075 1076 pcib = device_get_parent(bus); 1077 1078 b = cfg->bus; 1079 s = cfg->slot; 1080 f = cfg->func; 1081 1082 /* ATA devices needs special map treatment */ 1083 if ((pci_get_class(dev) == PCIC_STORAGE) && 1084 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1085 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1086 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 1087 else 1088 for (i = 0; i < cfg->nummaps;) 1089 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1090 rl, force, prefetchmask & (1 << i)); 1091 1092 /* 1093 * Add additional, quirked resources. 1094 */ 1095 for (q = &pci_quirks[0]; q->devid; q++) { 1096 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1097 && q->type == PCI_QUIRK_MAP_REG) 1098 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 1099 force, 0); 1100 } 1101 1102 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1103#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 1104 defined(__arm__) || defined(__alpha__) 1105 /* 1106 * Try to re-route interrupts. Sometimes the BIOS or 1107 * firmware may leave bogus values in these registers. 1108 * If the re-route fails, then just stick with what we 1109 * have. 1110 */ 1111 pci_assign_interrupt(bus, dev, 1); 1112#else 1113 pci_assign_interrupt(bus, dev, 0); 1114#endif 1115 } 1116} 1117 1118void 1119pci_add_children(device_t dev, int busno, size_t dinfo_size) 1120{ 1121#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1122 device_t pcib = device_get_parent(dev); 1123 struct pci_devinfo *dinfo; 1124 int maxslots; 1125 int s, f, pcifunchigh; 1126 uint8_t hdrtype; 1127 1128 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 1129 ("dinfo_size too small")); 1130 maxslots = PCIB_MAXSLOTS(pcib); 1131 for (s = 0; s <= maxslots; s++) { 1132 pcifunchigh = 0; 1133 f = 0; 1134 DELAY(1); 1135 hdrtype = REG(PCIR_HDRTYPE, 1); 1136 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1137 continue; 1138 if (hdrtype & PCIM_MFDEV) 1139 pcifunchigh = PCI_FUNCMAX; 1140 for (f = 0; f <= pcifunchigh; f++) { 1141 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1142 if (dinfo != NULL) { 1143 pci_add_child(dev, dinfo); 1144 } 1145 } 1146 } 1147#undef REG 1148} 1149 1150void 1151pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1152{ 1153 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1154 device_set_ivars(dinfo->cfg.dev, dinfo); 1155 resource_list_init(&dinfo->resources); 1156 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1157 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1158 pci_print_verbose(dinfo); 1159 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 1160} 1161 1162static int 1163pci_probe(device_t dev) 1164{ 1165 1166 device_set_desc(dev, "PCI bus"); 1167 1168 /* Allow other subclasses to override this driver. */ 1169 return (-1000); 1170} 1171 1172static int 1173pci_attach(device_t dev) 1174{ 1175 int busno; 1176 1177 /* 1178 * Since there can be multiple independantly numbered PCI 1179 * busses on some large alpha systems, we can't use the unit 1180 * number to decide what bus we are probing. We ask the parent 1181 * pcib what our bus number is. 1182 */ 1183 busno = pcib_get_bus(dev); 1184 if (bootverbose) 1185 device_printf(dev, "physical bus=%d\n", busno); 1186 1187 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1188 1189 return (bus_generic_attach(dev)); 1190} 1191 1192int 1193pci_suspend(device_t dev) 1194{ 1195 int dstate, error, i, numdevs; 1196 device_t acpi_dev, child, *devlist; 1197 struct pci_devinfo *dinfo; 1198 1199 /* 1200 * Save the PCI configuration space for each child and set the 1201 * device in the appropriate power state for this sleep state. 1202 */ 1203 acpi_dev = NULL; 1204 if (pci_do_power_resume) 1205 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1206 device_get_children(dev, &devlist, &numdevs); 1207 for (i = 0; i < numdevs; i++) { 1208 child = devlist[i]; 1209 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1210 pci_cfg_save(child, dinfo, 0); 1211 } 1212 1213 /* Suspend devices before potentially powering them down. */ 1214 error = bus_generic_suspend(dev); 1215 if (error) { 1216 free(devlist, M_TEMP); 1217 return (error); 1218 } 1219 1220 /* 1221 * Always set the device to D3. If ACPI suggests a different 1222 * power state, use it instead. If ACPI is not present, the 1223 * firmware is responsible for managing device power. Skip 1224 * children who aren't attached since they are powered down 1225 * separately. Only manage type 0 devices for now. 1226 */ 1227 for (i = 0; acpi_dev && i < numdevs; i++) { 1228 child = devlist[i]; 1229 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1230 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1231 dstate = PCI_POWERSTATE_D3; 1232 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1233 pci_set_powerstate(child, dstate); 1234 } 1235 } 1236 free(devlist, M_TEMP); 1237 return (0); 1238} 1239 1240int 1241pci_resume(device_t dev) 1242{ 1243 int i, numdevs; 1244 device_t acpi_dev, child, *devlist; 1245 struct pci_devinfo *dinfo; 1246 1247 /* 1248 * Set each child to D0 and restore its PCI configuration space. 1249 */ 1250 acpi_dev = NULL; 1251 if (pci_do_power_resume) 1252 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1253 device_get_children(dev, &devlist, &numdevs); 1254 for (i = 0; i < numdevs; i++) { 1255 /* 1256 * Notify ACPI we're going to D0 but ignore the result. If 1257 * ACPI is not present, the firmware is responsible for 1258 * managing device power. Only manage type 0 devices for now. 1259 */ 1260 child = devlist[i]; 1261 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1262 if (acpi_dev && device_is_attached(child) && 1263 dinfo->cfg.hdrtype == 0) { 1264 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1265 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1266 } 1267 1268 /* Now the device is powered up, restore its config space. */ 1269 pci_cfg_restore(child, dinfo); 1270 } 1271 free(devlist, M_TEMP); 1272 return (bus_generic_resume(dev)); 1273} 1274 1275static void 1276pci_load_vendor_data(void) 1277{ 1278 caddr_t vendordata, info; 1279 1280 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1281 info = preload_search_info(vendordata, MODINFO_ADDR); 1282 pci_vendordata = *(char **)info; 1283 info = preload_search_info(vendordata, MODINFO_SIZE); 1284 pci_vendordata_size = *(size_t *)info; 1285 /* terminate the database */ 1286 pci_vendordata[pci_vendordata_size] = '\n'; 1287 } 1288} 1289 1290void 1291pci_driver_added(device_t dev, driver_t *driver) 1292{ 1293 int numdevs; 1294 device_t *devlist; 1295 device_t child; 1296 struct pci_devinfo *dinfo; 1297 int i; 1298 1299 if (bootverbose) 1300 device_printf(dev, "driver added\n"); 1301 DEVICE_IDENTIFY(driver, dev); 1302 device_get_children(dev, &devlist, &numdevs); 1303 for (i = 0; i < numdevs; i++) { 1304 child = devlist[i]; 1305 if (device_get_state(child) != DS_NOTPRESENT) 1306 continue; 1307 dinfo = device_get_ivars(child); 1308 pci_print_verbose(dinfo); 1309 if (bootverbose) 1310 printf("pci%d:%d:%d: reprobing on driver added\n", 1311 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1312 pci_cfg_restore(child, dinfo); 1313 if (device_probe_and_attach(child) != 0) 1314 pci_cfg_save(child, dinfo, 1); 1315 } 1316 free(devlist, M_TEMP); 1317} 1318 1319int 1320pci_print_child(device_t dev, device_t child) 1321{ 1322 struct pci_devinfo *dinfo; 1323 struct resource_list *rl; 1324 int retval = 0; 1325 1326 dinfo = device_get_ivars(child); 1327 rl = &dinfo->resources; 1328 1329 retval += bus_print_child_header(dev, child); 1330 1331 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1332 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1333 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1334 if (device_get_flags(dev)) 1335 retval += printf(" flags %#x", device_get_flags(dev)); 1336 1337 retval += printf(" at device %d.%d", pci_get_slot(child), 1338 pci_get_function(child)); 1339 1340 retval += bus_print_child_footer(dev, child); 1341 1342 return (retval); 1343} 1344 1345static struct 1346{ 1347 int class; 1348 int subclass; 1349 char *desc; 1350} pci_nomatch_tab[] = { 1351 {PCIC_OLD, -1, "old"}, 1352 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1353 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1354 {PCIC_STORAGE, -1, "mass storage"}, 1355 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1356 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1357 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1358 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1359 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1360 {PCIC_NETWORK, -1, "network"}, 1361 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1362 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1363 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1364 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1365 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1366 {PCIC_DISPLAY, -1, "display"}, 1367 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1368 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1369 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1370 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1371 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1372 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1373 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1374 {PCIC_MEMORY, -1, "memory"}, 1375 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1376 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1377 {PCIC_BRIDGE, -1, "bridge"}, 1378 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1379 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1380 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1381 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1382 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1383 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1384 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1385 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1386 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1387 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1388 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1389 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1390 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1391 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1392 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1393 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1394 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1395 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1396 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1397 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1398 {PCIC_INPUTDEV, -1, "input device"}, 1399 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1400 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1401 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1402 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1403 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1404 {PCIC_DOCKING, -1, "docking station"}, 1405 {PCIC_PROCESSOR, -1, "processor"}, 1406 {PCIC_SERIALBUS, -1, "serial bus"}, 1407 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1408 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1409 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1410 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1411 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1412 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1413 {PCIC_WIRELESS, -1, "wireless controller"}, 1414 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1415 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1416 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1417 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1418 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1419 {PCIC_SATCOM, -1, "satellite communication"}, 1420 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1421 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1422 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1423 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1424 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1425 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1426 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1427 {PCIC_DASP, -1, "dasp"}, 1428 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1429 {0, 0, NULL} 1430}; 1431 1432void 1433pci_probe_nomatch(device_t dev, device_t child) 1434{ 1435 int i; 1436 char *cp, *scp, *device; 1437 1438 /* 1439 * Look for a listing for this device in a loaded device database. 1440 */ 1441 if ((device = pci_describe_device(child)) != NULL) { 1442 device_printf(dev, "<%s>", device); 1443 free(device, M_DEVBUF); 1444 } else { 1445 /* 1446 * Scan the class/subclass descriptions for a general 1447 * description. 1448 */ 1449 cp = "unknown"; 1450 scp = NULL; 1451 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1452 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1453 if (pci_nomatch_tab[i].subclass == -1) { 1454 cp = pci_nomatch_tab[i].desc; 1455 } else if (pci_nomatch_tab[i].subclass == 1456 pci_get_subclass(child)) { 1457 scp = pci_nomatch_tab[i].desc; 1458 } 1459 } 1460 } 1461 device_printf(dev, "<%s%s%s>", 1462 cp ? cp : "", 1463 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1464 scp ? scp : ""); 1465 } 1466 printf(" at device %d.%d (no driver attached)\n", 1467 pci_get_slot(child), pci_get_function(child)); 1468 if (pci_do_power_nodriver) 1469 pci_cfg_save(child, 1470 (struct pci_devinfo *) device_get_ivars(child), 1); 1471 return; 1472} 1473 1474/* 1475 * Parse the PCI device database, if loaded, and return a pointer to a 1476 * description of the device. 1477 * 1478 * The database is flat text formatted as follows: 1479 * 1480 * Any line not in a valid format is ignored. 1481 * Lines are terminated with newline '\n' characters. 1482 * 1483 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1484 * the vendor name. 1485 * 1486 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1487 * - devices cannot be listed without a corresponding VENDOR line. 1488 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1489 * another TAB, then the device name. 1490 */ 1491 1492/* 1493 * Assuming (ptr) points to the beginning of a line in the database, 1494 * return the vendor or device and description of the next entry. 1495 * The value of (vendor) or (device) inappropriate for the entry type 1496 * is set to -1. Returns nonzero at the end of the database. 1497 * 1498 * Note that this is slightly unrobust in the face of corrupt data; 1499 * we attempt to safeguard against this by spamming the end of the 1500 * database with a newline when we initialise. 1501 */ 1502static int 1503pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1504{ 1505 char *cp = *ptr; 1506 int left; 1507 1508 *device = -1; 1509 *vendor = -1; 1510 **desc = '\0'; 1511 for (;;) { 1512 left = pci_vendordata_size - (cp - pci_vendordata); 1513 if (left <= 0) { 1514 *ptr = cp; 1515 return(1); 1516 } 1517 1518 /* vendor entry? */ 1519 if (*cp != '\t' && 1520 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1521 break; 1522 /* device entry? */ 1523 if (*cp == '\t' && 1524 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1525 break; 1526 1527 /* skip to next line */ 1528 while (*cp != '\n' && left > 0) { 1529 cp++; 1530 left--; 1531 } 1532 if (*cp == '\n') { 1533 cp++; 1534 left--; 1535 } 1536 } 1537 /* skip to next line */ 1538 while (*cp != '\n' && left > 0) { 1539 cp++; 1540 left--; 1541 } 1542 if (*cp == '\n' && left > 0) 1543 cp++; 1544 *ptr = cp; 1545 return(0); 1546} 1547 1548static char * 1549pci_describe_device(device_t dev) 1550{ 1551 int vendor, device; 1552 char *desc, *vp, *dp, *line; 1553 1554 desc = vp = dp = NULL; 1555 1556 /* 1557 * If we have no vendor data, we can't do anything. 1558 */ 1559 if (pci_vendordata == NULL) 1560 goto out; 1561 1562 /* 1563 * Scan the vendor data looking for this device 1564 */ 1565 line = pci_vendordata; 1566 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1567 goto out; 1568 for (;;) { 1569 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1570 goto out; 1571 if (vendor == pci_get_vendor(dev)) 1572 break; 1573 } 1574 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1575 goto out; 1576 for (;;) { 1577 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1578 *dp = 0; 1579 break; 1580 } 1581 if (vendor != -1) { 1582 *dp = 0; 1583 break; 1584 } 1585 if (device == pci_get_device(dev)) 1586 break; 1587 } 1588 if (dp[0] == '\0') 1589 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1590 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1591 NULL) 1592 sprintf(desc, "%s, %s", vp, dp); 1593 out: 1594 if (vp != NULL) 1595 free(vp, M_DEVBUF); 1596 if (dp != NULL) 1597 free(dp, M_DEVBUF); 1598 return(desc); 1599} 1600 1601int 1602pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1603{ 1604 struct pci_devinfo *dinfo; 1605 pcicfgregs *cfg; 1606 1607 dinfo = device_get_ivars(child); 1608 cfg = &dinfo->cfg; 1609 1610 switch (which) { 1611 case PCI_IVAR_ETHADDR: 1612 /* 1613 * The generic accessor doesn't deal with failure, so 1614 * we set the return value, then return an error. 1615 */ 1616 *((uint8_t **) result) = NULL; 1617 return (EINVAL); 1618 case PCI_IVAR_SUBVENDOR: 1619 *result = cfg->subvendor; 1620 break; 1621 case PCI_IVAR_SUBDEVICE: 1622 *result = cfg->subdevice; 1623 break; 1624 case PCI_IVAR_VENDOR: 1625 *result = cfg->vendor; 1626 break; 1627 case PCI_IVAR_DEVICE: 1628 *result = cfg->device; 1629 break; 1630 case PCI_IVAR_DEVID: 1631 *result = (cfg->device << 16) | cfg->vendor; 1632 break; 1633 case PCI_IVAR_CLASS: 1634 *result = cfg->baseclass; 1635 break; 1636 case PCI_IVAR_SUBCLASS: 1637 *result = cfg->subclass; 1638 break; 1639 case PCI_IVAR_PROGIF: 1640 *result = cfg->progif; 1641 break; 1642 case PCI_IVAR_REVID: 1643 *result = cfg->revid; 1644 break; 1645 case PCI_IVAR_INTPIN: 1646 *result = cfg->intpin; 1647 break; 1648 case PCI_IVAR_IRQ: 1649 *result = cfg->intline; 1650 break; 1651 case PCI_IVAR_BUS: 1652 *result = cfg->bus; 1653 break; 1654 case PCI_IVAR_SLOT: 1655 *result = cfg->slot; 1656 break; 1657 case PCI_IVAR_FUNCTION: 1658 *result = cfg->func; 1659 break; 1660 case PCI_IVAR_CMDREG: 1661 *result = cfg->cmdreg; 1662 break; 1663 case PCI_IVAR_CACHELNSZ: 1664 *result = cfg->cachelnsz; 1665 break; 1666 case PCI_IVAR_MINGNT: 1667 *result = cfg->mingnt; 1668 break; 1669 case PCI_IVAR_MAXLAT: 1670 *result = cfg->maxlat; 1671 break; 1672 case PCI_IVAR_LATTIMER: 1673 *result = cfg->lattimer; 1674 break; 1675 default: 1676 return (ENOENT); 1677 } 1678 return (0); 1679} 1680 1681int 1682pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1683{ 1684 struct pci_devinfo *dinfo; 1685 1686 dinfo = device_get_ivars(child); 1687 1688 switch (which) { 1689 case PCI_IVAR_INTPIN: 1690 dinfo->cfg.intpin = value; 1691 return (0); 1692 case PCI_IVAR_ETHADDR: 1693 case PCI_IVAR_SUBVENDOR: 1694 case PCI_IVAR_SUBDEVICE: 1695 case PCI_IVAR_VENDOR: 1696 case PCI_IVAR_DEVICE: 1697 case PCI_IVAR_DEVID: 1698 case PCI_IVAR_CLASS: 1699 case PCI_IVAR_SUBCLASS: 1700 case PCI_IVAR_PROGIF: 1701 case PCI_IVAR_REVID: 1702 case PCI_IVAR_IRQ: 1703 case PCI_IVAR_BUS: 1704 case PCI_IVAR_SLOT: 1705 case PCI_IVAR_FUNCTION: 1706 return (EINVAL); /* disallow for now */ 1707 1708 default: 1709 return (ENOENT); 1710 } 1711} 1712 1713 1714#include "opt_ddb.h" 1715#ifdef DDB 1716#include <ddb/ddb.h> 1717#include <sys/cons.h> 1718 1719/* 1720 * List resources based on pci map registers, used for within ddb 1721 */ 1722 1723DB_SHOW_COMMAND(pciregs, db_pci_dump) 1724{ 1725 struct pci_devinfo *dinfo; 1726 struct devlist *devlist_head; 1727 struct pci_conf *p; 1728 const char *name; 1729 int i, error, none_count, quit; 1730 1731 none_count = 0; 1732 /* get the head of the device queue */ 1733 devlist_head = &pci_devq; 1734 1735 /* 1736 * Go through the list of devices and print out devices 1737 */ 1738 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1739 for (error = 0, i = 0, quit = 0, 1740 dinfo = STAILQ_FIRST(devlist_head); 1741 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1742 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1743 1744 /* Populate pd_name and pd_unit */ 1745 name = NULL; 1746 if (dinfo->cfg.dev) 1747 name = device_get_name(dinfo->cfg.dev); 1748 1749 p = &dinfo->conf; 1750 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1751 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1752 (name && *name) ? name : "none", 1753 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1754 none_count++, 1755 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1756 p->pc_sel.pc_func, (p->pc_class << 16) | 1757 (p->pc_subclass << 8) | p->pc_progif, 1758 (p->pc_subdevice << 16) | p->pc_subvendor, 1759 (p->pc_device << 16) | p->pc_vendor, 1760 p->pc_revid, p->pc_hdr); 1761 } 1762} 1763#endif /* DDB */ 1764 1765static struct resource * 1766pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1767 u_long start, u_long end, u_long count, u_int flags) 1768{ 1769 struct pci_devinfo *dinfo = device_get_ivars(child); 1770 struct resource_list *rl = &dinfo->resources; 1771 struct resource_list_entry *rle; 1772 struct resource *res; 1773 uint32_t map, testval; 1774 int mapsize; 1775 1776 /* 1777 * Weed out the bogons, and figure out how large the BAR/map 1778 * is. Bars that read back 0 here are bogus and unimplemented. 1779 * Note: atapci in legacy mode are special and handled elsewhere 1780 * in the code. If you have a atapci device in legacy mode and 1781 * it fails here, that other code is broken. 1782 */ 1783 res = NULL; 1784 map = pci_read_config(child, *rid, 4); 1785 pci_write_config(child, *rid, 0xffffffff, 4); 1786 testval = pci_read_config(child, *rid, 4); 1787 if (pci_mapbase(testval) == 0) 1788 goto out; 1789 if (pci_maptype(testval) & PCI_MAPMEM) { 1790 if (type != SYS_RES_MEMORY) { 1791 if (bootverbose) 1792 device_printf(dev, 1793 "child %s requested type %d for rid %#x," 1794 " but the BAR says it is an memio\n", 1795 device_get_nameunit(child), type, *rid); 1796 goto out; 1797 } 1798 } else { 1799 if (type != SYS_RES_IOPORT) { 1800 if (bootverbose) 1801 device_printf(dev, 1802 "child %s requested type %d for rid %#x," 1803 " but the BAR says it is an ioport\n", 1804 device_get_nameunit(child), type, *rid); 1805 goto out; 1806 } 1807 } 1808 /* 1809 * For real BARs, we need to override the size that 1810 * the driver requests, because that's what the BAR 1811 * actually uses and we would otherwise have a 1812 * situation where we might allocate the excess to 1813 * another driver, which won't work. 1814 */ 1815 mapsize = pci_mapsize(testval); 1816 count = 1 << mapsize; 1817 if (RF_ALIGNMENT(flags) < mapsize) 1818 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1819 1820 /* 1821 * Allocate enough resource, and then write back the 1822 * appropriate bar for that resource. 1823 */ 1824 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1825 start, end, count, flags); 1826 if (res == NULL) { 1827 device_printf(child, 1828 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 1829 count, *rid, type, start, end); 1830 goto out; 1831 } 1832 resource_list_add(rl, type, *rid, start, end, count); 1833 rle = resource_list_find(rl, type, *rid); 1834 if (rle == NULL) 1835 panic("pci_alloc_map: unexpectedly can't find resource."); 1836 rle->res = res; 1837 rle->start = rman_get_start(res); 1838 rle->end = rman_get_end(res); 1839 rle->count = count; 1840 if (bootverbose) 1841 device_printf(child, 1842 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1843 count, *rid, type, rman_get_start(res)); 1844 map = rman_get_start(res); 1845out:; 1846 pci_write_config(child, *rid, map, 4); 1847 return (res); 1848} 1849 1850 1851struct resource * 1852pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1853 u_long start, u_long end, u_long count, u_int flags) 1854{ 1855 struct pci_devinfo *dinfo = device_get_ivars(child); 1856 struct resource_list *rl = &dinfo->resources; 1857 struct resource_list_entry *rle; 1858 pcicfgregs *cfg = &dinfo->cfg; 1859 1860 /* 1861 * Perform lazy resource allocation 1862 */ 1863 if (device_get_parent(child) == dev) { 1864 switch (type) { 1865 case SYS_RES_IRQ: 1866 /* 1867 * If the child device doesn't have an 1868 * interrupt routed and is deserving of an 1869 * interrupt, try to assign it one. 1870 */ 1871 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1872 (cfg->intpin != 0)) 1873 pci_assign_interrupt(dev, child, 0); 1874 break; 1875 case SYS_RES_IOPORT: 1876 case SYS_RES_MEMORY: 1877 if (*rid < PCIR_BAR(cfg->nummaps)) { 1878 /* 1879 * Enable the I/O mode. We should 1880 * also be assigning resources too 1881 * when none are present. The 1882 * resource_list_alloc kind of sorta does 1883 * this... 1884 */ 1885 if (PCI_ENABLE_IO(dev, child, type)) 1886 return (NULL); 1887 } 1888 rle = resource_list_find(rl, type, *rid); 1889 if (rle == NULL) 1890 return (pci_alloc_map(dev, child, type, rid, 1891 start, end, count, flags)); 1892 break; 1893 } 1894 /* 1895 * If we've already allocated the resource, then 1896 * return it now. But first we may need to activate 1897 * it, since we don't allocate the resource as active 1898 * above. Normally this would be done down in the 1899 * nexus, but since we short-circuit that path we have 1900 * to do its job here. Not sure if we should free the 1901 * resource if it fails to activate. 1902 */ 1903 rle = resource_list_find(rl, type, *rid); 1904 if (rle != NULL && rle->res != NULL) { 1905 if (bootverbose) 1906 device_printf(child, 1907 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1908 rman_get_size(rle->res), *rid, type, 1909 rman_get_start(rle->res)); 1910 if ((flags & RF_ACTIVE) && 1911 bus_generic_activate_resource(dev, child, type, 1912 *rid, rle->res) != 0) 1913 return NULL; 1914 return (rle->res); 1915 } 1916 } 1917 return (resource_list_alloc(rl, dev, child, type, rid, 1918 start, end, count, flags)); 1919} 1920 1921void 1922pci_delete_resource(device_t dev, device_t child, int type, int rid) 1923{ 1924 struct pci_devinfo *dinfo; 1925 struct resource_list *rl; 1926 struct resource_list_entry *rle; 1927 1928 if (device_get_parent(child) != dev) 1929 return; 1930 1931 dinfo = device_get_ivars(child); 1932 rl = &dinfo->resources; 1933 rle = resource_list_find(rl, type, rid); 1934 if (rle) { 1935 if (rle->res) { 1936 if (rman_get_device(rle->res) != dev || 1937 rman_get_flags(rle->res) & RF_ACTIVE) { 1938 device_printf(dev, "delete_resource: " 1939 "Resource still owned by child, oops. " 1940 "(type=%d, rid=%d, addr=%lx)\n", 1941 rle->type, rle->rid, 1942 rman_get_start(rle->res)); 1943 return; 1944 } 1945 bus_release_resource(dev, type, rid, rle->res); 1946 } 1947 resource_list_delete(rl, type, rid); 1948 } 1949 /* 1950 * Why do we turn off the PCI configuration BAR when we delete a 1951 * resource? -- imp 1952 */ 1953 pci_write_config(child, rid, 0, 4); 1954 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1955} 1956 1957struct resource_list * 1958pci_get_resource_list (device_t dev, device_t child) 1959{ 1960 struct pci_devinfo *dinfo = device_get_ivars(child); 1961 1962 return (&dinfo->resources); 1963} 1964 1965uint32_t 1966pci_read_config_method(device_t dev, device_t child, int reg, int width) 1967{ 1968 struct pci_devinfo *dinfo = device_get_ivars(child); 1969 pcicfgregs *cfg = &dinfo->cfg; 1970 1971 return (PCIB_READ_CONFIG(device_get_parent(dev), 1972 cfg->bus, cfg->slot, cfg->func, reg, width)); 1973} 1974 1975void 1976pci_write_config_method(device_t dev, device_t child, int reg, 1977 uint32_t val, int width) 1978{ 1979 struct pci_devinfo *dinfo = device_get_ivars(child); 1980 pcicfgregs *cfg = &dinfo->cfg; 1981 1982 PCIB_WRITE_CONFIG(device_get_parent(dev), 1983 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1984} 1985 1986int 1987pci_child_location_str_method(device_t dev, device_t child, char *buf, 1988 size_t buflen) 1989{ 1990 1991 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1992 pci_get_function(child)); 1993 return (0); 1994} 1995 1996int 1997pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1998 size_t buflen) 1999{ 2000 struct pci_devinfo *dinfo; 2001 pcicfgregs *cfg; 2002 2003 dinfo = device_get_ivars(child); 2004 cfg = &dinfo->cfg; 2005 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2006 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2007 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2008 cfg->progif); 2009 return (0); 2010} 2011 2012int 2013pci_assign_interrupt_method(device_t dev, device_t child) 2014{ 2015 struct pci_devinfo *dinfo = device_get_ivars(child); 2016 pcicfgregs *cfg = &dinfo->cfg; 2017 2018 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2019 cfg->intpin)); 2020} 2021 2022static int 2023pci_modevent(module_t mod, int what, void *arg) 2024{ 2025 static struct cdev *pci_cdev; 2026 2027 switch (what) { 2028 case MOD_LOAD: 2029 STAILQ_INIT(&pci_devq); 2030 pci_generation = 0; 2031 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 2032 "pci"); 2033 pci_load_vendor_data(); 2034 break; 2035 2036 case MOD_UNLOAD: 2037 destroy_dev(pci_cdev); 2038 break; 2039 } 2040 2041 return (0); 2042} 2043 2044void 2045pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 2046{ 2047 int i; 2048 2049 /* 2050 * Only do header type 0 devices. Type 1 devices are bridges, 2051 * which we know need special treatment. Type 2 devices are 2052 * cardbus bridges which also require special treatment. 2053 * Other types are unknown, and we err on the side of safety 2054 * by ignoring them. 2055 */ 2056 if (dinfo->cfg.hdrtype != 0) 2057 return; 2058 2059 /* 2060 * Restore the device to full power mode. We must do this 2061 * before we restore the registers because moving from D3 to 2062 * D0 will cause the chip's BARs and some other registers to 2063 * be reset to some unknown power on reset values. Cut down 2064 * the noise on boot by doing nothing if we are already in 2065 * state D0. 2066 */ 2067 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2068 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2069 } 2070 for (i = 0; i < dinfo->cfg.nummaps; i++) 2071 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2072 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2073 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2074 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2075 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2076 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2077 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2078 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2079 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2080 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2081 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2082} 2083 2084void 2085pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2086{ 2087 int i; 2088 uint32_t cls; 2089 int ps; 2090 2091 /* 2092 * Only do header type 0 devices. Type 1 devices are bridges, which 2093 * we know need special treatment. Type 2 devices are cardbus bridges 2094 * which also require special treatment. Other types are unknown, and 2095 * we err on the side of safety by ignoring them. Powering down 2096 * bridges should not be undertaken lightly. 2097 */ 2098 if (dinfo->cfg.hdrtype != 0) 2099 return; 2100 for (i = 0; i < dinfo->cfg.nummaps; i++) 2101 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2102 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2103 2104 /* 2105 * Some drivers apparently write to these registers w/o updating our 2106 * cached copy. No harm happens if we update the copy, so do so here 2107 * so we can restore them. The COMMAND register is modified by the 2108 * bus w/o updating the cache. This should represent the normally 2109 * writable portion of the 'defined' part of type 0 headers. In 2110 * theory we also need to save/restore the PCI capability structures 2111 * we know about, but apart from power we don't know any that are 2112 * writable. 2113 */ 2114 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2115 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2116 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2117 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2118 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2119 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2120 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2121 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2122 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2123 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2124 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2125 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2126 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2127 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2128 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2129 2130 /* 2131 * don't set the state for display devices, base peripherals and 2132 * memory devices since bad things happen when they are powered down. 2133 * We should (a) have drivers that can easily detach and (b) use 2134 * generic drivers for these devices so that some device actually 2135 * attaches. We need to make sure that when we implement (a) we don't 2136 * power the device down on a reattach. 2137 */ 2138 cls = pci_get_class(dev); 2139 if (!setstate) 2140 return; 2141 switch (pci_do_power_nodriver) 2142 { 2143 case 0: /* NO powerdown at all */ 2144 return; 2145 case 1: /* Conservative about what to power down */ 2146 if (cls == PCIC_STORAGE) 2147 return; 2148 /*FALLTHROUGH*/ 2149 case 2: /* Agressive about what to power down */ 2150 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2151 cls == PCIC_BASEPERIPH) 2152 return; 2153 /*FALLTHROUGH*/ 2154 case 3: /* Power down everything */ 2155 break; 2156 } 2157 /* 2158 * PCI spec says we can only go into D3 state from D0 state. 2159 * Transition from D[12] into D0 before going to D3 state. 2160 */ 2161 ps = pci_get_powerstate(dev); 2162 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2163 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2164 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2165 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2166} 2167