pci.c revision 151645
1139778Simp/*- 212115Sdyson * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 312115Sdyson * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 412115Sdyson * Copyright (c) 2000, BSDi 512115Sdyson * All rights reserved. 612115Sdyson * 7139778Simp * Redistribution and use in source and binary forms, with or without 812115Sdyson * modification, are permitted provided that the following conditions 912115Sdyson * are met: 1012115Sdyson * 1. Redistributions of source code must retain the above copyright 1112115Sdyson * notice unmodified, this list of conditions, and the following 1212115Sdyson * disclaimer. 1312115Sdyson * 2. Redistributions in binary form must reproduce the above copyright 1412115Sdyson * notice, this list of conditions and the following disclaimer in the 1512115Sdyson * documentation and/or other materials provided with the distribution. 1612115Sdyson * 1712115Sdyson * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1812115Sdyson * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1912115Sdyson * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2012115Sdyson * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2112115Sdyson * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2212115Sdyson * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312115Sdyson * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412115Sdyson * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512115Sdyson * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2612115Sdyson * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712115Sdyson */ 2812115Sdyson 2912115Sdyson#include <sys/cdefs.h> 3012115Sdyson__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 151645 2005-10-25 06:53:45Z wpaul $"); 3112115Sdyson 3212115Sdyson#include "opt_bus.h" 3312115Sdyson 3412115Sdyson#include <sys/param.h> 3512115Sdyson#include <sys/systm.h> 3612115Sdyson#include <sys/malloc.h> 3712115Sdyson#include <sys/module.h> 3812115Sdyson#include <sys/linker.h> 3912115Sdyson#include <sys/fcntl.h> 4012115Sdyson#include <sys/conf.h> 4193016Sbde#include <sys/kernel.h> 4212115Sdyson#include <sys/queue.h> 4312115Sdyson#include <sys/sysctl.h> 4412115Sdyson#include <sys/types.h> 4512159Sbde 4612115Sdyson#include <vm/vm.h> 4760041Sphk#include <vm/pmap.h> 4812115Sdyson#include <vm/vm_extern.h> 49193377Sstas 5012115Sdyson#include <sys/bus.h> 5112115Sdyson#include <machine/bus.h> 5212115Sdyson#include <sys/rman.h> 5312115Sdyson#include <machine/resource.h> 5496753Siedowse 5512115Sdyson#include <sys/pciio.h> 5612115Sdyson#include <dev/pci/pcireg.h> 5712115Sdyson#include <dev/pci/pcivar.h> 58202283Slulf#include <dev/pci/pci_private.h> 59202283Slulf 60202283Slulf#include "pcib_if.h" 61202283Slulf#include "pci_if.h" 62202283Slulf 6312115Sdyson#if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 6496753Siedowse defined (__ia64__) 6596753Siedowse#include <contrib/dev/acpica/acpi.h> 6696753Siedowse#include "acpi_if.h" 6796753Siedowse#else 6896753Siedowse#define ACPI_PWR_FOR_SLEEP(x, y, z) 6996753Siedowse#endif 70141633Sphk 7196753Siedowsestatic uint32_t pci_mapbase(unsigned mapreg); 7296753Siedowsestatic int pci_maptype(unsigned mapreg); 73111742Sdesstatic int pci_mapsize(unsigned testval); 7412115Sdysonstatic int pci_maprange(unsigned mapreg); 7512115Sdysonstatic void pci_fixancient(pcicfgregs *cfg); 7612115Sdyson 7712115Sdysonstatic int pci_porten(device_t pcib, int b, int s, int f); 7812115Sdysonstatic int pci_memen(device_t pcib, int b, int s, int f); 7912115Sdysonstatic void pci_assign_interrupt(device_t bus, device_t dev, 8055477Sbde int force_route); 8155477Sbdestatic int pci_add_map(device_t pcib, device_t bus, device_t dev, 8255477Sbde int b, int s, int f, int reg, 8355477Sbde struct resource_list *rl); 8455477Sbdestatic void pci_add_resources(device_t pcib, device_t bus, 8555477Sbde device_t dev); 8655477Sbdestatic int pci_probe(device_t dev); 8755477Sbdestatic int pci_attach(device_t dev); 8855477Sbdestatic void pci_load_vendor_data(void); 8955477Sbdestatic int pci_describe_parse_line(char **ptr, int *vendor, 9055477Sbde int *device, char **desc); 9155477Sbdestatic char *pci_describe_device(device_t dev); 9255477Sbdestatic int pci_modevent(module_t mod, int what, void *arg); 9355477Sbdestatic void pci_hdrtypedata(device_t pcib, int b, int s, int f, 9455477Sbde pcicfgregs *cfg); 9555477Sbdestatic void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 9655477Sbde 9755477Sbdestatic device_method_t pci_methods[] = { 9855477Sbde /* Device interface */ 9955477Sbde DEVMETHOD(device_probe, pci_probe), 10055477Sbde DEVMETHOD(device_attach, pci_attach), 10155477Sbde DEVMETHOD(device_detach, bus_generic_detach), 10255477Sbde DEVMETHOD(device_shutdown, bus_generic_shutdown), 10355477Sbde DEVMETHOD(device_suspend, pci_suspend), 10455477Sbde DEVMETHOD(device_resume, pci_resume), 10555477Sbde 10655477Sbde /* Bus interface */ 10755477Sbde DEVMETHOD(bus_print_child, pci_print_child), 10855477Sbde DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 10955477Sbde DEVMETHOD(bus_read_ivar, pci_read_ivar), 11055477Sbde DEVMETHOD(bus_write_ivar, pci_write_ivar), 11155477Sbde DEVMETHOD(bus_driver_added, pci_driver_added), 11255477Sbde DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 11355477Sbde DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 11455477Sbde 115202283Slulf DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 11693014Sbde DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 11712159Sbde DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 11812115Sdyson DEVMETHOD(bus_delete_resource, pci_delete_resource), 11912115Sdyson DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 12012115Sdyson DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 12112115Sdyson DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 12212115Sdyson DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 12312115Sdyson DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 12412115Sdyson DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 12512115Sdyson 12612115Sdyson /* PCI interface */ 12712115Sdyson DEVMETHOD(pci_read_config, pci_read_config_method), 12812115Sdyson DEVMETHOD(pci_write_config, pci_write_config_method), 12912115Sdyson DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 13012115Sdyson DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 131111742Sdes DEVMETHOD(pci_enable_io, pci_enable_io_method), 13212115Sdyson DEVMETHOD(pci_disable_io, pci_disable_io_method), 13312115Sdyson DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 13412115Sdyson DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 13512115Sdyson DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 13612115Sdyson 13712115Sdyson { 0, 0 } 138111742Sdes}; 139111742Sdes 140111742SdesDEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 141111742Sdes 142111742Sdesdevclass_t pci_devclass; 14312115SdysonDRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 144111742SdesMODULE_VERSION(pci, 1); 145111742Sdes 14612115Sdysonstatic char *pci_vendordata; 147202283Slulfstatic size_t pci_vendordata_size; 14824649Sdfr 14912115Sdyson 15012115Sdysonstruct pci_quirk { 15112115Sdyson uint32_t devid; /* Vendor/device of the card */ 15212115Sdyson int type; 153202283Slulf#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 15412115Sdyson int arg1; 15565780Sbde int arg2; 15612115Sdyson}; 15765780Sbde 15865780Sbdestruct pci_quirk pci_quirks[] = { 15965780Sbde /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 16065780Sbde { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 16165780Sbde { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 16265780Sbde /* As does the Serverworks OSB4 (the SMBus mapping register) */ 16365780Sbde { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 16465780Sbde 16565780Sbde { 0 } 16665780Sbde}; 16765780Sbde 16865780Sbde/* map register information */ 16912115Sdyson#define PCI_MAPMEM 0x01 /* memory map */ 17012115Sdyson#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 17112115Sdyson#define PCI_MAPPORT 0x04 /* port map */ 17265780Sbde 17312115Sdysonstruct devlist pci_devq; 17412115Sdysonuint32_t pci_generation; 175184205Sdesuint32_t pci_numdevs = 0; 17612115Sdyson 17712115Sdyson/* sysctl vars */ 17812115SdysonSYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 17912115Sdyson 180202283Slulfstatic int pci_enable_io_modes = 1; 18124649SdfrTUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 18255477SbdeSYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 183202283Slulf &pci_enable_io_modes, 1, 18455477Sbde "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 18555477Sbdeenable these bits correctly. We'd like to do this all the time, but there\n\ 18655477Sbdeare some peripherals that this causes problems with."); 18755477Sbde 18855477Sbdestatic int pci_do_power_nodriver = 0; 18955477SbdeTUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 190125843SbdeSYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 19155477Sbde &pci_do_power_nodriver, 0, 19255477Sbde "Place a function into D3 state when no driver attaches to it. 0 means\n\ 19355477Sbdedisable. 1 means conservatively place devices into D3 state. 2 means\n\ 194125843Sbdeagressively place devices into D3 state. 3 means put absolutely everything\n\ 195125843Sbdein D3 state."); 19655477Sbde 19755477Sbdestatic int pci_do_power_resume = 1; 198125843SbdeTUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 19955477SbdeSYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 20055477Sbde &pci_do_power_resume, 1, 201202283Slulf "Transition from D3 -> D0 on resume."); 202202283Slulf 203202283Slulf/* Find a device_t by bus/slot/function */ 20455477Sbde 205202283Slulfdevice_t 20655477Sbdepci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 20755477Sbde{ 20855477Sbde struct pci_devinfo *dinfo; 20955477Sbde 210202283Slulf STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 21112115Sdyson if ((dinfo->cfg.bus == bus) && 21212115Sdyson (dinfo->cfg.slot == slot) && 213202283Slulf (dinfo->cfg.func == func)) { 214202283Slulf return (dinfo->cfg.dev); 215111742Sdes } 216111741Sdes } 21724649Sdfr 21824649Sdfr return (NULL); 21912115Sdyson} 22012115Sdyson 22112115Sdyson/* Find a device_t by vendor/device ID */ 22212115Sdyson 22312115Sdysondevice_t 22412115Sdysonpci_find_device(uint16_t vendor, uint16_t device) 22512115Sdyson{ 22612115Sdyson struct pci_devinfo *dinfo; 22712115Sdyson 22824649Sdfr STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 22924649Sdfr if ((dinfo->cfg.vendor == vendor) && 23065780Sbde (dinfo->cfg.device == device)) { 23124649Sdfr return (dinfo->cfg.dev); 23224649Sdfr } 23324649Sdfr } 234125843Sbde 235184205Sdes return (NULL); 236111119Simp} 23724649Sdfr 238202283Slulf/* return base address of memory or port map */ 23965780Sbde 24065780Sbdestatic uint32_t 241202283Slulfpci_mapbase(unsigned mapreg) 242202283Slulf{ 24324649Sdfr int mask = 0x03; 24424649Sdfr if ((mapreg & 0x01) == 0) 24524649Sdfr mask = 0x0f; 24624649Sdfr return (mapreg & ~mask); 24724649Sdfr} 24812115Sdyson 249184205Sdes/* return map type of memory or port map */ 25024649Sdfr 25124649Sdfrstatic int 252111742Sdespci_maptype(unsigned mapreg) 25312115Sdyson{ 25412115Sdyson static uint8_t maptype[0x10] = { 25512115Sdyson PCI_MAPMEM, PCI_MAPPORT, 25612115Sdyson PCI_MAPMEM, 0, 25712115Sdyson PCI_MAPMEM, PCI_MAPPORT, 25812115Sdyson 0, 0, 25912115Sdyson PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 26012115Sdyson PCI_MAPMEM|PCI_MAPMEMP, 0, 26112115Sdyson PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 26212115Sdyson 0, 0, 26312115Sdyson }; 26412115Sdyson 26512115Sdyson return maptype[mapreg & 0x0f]; 26612115Sdyson} 26712115Sdyson 26812115Sdyson/* return log2 of map size decoded for memory or port map */ 26912115Sdyson 27012115Sdysonstatic int 27112115Sdysonpci_mapsize(unsigned testval) 272125843Sbde{ 27312115Sdyson int ln2size; 27412115Sdyson 27512115Sdyson testval = pci_mapbase(testval); 27612115Sdyson ln2size = 0; 27712115Sdyson if (testval != 0) { 27812115Sdyson while ((testval & 1) == 0) 27912115Sdyson { 28012115Sdyson ln2size++; 28112115Sdyson testval >>= 1; 28212115Sdyson } 28312115Sdyson } 28412115Sdyson return (ln2size); 28512115Sdyson} 28612115Sdyson 28728787Sphk/* return log2 of address range supported by map register */ 28812115Sdyson 28912115Sdysonstatic int 29012115Sdysonpci_maprange(unsigned mapreg) 29112115Sdyson{ 29212115Sdyson int ln2range = 0; 29396752Siedowse switch (mapreg & 0x07) { 29496752Siedowse case 0x00: 29512115Sdyson case 0x01: 296202283Slulf case 0x05: 29712115Sdyson ln2range = 32; 29812115Sdyson break; 29912115Sdyson case 0x02: 30012115Sdyson ln2range = 20; 301202283Slulf break; 302202283Slulf case 0x04: 30312115Sdyson ln2range = 64; 30412115Sdyson break; 30512115Sdyson } 30612115Sdyson return (ln2range); 30712115Sdyson} 30812115Sdyson 30912115Sdyson/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 31012115Sdyson 31112115Sdysonstatic void 31212115Sdysonpci_fixancient(pcicfgregs *cfg) 31312115Sdyson{ 31412115Sdyson if (cfg->hdrtype != 0) 31512115Sdyson return; 31612115Sdyson 31712115Sdyson /* PCI to PCI bridges use header type 1 */ 318202283Slulf if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 319202283Slulf cfg->hdrtype = 1; 32012115Sdyson} 321202283Slulf 32212115Sdyson/* extract header type specific config data */ 32312115Sdyson 32412115Sdysonstatic void 32512115Sdysonpci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 32612115Sdyson{ 32712115Sdyson#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 328217584Sjhb switch (cfg->hdrtype) { 329217584Sjhb case 0: 33012115Sdyson cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 33112115Sdyson cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 33212115Sdyson cfg->nummaps = PCI_MAXMAPS_0; 33312115Sdyson break; 33412115Sdyson case 1: 33512115Sdyson cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 33612115Sdyson cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 33712115Sdyson cfg->nummaps = PCI_MAXMAPS_1; 33812115Sdyson break; 33912115Sdyson case 2: 340202283Slulf cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 341202283Slulf cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 34212115Sdyson cfg->nummaps = PCI_MAXMAPS_2; 34312115Sdyson break; 34412115Sdyson } 34512115Sdyson#undef REG 34612115Sdyson} 347111742Sdes 34812115Sdyson/* read configuration header into pcicfgregs structure */ 34912115Sdyson 35012115Sdysonstruct pci_devinfo * 35112115Sdysonpci_read_device(device_t pcib, int b, int s, int f, size_t size) 35212115Sdyson{ 35312115Sdyson#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 35412115Sdyson pcicfgregs *cfg = NULL; 35512115Sdyson struct pci_devinfo *devlist_entry; 35612115Sdyson struct devlist *devlist_head; 35712115Sdyson 35812115Sdyson devlist_head = &pci_devq; 35912115Sdyson 36012115Sdyson devlist_entry = NULL; 36112115Sdyson 36212115Sdyson if (REG(PCIR_DEVVENDOR, 4) != -1) { 36312115Sdyson devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 364202283Slulf if (devlist_entry == NULL) 365202283Slulf return (NULL); 36612115Sdyson 367202283Slulf cfg = &devlist_entry->cfg; 36812115Sdyson 36912115Sdyson cfg->bus = b; 370202283Slulf cfg->slot = s; 371202283Slulf cfg->func = f; 372202283Slulf cfg->vendor = REG(PCIR_VENDOR, 2); 37396749Siedowse cfg->device = REG(PCIR_DEVICE, 2); 37412115Sdyson cfg->cmdreg = REG(PCIR_COMMAND, 2); 37512115Sdyson cfg->statreg = REG(PCIR_STATUS, 2); 37612115Sdyson cfg->baseclass = REG(PCIR_CLASS, 1); 37712115Sdyson cfg->subclass = REG(PCIR_SUBCLASS, 1); 378202283Slulf cfg->progif = REG(PCIR_PROGIF, 1); 379202283Slulf cfg->revid = REG(PCIR_REVID, 1); 38012115Sdyson cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 38112115Sdyson cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 38212115Sdyson cfg->lattimer = REG(PCIR_LATTIMER, 1); 383202283Slulf cfg->intpin = REG(PCIR_INTPIN, 1); 38412115Sdyson cfg->intline = REG(PCIR_INTLINE, 1); 38512115Sdyson 38612115Sdyson cfg->mingnt = REG(PCIR_MINGNT, 1); 387202283Slulf cfg->maxlat = REG(PCIR_MAXLAT, 1); 38812115Sdyson 38912115Sdyson cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 39043301Sdillon cfg->hdrtype &= ~PCIM_MFDEV; 391202283Slulf 39296749Siedowse pci_fixancient(cfg); 39312115Sdyson pci_hdrtypedata(pcib, b, s, f, cfg); 39412115Sdyson 39512115Sdyson if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 39612115Sdyson pci_read_extcap(pcib, cfg); 39712115Sdyson 39812115Sdyson STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 39912115Sdyson 40012115Sdyson devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 40112115Sdyson devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 40212115Sdyson devlist_entry->conf.pc_sel.pc_func = cfg->func; 40312115Sdyson devlist_entry->conf.pc_hdr = cfg->hdrtype; 40412115Sdyson 40512115Sdyson devlist_entry->conf.pc_subvendor = cfg->subvendor; 40612115Sdyson devlist_entry->conf.pc_subdevice = cfg->subdevice; 40712115Sdyson devlist_entry->conf.pc_vendor = cfg->vendor; 40812115Sdyson devlist_entry->conf.pc_device = cfg->device; 40996753Siedowse 41096753Siedowse devlist_entry->conf.pc_class = cfg->baseclass; 41112115Sdyson devlist_entry->conf.pc_subclass = cfg->subclass; 412202283Slulf devlist_entry->conf.pc_progif = cfg->progif; 41312115Sdyson devlist_entry->conf.pc_revid = cfg->revid; 414202283Slulf 41512147Sdyson pci_numdevs++; 41612115Sdyson pci_generation++; 417202283Slulf } 41812115Sdyson return (devlist_entry); 419202283Slulf#undef REG 42012115Sdyson} 42112115Sdyson 42212115Sdysonstatic void 42312115Sdysonpci_read_extcap(device_t pcib, pcicfgregs *cfg) 42412115Sdyson{ 42512115Sdyson#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 42612115Sdyson int ptr, nextptr, ptrptr; 42712115Sdyson 42812115Sdyson switch (cfg->hdrtype & PCIM_HDRTYPE) { 42912115Sdyson case 0: 43012115Sdyson ptrptr = PCIR_CAP_PTR; 431202283Slulf break; 43212115Sdyson case 2: 433202283Slulf ptrptr = 0x14; 434202283Slulf break; 43512115Sdyson default: 43612115Sdyson return; /* no extended capabilities support */ 43712115Sdyson } 438202283Slulf nextptr = REG(ptrptr, 1); /* sanity check? */ 439202283Slulf 44012115Sdyson /* 44112115Sdyson * Read capability entries. 44212115Sdyson */ 443202283Slulf while (nextptr != 0) { 44412115Sdyson /* Sanity check */ 44512115Sdyson if (nextptr > 255) { 446202283Slulf printf("illegal PCI extended capability offset %d\n", 447202283Slulf nextptr); 44812115Sdyson return; 44912115Sdyson } 45012115Sdyson /* Find the next entry */ 45112115Sdyson ptr = nextptr; 45212115Sdyson nextptr = REG(ptr + 1, 1); 45312115Sdyson 45412115Sdyson /* Process this entry */ 45512115Sdyson switch (REG(ptr, 1)) { 456202283Slulf case PCIY_PMG: /* PCI power management */ 457202283Slulf if (cfg->pp.pp_cap == 0) { 45812115Sdyson cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 459202283Slulf cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 46012115Sdyson cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 46112115Sdyson if ((nextptr - ptr) > PCIR_POWER_DATA) 46212115Sdyson cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 46312115Sdyson } 46412115Sdyson break; 46512115Sdyson case PCIY_MSI: /* PCI MSI */ 466202283Slulf cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 46712115Sdyson if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 46812115Sdyson cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 46912115Sdyson else 470202283Slulf cfg->msi.msi_data = PCIR_MSI_DATA; 471202283Slulf cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 472202283Slulf PCIM_MSICTRL_MMC_MASK)>>1); 473202283Slulf default: 474202283Slulf break; 47512115Sdyson } 47612115Sdyson } 47712115Sdyson#undef REG 47812115Sdyson} 47912115Sdyson 48012115Sdyson/* free pcicfgregs structure and all depending data structures */ 48112115Sdyson 48212115Sdysonint 483202283Slulfpci_freecfg(struct pci_devinfo *dinfo) 484202283Slulf{ 48512115Sdyson struct devlist *devlist_head; 48612115Sdyson 487202283Slulf devlist_head = &pci_devq; 48812115Sdyson 48912115Sdyson STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 49012115Sdyson free(dinfo, M_DEVBUF); 49112115Sdyson 49212115Sdyson /* increment the generation count */ 49312115Sdyson pci_generation++; 49412115Sdyson 49512115Sdyson /* we're losing one device */ 49612115Sdyson pci_numdevs--; 49712115Sdyson return (0); 49812115Sdyson} 49912115Sdyson 50012115Sdyson/* 50183366Sjulian * PCI power manangement 50212115Sdyson */ 50312115Sdysonint 50412115Sdysonpci_set_powerstate_method(device_t dev, device_t child, int state) 50512115Sdyson{ 50612115Sdyson struct pci_devinfo *dinfo = device_get_ivars(child); 50712115Sdyson pcicfgregs *cfg = &dinfo->cfg; 50812115Sdyson uint16_t status; 50912115Sdyson int result, oldstate, highest, delay; 51012115Sdyson 51112115Sdyson if (cfg->pp.pp_cap == 0) 51212115Sdyson return (EOPNOTSUPP); 513202283Slulf 51412115Sdyson /* 51512115Sdyson * Optimize a no state change request away. While it would be OK to 51612115Sdyson * write to the hardware in theory, some devices have shown odd 51712115Sdyson * behavior when going from D3 -> D3. 51812115Sdyson */ 51912115Sdyson oldstate = pci_get_powerstate(child); 52012115Sdyson if (oldstate == state) 52112115Sdyson return (0); 522202283Slulf 52312115Sdyson /* 52412115Sdyson * The PCI power management specification states that after a state 52512115Sdyson * transition between PCI power states, system software must 52612115Sdyson * guarantee a minimal delay before the function accesses the device. 52712115Sdyson * Compute the worst case delay that we need to guarantee before we 52812115Sdyson * access the device. Many devices will be responsive much more 52912115Sdyson * quickly than this delay, but there are some that don't respond 53012115Sdyson * instantly to state changes. Transitions to/from D3 state require 53112115Sdyson * 10ms, while D2 requires 200us, and D0/1 require none. The delay 53212115Sdyson * is done below with DELAY rather than a sleeper function because 53312115Sdyson * this function can be called from contexts where we cannot sleep. 53412115Sdyson */ 53512115Sdyson highest = (oldstate > state) ? oldstate : state; 53612115Sdyson if (highest == PCI_POWERSTATE_D3) 53712115Sdyson delay = 10000; 53812115Sdyson else if (highest == PCI_POWERSTATE_D2) 53912115Sdyson delay = 200; 54012115Sdyson else 54112115Sdyson delay = 0; 54212115Sdyson status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 54312115Sdyson & ~PCIM_PSTAT_DMASK; 54412115Sdyson result = 0; 54512115Sdyson switch (state) { 54612115Sdyson case PCI_POWERSTATE_D0: 54712115Sdyson status |= PCIM_PSTAT_D0; 54812115Sdyson break; 54912115Sdyson case PCI_POWERSTATE_D1: 55012115Sdyson if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 55112115Sdyson return (EOPNOTSUPP); 55212115Sdyson status |= PCIM_PSTAT_D1; 55312115Sdyson break; 554202283Slulf case PCI_POWERSTATE_D2: 55512115Sdyson if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 556202283Slulf return (EOPNOTSUPP); 557202283Slulf status |= PCIM_PSTAT_D2; 55812115Sdyson break; 55912115Sdyson case PCI_POWERSTATE_D3: 560105420Sbde status |= PCIM_PSTAT_D3; 56112115Sdyson break; 56212115Sdyson default: 56312115Sdyson return (EINVAL); 56412115Sdyson } 56512115Sdyson 56612115Sdyson if (bootverbose) 56712115Sdyson printf( 568202283Slulf "pci%d:%d:%d: Transition from D%d to D%d\n", 569202283Slulf dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 57012115Sdyson oldstate, state); 57112115Sdyson 57212115Sdyson PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 57312115Sdyson if (delay) 57412115Sdyson DELAY(delay); 57512115Sdyson return (0); 57612115Sdyson} 57712115Sdyson 57883366Sjulianint 57912115Sdysonpci_get_powerstate_method(device_t dev, device_t child) 58012115Sdyson{ 58112115Sdyson struct pci_devinfo *dinfo = device_get_ivars(child); 58212115Sdyson pcicfgregs *cfg = &dinfo->cfg; 58312115Sdyson uint16_t status; 58412115Sdyson int result; 58512115Sdyson 58612115Sdyson if (cfg->pp.pp_cap != 0) { 58712115Sdyson status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 58812115Sdyson switch (status & PCIM_PSTAT_DMASK) { 58912115Sdyson case PCIM_PSTAT_D0: 590202283Slulf result = PCI_POWERSTATE_D0; 59112115Sdyson break; 59212115Sdyson case PCIM_PSTAT_D1: 59312115Sdyson result = PCI_POWERSTATE_D1; 59412115Sdyson break; 595202283Slulf case PCIM_PSTAT_D2: 59692462Smckusick result = PCI_POWERSTATE_D2; 59712115Sdyson break; 59812115Sdyson case PCIM_PSTAT_D3: 59912115Sdyson result = PCI_POWERSTATE_D3; 60012115Sdyson break; 60112115Sdyson default: 60212115Sdyson result = PCI_POWERSTATE_UNKNOWN; 60312115Sdyson break; 60412115Sdyson } 60512115Sdyson } else { 60612115Sdyson /* No support, device is always at D0 */ 60712115Sdyson result = PCI_POWERSTATE_D0; 60812115Sdyson } 60912115Sdyson return (result); 61012115Sdyson} 61112115Sdyson 61212115Sdyson/* 61312115Sdyson * Some convenience functions for PCI device drivers. 61412115Sdyson */ 61512115Sdyson 61612115Sdysonstatic __inline void 61712115Sdysonpci_set_command_bit(device_t dev, device_t child, uint16_t bit) 61812115Sdyson{ 61912115Sdyson uint16_t command; 62012115Sdyson 621144299Sjeff command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 62283366Sjulian command |= bit; 62312115Sdyson PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 62412115Sdyson} 62512115Sdyson 62612115Sdysonstatic __inline void 62712115Sdysonpci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 628202283Slulf{ 62912115Sdyson uint16_t command; 630202283Slulf 63192462Smckusick command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 63212115Sdyson command &= ~bit; 63312115Sdyson PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 63412115Sdyson} 63512115Sdyson 63612115Sdysonint 63712115Sdysonpci_enable_busmaster_method(device_t dev, device_t child) 63812115Sdyson{ 63912115Sdyson pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 64012115Sdyson return (0); 64112115Sdyson} 64212115Sdyson 64312115Sdysonint 64412115Sdysonpci_disable_busmaster_method(device_t dev, device_t child) 64512115Sdyson{ 64612115Sdyson pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 64712115Sdyson return (0); 64812115Sdyson} 64912115Sdyson 65012115Sdysonint 65112115Sdysonpci_enable_io_method(device_t dev, device_t child, int space) 65212115Sdyson{ 65312115Sdyson uint16_t command; 65412115Sdyson uint16_t bit; 65512115Sdyson char *error; 65612115Sdyson 65712115Sdyson bit = 0; 65812115Sdyson error = NULL; 659202283Slulf 660175294Sattilio switch(space) { 661202283Slulf case SYS_RES_IOPORT: 662202283Slulf bit = PCIM_CMD_PORTEN; 663145006Sjeff error = "port"; 66412115Sdyson break; 66512115Sdyson case SYS_RES_MEMORY: 666202283Slulf bit = PCIM_CMD_MEMEN; 66712115Sdyson error = "memory"; 668202283Slulf break; 669202283Slulf default: 670202283Slulf return (EINVAL); 671202283Slulf } 672202283Slulf pci_set_command_bit(dev, child, bit); 673202283Slulf /* Some devices seem to need a brief stall here, what do to? */ 674202283Slulf command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 675202283Slulf if (command & bit) 676202283Slulf return (0); 677202283Slulf device_printf(child, "failed to enable %s mapping!\n", error); 678202283Slulf return (ENXIO); 67912115Sdyson} 68012115Sdyson 681202283Slulfint 68292462Smckusickpci_disable_io_method(device_t dev, device_t child, int space) 68312115Sdyson{ 68412115Sdyson uint16_t command; 68512115Sdyson uint16_t bit; 68612115Sdyson char *error; 68712115Sdyson 68812115Sdyson bit = 0; 68912115Sdyson error = NULL; 69012115Sdyson 69112115Sdyson switch(space) { 69212115Sdyson case SYS_RES_IOPORT: 69312115Sdyson bit = PCIM_CMD_PORTEN; 69412115Sdyson error = "port"; 69596749Siedowse break; 69696749Siedowse case SYS_RES_MEMORY: 69796749Siedowse bit = PCIM_CMD_MEMEN; 69896749Siedowse error = "memory"; 69996749Siedowse break; 70096749Siedowse default: 70196749Siedowse return (EINVAL); 70296749Siedowse } 70396749Siedowse pci_clear_command_bit(dev, child, bit); 704202283Slulf command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 705202283Slulf if (command & bit) { 706202283Slulf device_printf(child, "failed to disable %s mapping!\n", error); 707202283Slulf return (ENXIO); 70896749Siedowse } 709202283Slulf return (0); 710202283Slulf} 71196749Siedowse 71296749Siedowse/* 71312115Sdyson * New style pci driver. Parent device is either a pci-host-bridge or a 71412115Sdyson * pci-pci-bridge. Both kinds are represented by instances of pcib. 71512115Sdyson */ 71612115Sdyson 71712115Sdysonvoid 71812115Sdysonpci_print_verbose(struct pci_devinfo *dinfo) 71912115Sdyson{ 72012115Sdyson if (bootverbose) { 72112115Sdyson pcicfgregs *cfg = &dinfo->cfg; 72212115Sdyson 72312115Sdyson printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 72412159Sbde cfg->vendor, cfg->device, cfg->revid); 72512115Sdyson printf("\tbus=%d, slot=%d, func=%d\n", 72612115Sdyson cfg->bus, cfg->slot, cfg->func); 727202283Slulf printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 72812115Sdyson cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 72912115Sdyson cfg->mfdev); 730202283Slulf printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 73112115Sdyson cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 732111742Sdes printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 73312115Sdyson cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 734202283Slulf cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 735111742Sdes if (cfg->intpin > 0) 736202283Slulf printf("\tintpin=%c, irq=%d\n", 737111742Sdes cfg->intpin +'a' -1, cfg->intline); 738202283Slulf if (cfg->pp.pp_cap) { 739111742Sdes uint16_t status; 740202283Slulf 741111742Sdes status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 742111742Sdes printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 74312115Sdyson cfg->pp.pp_cap & PCIM_PCAP_SPEC, 744111742Sdes cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 74512115Sdyson cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 74612115Sdyson status & PCIM_PSTAT_DMASK); 747111742Sdes } 748111742Sdes if (cfg->msi.msi_data) { 749111742Sdes int ctrl; 750202283Slulf 751202283Slulf ctrl = cfg->msi.msi_ctrl; 752111742Sdes printf("\tMSI supports %d message%s%s%s\n", 753111742Sdes cfg->msi.msi_msgnum, 75412115Sdyson (cfg->msi.msi_msgnum == 1) ? "" : "s", 75512115Sdyson (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 75612115Sdyson (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 75712115Sdyson } 75812115Sdyson } 75912115Sdyson} 76012115Sdyson 76112115Sdysonstatic int 76212115Sdysonpci_porten(device_t pcib, int b, int s, int f) 76312115Sdyson{ 76412115Sdyson return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 76512115Sdyson & PCIM_CMD_PORTEN) != 0; 76612115Sdyson} 76712115Sdyson 76896752Siedowsestatic int 76912115Sdysonpci_memen(device_t pcib, int b, int s, int f) 770202283Slulf{ 77196752Siedowse return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 77212115Sdyson & PCIM_CMD_MEMEN) != 0; 773202283Slulf} 77412115Sdyson 77512115Sdyson/* 77612115Sdyson * Add a resource based on a pci map register. Return 1 if the map 77712115Sdyson * register is a 32bit map register or 2 if it is a 64bit register. 77812115Sdyson */ 779202283Slulfstatic int 78012115Sdysonpci_add_map(device_t pcib, device_t bus, device_t dev, 78112115Sdyson int b, int s, int f, int reg, struct resource_list *rl) 782153110Sru{ 78312115Sdyson uint32_t map; 78412115Sdyson uint64_t base; 78512115Sdyson uint64_t start, end, count; 78612115Sdyson uint8_t ln2size; 787202283Slulf uint8_t ln2range; 788202283Slulf uint32_t testval; 789193377Sstas uint16_t cmd; 790202283Slulf int type; 791202283Slulf int barlen; 79255477Sbde 793202283Slulf map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 794202283Slulf PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 795202283Slulf testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 79612115Sdyson PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 79712115Sdyson 79812115Sdyson if (pci_maptype(map) & PCI_MAPMEM) 79912115Sdyson type = SYS_RES_MEMORY; 80012115Sdyson else 80112115Sdyson type = SYS_RES_IOPORT; 80212115Sdyson ln2size = pci_mapsize(testval); 80312115Sdyson ln2range = pci_maprange(testval); 80412115Sdyson base = pci_mapbase(map); 80512115Sdyson barlen = ln2range == 64 ? 2 : 1; 806202283Slulf 80712115Sdyson /* 80812115Sdyson * For I/O registers, if bottom bit is set, and the next bit up 80912115Sdyson * isn't clear, we know we have a BAR that doesn't conform to the 81012115Sdyson * spec, so ignore it. Also, sanity check the size of the data 81112115Sdyson * areas to the type of memory involved. Memory must be at least 81212115Sdyson * 32 bytes in size, while I/O ranges must be at least 4. 81312115Sdyson */ 81483366Sjulian if ((testval & 0x1) == 0x1 && 81512115Sdyson (testval & 0x2) != 0) 81612115Sdyson return (barlen); 81796749Siedowse if ((type == SYS_RES_MEMORY && ln2size < 5) || 81812115Sdyson (type == SYS_RES_IOPORT && ln2size < 2)) 81912115Sdyson return (barlen); 82012115Sdyson 821202283Slulf if (ln2range == 64) 82212115Sdyson /* Read the other half of a 64bit map register */ 82312115Sdyson base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 82412115Sdyson 82512115Sdyson if (bootverbose) { 82612115Sdyson printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 82712115Sdyson reg, pci_maptype(map), ln2range, 82812115Sdyson (unsigned int) base, ln2size); 82912115Sdyson if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 83012115Sdyson printf(", port disabled\n"); 83112115Sdyson else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 83212115Sdyson printf(", memory disabled\n"); 83312115Sdyson else 83412115Sdyson printf(", enabled\n"); 83512115Sdyson } 83612115Sdyson 83712115Sdyson /* 83812115Sdyson * If base is 0, then we have problems. It is best to ignore 83912115Sdyson * such entries for the moment. These will be allocated later if 84012115Sdyson * the driver specifically requests them. 84112115Sdyson * 84212115Sdyson * Similarly treat maps whose values is the same as the test value 84312115Sdyson * read back. These maps have had all f's written to them by the 84412115Sdyson * BIOS in an attempt to disable the resources. 84512115Sdyson */ 84612115Sdyson if (base == 0 || map == testval) 84712115Sdyson return (barlen); 84896749Siedowse 84996749Siedowse /* 85012115Sdyson * This code theoretically does the right thing, but has 85112115Sdyson * undesirable side effects in some cases where peripherals 85212115Sdyson * respond oddly to having these bits enabled. Let the user 85312115Sdyson * be able to turn them off (since pci_enable_io_modes is 1 by 85412115Sdyson * default). 85512115Sdyson */ 85612115Sdyson if (pci_enable_io_modes) { 85712115Sdyson /* Turn on resources that have been left off by a lazy BIOS */ 858202283Slulf if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 859202283Slulf cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 860202283Slulf cmd |= PCIM_CMD_PORTEN; 861202283Slulf PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 862202283Slulf } 863202283Slulf if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 86412115Sdyson cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 865202283Slulf cmd |= PCIM_CMD_MEMEN; 866202283Slulf PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 86712115Sdyson } 86812115Sdyson } else { 86912115Sdyson if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 87012115Sdyson return (barlen); 871202283Slulf if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 872202283Slulf return (barlen); 873202283Slulf } 87412115Sdyson 87512115Sdyson start = base; 87612115Sdyson end = base + (1 << ln2size) - 1; 87712115Sdyson count = 1 << ln2size; 87812115Sdyson resource_list_add(rl, type, reg, start, end, count); 87912115Sdyson 880202283Slulf /* 88112115Sdyson * Not quite sure what to do on failure of allocating the resource 88212115Sdyson * since I can postulate several right answers. 883202283Slulf */ 88412115Sdyson resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 88512115Sdyson return (barlen); 88612115Sdyson} 887202283Slulf 888202283Slulf/* 889202283Slulf * For ATA devices we need to decide early what addressing mode to use. 89012115Sdyson * Legacy demands that the primary and secondary ATA ports sits on the 89112115Sdyson * same addresses that old ISA hardware did. This dictates that we use 892126853Sphk * those addresses and ignore the BAR's if we cannot set PCI native 89312115Sdyson * addressing mode. 89412115Sdyson */ 89596749Siedowsestatic void 89683366Sjulianpci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 89712115Sdyson int s, int f, struct resource_list *rl) 89812115Sdyson{ 89912115Sdyson int rid, type, progif; 90012115Sdyson#if 0 90112115Sdyson /* if this device supports PCI native addressing use it */ 90212115Sdyson progif = pci_read_config(dev, PCIR_PROGIF, 1); 90312115Sdyson if ((progif & 0x8a) == 0x8a) { 90412115Sdyson if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 90512115Sdyson pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 90612115Sdyson printf("Trying ATA native PCI addressing mode\n"); 90712115Sdyson pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 90812115Sdyson } 90912115Sdyson } 91012115Sdyson#endif 91112115Sdyson progif = pci_read_config(dev, PCIR_PROGIF, 1); 91212115Sdyson type = SYS_RES_IOPORT; 91312115Sdyson if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 91412115Sdyson pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 91512115Sdyson pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 91612115Sdyson } 91796752Siedowse else { 918202283Slulf rid = PCIR_BAR(0); 91912115Sdyson resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 92012115Sdyson resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 921111742Sdes rid = PCIR_BAR(1); 92212115Sdyson resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 92312115Sdyson resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 92412115Sdyson } 92512115Sdyson if (progif & PCIP_STORAGE_IDE_MODESEC) { 92612115Sdyson pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 92743301Sdillon pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 92896749Siedowse } 92996749Siedowse else { 93012115Sdyson rid = PCIR_BAR(2); 931202283Slulf resource_list_add(rl, type, rid, 0x170, 0x177, 8); 932126853Sphk resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 93312115Sdyson rid = PCIR_BAR(3); 93412115Sdyson resource_list_add(rl, type, rid, 0x376, 0x376, 1); 93512115Sdyson resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 93612115Sdyson } 93712115Sdyson pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 93812115Sdyson pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl); 93996749Siedowse} 94043301Sdillon 94112115Sdysonstatic void 942202283Slulfpci_assign_interrupt(device_t bus, device_t dev, int force_route) 943202283Slulf{ 944202283Slulf struct pci_devinfo *dinfo = device_get_ivars(dev); 945202283Slulf pcicfgregs *cfg = &dinfo->cfg; 946202283Slulf char tunable_name[64]; 947202283Slulf int irq; 948202283Slulf 949126853Sphk /* Has to have an intpin to have an interrupt. */ 95012115Sdyson if (cfg->intpin == 0) 95112115Sdyson return; 95212115Sdyson 95312115Sdyson /* Let the user override the IRQ with a tunable. */ 95412115Sdyson irq = PCI_INVALID_IRQ; 95512115Sdyson snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 95612115Sdyson cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 95712115Sdyson if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 95812115Sdyson irq = PCI_INVALID_IRQ; 95912115Sdyson 96012115Sdyson /* 96112115Sdyson * If we didn't get an IRQ via the tunable, then we either use the 96212115Sdyson * IRQ value in the intline register or we ask the bus to route an 96312115Sdyson * interrupt for us. If force_route is true, then we only use the 96412115Sdyson * value in the intline register if the bus was unable to assign an 965202283Slulf * IRQ. 96612115Sdyson */ 96712115Sdyson if (!PCI_INTERRUPT_VALID(irq)) { 96812115Sdyson if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 96996749Siedowse irq = PCI_ASSIGN_INTERRUPT(bus, dev); 97096749Siedowse if (!PCI_INTERRUPT_VALID(irq)) 97112115Sdyson irq = cfg->intline; 972202283Slulf } 973193377Sstas 974202283Slulf /* If after all that we don't have an IRQ, just bail. */ 975202283Slulf if (!PCI_INTERRUPT_VALID(irq)) 97655477Sbde return; 977202283Slulf 978126853Sphk /* Update the config register if it changed. */ 97912115Sdyson if (irq != cfg->intline) { 98012115Sdyson cfg->intline = irq; 98112115Sdyson pci_write_config(dev, PCIR_INTLINE, irq, 1); 98212115Sdyson } 98312115Sdyson 98412115Sdyson /* Add this IRQ as rid 0 interrupt resource. */ 98512115Sdyson resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 98612115Sdyson} 98712115Sdyson 98812115Sdysonstatic void 98912115Sdysonpci_add_resources(device_t pcib, device_t bus, device_t dev) 99012115Sdyson{ 99112115Sdyson struct pci_devinfo *dinfo = device_get_ivars(dev); 99212115Sdyson pcicfgregs *cfg = &dinfo->cfg; 99312115Sdyson struct resource_list *rl = &dinfo->resources; 99496752Siedowse struct pci_quirk *q; 99512115Sdyson int b, i, f, s; 99612115Sdyson 99712115Sdyson b = cfg->bus; 99896752Siedowse s = cfg->slot; 99912115Sdyson f = cfg->func; 1000202283Slulf 100112115Sdyson /* ATA devices needs special map treatment */ 100212115Sdyson if ((pci_get_class(dev) == PCIC_STORAGE) && 100312115Sdyson (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1004202283Slulf (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1005101744Srwatson pci_ata_maps(pcib, bus, dev, b, s, f, rl); 1006101744Srwatson else 1007101941Srwatson for (i = 0; i < cfg->nummaps;) 100812115Sdyson i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 100912115Sdyson rl); 101012115Sdyson 101112115Sdyson for (q = &pci_quirks[0]; q->devid; q++) { 101212115Sdyson if (q->devid == ((cfg->device << 16) | cfg->vendor) 101312115Sdyson && q->type == PCI_QUIRK_MAP_REG) 101412115Sdyson pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 1015202283Slulf } 101612115Sdyson 101712115Sdyson if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1018202283Slulf#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 101912115Sdyson defined(__arm__) || defined(__alpha__) 102012115Sdyson /* 1021202283Slulf * Try to re-route interrupts. Sometimes the BIOS or 102212115Sdyson * firmware may leave bogus values in these registers. 102312115Sdyson * If the re-route fails, then just stick with what we 1024202283Slulf * have. 102512115Sdyson */ 102612115Sdyson pci_assign_interrupt(bus, dev, 1); 102712115Sdyson#else 102812115Sdyson pci_assign_interrupt(bus, dev, 0); 102912115Sdyson#endif 103012115Sdyson } 103112115Sdyson} 103212115Sdyson 1033202283Slulfvoid 103412115Sdysonpci_add_children(device_t dev, int busno, size_t dinfo_size) 103512115Sdyson{ 103612115Sdyson#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 103712115Sdyson device_t pcib = device_get_parent(dev); 103812115Sdyson struct pci_devinfo *dinfo; 103912115Sdyson int maxslots; 104012115Sdyson int s, f, pcifunchigh; 104112115Sdyson uint8_t hdrtype; 104212115Sdyson 104312115Sdyson KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 104412115Sdyson ("dinfo_size too small")); 104512115Sdyson maxslots = PCIB_MAXSLOTS(pcib); 104612115Sdyson for (s = 0; s <= maxslots; s++) { 104712115Sdyson pcifunchigh = 0; 104812115Sdyson f = 0; 104912115Sdyson DELAY(1); 105012115Sdyson hdrtype = REG(PCIR_HDRTYPE, 1); 105112115Sdyson if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 105212115Sdyson continue; 105312115Sdyson if (hdrtype & PCIM_MFDEV) 105412115Sdyson pcifunchigh = PCI_FUNCMAX; 105512115Sdyson for (f = 0; f <= pcifunchigh; f++) { 105612115Sdyson dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 105712115Sdyson if (dinfo != NULL) { 105812115Sdyson pci_add_child(dev, dinfo); 105912115Sdyson } 106012115Sdyson } 106112115Sdyson } 106212115Sdyson#undef REG 106312115Sdyson} 106412115Sdyson 106512115Sdysonvoid 106612115Sdysonpci_add_child(device_t bus, struct pci_devinfo *dinfo) 106712115Sdyson{ 106812115Sdyson device_t pcib; 106912115Sdyson 107012115Sdyson pcib = device_get_parent(bus); 1071194296Skib dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1072194296Skib device_set_ivars(dinfo->cfg.dev, dinfo); 107312115Sdyson resource_list_init(&dinfo->resources); 107412115Sdyson pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 107557710Sbde pci_cfg_restore(dinfo->cfg.dev, dinfo); 107612115Sdyson pci_print_verbose(dinfo); 107712115Sdyson pci_add_resources(pcib, bus, dinfo->cfg.dev); 107812115Sdyson} 107912115Sdyson 108012115Sdysonstatic int 108112115Sdysonpci_probe(device_t dev) 108212115Sdyson{ 108312115Sdyson 108412115Sdyson device_set_desc(dev, "PCI bus"); 108512115Sdyson 108612115Sdyson /* Allow other subclasses to override this driver. */ 108712115Sdyson return (-1000); 108812115Sdyson} 108992462Smckusick 109092462Smckusickstatic int 109112115Sdysonpci_attach(device_t dev) 109212115Sdyson{ 109312115Sdyson int busno; 109412115Sdyson 109512115Sdyson /* 109612115Sdyson * Since there can be multiple independantly numbered PCI 109712115Sdyson * busses on some large alpha systems, we can't use the unit 109812115Sdyson * number to decide what bus we are probing. We ask the parent 109912115Sdyson * pcib what our bus number is. 110012115Sdyson */ 110112115Sdyson busno = pcib_get_bus(dev); 110212115Sdyson if (bootverbose) 1103 device_printf(dev, "physical bus=%d\n", busno); 1104 1105 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1106 1107 return (bus_generic_attach(dev)); 1108} 1109 1110int 1111pci_suspend(device_t dev) 1112{ 1113 int dstate, error, i, numdevs; 1114 device_t acpi_dev, child, *devlist; 1115 struct pci_devinfo *dinfo; 1116 1117 /* 1118 * Save the PCI configuration space for each child and set the 1119 * device in the appropriate power state for this sleep state. 1120 */ 1121 acpi_dev = NULL; 1122 if (pci_do_power_resume) 1123 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1124 device_get_children(dev, &devlist, &numdevs); 1125 for (i = 0; i < numdevs; i++) { 1126 child = devlist[i]; 1127 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1128 pci_cfg_save(child, dinfo, 0); 1129 } 1130 1131 /* Suspend devices before potentially powering them down. */ 1132 error = bus_generic_suspend(dev); 1133 if (error) { 1134 free(devlist, M_TEMP); 1135 return (error); 1136 } 1137 1138 /* 1139 * Always set the device to D3. If ACPI suggests a different 1140 * power state, use it instead. If ACPI is not present, the 1141 * firmware is responsible for managing device power. Skip 1142 * children who aren't attached since they are powered down 1143 * separately. Only manage type 0 devices for now. 1144 */ 1145 for (i = 0; acpi_dev && i < numdevs; i++) { 1146 child = devlist[i]; 1147 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1148 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1149 dstate = PCI_POWERSTATE_D3; 1150 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1151 pci_set_powerstate(child, dstate); 1152 } 1153 } 1154 free(devlist, M_TEMP); 1155 return (0); 1156} 1157 1158int 1159pci_resume(device_t dev) 1160{ 1161 int i, numdevs; 1162 device_t acpi_dev, child, *devlist; 1163 struct pci_devinfo *dinfo; 1164 1165 /* 1166 * Set each child to D0 and restore its PCI configuration space. 1167 */ 1168 acpi_dev = NULL; 1169 if (pci_do_power_resume) 1170 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1171 device_get_children(dev, &devlist, &numdevs); 1172 for (i = 0; i < numdevs; i++) { 1173 /* 1174 * Notify ACPI we're going to D0 but ignore the result. If 1175 * ACPI is not present, the firmware is responsible for 1176 * managing device power. Only manage type 0 devices for now. 1177 */ 1178 child = devlist[i]; 1179 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1180 if (acpi_dev && device_is_attached(child) && 1181 dinfo->cfg.hdrtype == 0) { 1182 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1183 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1184 } 1185 1186 /* Now the device is powered up, restore its config space. */ 1187 pci_cfg_restore(child, dinfo); 1188 } 1189 free(devlist, M_TEMP); 1190 return (bus_generic_resume(dev)); 1191} 1192 1193static void 1194pci_load_vendor_data(void) 1195{ 1196 caddr_t vendordata, info; 1197 1198 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1199 info = preload_search_info(vendordata, MODINFO_ADDR); 1200 pci_vendordata = *(char **)info; 1201 info = preload_search_info(vendordata, MODINFO_SIZE); 1202 pci_vendordata_size = *(size_t *)info; 1203 /* terminate the database */ 1204 pci_vendordata[pci_vendordata_size] = '\n'; 1205 } 1206} 1207 1208void 1209pci_driver_added(device_t dev, driver_t *driver) 1210{ 1211 int numdevs; 1212 device_t *devlist; 1213 device_t child; 1214 struct pci_devinfo *dinfo; 1215 int i; 1216 1217 if (bootverbose) 1218 device_printf(dev, "driver added\n"); 1219 DEVICE_IDENTIFY(driver, dev); 1220 device_get_children(dev, &devlist, &numdevs); 1221 for (i = 0; i < numdevs; i++) { 1222 child = devlist[i]; 1223 if (device_get_state(child) != DS_NOTPRESENT) 1224 continue; 1225 dinfo = device_get_ivars(child); 1226 pci_print_verbose(dinfo); 1227 if (bootverbose) 1228 printf("pci%d:%d:%d: reprobing on driver added\n", 1229 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1230 pci_cfg_restore(child, dinfo); 1231 if (device_probe_and_attach(child) != 0) 1232 pci_cfg_save(child, dinfo, 1); 1233 } 1234 free(devlist, M_TEMP); 1235} 1236 1237int 1238pci_print_child(device_t dev, device_t child) 1239{ 1240 struct pci_devinfo *dinfo; 1241 struct resource_list *rl; 1242 int retval = 0; 1243 1244 dinfo = device_get_ivars(child); 1245 rl = &dinfo->resources; 1246 1247 retval += bus_print_child_header(dev, child); 1248 1249 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1250 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1251 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1252 if (device_get_flags(dev)) 1253 retval += printf(" flags %#x", device_get_flags(dev)); 1254 1255 retval += printf(" at device %d.%d", pci_get_slot(child), 1256 pci_get_function(child)); 1257 1258 retval += bus_print_child_footer(dev, child); 1259 1260 return (retval); 1261} 1262 1263static struct 1264{ 1265 int class; 1266 int subclass; 1267 char *desc; 1268} pci_nomatch_tab[] = { 1269 {PCIC_OLD, -1, "old"}, 1270 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1271 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1272 {PCIC_STORAGE, -1, "mass storage"}, 1273 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1274 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1275 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1276 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1277 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1278 {PCIC_NETWORK, -1, "network"}, 1279 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1280 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1281 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1282 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1283 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1284 {PCIC_DISPLAY, -1, "display"}, 1285 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1286 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1287 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1288 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1289 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1290 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1291 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1292 {PCIC_MEMORY, -1, "memory"}, 1293 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1294 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1295 {PCIC_BRIDGE, -1, "bridge"}, 1296 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1297 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1298 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1299 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1300 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1301 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1302 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1303 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1304 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1305 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1306 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1307 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1308 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1309 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1310 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1311 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1312 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1313 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1314 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1315 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1316 {PCIC_INPUTDEV, -1, "input device"}, 1317 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1318 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1319 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1320 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1321 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1322 {PCIC_DOCKING, -1, "docking station"}, 1323 {PCIC_PROCESSOR, -1, "processor"}, 1324 {PCIC_SERIALBUS, -1, "serial bus"}, 1325 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1326 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1327 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1328 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1329 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1330 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1331 {PCIC_WIRELESS, -1, "wireless controller"}, 1332 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1333 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1334 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1335 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1336 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1337 {PCIC_SATCOM, -1, "satellite communication"}, 1338 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1339 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1340 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1341 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1342 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1343 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1344 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1345 {PCIC_DASP, -1, "dasp"}, 1346 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1347 {0, 0, NULL} 1348}; 1349 1350void 1351pci_probe_nomatch(device_t dev, device_t child) 1352{ 1353 int i; 1354 char *cp, *scp, *device; 1355 1356 /* 1357 * Look for a listing for this device in a loaded device database. 1358 */ 1359 if ((device = pci_describe_device(child)) != NULL) { 1360 device_printf(dev, "<%s>", device); 1361 free(device, M_DEVBUF); 1362 } else { 1363 /* 1364 * Scan the class/subclass descriptions for a general 1365 * description. 1366 */ 1367 cp = "unknown"; 1368 scp = NULL; 1369 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1370 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1371 if (pci_nomatch_tab[i].subclass == -1) { 1372 cp = pci_nomatch_tab[i].desc; 1373 } else if (pci_nomatch_tab[i].subclass == 1374 pci_get_subclass(child)) { 1375 scp = pci_nomatch_tab[i].desc; 1376 } 1377 } 1378 } 1379 device_printf(dev, "<%s%s%s>", 1380 cp ? cp : "", 1381 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1382 scp ? scp : ""); 1383 } 1384 printf(" at device %d.%d (no driver attached)\n", 1385 pci_get_slot(child), pci_get_function(child)); 1386 if (pci_do_power_nodriver) 1387 pci_cfg_save(child, 1388 (struct pci_devinfo *) device_get_ivars(child), 1); 1389 return; 1390} 1391 1392/* 1393 * Parse the PCI device database, if loaded, and return a pointer to a 1394 * description of the device. 1395 * 1396 * The database is flat text formatted as follows: 1397 * 1398 * Any line not in a valid format is ignored. 1399 * Lines are terminated with newline '\n' characters. 1400 * 1401 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1402 * the vendor name. 1403 * 1404 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1405 * - devices cannot be listed without a corresponding VENDOR line. 1406 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1407 * another TAB, then the device name. 1408 */ 1409 1410/* 1411 * Assuming (ptr) points to the beginning of a line in the database, 1412 * return the vendor or device and description of the next entry. 1413 * The value of (vendor) or (device) inappropriate for the entry type 1414 * is set to -1. Returns nonzero at the end of the database. 1415 * 1416 * Note that this is slightly unrobust in the face of corrupt data; 1417 * we attempt to safeguard against this by spamming the end of the 1418 * database with a newline when we initialise. 1419 */ 1420static int 1421pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1422{ 1423 char *cp = *ptr; 1424 int left; 1425 1426 *device = -1; 1427 *vendor = -1; 1428 **desc = '\0'; 1429 for (;;) { 1430 left = pci_vendordata_size - (cp - pci_vendordata); 1431 if (left <= 0) { 1432 *ptr = cp; 1433 return(1); 1434 } 1435 1436 /* vendor entry? */ 1437 if (*cp != '\t' && 1438 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1439 break; 1440 /* device entry? */ 1441 if (*cp == '\t' && 1442 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1443 break; 1444 1445 /* skip to next line */ 1446 while (*cp != '\n' && left > 0) { 1447 cp++; 1448 left--; 1449 } 1450 if (*cp == '\n') { 1451 cp++; 1452 left--; 1453 } 1454 } 1455 /* skip to next line */ 1456 while (*cp != '\n' && left > 0) { 1457 cp++; 1458 left--; 1459 } 1460 if (*cp == '\n' && left > 0) 1461 cp++; 1462 *ptr = cp; 1463 return(0); 1464} 1465 1466static char * 1467pci_describe_device(device_t dev) 1468{ 1469 int vendor, device; 1470 char *desc, *vp, *dp, *line; 1471 1472 desc = vp = dp = NULL; 1473 1474 /* 1475 * If we have no vendor data, we can't do anything. 1476 */ 1477 if (pci_vendordata == NULL) 1478 goto out; 1479 1480 /* 1481 * Scan the vendor data looking for this device 1482 */ 1483 line = pci_vendordata; 1484 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1485 goto out; 1486 for (;;) { 1487 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1488 goto out; 1489 if (vendor == pci_get_vendor(dev)) 1490 break; 1491 } 1492 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1493 goto out; 1494 for (;;) { 1495 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1496 *dp = 0; 1497 break; 1498 } 1499 if (vendor != -1) { 1500 *dp = 0; 1501 break; 1502 } 1503 if (device == pci_get_device(dev)) 1504 break; 1505 } 1506 if (dp[0] == '\0') 1507 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1508 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1509 NULL) 1510 sprintf(desc, "%s, %s", vp, dp); 1511 out: 1512 if (vp != NULL) 1513 free(vp, M_DEVBUF); 1514 if (dp != NULL) 1515 free(dp, M_DEVBUF); 1516 return(desc); 1517} 1518 1519int 1520pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1521{ 1522 struct pci_devinfo *dinfo; 1523 pcicfgregs *cfg; 1524 1525 dinfo = device_get_ivars(child); 1526 cfg = &dinfo->cfg; 1527 1528 switch (which) { 1529 case PCI_IVAR_ETHADDR: 1530 /* 1531 * The generic accessor doesn't deal with failure, so 1532 * we set the return value, then return an error. 1533 */ 1534 *((uint8_t **) result) = NULL; 1535 return (EINVAL); 1536 case PCI_IVAR_SUBVENDOR: 1537 *result = cfg->subvendor; 1538 break; 1539 case PCI_IVAR_SUBDEVICE: 1540 *result = cfg->subdevice; 1541 break; 1542 case PCI_IVAR_VENDOR: 1543 *result = cfg->vendor; 1544 break; 1545 case PCI_IVAR_DEVICE: 1546 *result = cfg->device; 1547 break; 1548 case PCI_IVAR_DEVID: 1549 *result = (cfg->device << 16) | cfg->vendor; 1550 break; 1551 case PCI_IVAR_CLASS: 1552 *result = cfg->baseclass; 1553 break; 1554 case PCI_IVAR_SUBCLASS: 1555 *result = cfg->subclass; 1556 break; 1557 case PCI_IVAR_PROGIF: 1558 *result = cfg->progif; 1559 break; 1560 case PCI_IVAR_REVID: 1561 *result = cfg->revid; 1562 break; 1563 case PCI_IVAR_INTPIN: 1564 *result = cfg->intpin; 1565 break; 1566 case PCI_IVAR_IRQ: 1567 *result = cfg->intline; 1568 break; 1569 case PCI_IVAR_BUS: 1570 *result = cfg->bus; 1571 break; 1572 case PCI_IVAR_SLOT: 1573 *result = cfg->slot; 1574 break; 1575 case PCI_IVAR_FUNCTION: 1576 *result = cfg->func; 1577 break; 1578 case PCI_IVAR_CMDREG: 1579 *result = cfg->cmdreg; 1580 break; 1581 case PCI_IVAR_CACHELNSZ: 1582 *result = cfg->cachelnsz; 1583 break; 1584 case PCI_IVAR_MINGNT: 1585 *result = cfg->mingnt; 1586 break; 1587 case PCI_IVAR_MAXLAT: 1588 *result = cfg->maxlat; 1589 break; 1590 case PCI_IVAR_LATTIMER: 1591 *result = cfg->lattimer; 1592 break; 1593 default: 1594 return (ENOENT); 1595 } 1596 return (0); 1597} 1598 1599int 1600pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1601{ 1602 struct pci_devinfo *dinfo; 1603 1604 dinfo = device_get_ivars(child); 1605 1606 switch (which) { 1607 case PCI_IVAR_INTPIN: 1608 dinfo->cfg.intpin = value; 1609 return (0); 1610 case PCI_IVAR_ETHADDR: 1611 case PCI_IVAR_SUBVENDOR: 1612 case PCI_IVAR_SUBDEVICE: 1613 case PCI_IVAR_VENDOR: 1614 case PCI_IVAR_DEVICE: 1615 case PCI_IVAR_DEVID: 1616 case PCI_IVAR_CLASS: 1617 case PCI_IVAR_SUBCLASS: 1618 case PCI_IVAR_PROGIF: 1619 case PCI_IVAR_REVID: 1620 case PCI_IVAR_IRQ: 1621 case PCI_IVAR_BUS: 1622 case PCI_IVAR_SLOT: 1623 case PCI_IVAR_FUNCTION: 1624 return (EINVAL); /* disallow for now */ 1625 1626 default: 1627 return (ENOENT); 1628 } 1629} 1630 1631 1632#include "opt_ddb.h" 1633#ifdef DDB 1634#include <ddb/ddb.h> 1635#include <sys/cons.h> 1636 1637/* 1638 * List resources based on pci map registers, used for within ddb 1639 */ 1640 1641DB_SHOW_COMMAND(pciregs, db_pci_dump) 1642{ 1643 struct pci_devinfo *dinfo; 1644 struct devlist *devlist_head; 1645 struct pci_conf *p; 1646 const char *name; 1647 int i, error, none_count, quit; 1648 1649 none_count = 0; 1650 /* get the head of the device queue */ 1651 devlist_head = &pci_devq; 1652 1653 /* 1654 * Go through the list of devices and print out devices 1655 */ 1656 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1657 for (error = 0, i = 0, quit = 0, 1658 dinfo = STAILQ_FIRST(devlist_head); 1659 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1660 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1661 1662 /* Populate pd_name and pd_unit */ 1663 name = NULL; 1664 if (dinfo->cfg.dev) 1665 name = device_get_name(dinfo->cfg.dev); 1666 1667 p = &dinfo->conf; 1668 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1669 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1670 (name && *name) ? name : "none", 1671 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1672 none_count++, 1673 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1674 p->pc_sel.pc_func, (p->pc_class << 16) | 1675 (p->pc_subclass << 8) | p->pc_progif, 1676 (p->pc_subdevice << 16) | p->pc_subvendor, 1677 (p->pc_device << 16) | p->pc_vendor, 1678 p->pc_revid, p->pc_hdr); 1679 } 1680} 1681#endif /* DDB */ 1682 1683static struct resource * 1684pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1685 u_long start, u_long end, u_long count, u_int flags) 1686{ 1687 struct pci_devinfo *dinfo = device_get_ivars(child); 1688 struct resource_list *rl = &dinfo->resources; 1689 struct resource_list_entry *rle; 1690 struct resource *res; 1691 uint32_t map, testval; 1692 int mapsize; 1693 1694 /* 1695 * Weed out the bogons, and figure out how large the BAR/map 1696 * is. Bars that read back 0 here are bogus and unimplemented. 1697 * Note: atapci in legacy mode are special and handled elsewhere 1698 * in the code. If you have a atapci device in legacy mode and 1699 * it fails here, that other code is broken. 1700 */ 1701 res = NULL; 1702 map = pci_read_config(child, *rid, 4); 1703 pci_write_config(child, *rid, 0xffffffff, 4); 1704 testval = pci_read_config(child, *rid, 4); 1705 if (pci_mapbase(testval) == 0) 1706 goto out; 1707 if (pci_maptype(testval) & PCI_MAPMEM) { 1708 if (type != SYS_RES_MEMORY) { 1709 if (bootverbose) 1710 device_printf(dev, 1711 "child %s requested type %d for rid %#x," 1712 " but the BAR says it is an memio\n", 1713 device_get_nameunit(child), type, *rid); 1714 goto out; 1715 } 1716 } else { 1717 if (type != SYS_RES_IOPORT) { 1718 if (bootverbose) 1719 device_printf(dev, 1720 "child %s requested type %d for rid %#x," 1721 " but the BAR says it is an ioport\n", 1722 device_get_nameunit(child), type, *rid); 1723 goto out; 1724 } 1725 } 1726 /* 1727 * For real BARs, we need to override the size that 1728 * the driver requests, because that's what the BAR 1729 * actually uses and we would otherwise have a 1730 * situation where we might allocate the excess to 1731 * another driver, which won't work. 1732 */ 1733 mapsize = pci_mapsize(testval); 1734 count = 1 << mapsize; 1735 if (RF_ALIGNMENT(flags) < mapsize) 1736 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1737 1738 /* 1739 * Allocate enough resource, and then write back the 1740 * appropriate bar for that resource. 1741 */ 1742 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1743 start, end, count, flags); 1744 if (res == NULL) { 1745 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1746 count, *rid, type); 1747 goto out; 1748 } 1749 resource_list_add(rl, type, *rid, start, end, count); 1750 rle = resource_list_find(rl, type, *rid); 1751 if (rle == NULL) 1752 panic("pci_alloc_map: unexpectedly can't find resource."); 1753 rle->res = res; 1754 if (bootverbose) 1755 device_printf(child, 1756 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1757 count, *rid, type, rman_get_start(res)); 1758 map = rman_get_start(res); 1759out:; 1760 pci_write_config(child, *rid, map, 4); 1761 return (res); 1762} 1763 1764 1765struct resource * 1766pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1767 u_long start, u_long end, u_long count, u_int flags) 1768{ 1769 struct pci_devinfo *dinfo = device_get_ivars(child); 1770 struct resource_list *rl = &dinfo->resources; 1771 struct resource_list_entry *rle; 1772 pcicfgregs *cfg = &dinfo->cfg; 1773 1774 /* 1775 * Perform lazy resource allocation 1776 */ 1777 if (device_get_parent(child) == dev) { 1778 switch (type) { 1779 case SYS_RES_IRQ: 1780 /* 1781 * If the child device doesn't have an 1782 * interrupt routed and is deserving of an 1783 * interrupt, try to assign it one. 1784 */ 1785 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1786 (cfg->intpin != 0)) 1787 pci_assign_interrupt(dev, child, 0); 1788 break; 1789 case SYS_RES_IOPORT: 1790 case SYS_RES_MEMORY: 1791 if (*rid < PCIR_BAR(cfg->nummaps)) { 1792 /* 1793 * Enable the I/O mode. We should 1794 * also be assigning resources too 1795 * when none are present. The 1796 * resource_list_alloc kind of sorta does 1797 * this... 1798 */ 1799 if (PCI_ENABLE_IO(dev, child, type)) 1800 return (NULL); 1801 } 1802 rle = resource_list_find(rl, type, *rid); 1803 if (rle == NULL) 1804 return (pci_alloc_map(dev, child, type, rid, 1805 start, end, count, flags)); 1806 break; 1807 } 1808 /* 1809 * If we've already allocated the resource, then 1810 * return it now. But first we may need to activate 1811 * it, since we don't allocate the resource as active 1812 * above. Normally this would be done down in the 1813 * nexus, but since we short-circuit that path we have 1814 * to do its job here. Not sure if we should free the 1815 * resource if it fails to activate. 1816 */ 1817 rle = resource_list_find(rl, type, *rid); 1818 if (rle != NULL && rle->res != NULL) { 1819 if (bootverbose) 1820 device_printf(child, 1821 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1822 rman_get_size(rle->res), *rid, type, 1823 rman_get_start(rle->res)); 1824 if ((flags & RF_ACTIVE) && 1825 bus_generic_activate_resource(dev, child, type, 1826 *rid, rle->res) != 0) 1827 return NULL; 1828 return (rle->res); 1829 } 1830 } 1831 return (resource_list_alloc(rl, dev, child, type, rid, 1832 start, end, count, flags)); 1833} 1834 1835void 1836pci_delete_resource(device_t dev, device_t child, int type, int rid) 1837{ 1838 struct pci_devinfo *dinfo; 1839 struct resource_list *rl; 1840 struct resource_list_entry *rle; 1841 1842 if (device_get_parent(child) != dev) 1843 return; 1844 1845 dinfo = device_get_ivars(child); 1846 rl = &dinfo->resources; 1847 rle = resource_list_find(rl, type, rid); 1848 if (rle) { 1849 if (rle->res) { 1850 if (rman_get_device(rle->res) != dev || 1851 rman_get_flags(rle->res) & RF_ACTIVE) { 1852 device_printf(dev, "delete_resource: " 1853 "Resource still owned by child, oops. " 1854 "(type=%d, rid=%d, addr=%lx)\n", 1855 rle->type, rle->rid, 1856 rman_get_start(rle->res)); 1857 return; 1858 } 1859 bus_release_resource(dev, type, rid, rle->res); 1860 } 1861 resource_list_delete(rl, type, rid); 1862 } 1863 /* 1864 * Why do we turn off the PCI configuration BAR when we delete a 1865 * resource? -- imp 1866 */ 1867 pci_write_config(child, rid, 0, 4); 1868 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1869} 1870 1871struct resource_list * 1872pci_get_resource_list (device_t dev, device_t child) 1873{ 1874 struct pci_devinfo *dinfo = device_get_ivars(child); 1875 1876 return (&dinfo->resources); 1877} 1878 1879uint32_t 1880pci_read_config_method(device_t dev, device_t child, int reg, int width) 1881{ 1882 struct pci_devinfo *dinfo = device_get_ivars(child); 1883 pcicfgregs *cfg = &dinfo->cfg; 1884 1885 return (PCIB_READ_CONFIG(device_get_parent(dev), 1886 cfg->bus, cfg->slot, cfg->func, reg, width)); 1887} 1888 1889void 1890pci_write_config_method(device_t dev, device_t child, int reg, 1891 uint32_t val, int width) 1892{ 1893 struct pci_devinfo *dinfo = device_get_ivars(child); 1894 pcicfgregs *cfg = &dinfo->cfg; 1895 1896 PCIB_WRITE_CONFIG(device_get_parent(dev), 1897 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1898} 1899 1900int 1901pci_child_location_str_method(device_t dev, device_t child, char *buf, 1902 size_t buflen) 1903{ 1904 1905 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1906 pci_get_function(child)); 1907 return (0); 1908} 1909 1910int 1911pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1912 size_t buflen) 1913{ 1914 struct pci_devinfo *dinfo; 1915 pcicfgregs *cfg; 1916 1917 dinfo = device_get_ivars(child); 1918 cfg = &dinfo->cfg; 1919 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1920 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1921 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1922 cfg->progif); 1923 return (0); 1924} 1925 1926int 1927pci_assign_interrupt_method(device_t dev, device_t child) 1928{ 1929 struct pci_devinfo *dinfo = device_get_ivars(child); 1930 pcicfgregs *cfg = &dinfo->cfg; 1931 1932 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1933 cfg->intpin)); 1934} 1935 1936static int 1937pci_modevent(module_t mod, int what, void *arg) 1938{ 1939 static struct cdev *pci_cdev; 1940 1941 switch (what) { 1942 case MOD_LOAD: 1943 STAILQ_INIT(&pci_devq); 1944 pci_generation = 0; 1945 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1946 "pci"); 1947 pci_load_vendor_data(); 1948 break; 1949 1950 case MOD_UNLOAD: 1951 destroy_dev(pci_cdev); 1952 break; 1953 } 1954 1955 return (0); 1956} 1957 1958void 1959pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1960{ 1961 int i; 1962 1963 /* 1964 * Only do header type 0 devices. Type 1 devices are bridges, 1965 * which we know need special treatment. Type 2 devices are 1966 * cardbus bridges which also require special treatment. 1967 * Other types are unknown, and we err on the side of safety 1968 * by ignoring them. 1969 */ 1970 if (dinfo->cfg.hdrtype != 0) 1971 return; 1972 1973 /* 1974 * Restore the device to full power mode. We must do this 1975 * before we restore the registers because moving from D3 to 1976 * D0 will cause the chip's BARs and some other registers to 1977 * be reset to some unknown power on reset values. Cut down 1978 * the noise on boot by doing nothing if we are already in 1979 * state D0. 1980 */ 1981 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1982 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1983 } 1984 for (i = 0; i < dinfo->cfg.nummaps; i++) 1985 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1986 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1987 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1988 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1989 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1990 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1991 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1992 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1993 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1994 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1995 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1996} 1997 1998void 1999pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2000{ 2001 int i; 2002 uint32_t cls; 2003 int ps; 2004 2005 /* 2006 * Only do header type 0 devices. Type 1 devices are bridges, which 2007 * we know need special treatment. Type 2 devices are cardbus bridges 2008 * which also require special treatment. Other types are unknown, and 2009 * we err on the side of safety by ignoring them. Powering down 2010 * bridges should not be undertaken lightly. 2011 */ 2012 if (dinfo->cfg.hdrtype != 0) 2013 return; 2014 for (i = 0; i < dinfo->cfg.nummaps; i++) 2015 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2016 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2017 2018 /* 2019 * Some drivers apparently write to these registers w/o updating our 2020 * cached copy. No harm happens if we update the copy, so do so here 2021 * so we can restore them. The COMMAND register is modified by the 2022 * bus w/o updating the cache. This should represent the normally 2023 * writable portion of the 'defined' part of type 0 headers. In 2024 * theory we also need to save/restore the PCI capability structures 2025 * we know about, but apart from power we don't know any that are 2026 * writable. 2027 */ 2028 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2029 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2030 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2031 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2032 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2033 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2034 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2035 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2036 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2037 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2038 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2039 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2040 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2041 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2042 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2043 2044 /* 2045 * don't set the state for display devices, base peripherals and 2046 * memory devices since bad things happen when they are powered down. 2047 * We should (a) have drivers that can easily detach and (b) use 2048 * generic drivers for these devices so that some device actually 2049 * attaches. We need to make sure that when we implement (a) we don't 2050 * power the device down on a reattach. 2051 */ 2052 cls = pci_get_class(dev); 2053 if (!setstate) 2054 return; 2055 switch (pci_do_power_nodriver) 2056 { 2057 case 0: /* NO powerdown at all */ 2058 return; 2059 case 1: /* Conservative about what to power down */ 2060 if (cls == PCIC_STORAGE) 2061 return; 2062 /*FALLTHROUGH*/ 2063 case 2: /* Agressive about what to power down */ 2064 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2065 cls == PCIC_BASEPERIPH) 2066 return; 2067 /*FALLTHROUGH*/ 2068 case 3: /* Power down everything */ 2069 break; 2070 } 2071 /* 2072 * PCI spec says we can only go into D3 state from D0 state. 2073 * Transition from D[12] into D0 before going to D3 state. 2074 */ 2075 ps = pci_get_powerstate(dev); 2076 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2077 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2078 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2079 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2080} 2081