pci.c revision 150715
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 150715 2005-09-29 15:04:41Z jhb $"); 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63#if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65#include <contrib/dev/acpica/acpi.h> 66#include "acpi_if.h" 67#else 68#define ACPI_PWR_FOR_SLEEP(x, y, z) 69#endif 70 71static uint32_t pci_mapbase(unsigned mapreg); 72static int pci_maptype(unsigned mapreg); 73static int pci_mapsize(unsigned testval); 74static int pci_maprange(unsigned mapreg); 75static void pci_fixancient(pcicfgregs *cfg); 76 77static int pci_porten(device_t pcib, int b, int s, int f); 78static int pci_memen(device_t pcib, int b, int s, int f); 79static void pci_assign_interrupt(device_t bus, device_t dev, 80 int force_route); 81static int pci_add_map(device_t pcib, device_t bus, device_t dev, 82 int b, int s, int f, int reg, 83 struct resource_list *rl); 84static void pci_add_resources(device_t pcib, device_t bus, 85 device_t dev); 86static int pci_probe(device_t dev); 87static int pci_attach(device_t dev); 88static void pci_load_vendor_data(void); 89static int pci_describe_parse_line(char **ptr, int *vendor, 90 int *device, char **desc); 91static char *pci_describe_device(device_t dev); 92static int pci_modevent(module_t mod, int what, void *arg); 93static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 94 pcicfgregs *cfg); 95static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 96 97static device_method_t pci_methods[] = { 98 /* Device interface */ 99 DEVMETHOD(device_probe, pci_probe), 100 DEVMETHOD(device_attach, pci_attach), 101 DEVMETHOD(device_detach, bus_generic_detach), 102 DEVMETHOD(device_shutdown, bus_generic_shutdown), 103 DEVMETHOD(device_suspend, pci_suspend), 104 DEVMETHOD(device_resume, pci_resume), 105 106 /* Bus interface */ 107 DEVMETHOD(bus_print_child, pci_print_child), 108 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 109 DEVMETHOD(bus_read_ivar, pci_read_ivar), 110 DEVMETHOD(bus_write_ivar, pci_write_ivar), 111 DEVMETHOD(bus_driver_added, pci_driver_added), 112 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 113 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 114 115 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 116 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 117 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 118 DEVMETHOD(bus_delete_resource, pci_delete_resource), 119 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 120 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 121 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 122 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 123 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 124 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 125 126 /* PCI interface */ 127 DEVMETHOD(pci_read_config, pci_read_config_method), 128 DEVMETHOD(pci_write_config, pci_write_config_method), 129 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 130 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 131 DEVMETHOD(pci_enable_io, pci_enable_io_method), 132 DEVMETHOD(pci_disable_io, pci_disable_io_method), 133 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 134 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 135 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 136 137 { 0, 0 } 138}; 139 140DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 141 142devclass_t pci_devclass; 143DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 144MODULE_VERSION(pci, 1); 145 146static char *pci_vendordata; 147static size_t pci_vendordata_size; 148 149 150struct pci_quirk { 151 uint32_t devid; /* Vendor/device of the card */ 152 int type; 153#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 154 int arg1; 155 int arg2; 156}; 157 158struct pci_quirk pci_quirks[] = { 159 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 160 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 161 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 163 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 164 165 { 0 } 166}; 167 168/* map register information */ 169#define PCI_MAPMEM 0x01 /* memory map */ 170#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 171#define PCI_MAPPORT 0x04 /* port map */ 172 173struct devlist pci_devq; 174uint32_t pci_generation; 175uint32_t pci_numdevs = 0; 176 177/* sysctl vars */ 178SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 179 180static int pci_enable_io_modes = 1; 181TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 182SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 183 &pci_enable_io_modes, 1, 184 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 185enable these bits correctly. We'd like to do this all the time, but there\n\ 186are some peripherals that this causes problems with."); 187 188static int pci_do_power_nodriver = 0; 189TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 190SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 191 &pci_do_power_nodriver, 0, 192 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 193disable. 1 means conservatively place devices into D3 state. 2 means\n\ 194agressively place devices into D3 state. 3 means put absolutely everything\n\ 195in D3 state."); 196 197static int pci_do_power_resume = 1; 198TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 199SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 200 &pci_do_power_resume, 1, 201 "Transition from D3 -> D0 on resume."); 202 203/* Find a device_t by bus/slot/function */ 204 205device_t 206pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 207{ 208 struct pci_devinfo *dinfo; 209 210 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 211 if ((dinfo->cfg.bus == bus) && 212 (dinfo->cfg.slot == slot) && 213 (dinfo->cfg.func == func)) { 214 return (dinfo->cfg.dev); 215 } 216 } 217 218 return (NULL); 219} 220 221/* Find a device_t by vendor/device ID */ 222 223device_t 224pci_find_device(uint16_t vendor, uint16_t device) 225{ 226 struct pci_devinfo *dinfo; 227 228 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 229 if ((dinfo->cfg.vendor == vendor) && 230 (dinfo->cfg.device == device)) { 231 return (dinfo->cfg.dev); 232 } 233 } 234 235 return (NULL); 236} 237 238/* return base address of memory or port map */ 239 240static uint32_t 241pci_mapbase(unsigned mapreg) 242{ 243 int mask = 0x03; 244 if ((mapreg & 0x01) == 0) 245 mask = 0x0f; 246 return (mapreg & ~mask); 247} 248 249/* return map type of memory or port map */ 250 251static int 252pci_maptype(unsigned mapreg) 253{ 254 static uint8_t maptype[0x10] = { 255 PCI_MAPMEM, PCI_MAPPORT, 256 PCI_MAPMEM, 0, 257 PCI_MAPMEM, PCI_MAPPORT, 258 0, 0, 259 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 260 PCI_MAPMEM|PCI_MAPMEMP, 0, 261 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 262 0, 0, 263 }; 264 265 return maptype[mapreg & 0x0f]; 266} 267 268/* return log2 of map size decoded for memory or port map */ 269 270static int 271pci_mapsize(unsigned testval) 272{ 273 int ln2size; 274 275 testval = pci_mapbase(testval); 276 ln2size = 0; 277 if (testval != 0) { 278 while ((testval & 1) == 0) 279 { 280 ln2size++; 281 testval >>= 1; 282 } 283 } 284 return (ln2size); 285} 286 287/* return log2 of address range supported by map register */ 288 289static int 290pci_maprange(unsigned mapreg) 291{ 292 int ln2range = 0; 293 switch (mapreg & 0x07) { 294 case 0x00: 295 case 0x01: 296 case 0x05: 297 ln2range = 32; 298 break; 299 case 0x02: 300 ln2range = 20; 301 break; 302 case 0x04: 303 ln2range = 64; 304 break; 305 } 306 return (ln2range); 307} 308 309/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 310 311static void 312pci_fixancient(pcicfgregs *cfg) 313{ 314 if (cfg->hdrtype != 0) 315 return; 316 317 /* PCI to PCI bridges use header type 1 */ 318 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 319 cfg->hdrtype = 1; 320} 321 322/* extract header type specific config data */ 323 324static void 325pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 326{ 327#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 328 switch (cfg->hdrtype) { 329 case 0: 330 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 331 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 332 cfg->nummaps = PCI_MAXMAPS_0; 333 break; 334 case 1: 335 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 336 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 337 cfg->nummaps = PCI_MAXMAPS_1; 338 break; 339 case 2: 340 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 341 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 342 cfg->nummaps = PCI_MAXMAPS_2; 343 break; 344 } 345#undef REG 346} 347 348/* read configuration header into pcicfgregs structure */ 349 350struct pci_devinfo * 351pci_read_device(device_t pcib, int b, int s, int f, size_t size) 352{ 353#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 354 pcicfgregs *cfg = NULL; 355 struct pci_devinfo *devlist_entry; 356 struct devlist *devlist_head; 357 358 devlist_head = &pci_devq; 359 360 devlist_entry = NULL; 361 362 if (REG(PCIR_DEVVENDOR, 4) != -1) { 363 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 364 if (devlist_entry == NULL) 365 return (NULL); 366 367 cfg = &devlist_entry->cfg; 368 369 cfg->bus = b; 370 cfg->slot = s; 371 cfg->func = f; 372 cfg->vendor = REG(PCIR_VENDOR, 2); 373 cfg->device = REG(PCIR_DEVICE, 2); 374 cfg->cmdreg = REG(PCIR_COMMAND, 2); 375 cfg->statreg = REG(PCIR_STATUS, 2); 376 cfg->baseclass = REG(PCIR_CLASS, 1); 377 cfg->subclass = REG(PCIR_SUBCLASS, 1); 378 cfg->progif = REG(PCIR_PROGIF, 1); 379 cfg->revid = REG(PCIR_REVID, 1); 380 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 381 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 382 cfg->lattimer = REG(PCIR_LATTIMER, 1); 383 cfg->intpin = REG(PCIR_INTPIN, 1); 384 cfg->intline = REG(PCIR_INTLINE, 1); 385 386 cfg->mingnt = REG(PCIR_MINGNT, 1); 387 cfg->maxlat = REG(PCIR_MAXLAT, 1); 388 389 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 390 cfg->hdrtype &= ~PCIM_MFDEV; 391 392 pci_fixancient(cfg); 393 pci_hdrtypedata(pcib, b, s, f, cfg); 394 395 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 396 pci_read_extcap(pcib, cfg); 397 398 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 399 400 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 401 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 402 devlist_entry->conf.pc_sel.pc_func = cfg->func; 403 devlist_entry->conf.pc_hdr = cfg->hdrtype; 404 405 devlist_entry->conf.pc_subvendor = cfg->subvendor; 406 devlist_entry->conf.pc_subdevice = cfg->subdevice; 407 devlist_entry->conf.pc_vendor = cfg->vendor; 408 devlist_entry->conf.pc_device = cfg->device; 409 410 devlist_entry->conf.pc_class = cfg->baseclass; 411 devlist_entry->conf.pc_subclass = cfg->subclass; 412 devlist_entry->conf.pc_progif = cfg->progif; 413 devlist_entry->conf.pc_revid = cfg->revid; 414 415 pci_numdevs++; 416 pci_generation++; 417 } 418 return (devlist_entry); 419#undef REG 420} 421 422static void 423pci_read_extcap(device_t pcib, pcicfgregs *cfg) 424{ 425#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 426 int ptr, nextptr, ptrptr; 427 428 switch (cfg->hdrtype & PCIM_HDRTYPE) { 429 case 0: 430 ptrptr = PCIR_CAP_PTR; 431 break; 432 case 2: 433 ptrptr = 0x14; 434 break; 435 default: 436 return; /* no extended capabilities support */ 437 } 438 nextptr = REG(ptrptr, 1); /* sanity check? */ 439 440 /* 441 * Read capability entries. 442 */ 443 while (nextptr != 0) { 444 /* Sanity check */ 445 if (nextptr > 255) { 446 printf("illegal PCI extended capability offset %d\n", 447 nextptr); 448 return; 449 } 450 /* Find the next entry */ 451 ptr = nextptr; 452 nextptr = REG(ptr + 1, 1); 453 454 /* Process this entry */ 455 switch (REG(ptr, 1)) { 456 case PCIY_PMG: /* PCI power management */ 457 if (cfg->pp.pp_cap == 0) { 458 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 459 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 460 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 461 if ((nextptr - ptr) > PCIR_POWER_DATA) 462 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 463 } 464 break; 465 case PCIY_MSI: /* PCI MSI */ 466 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 467 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 468 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 469 else 470 cfg->msi.msi_data = PCIR_MSI_DATA; 471 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 472 PCIM_MSICTRL_MMC_MASK)>>1); 473 default: 474 break; 475 } 476 } 477#undef REG 478} 479 480/* free pcicfgregs structure and all depending data structures */ 481 482int 483pci_freecfg(struct pci_devinfo *dinfo) 484{ 485 struct devlist *devlist_head; 486 487 devlist_head = &pci_devq; 488 489 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 490 free(dinfo, M_DEVBUF); 491 492 /* increment the generation count */ 493 pci_generation++; 494 495 /* we're losing one device */ 496 pci_numdevs--; 497 return (0); 498} 499 500/* 501 * PCI power manangement 502 */ 503int 504pci_set_powerstate_method(device_t dev, device_t child, int state) 505{ 506 struct pci_devinfo *dinfo = device_get_ivars(child); 507 pcicfgregs *cfg = &dinfo->cfg; 508 uint16_t status; 509 int result, oldstate, highest, delay; 510 511 if (cfg->pp.pp_cap == 0) 512 return (EOPNOTSUPP); 513 514 /* 515 * Optimize a no state change request away. While it would be OK to 516 * write to the hardware in theory, some devices have shown odd 517 * behavior when going from D3 -> D3. 518 */ 519 oldstate = pci_get_powerstate(child); 520 if (oldstate == state) 521 return (0); 522 523 /* 524 * The PCI power management specification states that after a state 525 * transition between PCI power states, system software must 526 * guarantee a minimal delay before the function accesses the device. 527 * Compute the worst case delay that we need to guarantee before we 528 * access the device. Many devices will be responsive much more 529 * quickly than this delay, but there are some that don't respond 530 * instantly to state changes. Transitions to/from D3 state require 531 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 532 * is done below with DELAY rather than a sleeper function because 533 * this function can be called from contexts where we cannot sleep. 534 */ 535 highest = (oldstate > state) ? oldstate : state; 536 if (highest == PCI_POWERSTATE_D3) 537 delay = 10000; 538 else if (highest == PCI_POWERSTATE_D2) 539 delay = 200; 540 else 541 delay = 0; 542 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 543 & ~PCIM_PSTAT_DMASK; 544 result = 0; 545 switch (state) { 546 case PCI_POWERSTATE_D0: 547 status |= PCIM_PSTAT_D0; 548 break; 549 case PCI_POWERSTATE_D1: 550 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 551 return (EOPNOTSUPP); 552 status |= PCIM_PSTAT_D1; 553 break; 554 case PCI_POWERSTATE_D2: 555 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 556 return (EOPNOTSUPP); 557 status |= PCIM_PSTAT_D2; 558 break; 559 case PCI_POWERSTATE_D3: 560 status |= PCIM_PSTAT_D3; 561 break; 562 default: 563 return (EINVAL); 564 } 565 566 if (bootverbose) 567 printf( 568 "pci%d:%d:%d: Transition from D%d to D%d\n", 569 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 570 oldstate, state); 571 572 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 573 if (delay) 574 DELAY(delay); 575 return (0); 576} 577 578int 579pci_get_powerstate_method(device_t dev, device_t child) 580{ 581 struct pci_devinfo *dinfo = device_get_ivars(child); 582 pcicfgregs *cfg = &dinfo->cfg; 583 uint16_t status; 584 int result; 585 586 if (cfg->pp.pp_cap != 0) { 587 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 588 switch (status & PCIM_PSTAT_DMASK) { 589 case PCIM_PSTAT_D0: 590 result = PCI_POWERSTATE_D0; 591 break; 592 case PCIM_PSTAT_D1: 593 result = PCI_POWERSTATE_D1; 594 break; 595 case PCIM_PSTAT_D2: 596 result = PCI_POWERSTATE_D2; 597 break; 598 case PCIM_PSTAT_D3: 599 result = PCI_POWERSTATE_D3; 600 break; 601 default: 602 result = PCI_POWERSTATE_UNKNOWN; 603 break; 604 } 605 } else { 606 /* No support, device is always at D0 */ 607 result = PCI_POWERSTATE_D0; 608 } 609 return (result); 610} 611 612/* 613 * Some convenience functions for PCI device drivers. 614 */ 615 616static __inline void 617pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 618{ 619 uint16_t command; 620 621 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 622 command |= bit; 623 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 624} 625 626static __inline void 627pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 628{ 629 uint16_t command; 630 631 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 632 command &= ~bit; 633 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 634} 635 636int 637pci_enable_busmaster_method(device_t dev, device_t child) 638{ 639 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 640 return (0); 641} 642 643int 644pci_disable_busmaster_method(device_t dev, device_t child) 645{ 646 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 647 return (0); 648} 649 650int 651pci_enable_io_method(device_t dev, device_t child, int space) 652{ 653 uint16_t command; 654 uint16_t bit; 655 char *error; 656 657 bit = 0; 658 error = NULL; 659 660 switch(space) { 661 case SYS_RES_IOPORT: 662 bit = PCIM_CMD_PORTEN; 663 error = "port"; 664 break; 665 case SYS_RES_MEMORY: 666 bit = PCIM_CMD_MEMEN; 667 error = "memory"; 668 break; 669 default: 670 return (EINVAL); 671 } 672 pci_set_command_bit(dev, child, bit); 673 /* Some devices seem to need a brief stall here, what do to? */ 674 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 675 if (command & bit) 676 return (0); 677 device_printf(child, "failed to enable %s mapping!\n", error); 678 return (ENXIO); 679} 680 681int 682pci_disable_io_method(device_t dev, device_t child, int space) 683{ 684 uint16_t command; 685 uint16_t bit; 686 char *error; 687 688 bit = 0; 689 error = NULL; 690 691 switch(space) { 692 case SYS_RES_IOPORT: 693 bit = PCIM_CMD_PORTEN; 694 error = "port"; 695 break; 696 case SYS_RES_MEMORY: 697 bit = PCIM_CMD_MEMEN; 698 error = "memory"; 699 break; 700 default: 701 return (EINVAL); 702 } 703 pci_clear_command_bit(dev, child, bit); 704 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 705 if (command & bit) { 706 device_printf(child, "failed to disable %s mapping!\n", error); 707 return (ENXIO); 708 } 709 return (0); 710} 711 712/* 713 * New style pci driver. Parent device is either a pci-host-bridge or a 714 * pci-pci-bridge. Both kinds are represented by instances of pcib. 715 */ 716 717void 718pci_print_verbose(struct pci_devinfo *dinfo) 719{ 720 if (bootverbose) { 721 pcicfgregs *cfg = &dinfo->cfg; 722 723 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 724 cfg->vendor, cfg->device, cfg->revid); 725 printf("\tbus=%d, slot=%d, func=%d\n", 726 cfg->bus, cfg->slot, cfg->func); 727 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 728 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 729 cfg->mfdev); 730 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 731 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 732 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 733 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 734 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 735 if (cfg->intpin > 0) 736 printf("\tintpin=%c, irq=%d\n", 737 cfg->intpin +'a' -1, cfg->intline); 738 if (cfg->pp.pp_cap) { 739 uint16_t status; 740 741 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 742 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 743 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 744 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 745 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 746 status & PCIM_PSTAT_DMASK); 747 } 748 if (cfg->msi.msi_data) { 749 int ctrl; 750 751 ctrl = cfg->msi.msi_ctrl; 752 printf("\tMSI supports %d message%s%s%s\n", 753 cfg->msi.msi_msgnum, 754 (cfg->msi.msi_msgnum == 1) ? "" : "s", 755 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 756 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 757 } 758 } 759} 760 761static int 762pci_porten(device_t pcib, int b, int s, int f) 763{ 764 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 765 & PCIM_CMD_PORTEN) != 0; 766} 767 768static int 769pci_memen(device_t pcib, int b, int s, int f) 770{ 771 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 772 & PCIM_CMD_MEMEN) != 0; 773} 774 775/* 776 * Add a resource based on a pci map register. Return 1 if the map 777 * register is a 32bit map register or 2 if it is a 64bit register. 778 */ 779static int 780pci_add_map(device_t pcib, device_t bus, device_t dev, 781 int b, int s, int f, int reg, struct resource_list *rl) 782{ 783 uint32_t map; 784 uint64_t base; 785 uint64_t start, end, count; 786 uint8_t ln2size; 787 uint8_t ln2range; 788 uint32_t testval; 789 uint16_t cmd; 790 int type; 791 int barlen; 792 793 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 794 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 795 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 796 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 797 798 if (pci_maptype(map) & PCI_MAPMEM) 799 type = SYS_RES_MEMORY; 800 else 801 type = SYS_RES_IOPORT; 802 ln2size = pci_mapsize(testval); 803 ln2range = pci_maprange(testval); 804 base = pci_mapbase(map); 805 barlen = ln2range == 64 ? 2 : 1; 806 807 /* 808 * For I/O registers, if bottom bit is set, and the next bit up 809 * isn't clear, we know we have a BAR that doesn't conform to the 810 * spec, so ignore it. Also, sanity check the size of the data 811 * areas to the type of memory involved. Memory must be at least 812 * 32 bytes in size, while I/O ranges must be at least 4. 813 */ 814 if ((testval & 0x1) == 0x1 && 815 (testval & 0x2) != 0) 816 return (barlen); 817 if ((type == SYS_RES_MEMORY && ln2size < 5) || 818 (type == SYS_RES_IOPORT && ln2size < 2)) 819 return (barlen); 820 821 if (ln2range == 64) 822 /* Read the other half of a 64bit map register */ 823 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 824 825 if (bootverbose) { 826 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 827 reg, pci_maptype(map), ln2range, 828 (unsigned int) base, ln2size); 829 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 830 printf(", port disabled\n"); 831 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 832 printf(", memory disabled\n"); 833 else 834 printf(", enabled\n"); 835 } 836 837 /* 838 * If base is 0, then we have problems. It is best to ignore 839 * such entries for the moment. These will be allocated later if 840 * the driver specifically requests them. 841 * 842 * Similarly treat maps whose values is the same as the test value 843 * read back. These maps have had all f's written to them by the 844 * BIOS in an attempt to disable the resources. 845 */ 846 if (base == 0 || map == testval) 847 return (barlen); 848 849 /* 850 * This code theoretically does the right thing, but has 851 * undesirable side effects in some cases where peripherals 852 * respond oddly to having these bits enabled. Let the user 853 * be able to turn them off (since pci_enable_io_modes is 1 by 854 * default). 855 */ 856 if (pci_enable_io_modes) { 857 /* Turn on resources that have been left off by a lazy BIOS */ 858 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 859 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 860 cmd |= PCIM_CMD_PORTEN; 861 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 862 } 863 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 864 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 865 cmd |= PCIM_CMD_MEMEN; 866 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 867 } 868 } else { 869 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 870 return (barlen); 871 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 872 return (barlen); 873 } 874 875 start = base; 876 end = base + (1 << ln2size) - 1; 877 count = 1 << ln2size; 878 resource_list_add(rl, type, reg, start, end, count); 879 880 /* 881 * Not quite sure what to do on failure of allocating the resource 882 * since I can postulate several right answers. 883 */ 884 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 885 return (barlen); 886} 887 888/* 889 * For ATA devices we need to decide early what addressing mode to use. 890 * Legacy demands that the primary and secondary ATA ports sits on the 891 * same addresses that old ISA hardware did. This dictates that we use 892 * those addresses and ignore the BAR's if we cannot set PCI native 893 * addressing mode. 894 */ 895static void 896pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 897 int s, int f, struct resource_list *rl) 898{ 899 int rid, type, progif; 900#if 0 901 /* if this device supports PCI native addressing use it */ 902 progif = pci_read_config(dev, PCIR_PROGIF, 1); 903 if ((progif & 0x8a) == 0x8a) { 904 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 905 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 906 printf("Trying ATA native PCI addressing mode\n"); 907 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 908 } 909 } 910#endif 911 progif = pci_read_config(dev, PCIR_PROGIF, 1); 912 type = SYS_RES_IOPORT; 913 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 914 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 915 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 916 } 917 else { 918 rid = PCIR_BAR(0); 919 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 920 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 921 rid = PCIR_BAR(1); 922 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 923 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 924 } 925 if (progif & PCIP_STORAGE_IDE_MODESEC) { 926 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 927 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 928 } 929 else { 930 rid = PCIR_BAR(2); 931 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 932 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 933 rid = PCIR_BAR(3); 934 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 935 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 936 } 937 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 938 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl); 939} 940 941static void 942pci_assign_interrupt(device_t bus, device_t dev, int force_route) 943{ 944 struct pci_devinfo *dinfo = device_get_ivars(dev); 945 pcicfgregs *cfg = &dinfo->cfg; 946 char tunable_name[64]; 947 int irq; 948 949 /* Has to have an intpin to have an interrupt. */ 950 if (cfg->intpin == 0) 951 return; 952 953 /* Let the user override the IRQ with a tunable. */ 954 irq = PCI_INVALID_IRQ; 955 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 956 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 957 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 958 irq = PCI_INVALID_IRQ; 959 960 /* 961 * If we didn't get an IRQ via the tunable, then we either use the 962 * IRQ value in the intline register or we ask the bus to route an 963 * interrupt for us. If force_route is true, then we only use the 964 * value in the intline register if the bus was unable to assign an 965 * IRQ. 966 */ 967 if (!PCI_INTERRUPT_VALID(irq)) { 968 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 969 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 970 if (!PCI_INTERRUPT_VALID(irq)) 971 irq = cfg->intline; 972 } 973 974 /* If after all that we don't have an IRQ, just bail. */ 975 if (!PCI_INTERRUPT_VALID(irq)) 976 return; 977 978 /* Update the config register if it changed. */ 979 if (irq != cfg->intline) { 980 cfg->intline = irq; 981 pci_write_config(dev, PCIR_INTLINE, irq, 1); 982 } 983 984 /* Add this IRQ as rid 0 interrupt resource. */ 985 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 986} 987 988static void 989pci_add_resources(device_t pcib, device_t bus, device_t dev) 990{ 991 struct pci_devinfo *dinfo = device_get_ivars(dev); 992 pcicfgregs *cfg = &dinfo->cfg; 993 struct resource_list *rl = &dinfo->resources; 994 struct pci_quirk *q; 995 int b, i, f, s; 996 997 b = cfg->bus; 998 s = cfg->slot; 999 f = cfg->func; 1000 1001 /* ATA devices needs special map treatment */ 1002 if ((pci_get_class(dev) == PCIC_STORAGE) && 1003 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1004 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1005 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 1006 else 1007 for (i = 0; i < cfg->nummaps;) 1008 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1009 rl); 1010 1011 for (q = &pci_quirks[0]; q->devid; q++) { 1012 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1013 && q->type == PCI_QUIRK_MAP_REG) 1014 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 1015 } 1016 1017 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1018#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 1019 defined(__arm__) || defined(__alpha__) 1020 /* 1021 * Try to re-route interrupts. Sometimes the BIOS or 1022 * firmware may leave bogus values in these registers. 1023 * If the re-route fails, then just stick with what we 1024 * have. 1025 */ 1026 pci_assign_interrupt(bus, dev, 1); 1027#else 1028 pci_assign_interrupt(bus, dev, 0); 1029#endif 1030 } 1031} 1032 1033void 1034pci_add_children(device_t dev, int busno, size_t dinfo_size) 1035{ 1036#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1037 device_t pcib = device_get_parent(dev); 1038 struct pci_devinfo *dinfo; 1039 int maxslots; 1040 int s, f, pcifunchigh; 1041 uint8_t hdrtype; 1042 1043 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 1044 ("dinfo_size too small")); 1045 maxslots = PCIB_MAXSLOTS(pcib); 1046 for (s = 0; s <= maxslots; s++) { 1047 pcifunchigh = 0; 1048 f = 0; 1049 hdrtype = REG(PCIR_HDRTYPE, 1); 1050 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1051 continue; 1052 if (hdrtype & PCIM_MFDEV) 1053 pcifunchigh = PCI_FUNCMAX; 1054 for (f = 0; f <= pcifunchigh; f++) { 1055 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1056 if (dinfo != NULL) { 1057 pci_add_child(dev, dinfo); 1058 } 1059 } 1060 } 1061#undef REG 1062} 1063 1064void 1065pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1066{ 1067 device_t pcib; 1068 1069 pcib = device_get_parent(bus); 1070 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1071 device_set_ivars(dinfo->cfg.dev, dinfo); 1072 resource_list_init(&dinfo->resources); 1073 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1074 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1075 pci_print_verbose(dinfo); 1076 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1077} 1078 1079static int 1080pci_probe(device_t dev) 1081{ 1082 1083 device_set_desc(dev, "PCI bus"); 1084 1085 /* Allow other subclasses to override this driver. */ 1086 return (-1000); 1087} 1088 1089static int 1090pci_attach(device_t dev) 1091{ 1092 int busno; 1093 1094 /* 1095 * Since there can be multiple independantly numbered PCI 1096 * busses on some large alpha systems, we can't use the unit 1097 * number to decide what bus we are probing. We ask the parent 1098 * pcib what our bus number is. 1099 */ 1100 busno = pcib_get_bus(dev); 1101 if (bootverbose) 1102 device_printf(dev, "physical bus=%d\n", busno); 1103 1104 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1105 1106 return (bus_generic_attach(dev)); 1107} 1108 1109int 1110pci_suspend(device_t dev) 1111{ 1112 int dstate, error, i, numdevs; 1113 device_t acpi_dev, child, *devlist; 1114 struct pci_devinfo *dinfo; 1115 1116 /* 1117 * Save the PCI configuration space for each child and set the 1118 * device in the appropriate power state for this sleep state. 1119 */ 1120 acpi_dev = NULL; 1121 if (pci_do_power_resume) 1122 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1123 device_get_children(dev, &devlist, &numdevs); 1124 for (i = 0; i < numdevs; i++) { 1125 child = devlist[i]; 1126 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1127 pci_cfg_save(child, dinfo, 0); 1128 } 1129 1130 /* Suspend devices before potentially powering them down. */ 1131 error = bus_generic_suspend(dev); 1132 if (error) { 1133 free(devlist, M_TEMP); 1134 return (error); 1135 } 1136 1137 /* 1138 * Always set the device to D3. If ACPI suggests a different 1139 * power state, use it instead. If ACPI is not present, the 1140 * firmware is responsible for managing device power. Skip 1141 * children who aren't attached since they are powered down 1142 * separately. Only manage type 0 devices for now. 1143 */ 1144 for (i = 0; acpi_dev && i < numdevs; i++) { 1145 child = devlist[i]; 1146 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1147 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1148 dstate = PCI_POWERSTATE_D3; 1149 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1150 pci_set_powerstate(child, dstate); 1151 } 1152 } 1153 free(devlist, M_TEMP); 1154 return (0); 1155} 1156 1157int 1158pci_resume(device_t dev) 1159{ 1160 int i, numdevs; 1161 device_t acpi_dev, child, *devlist; 1162 struct pci_devinfo *dinfo; 1163 1164 /* 1165 * Set each child to D0 and restore its PCI configuration space. 1166 */ 1167 acpi_dev = NULL; 1168 if (pci_do_power_resume) 1169 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1170 device_get_children(dev, &devlist, &numdevs); 1171 for (i = 0; i < numdevs; i++) { 1172 /* 1173 * Notify ACPI we're going to D0 but ignore the result. If 1174 * ACPI is not present, the firmware is responsible for 1175 * managing device power. Only manage type 0 devices for now. 1176 */ 1177 child = devlist[i]; 1178 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1179 if (acpi_dev && device_is_attached(child) && 1180 dinfo->cfg.hdrtype == 0) { 1181 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1182 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1183 } 1184 1185 /* Now the device is powered up, restore its config space. */ 1186 pci_cfg_restore(child, dinfo); 1187 } 1188 free(devlist, M_TEMP); 1189 return (bus_generic_resume(dev)); 1190} 1191 1192static void 1193pci_load_vendor_data(void) 1194{ 1195 caddr_t vendordata, info; 1196 1197 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1198 info = preload_search_info(vendordata, MODINFO_ADDR); 1199 pci_vendordata = *(char **)info; 1200 info = preload_search_info(vendordata, MODINFO_SIZE); 1201 pci_vendordata_size = *(size_t *)info; 1202 /* terminate the database */ 1203 pci_vendordata[pci_vendordata_size] = '\n'; 1204 } 1205} 1206 1207void 1208pci_driver_added(device_t dev, driver_t *driver) 1209{ 1210 int numdevs; 1211 device_t *devlist; 1212 device_t child; 1213 struct pci_devinfo *dinfo; 1214 int i; 1215 1216 if (bootverbose) 1217 device_printf(dev, "driver added\n"); 1218 DEVICE_IDENTIFY(driver, dev); 1219 device_get_children(dev, &devlist, &numdevs); 1220 for (i = 0; i < numdevs; i++) { 1221 child = devlist[i]; 1222 if (device_get_state(child) != DS_NOTPRESENT) 1223 continue; 1224 dinfo = device_get_ivars(child); 1225 pci_print_verbose(dinfo); 1226 if (bootverbose) 1227 printf("pci%d:%d:%d: reprobing on driver added\n", 1228 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1229 pci_cfg_restore(child, dinfo); 1230 if (device_probe_and_attach(child) != 0) 1231 pci_cfg_save(child, dinfo, 1); 1232 } 1233 free(devlist, M_TEMP); 1234} 1235 1236int 1237pci_print_child(device_t dev, device_t child) 1238{ 1239 struct pci_devinfo *dinfo; 1240 struct resource_list *rl; 1241 int retval = 0; 1242 1243 dinfo = device_get_ivars(child); 1244 rl = &dinfo->resources; 1245 1246 retval += bus_print_child_header(dev, child); 1247 1248 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1249 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1250 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1251 if (device_get_flags(dev)) 1252 retval += printf(" flags %#x", device_get_flags(dev)); 1253 1254 retval += printf(" at device %d.%d", pci_get_slot(child), 1255 pci_get_function(child)); 1256 1257 retval += bus_print_child_footer(dev, child); 1258 1259 return (retval); 1260} 1261 1262static struct 1263{ 1264 int class; 1265 int subclass; 1266 char *desc; 1267} pci_nomatch_tab[] = { 1268 {PCIC_OLD, -1, "old"}, 1269 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1270 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1271 {PCIC_STORAGE, -1, "mass storage"}, 1272 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1273 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1274 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1275 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1276 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1277 {PCIC_NETWORK, -1, "network"}, 1278 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1279 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1280 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1281 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1282 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1283 {PCIC_DISPLAY, -1, "display"}, 1284 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1285 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1286 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1287 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1288 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1289 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1290 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1291 {PCIC_MEMORY, -1, "memory"}, 1292 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1293 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1294 {PCIC_BRIDGE, -1, "bridge"}, 1295 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1296 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1297 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1298 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1299 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1300 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1301 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1302 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1303 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1304 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1305 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1306 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1307 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1308 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1309 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1310 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1311 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1312 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1313 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1314 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1315 {PCIC_INPUTDEV, -1, "input device"}, 1316 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1317 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1318 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1319 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1320 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1321 {PCIC_DOCKING, -1, "docking station"}, 1322 {PCIC_PROCESSOR, -1, "processor"}, 1323 {PCIC_SERIALBUS, -1, "serial bus"}, 1324 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1325 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1326 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1327 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1328 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1329 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1330 {PCIC_WIRELESS, -1, "wireless controller"}, 1331 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1332 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1333 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1334 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1335 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1336 {PCIC_SATCOM, -1, "satellite communication"}, 1337 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1338 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1339 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1340 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1341 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1342 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1343 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1344 {PCIC_DASP, -1, "dasp"}, 1345 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1346 {0, 0, NULL} 1347}; 1348 1349void 1350pci_probe_nomatch(device_t dev, device_t child) 1351{ 1352 int i; 1353 char *cp, *scp, *device; 1354 1355 /* 1356 * Look for a listing for this device in a loaded device database. 1357 */ 1358 if ((device = pci_describe_device(child)) != NULL) { 1359 device_printf(dev, "<%s>", device); 1360 free(device, M_DEVBUF); 1361 } else { 1362 /* 1363 * Scan the class/subclass descriptions for a general 1364 * description. 1365 */ 1366 cp = "unknown"; 1367 scp = NULL; 1368 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1369 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1370 if (pci_nomatch_tab[i].subclass == -1) { 1371 cp = pci_nomatch_tab[i].desc; 1372 } else if (pci_nomatch_tab[i].subclass == 1373 pci_get_subclass(child)) { 1374 scp = pci_nomatch_tab[i].desc; 1375 } 1376 } 1377 } 1378 device_printf(dev, "<%s%s%s>", 1379 cp ? cp : "", 1380 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1381 scp ? scp : ""); 1382 } 1383 printf(" at device %d.%d (no driver attached)\n", 1384 pci_get_slot(child), pci_get_function(child)); 1385 if (pci_do_power_nodriver) 1386 pci_cfg_save(child, 1387 (struct pci_devinfo *) device_get_ivars(child), 1); 1388 return; 1389} 1390 1391/* 1392 * Parse the PCI device database, if loaded, and return a pointer to a 1393 * description of the device. 1394 * 1395 * The database is flat text formatted as follows: 1396 * 1397 * Any line not in a valid format is ignored. 1398 * Lines are terminated with newline '\n' characters. 1399 * 1400 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1401 * the vendor name. 1402 * 1403 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1404 * - devices cannot be listed without a corresponding VENDOR line. 1405 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1406 * another TAB, then the device name. 1407 */ 1408 1409/* 1410 * Assuming (ptr) points to the beginning of a line in the database, 1411 * return the vendor or device and description of the next entry. 1412 * The value of (vendor) or (device) inappropriate for the entry type 1413 * is set to -1. Returns nonzero at the end of the database. 1414 * 1415 * Note that this is slightly unrobust in the face of corrupt data; 1416 * we attempt to safeguard against this by spamming the end of the 1417 * database with a newline when we initialise. 1418 */ 1419static int 1420pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1421{ 1422 char *cp = *ptr; 1423 int left; 1424 1425 *device = -1; 1426 *vendor = -1; 1427 **desc = '\0'; 1428 for (;;) { 1429 left = pci_vendordata_size - (cp - pci_vendordata); 1430 if (left <= 0) { 1431 *ptr = cp; 1432 return(1); 1433 } 1434 1435 /* vendor entry? */ 1436 if (*cp != '\t' && 1437 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1438 break; 1439 /* device entry? */ 1440 if (*cp == '\t' && 1441 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1442 break; 1443 1444 /* skip to next line */ 1445 while (*cp != '\n' && left > 0) { 1446 cp++; 1447 left--; 1448 } 1449 if (*cp == '\n') { 1450 cp++; 1451 left--; 1452 } 1453 } 1454 /* skip to next line */ 1455 while (*cp != '\n' && left > 0) { 1456 cp++; 1457 left--; 1458 } 1459 if (*cp == '\n' && left > 0) 1460 cp++; 1461 *ptr = cp; 1462 return(0); 1463} 1464 1465static char * 1466pci_describe_device(device_t dev) 1467{ 1468 int vendor, device; 1469 char *desc, *vp, *dp, *line; 1470 1471 desc = vp = dp = NULL; 1472 1473 /* 1474 * If we have no vendor data, we can't do anything. 1475 */ 1476 if (pci_vendordata == NULL) 1477 goto out; 1478 1479 /* 1480 * Scan the vendor data looking for this device 1481 */ 1482 line = pci_vendordata; 1483 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1484 goto out; 1485 for (;;) { 1486 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1487 goto out; 1488 if (vendor == pci_get_vendor(dev)) 1489 break; 1490 } 1491 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1492 goto out; 1493 for (;;) { 1494 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1495 *dp = 0; 1496 break; 1497 } 1498 if (vendor != -1) { 1499 *dp = 0; 1500 break; 1501 } 1502 if (device == pci_get_device(dev)) 1503 break; 1504 } 1505 if (dp[0] == '\0') 1506 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1507 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1508 NULL) 1509 sprintf(desc, "%s, %s", vp, dp); 1510 out: 1511 if (vp != NULL) 1512 free(vp, M_DEVBUF); 1513 if (dp != NULL) 1514 free(dp, M_DEVBUF); 1515 return(desc); 1516} 1517 1518int 1519pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1520{ 1521 struct pci_devinfo *dinfo; 1522 pcicfgregs *cfg; 1523 1524 dinfo = device_get_ivars(child); 1525 cfg = &dinfo->cfg; 1526 1527 switch (which) { 1528 case PCI_IVAR_ETHADDR: 1529 /* 1530 * The generic accessor doesn't deal with failure, so 1531 * we set the return value, then return an error. 1532 */ 1533 *((uint8_t **) result) = NULL; 1534 return (EINVAL); 1535 case PCI_IVAR_SUBVENDOR: 1536 *result = cfg->subvendor; 1537 break; 1538 case PCI_IVAR_SUBDEVICE: 1539 *result = cfg->subdevice; 1540 break; 1541 case PCI_IVAR_VENDOR: 1542 *result = cfg->vendor; 1543 break; 1544 case PCI_IVAR_DEVICE: 1545 *result = cfg->device; 1546 break; 1547 case PCI_IVAR_DEVID: 1548 *result = (cfg->device << 16) | cfg->vendor; 1549 break; 1550 case PCI_IVAR_CLASS: 1551 *result = cfg->baseclass; 1552 break; 1553 case PCI_IVAR_SUBCLASS: 1554 *result = cfg->subclass; 1555 break; 1556 case PCI_IVAR_PROGIF: 1557 *result = cfg->progif; 1558 break; 1559 case PCI_IVAR_REVID: 1560 *result = cfg->revid; 1561 break; 1562 case PCI_IVAR_INTPIN: 1563 *result = cfg->intpin; 1564 break; 1565 case PCI_IVAR_IRQ: 1566 *result = cfg->intline; 1567 break; 1568 case PCI_IVAR_BUS: 1569 *result = cfg->bus; 1570 break; 1571 case PCI_IVAR_SLOT: 1572 *result = cfg->slot; 1573 break; 1574 case PCI_IVAR_FUNCTION: 1575 *result = cfg->func; 1576 break; 1577 case PCI_IVAR_CMDREG: 1578 *result = cfg->cmdreg; 1579 break; 1580 case PCI_IVAR_CACHELNSZ: 1581 *result = cfg->cachelnsz; 1582 break; 1583 case PCI_IVAR_MINGNT: 1584 *result = cfg->mingnt; 1585 break; 1586 case PCI_IVAR_MAXLAT: 1587 *result = cfg->maxlat; 1588 break; 1589 case PCI_IVAR_LATTIMER: 1590 *result = cfg->lattimer; 1591 break; 1592 default: 1593 return (ENOENT); 1594 } 1595 return (0); 1596} 1597 1598int 1599pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1600{ 1601 struct pci_devinfo *dinfo; 1602 1603 dinfo = device_get_ivars(child); 1604 1605 switch (which) { 1606 case PCI_IVAR_INTPIN: 1607 dinfo->cfg.intpin = value; 1608 return (0); 1609 case PCI_IVAR_ETHADDR: 1610 case PCI_IVAR_SUBVENDOR: 1611 case PCI_IVAR_SUBDEVICE: 1612 case PCI_IVAR_VENDOR: 1613 case PCI_IVAR_DEVICE: 1614 case PCI_IVAR_DEVID: 1615 case PCI_IVAR_CLASS: 1616 case PCI_IVAR_SUBCLASS: 1617 case PCI_IVAR_PROGIF: 1618 case PCI_IVAR_REVID: 1619 case PCI_IVAR_IRQ: 1620 case PCI_IVAR_BUS: 1621 case PCI_IVAR_SLOT: 1622 case PCI_IVAR_FUNCTION: 1623 return (EINVAL); /* disallow for now */ 1624 1625 default: 1626 return (ENOENT); 1627 } 1628} 1629 1630 1631#include "opt_ddb.h" 1632#ifdef DDB 1633#include <ddb/ddb.h> 1634#include <sys/cons.h> 1635 1636/* 1637 * List resources based on pci map registers, used for within ddb 1638 */ 1639 1640DB_SHOW_COMMAND(pciregs, db_pci_dump) 1641{ 1642 struct pci_devinfo *dinfo; 1643 struct devlist *devlist_head; 1644 struct pci_conf *p; 1645 const char *name; 1646 int i, error, none_count, quit; 1647 1648 none_count = 0; 1649 /* get the head of the device queue */ 1650 devlist_head = &pci_devq; 1651 1652 /* 1653 * Go through the list of devices and print out devices 1654 */ 1655 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1656 for (error = 0, i = 0, quit = 0, 1657 dinfo = STAILQ_FIRST(devlist_head); 1658 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1659 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1660 1661 /* Populate pd_name and pd_unit */ 1662 name = NULL; 1663 if (dinfo->cfg.dev) 1664 name = device_get_name(dinfo->cfg.dev); 1665 1666 p = &dinfo->conf; 1667 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1668 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1669 (name && *name) ? name : "none", 1670 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1671 none_count++, 1672 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1673 p->pc_sel.pc_func, (p->pc_class << 16) | 1674 (p->pc_subclass << 8) | p->pc_progif, 1675 (p->pc_subdevice << 16) | p->pc_subvendor, 1676 (p->pc_device << 16) | p->pc_vendor, 1677 p->pc_revid, p->pc_hdr); 1678 } 1679} 1680#endif /* DDB */ 1681 1682static struct resource * 1683pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1684 u_long start, u_long end, u_long count, u_int flags) 1685{ 1686 struct pci_devinfo *dinfo = device_get_ivars(child); 1687 struct resource_list *rl = &dinfo->resources; 1688 struct resource_list_entry *rle; 1689 struct resource *res; 1690 uint32_t map, testval; 1691 int mapsize; 1692 1693 /* 1694 * Weed out the bogons, and figure out how large the BAR/map 1695 * is. Bars that read back 0 here are bogus and unimplemented. 1696 * Note: atapci in legacy mode are special and handled elsewhere 1697 * in the code. If you have a atapci device in legacy mode and 1698 * it fails here, that other code is broken. 1699 */ 1700 res = NULL; 1701 map = pci_read_config(child, *rid, 4); 1702 pci_write_config(child, *rid, 0xffffffff, 4); 1703 testval = pci_read_config(child, *rid, 4); 1704 if (pci_mapbase(testval) == 0) 1705 goto out; 1706 if (pci_maptype(testval) & PCI_MAPMEM) { 1707 if (type != SYS_RES_MEMORY) { 1708 if (bootverbose) 1709 device_printf(dev, 1710 "child %s requested type %d for rid %#x," 1711 " but the BAR says it is an memio\n", 1712 device_get_nameunit(child), type, *rid); 1713 goto out; 1714 } 1715 } else { 1716 if (type != SYS_RES_IOPORT) { 1717 if (bootverbose) 1718 device_printf(dev, 1719 "child %s requested type %d for rid %#x," 1720 " but the BAR says it is an ioport\n", 1721 device_get_nameunit(child), type, *rid); 1722 goto out; 1723 } 1724 } 1725 /* 1726 * For real BARs, we need to override the size that 1727 * the driver requests, because that's what the BAR 1728 * actually uses and we would otherwise have a 1729 * situation where we might allocate the excess to 1730 * another driver, which won't work. 1731 */ 1732 mapsize = pci_mapsize(testval); 1733 count = 1 << mapsize; 1734 if (RF_ALIGNMENT(flags) < mapsize) 1735 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1736 1737 /* 1738 * Allocate enough resource, and then write back the 1739 * appropriate bar for that resource. 1740 */ 1741 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1742 start, end, count, flags); 1743 if (res == NULL) { 1744 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1745 count, *rid, type); 1746 goto out; 1747 } 1748 resource_list_add(rl, type, *rid, start, end, count); 1749 rle = resource_list_find(rl, type, *rid); 1750 if (rle == NULL) 1751 panic("pci_alloc_map: unexpectedly can't find resource."); 1752 rle->res = res; 1753 if (bootverbose) 1754 device_printf(child, 1755 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1756 count, *rid, type, rman_get_start(res)); 1757 map = rman_get_start(res); 1758out:; 1759 pci_write_config(child, *rid, map, 4); 1760 return (res); 1761} 1762 1763 1764struct resource * 1765pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1766 u_long start, u_long end, u_long count, u_int flags) 1767{ 1768 struct pci_devinfo *dinfo = device_get_ivars(child); 1769 struct resource_list *rl = &dinfo->resources; 1770 struct resource_list_entry *rle; 1771 pcicfgregs *cfg = &dinfo->cfg; 1772 1773 /* 1774 * Perform lazy resource allocation 1775 */ 1776 if (device_get_parent(child) == dev) { 1777 switch (type) { 1778 case SYS_RES_IRQ: 1779 /* 1780 * If the child device doesn't have an 1781 * interrupt routed and is deserving of an 1782 * interrupt, try to assign it one. 1783 */ 1784 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1785 (cfg->intpin != 0)) 1786 pci_assign_interrupt(dev, child, 0); 1787 break; 1788 case SYS_RES_IOPORT: 1789 case SYS_RES_MEMORY: 1790 if (*rid < PCIR_BAR(cfg->nummaps)) { 1791 /* 1792 * Enable the I/O mode. We should 1793 * also be assigning resources too 1794 * when none are present. The 1795 * resource_list_alloc kind of sorta does 1796 * this... 1797 */ 1798 if (PCI_ENABLE_IO(dev, child, type)) 1799 return (NULL); 1800 } 1801 rle = resource_list_find(rl, type, *rid); 1802 if (rle == NULL) 1803 return (pci_alloc_map(dev, child, type, rid, 1804 start, end, count, flags)); 1805 break; 1806 } 1807 /* 1808 * If we've already allocated the resource, then 1809 * return it now. But first we may need to activate 1810 * it, since we don't allocate the resource as active 1811 * above. Normally this would be done down in the 1812 * nexus, but since we short-circuit that path we have 1813 * to do its job here. Not sure if we should free the 1814 * resource if it fails to activate. 1815 */ 1816 rle = resource_list_find(rl, type, *rid); 1817 if (rle != NULL && rle->res != NULL) { 1818 if (bootverbose) 1819 device_printf(child, 1820 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1821 rman_get_size(rle->res), *rid, type, 1822 rman_get_start(rle->res)); 1823 if ((flags & RF_ACTIVE) && 1824 bus_generic_activate_resource(dev, child, type, 1825 *rid, rle->res) != 0) 1826 return NULL; 1827 return (rle->res); 1828 } 1829 } 1830 return (resource_list_alloc(rl, dev, child, type, rid, 1831 start, end, count, flags)); 1832} 1833 1834void 1835pci_delete_resource(device_t dev, device_t child, int type, int rid) 1836{ 1837 struct pci_devinfo *dinfo; 1838 struct resource_list *rl; 1839 struct resource_list_entry *rle; 1840 1841 if (device_get_parent(child) != dev) 1842 return; 1843 1844 dinfo = device_get_ivars(child); 1845 rl = &dinfo->resources; 1846 rle = resource_list_find(rl, type, rid); 1847 if (rle) { 1848 if (rle->res) { 1849 if (rman_get_device(rle->res) != dev || 1850 rman_get_flags(rle->res) & RF_ACTIVE) { 1851 device_printf(dev, "delete_resource: " 1852 "Resource still owned by child, oops. " 1853 "(type=%d, rid=%d, addr=%lx)\n", 1854 rle->type, rle->rid, 1855 rman_get_start(rle->res)); 1856 return; 1857 } 1858 bus_release_resource(dev, type, rid, rle->res); 1859 } 1860 resource_list_delete(rl, type, rid); 1861 } 1862 /* 1863 * Why do we turn off the PCI configuration BAR when we delete a 1864 * resource? -- imp 1865 */ 1866 pci_write_config(child, rid, 0, 4); 1867 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1868} 1869 1870struct resource_list * 1871pci_get_resource_list (device_t dev, device_t child) 1872{ 1873 struct pci_devinfo *dinfo = device_get_ivars(child); 1874 1875 return (&dinfo->resources); 1876} 1877 1878uint32_t 1879pci_read_config_method(device_t dev, device_t child, int reg, int width) 1880{ 1881 struct pci_devinfo *dinfo = device_get_ivars(child); 1882 pcicfgregs *cfg = &dinfo->cfg; 1883 1884 return (PCIB_READ_CONFIG(device_get_parent(dev), 1885 cfg->bus, cfg->slot, cfg->func, reg, width)); 1886} 1887 1888void 1889pci_write_config_method(device_t dev, device_t child, int reg, 1890 uint32_t val, int width) 1891{ 1892 struct pci_devinfo *dinfo = device_get_ivars(child); 1893 pcicfgregs *cfg = &dinfo->cfg; 1894 1895 PCIB_WRITE_CONFIG(device_get_parent(dev), 1896 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1897} 1898 1899int 1900pci_child_location_str_method(device_t dev, device_t child, char *buf, 1901 size_t buflen) 1902{ 1903 1904 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1905 pci_get_function(child)); 1906 return (0); 1907} 1908 1909int 1910pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1911 size_t buflen) 1912{ 1913 struct pci_devinfo *dinfo; 1914 pcicfgregs *cfg; 1915 1916 dinfo = device_get_ivars(child); 1917 cfg = &dinfo->cfg; 1918 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1919 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1920 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1921 cfg->progif); 1922 return (0); 1923} 1924 1925int 1926pci_assign_interrupt_method(device_t dev, device_t child) 1927{ 1928 struct pci_devinfo *dinfo = device_get_ivars(child); 1929 pcicfgregs *cfg = &dinfo->cfg; 1930 1931 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1932 cfg->intpin)); 1933} 1934 1935static int 1936pci_modevent(module_t mod, int what, void *arg) 1937{ 1938 static struct cdev *pci_cdev; 1939 1940 switch (what) { 1941 case MOD_LOAD: 1942 STAILQ_INIT(&pci_devq); 1943 pci_generation = 0; 1944 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1945 "pci"); 1946 pci_load_vendor_data(); 1947 break; 1948 1949 case MOD_UNLOAD: 1950 destroy_dev(pci_cdev); 1951 break; 1952 } 1953 1954 return (0); 1955} 1956 1957void 1958pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1959{ 1960 int i; 1961 1962 /* 1963 * Only do header type 0 devices. Type 1 devices are bridges, 1964 * which we know need special treatment. Type 2 devices are 1965 * cardbus bridges which also require special treatment. 1966 * Other types are unknown, and we err on the side of safety 1967 * by ignoring them. 1968 */ 1969 if (dinfo->cfg.hdrtype != 0) 1970 return; 1971 1972 /* 1973 * Restore the device to full power mode. We must do this 1974 * before we restore the registers because moving from D3 to 1975 * D0 will cause the chip's BARs and some other registers to 1976 * be reset to some unknown power on reset values. Cut down 1977 * the noise on boot by doing nothing if we are already in 1978 * state D0. 1979 */ 1980 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1981 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1982 } 1983 for (i = 0; i < dinfo->cfg.nummaps; i++) 1984 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1985 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1986 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1987 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1988 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1989 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1990 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1991 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1992 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1993 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1994 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1995} 1996 1997void 1998pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1999{ 2000 int i; 2001 uint32_t cls; 2002 int ps; 2003 2004 /* 2005 * Only do header type 0 devices. Type 1 devices are bridges, which 2006 * we know need special treatment. Type 2 devices are cardbus bridges 2007 * which also require special treatment. Other types are unknown, and 2008 * we err on the side of safety by ignoring them. Powering down 2009 * bridges should not be undertaken lightly. 2010 */ 2011 if (dinfo->cfg.hdrtype != 0) 2012 return; 2013 for (i = 0; i < dinfo->cfg.nummaps; i++) 2014 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2015 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2016 2017 /* 2018 * Some drivers apparently write to these registers w/o updating our 2019 * cached copy. No harm happens if we update the copy, so do so here 2020 * so we can restore them. The COMMAND register is modified by the 2021 * bus w/o updating the cache. This should represent the normally 2022 * writable portion of the 'defined' part of type 0 headers. In 2023 * theory we also need to save/restore the PCI capability structures 2024 * we know about, but apart from power we don't know any that are 2025 * writable. 2026 */ 2027 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2028 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2029 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2030 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2031 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2032 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2033 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2034 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2035 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2036 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2037 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2038 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2039 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2040 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2041 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2042 2043 /* 2044 * don't set the state for display devices, base peripherals and 2045 * memory devices since bad things happen when they are powered down. 2046 * We should (a) have drivers that can easily detach and (b) use 2047 * generic drivers for these devices so that some device actually 2048 * attaches. We need to make sure that when we implement (a) we don't 2049 * power the device down on a reattach. 2050 */ 2051 cls = pci_get_class(dev); 2052 if (!setstate) 2053 return; 2054 switch (pci_do_power_nodriver) 2055 { 2056 case 0: /* NO powerdown at all */ 2057 return; 2058 case 1: /* Conservative about what to power down */ 2059 if (cls == PCIC_STORAGE) 2060 return; 2061 /*FALLTHROUGH*/ 2062 case 2: /* Agressive about what to power down */ 2063 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2064 cls == PCIC_BASEPERIPH) 2065 return; 2066 /*FALLTHROUGH*/ 2067 case 3: /* Power down everything */ 2068 break; 2069 } 2070 /* 2071 * PCI spec says we can only go into D3 state from D0 state. 2072 * Transition from D[12] into D0 before going to D3 state. 2073 */ 2074 ps = pci_get_powerstate(dev); 2075 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2076 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2077 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2078 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2079} 2080