pci.c revision 150430
11541Srgrimes/*- 21541Srgrimes * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 31541Srgrimes * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 41541Srgrimes * Copyright (c) 2000, BSDi 51541Srgrimes * All rights reserved. 61541Srgrimes * 71541Srgrimes * Redistribution and use in source and binary forms, with or without 812623Sphk * modification, are permitted provided that the following conditions 912623Sphk * are met: 1012623Sphk * 1. Redistributions of source code must retain the above copyright 111541Srgrimes * notice unmodified, this list of conditions, and the following 121541Srgrimes * disclaimer. 131541Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 141541Srgrimes * notice, this list of conditions and the following disclaimer in the 151541Srgrimes * documentation and/or other materials provided with the distribution. 161541Srgrimes * 171541Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 181541Srgrimes * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 191541Srgrimes * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 201541Srgrimes * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 211541Srgrimes * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 221541Srgrimes * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231541Srgrimes * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241541Srgrimes * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251541Srgrimes * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 261541Srgrimes * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271541Srgrimes */ 281541Srgrimes 291541Srgrimes#include <sys/cdefs.h> 301541Srgrimes__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 150430 2005-09-21 19:47:00Z imp $"); 311541Srgrimes 321541Srgrimes#include "opt_bus.h" 331541Srgrimes 341541Srgrimes#include <sys/param.h> 351541Srgrimes#include <sys/systm.h> 361541Srgrimes#include <sys/malloc.h> 371541Srgrimes#include <sys/module.h> 381541Srgrimes#include <sys/linker.h> 391541Srgrimes#include <sys/fcntl.h> 4050477Speter#include <sys/conf.h> 411541Srgrimes#include <sys/kernel.h> 421541Srgrimes#include <sys/queue.h> 4331778Seivind#include <sys/sysctl.h> 4431778Seivind#include <sys/types.h> 451541Srgrimes 4648274Speter#include <vm/vm.h> 4748274Speter#include <vm/pmap.h> 481541Srgrimes#include <vm/vm_extern.h> 4912623Sphk 5012662Sdg#include <sys/bus.h> 5182746Sdillon#include <machine/bus.h> 5282746Sdillon#include <sys/rman.h> 5393616Salfred#include <machine/resource.h> 5415103Sphk 5512645Sbde#include <sys/pciio.h> 5612662Sdg#include <dev/pci/pcireg.h> 5712645Sbde#include <dev/pci/pcivar.h> 5830354Sphk#include <dev/pci/pci_private.h> 5963212Sabial 60100833Struckman#include "pcib_if.h" 6130309Sphk#include "pci_if.h" 6212429Sphk 6393625Srwatson#if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 6412429Sphk defined (__ia64__) 6593625Srwatson#include <contrib/dev/acpica/acpi.h> 6612429Sphk#include "acpi_if.h" 6793625Srwatson#else 6893625Srwatson#define ACPI_PWR_FOR_SLEEP(x, y, z) 6993625Srwatson#endif 7093616Salfred 7162573Sphkstatic uint32_t pci_mapbase(unsigned mapreg); 7212429Sphkstatic int pci_maptype(unsigned mapreg); 7344078Sdfrstatic int pci_mapsize(unsigned testval); 7412152Sphkstatic int pci_maprange(unsigned mapreg); 7563212Sabialstatic void pci_fixancient(pcicfgregs *cfg); 7663212Sabial 7763212Sabialstatic int pci_porten(device_t pcib, int b, int s, int f); 7863212Sabialstatic int pci_memen(device_t pcib, int b, int s, int f); 7963212Sabialstatic int pci_add_map(device_t pcib, device_t bus, device_t dev, 8063212Sabial int b, int s, int f, int reg, 8163212Sabial struct resource_list *rl); 8263212Sabialstatic void pci_add_resources(device_t pcib, device_t bus, 8363212Sabial device_t dev); 8463212Sabialstatic int pci_probe(device_t dev); 8563212Sabialstatic int pci_attach(device_t dev); 8663212Sabialstatic void pci_load_vendor_data(void); 8763212Sabialstatic int pci_describe_parse_line(char **ptr, int *vendor, 8812623Sphk int *device, char **desc); 8912623Sphkstatic char *pci_describe_device(device_t dev); 9012623Sphkstatic int pci_modevent(module_t mod, int what, void *arg); 9144078Sdfrstatic void pci_hdrtypedata(device_t pcib, int b, int s, int f, 9212623Sphk pcicfgregs *cfg); 9312429Sphkstatic void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 9480338Sroam 9580338Sroamstatic device_method_t pci_methods[] = { 9612152Sphk /* Device interface */ 9744078Sdfr DEVMETHOD(device_probe, pci_probe), 9844078Sdfr DEVMETHOD(device_attach, pci_attach), 9944078Sdfr DEVMETHOD(device_detach, bus_generic_detach), 10012197Sbde DEVMETHOD(device_shutdown, bus_generic_shutdown), 10144078Sdfr DEVMETHOD(device_suspend, pci_suspend), 10263212Sabial DEVMETHOD(device_resume, pci_resume), 10363212Sabial 10463212Sabial /* Bus interface */ 10563212Sabial DEVMETHOD(bus_print_child, pci_print_child), 10663212Sabial DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 10763212Sabial DEVMETHOD(bus_read_ivar, pci_read_ivar), 10863212Sabial DEVMETHOD(bus_write_ivar, pci_write_ivar), 10963212Sabial DEVMETHOD(bus_driver_added, pci_driver_added), 11063212Sabial DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 11163212Sabial DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 11263212Sabial 11363212Sabial DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 11463212Sabial DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 11563212Sabial DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 11644078Sdfr DEVMETHOD(bus_delete_resource, pci_delete_resource), 11780339Sroam DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 11880339Sroam DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 11980339Sroam DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 12080339Sroam DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 12144078Sdfr DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 12244078Sdfr DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 12380339Sroam 12471510Smckusick /* PCI interface */ 12571510Smckusick DEVMETHOD(pci_read_config, pci_read_config_method), 12671510Smckusick DEVMETHOD(pci_write_config, pci_write_config_method), 12771510Smckusick DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 12844078Sdfr DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 12984832Sroam DEVMETHOD(pci_enable_io, pci_enable_io_method), 13084832Sroam DEVMETHOD(pci_disable_io, pci_disable_io_method), 13184832Sroam DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 13284832Sroam DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 13384832Sroam DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 13484832Sroam 13544078Sdfr { 0, 0 } 13644078Sdfr}; 13744078Sdfr 13844078SdfrDEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 13944078Sdfr 14044078Sdfrdevclass_t pci_devclass; 14144078SdfrDRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 14244078SdfrMODULE_VERSION(pci, 1); 14344078Sdfr 14444078Sdfrstatic char *pci_vendordata; 14544078Sdfrstatic size_t pci_vendordata_size; 14644078Sdfr 14744078Sdfr 14844078Sdfrstruct pci_quirk { 14912152Sphk uint32_t devid; /* Vendor/device of the card */ 15012131Sphk int type; 15180338Sroam#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 15280338Sroam int arg1; 15312152Sphk int arg2; 15460938Sjake}; 15544078Sdfr 15612152Sphkstruct pci_quirk pci_quirks[] = { 15763212Sabial /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 15863212Sabial { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 15963212Sabial { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 16063212Sabial /* As does the Serverworks OSB4 (the SMBus mapping register) */ 16163212Sabial { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 16263212Sabial 16363212Sabial { 0 } 16463212Sabial}; 16563212Sabial 16663212Sabial/* map register information */ 16763212Sabial#define PCI_MAPMEM 0x01 /* memory map */ 16863212Sabial#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 16963212Sabial#define PCI_MAPPORT 0x04 /* port map */ 17063212Sabial 17163212Sabialstruct devlist pci_devq; 17263212Sabialuint32_t pci_generation; 17363212Sabialuint32_t pci_numdevs = 0; 17463212Sabial 17563212Sabial/* sysctl vars */ 17663212SabialSYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 17763212Sabial 17863212Sabialstatic int pci_enable_io_modes = 1; 17963212SabialTUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 18063212SabialSYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 18163212Sabial &pci_enable_io_modes, 1, 18263212Sabial "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 18363212Sabialenable these bits correctly. We'd like to do this all the time, but there\n\ 18463212Sabialare some peripherals that this causes problems with."); 18563212Sabial 18663212Sabialstatic int pci_do_power_nodriver = 0; 18763212SabialTUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 18863212SabialSYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 18963212Sabial &pci_do_power_nodriver, 0, 19063212Sabial "Place a function into D3 state when no driver attaches to it. 0 means\n\ 19163212Sabialdisable. 1 means conservatively place devices into D3 state. 2 means\n\ 19263212Sabialagressively place devices into D3 state. 3 means put absolutely everything\n\ 19363212Sabialin D3 state."); 19463212Sabial 19563212Sabialstatic int pci_do_power_resume = 1; 19663212SabialTUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 19763212SabialSYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 19863212Sabial &pci_do_power_resume, 1, 19963212Sabial "Transition from D3 -> D0 on resume."); 20063212Sabial 20163212Sabial/* Find a device_t by bus/slot/function */ 20263212Sabial 20363212Sabialdevice_t 20463212Sabialpci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 20563212Sabial{ 20663212Sabial struct pci_devinfo *dinfo; 20763212Sabial 20863212Sabial STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 20963212Sabial if ((dinfo->cfg.bus == bus) && 21063212Sabial (dinfo->cfg.slot == slot) && 21163212Sabial (dinfo->cfg.func == func)) { 21263212Sabial return (dinfo->cfg.dev); 21363212Sabial } 21463212Sabial } 21563212Sabial 21663212Sabial return (NULL); 21763212Sabial} 21863212Sabial 21963212Sabial/* Find a device_t by vendor/device ID */ 22063212Sabial 22163212Sabialdevice_t 22263212Sabialpci_find_device(uint16_t vendor, uint16_t device) 22363212Sabial{ 22463212Sabial struct pci_devinfo *dinfo; 22563978Speter 22663212Sabial STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 22763212Sabial if ((dinfo->cfg.vendor == vendor) && 22863212Sabial (dinfo->cfg.device == device)) { 22963212Sabial return (dinfo->cfg.dev); 23063212Sabial } 23163212Sabial } 23263212Sabial 23363212Sabial return (NULL); 23463212Sabial} 23563212Sabial 23663212Sabial/* return base address of memory or port map */ 23763212Sabial 23863212Sabialstatic uint32_t 23971999Sphkpci_mapbase(unsigned mapreg) 24063212Sabial{ 24163212Sabial int mask = 0x03; 24263212Sabial if ((mapreg & 0x01) == 0) 24363212Sabial mask = 0x0f; 24463212Sabial return (mapreg & ~mask); 24563212Sabial} 24644078Sdfr 24763212Sabial/* return map type of memory or port map */ 24863212Sabial 24963212Sabialstatic int 25063212Sabialpci_maptype(unsigned mapreg) 25163212Sabial{ 25263212Sabial static uint8_t maptype[0x10] = { 25363212Sabial PCI_MAPMEM, PCI_MAPPORT, 25463212Sabial PCI_MAPMEM, 0, 25563212Sabial PCI_MAPMEM, PCI_MAPPORT, 25663212Sabial 0, 0, 25763212Sabial PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 25863212Sabial PCI_MAPMEM|PCI_MAPMEMP, 0, 25963212Sabial PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 26063212Sabial 0, 0, 26163212Sabial }; 26263212Sabial 26363212Sabial return maptype[mapreg & 0x0f]; 26463212Sabial} 26563212Sabial 26663212Sabial/* return log2 of map size decoded for memory or port map */ 26763212Sabial 26863212Sabialstatic int 26963212Sabialpci_mapsize(unsigned testval) 27063212Sabial{ 27163212Sabial int ln2size; 27263212Sabial 27363212Sabial testval = pci_mapbase(testval); 27463212Sabial ln2size = 0; 27563212Sabial if (testval != 0) { 27663212Sabial while ((testval & 1) == 0) 27763212Sabial { 27863212Sabial ln2size++; 27963212Sabial testval >>= 1; 28063212Sabial } 28163212Sabial } 28263212Sabial return (ln2size); 28363212Sabial} 28463212Sabial 28563212Sabial/* return log2 of address range supported by map register */ 28663212Sabial 28763212Sabialstatic int 28863212Sabialpci_maprange(unsigned mapreg) 28963212Sabial{ 29063212Sabial int ln2range = 0; 29163212Sabial switch (mapreg & 0x07) { 29263212Sabial case 0x00: 29363212Sabial case 0x01: 29463212Sabial case 0x05: 29563212Sabial ln2range = 32; 29663212Sabial break; 29763212Sabial case 0x02: 29863212Sabial ln2range = 20; 29963212Sabial break; 30063212Sabial case 0x04: 30163212Sabial ln2range = 64; 30263212Sabial break; 30363212Sabial } 30463212Sabial return (ln2range); 30563212Sabial} 30663212Sabial 30763212Sabial/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 30863212Sabial 30963212Sabialstatic void 31063212Sabialpci_fixancient(pcicfgregs *cfg) 31163212Sabial{ 31263212Sabial if (cfg->hdrtype != 0) 31363212Sabial return; 31463212Sabial 31588006Sluigi /* PCI to PCI bridges use header type 1 */ 316100113Smarkm if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 31763978Speter cfg->hdrtype = 1; 31863978Speter} 31963212Sabial 32063212Sabial/* extract header type specific config data */ 32163212Sabial 32263212Sabialstatic void 32363212Sabialpci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 32463212Sabial{ 32563212Sabial#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 32663212Sabial switch (cfg->hdrtype) { 32763212Sabial case 0: 32863212Sabial cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 32963212Sabial cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 33063212Sabial cfg->nummaps = PCI_MAXMAPS_0; 33170679Sjhb break; 33270679Sjhb case 1: 33363212Sabial cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 33463212Sabial cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 33563212Sabial cfg->nummaps = PCI_MAXMAPS_1; 33663978Speter break; 33763212Sabial case 2: 33863212Sabial cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 33963212Sabial cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 34063212Sabial cfg->nummaps = PCI_MAXMAPS_2; 34163212Sabial break; 34263212Sabial } 34363212Sabial#undef REG 34463212Sabial} 34563212Sabial 34663212Sabial/* read configuration header into pcicfgregs structure */ 34763212Sabial 34863212Sabialstruct pci_devinfo * 34963212Sabialpci_read_device(device_t pcib, int b, int s, int f, size_t size) 35063212Sabial{ 35163212Sabial#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 35263212Sabial pcicfgregs *cfg = NULL; 35363212Sabial struct pci_devinfo *devlist_entry; 35463212Sabial struct devlist *devlist_head; 35569781Sdwmalone 35663212Sabial devlist_head = &pci_devq; 35763212Sabial 35863212Sabial devlist_entry = NULL; 35963212Sabial 36063212Sabial if (REG(PCIR_DEVVENDOR, 4) != -1) { 36163978Speter devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 36263978Speter if (devlist_entry == NULL) 36363978Speter return (NULL); 36463978Speter 36563212Sabial cfg = &devlist_entry->cfg; 36663212Sabial 36763212Sabial cfg->bus = b; 36863212Sabial cfg->slot = s; 36963212Sabial cfg->func = f; 37063212Sabial cfg->vendor = REG(PCIR_VENDOR, 2); 37163212Sabial cfg->device = REG(PCIR_DEVICE, 2); 37263212Sabial cfg->cmdreg = REG(PCIR_COMMAND, 2); 37363212Sabial cfg->statreg = REG(PCIR_STATUS, 2); 37463212Sabial cfg->baseclass = REG(PCIR_CLASS, 1); 37563212Sabial cfg->subclass = REG(PCIR_SUBCLASS, 1); 37663212Sabial cfg->progif = REG(PCIR_PROGIF, 1); 37788006Sluigi cfg->revid = REG(PCIR_REVID, 1); 37888006Sluigi cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 37988006Sluigi cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 38088006Sluigi cfg->lattimer = REG(PCIR_LATTIMER, 1); 381100113Smarkm cfg->intpin = REG(PCIR_INTPIN, 1); 38288006Sluigi cfg->intline = REG(PCIR_INTLINE, 1); 38363212Sabial 38463212Sabial cfg->mingnt = REG(PCIR_MINGNT, 1); 38563212Sabial cfg->maxlat = REG(PCIR_MAXLAT, 1); 38663212Sabial 38763212Sabial cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 38863212Sabial cfg->hdrtype &= ~PCIM_MFDEV; 38963212Sabial 39063212Sabial pci_fixancient(cfg); 39163212Sabial pci_hdrtypedata(pcib, b, s, f, cfg); 39244078Sdfr 39344078Sdfr if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 39478161Speter pci_read_extcap(pcib, cfg); 39512152Sphk 39680338Sroam STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 39780338Sroam 39838869Sbde devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 39978161Speter devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 40078161Speter devlist_entry->conf.pc_sel.pc_func = cfg->func; 40193625Srwatson devlist_entry->conf.pc_hdr = cfg->hdrtype; 40278161Speter 40378161Speter devlist_entry->conf.pc_subvendor = cfg->subvendor; 40438869Sbde devlist_entry->conf.pc_subdevice = cfg->subdevice; 40544078Sdfr devlist_entry->conf.pc_vendor = cfg->vendor; 40644078Sdfr devlist_entry->conf.pc_device = cfg->device; 40712623Sphk 40812623Sphk devlist_entry->conf.pc_class = cfg->baseclass; 40912623Sphk devlist_entry->conf.pc_subclass = cfg->subclass; 41012650Sphk devlist_entry->conf.pc_progif = cfg->progif; 41112650Sphk devlist_entry->conf.pc_revid = cfg->revid; 41212650Sphk 41312650Sphk pci_numdevs++; 41412650Sphk pci_generation++; 41512650Sphk } 41612650Sphk return (devlist_entry); 41712650Sphk#undef REG 41812623Sphk} 41912623Sphk 42042467Sphkstatic void 42112623Sphkpci_read_extcap(device_t pcib, pcicfgregs *cfg) 42212650Sphk{ 42388006Sluigi#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 42412623Sphk int ptr, nextptr, ptrptr; 42512623Sphk 42612152Sphk switch (cfg->hdrtype & PCIM_HDRTYPE) { 42744078Sdfr case 0: 42812152Sphk ptrptr = PCIR_CAP_PTR; 42944078Sdfr break; 43044078Sdfr case 2: 43112152Sphk ptrptr = 0x14; 43244078Sdfr break; 43312152Sphk default: 43412152Sphk return; /* no extended capabilities support */ 43512152Sphk } 43612152Sphk nextptr = REG(ptrptr, 1); /* sanity check? */ 43744078Sdfr 43812152Sphk /* 43912152Sphk * Read capability entries. 44044078Sdfr */ 44144078Sdfr while (nextptr != 0) { 44212152Sphk /* Sanity check */ 44344078Sdfr if (nextptr > 255) { 44415241Sphk printf("illegal PCI extended capability offset %d\n", 44515241Sphk nextptr); 44644078Sdfr return; 44712243Sphk } 44815241Sphk /* Find the next entry */ 44944078Sdfr ptr = nextptr; 45012152Sphk nextptr = REG(ptr + 1, 1); 45144078Sdfr 45212152Sphk /* Process this entry */ 45312152Sphk switch (REG(ptr, 1)) { 45412152Sphk case PCIY_PMG: /* PCI power management */ 45512152Sphk if (cfg->pp.pp_cap == 0) { 45612152Sphk cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 45712152Sphk cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 45812152Sphk cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 45912152Sphk if ((nextptr - ptr) > PCIR_POWER_DATA) 46012152Sphk cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 46112152Sphk } 46212152Sphk break; 46312152Sphk case PCIY_MSI: /* PCI MSI */ 46412152Sphk cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 46562573Sphk if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 46612152Sphk cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 46787024Speter else 46887024Speter cfg->msi.msi_data = PCIR_MSI_DATA; 46993593Sjhb cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 47087024Speter PCIM_MSICTRL_MMC_MASK)>>1); 47187024Speter default: 47244078Sdfr break; 47312152Sphk } 47412152Sphk } 47512152Sphk#undef REG 47612152Sphk} 47712623Sphk 47812152Sphk/* free pcicfgregs structure and all depending data structures */ 47912623Sphk 48062573Sphkint 48112623Sphkpci_freecfg(struct pci_devinfo *dinfo) 48212623Sphk{ 48312623Sphk struct devlist *devlist_head; 48444078Sdfr 48544078Sdfr devlist_head = &pci_devq; 48644972Sphk 48712623Sphk STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 48812131Sphk free(dinfo, M_DEVBUF); 48912623Sphk 49012623Sphk /* increment the generation count */ 49141514Sarchie pci_generation++; 49212623Sphk 49312623Sphk /* we're losing one device */ 49412623Sphk pci_numdevs--; 49512623Sphk return (0); 49612623Sphk} 49712623Sphk 49812623Sphk/* 49912623Sphk * PCI power manangement 50012623Sphk */ 50112623Sphkint 50244972Sphkpci_set_powerstate_method(device_t dev, device_t child, int state) 50344078Sdfr{ 50444078Sdfr struct pci_devinfo *dinfo = device_get_ivars(child); 50512623Sphk pcicfgregs *cfg = &dinfo->cfg; 50612131Sphk uint16_t status; 50712623Sphk int result, oldstate, highest, delay; 50812623Sphk 50912623Sphk if (cfg->pp.pp_cap == 0) 51044078Sdfr return (EOPNOTSUPP); 51144078Sdfr 51212623Sphk /* 51312623Sphk * Optimize a no state change request away. While it would be OK to 51412623Sphk * write to the hardware in theory, some devices have shown odd 51512623Sphk * behavior when going from D3 -> D3. 51612623Sphk */ 51712623Sphk oldstate = pci_get_powerstate(child); 51844972Sphk if (oldstate == state) 51912623Sphk return (0); 52012623Sphk 52144078Sdfr /* 52212623Sphk * The PCI power management specification states that after a state 52312623Sphk * transition between PCI power states, system software must 52444972Sphk * guarantee a minimal delay before the function accesses the device. 52512623Sphk * Compute the worst case delay that we need to guarantee before we 52612623Sphk * access the device. Many devices will be responsive much more 52744972Sphk * quickly than this delay, but there are some that don't respond 52812623Sphk * instantly to state changes. Transitions to/from D3 state require 52912623Sphk * 10ms, while D2 requires 200us, and D0/1 require none. The delay 53012623Sphk * is done below with DELAY rather than a sleeper function because 53112623Sphk * this function can be called from contexts where we cannot sleep. 53212623Sphk */ 53312623Sphk highest = (oldstate > state) ? oldstate : state; 53412623Sphk if (highest == PCI_POWERSTATE_D3) 53563978Speter delay = 10000; 53644078Sdfr else if (highest == PCI_POWERSTATE_D2) 53712623Sphk delay = 200; 53844078Sdfr else 53912623Sphk delay = 0; 54012623Sphk status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 54144078Sdfr & ~PCIM_PSTAT_DMASK; 54244078Sdfr result = 0; 54344078Sdfr switch (state) { 54412623Sphk case PCI_POWERSTATE_D0: 545101650Smux status |= PCIM_PSTAT_D0; 546101650Smux break; 547101650Smux case PCI_POWERSTATE_D1: 54812623Sphk if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 54944078Sdfr return (EOPNOTSUPP); 55012623Sphk status |= PCIM_PSTAT_D1; 55144078Sdfr break; 55212623Sphk case PCI_POWERSTATE_D2: 55312623Sphk if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 55444078Sdfr return (EOPNOTSUPP); 55563978Speter status |= PCIM_PSTAT_D2; 55644078Sdfr break; 55715241Sphk case PCI_POWERSTATE_D3: 55815241Sphk status |= PCIM_PSTAT_D3; 55912623Sphk break; 56012623Sphk default: 56144078Sdfr return (EINVAL); 56212623Sphk } 56312623Sphk 56444078Sdfr if (bootverbose) 56544078Sdfr printf( 56612623Sphk "pci%d:%d:%d: Transition from D%d to D%d\n", 56744078Sdfr dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 56812623Sphk oldstate, state); 56944078Sdfr 57063978Speter PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 57144078Sdfr if (delay) 57212623Sphk DELAY(delay); 57315241Sphk return (0); 57412623Sphk} 57544078Sdfr 57612623Sphkint 57712623Sphkpci_get_powerstate_method(device_t dev, device_t child) 57844078Sdfr{ 57912623Sphk struct pci_devinfo *dinfo = device_get_ivars(child); 58012623Sphk pcicfgregs *cfg = &dinfo->cfg; 58144078Sdfr uint16_t status; 58263978Speter int result; 58344078Sdfr 58412623Sphk if (cfg->pp.pp_cap != 0) { 58515241Sphk status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 58612623Sphk switch (status & PCIM_PSTAT_DMASK) { 58712623Sphk case PCIM_PSTAT_D0: 58812623Sphk result = PCI_POWERSTATE_D0; 58912623Sphk break; 59012623Sphk case PCIM_PSTAT_D1: 59112623Sphk result = PCI_POWERSTATE_D1; 59212623Sphk break; 59362573Sphk case PCIM_PSTAT_D2: 59412623Sphk result = PCI_POWERSTATE_D2; 59512623Sphk break; 59612623Sphk case PCIM_PSTAT_D3: 59712623Sphk result = PCI_POWERSTATE_D3; 59812623Sphk break; 59944078Sdfr default: 60012623Sphk result = PCI_POWERSTATE_UNKNOWN; 60112623Sphk break; 60263978Speter } 60312623Sphk } else { 60412623Sphk /* No support, device is always at D0 */ 60512650Sphk result = PCI_POWERSTATE_D0; 60612623Sphk } 60712623Sphk return (result); 60812623Sphk} 60912623Sphk 61012623Sphk/* 61112623Sphk * Some convenience functions for PCI device drivers. 61244078Sdfr */ 61312623Sphk 61444078Sdfrstatic __inline void 61544078Sdfrpci_set_command_bit(device_t dev, device_t child, uint16_t bit) 61644078Sdfr{ 61712623Sphk uint16_t command; 61812623Sphk 61912623Sphk command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 62012623Sphk command |= bit; 62112623Sphk PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 62212623Sphk} 62312623Sphk 62412623Sphkstatic __inline void 62512623Sphkpci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 62612623Sphk{ 62712623Sphk uint16_t command; 62812623Sphk 62912623Sphk command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 63012623Sphk command &= ~bit; 63112623Sphk PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 63212623Sphk} 63312623Sphk 63444078Sdfrint 63512623Sphkpci_enable_busmaster_method(device_t dev, device_t child) 63644078Sdfr{ 63744078Sdfr pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 63844078Sdfr return (0); 63912623Sphk} 64012623Sphk 64144078Sdfrint 64212623Sphkpci_disable_busmaster_method(device_t dev, device_t child) 64312623Sphk{ 64412623Sphk pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 64544078Sdfr return (0); 64644078Sdfr} 64712623Sphk 64812623Sphkint 64912623Sphkpci_enable_io_method(device_t dev, device_t child, int space) 65044078Sdfr{ 65112623Sphk uint16_t command; 65212623Sphk uint16_t bit; 65344078Sdfr char *error; 65412623Sphk 65512623Sphk bit = 0; 65644078Sdfr error = NULL; 65744078Sdfr 65812623Sphk switch(space) { 65912623Sphk case SYS_RES_IOPORT: 66012623Sphk bit = PCIM_CMD_PORTEN; 66112623Sphk error = "port"; 66212623Sphk break; 66312623Sphk case SYS_RES_MEMORY: 66412623Sphk bit = PCIM_CMD_MEMEN; 66512623Sphk error = "memory"; 66612623Sphk break; 66712623Sphk default: 66812623Sphk return (EINVAL); 66962573Sphk } 67012623Sphk pci_set_command_bit(dev, child, bit); 67112623Sphk /* Some devices seem to need a brief stall here, what do to? */ 67212623Sphk command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 67312623Sphk if (command & bit) 67412623Sphk return (0); 67512623Sphk device_printf(child, "failed to enable %s mapping!\n", error); 67612623Sphk return (ENXIO); 67745140Sphk} 67845140Sphk 67912623Sphkint 68012623Sphkpci_disable_io_method(device_t dev, device_t child, int space) 68112623Sphk{ 68212623Sphk uint16_t command; 68312623Sphk uint16_t bit; 68412623Sphk char *error; 68512623Sphk 68612623Sphk bit = 0; 68712623Sphk error = NULL; 68812623Sphk 68912623Sphk switch(space) { 69012623Sphk case SYS_RES_IOPORT: 69112623Sphk bit = PCIM_CMD_PORTEN; 69212623Sphk error = "port"; 69312623Sphk break; 69412623Sphk case SYS_RES_MEMORY: 69512623Sphk bit = PCIM_CMD_MEMEN; 69612623Sphk error = "memory"; 69712650Sphk break; 69812623Sphk default: 69912623Sphk return (EINVAL); 70012623Sphk } 70112910Sphk pci_clear_command_bit(dev, child, bit); 70212623Sphk command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 70312623Sphk if (command & bit) { 70412623Sphk device_printf(child, "failed to disable %s mapping!\n", error); 70562573Sphk return (ENXIO); 70612623Sphk } 70744078Sdfr return (0); 70853977Sgreen} 70912623Sphk 71053977Sgreen/* 71153977Sgreen * New style pci driver. Parent device is either a pci-host-bridge or a 71253977Sgreen * pci-pci-bridge. Both kinds are represented by instances of pcib. 71312623Sphk */ 71444078Sdfr 71553977Sgreenvoid 71653977Sgreenpci_print_verbose(struct pci_devinfo *dinfo) 71753977Sgreen{ 71853977Sgreen if (bootverbose) { 71953977Sgreen pcicfgregs *cfg = &dinfo->cfg; 72012650Sphk 72112623Sphk printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 72212623Sphk cfg->vendor, cfg->device, cfg->revid); 72342467Sphk printf("\tbus=%d, slot=%d, func=%d\n", 72412623Sphk cfg->bus, cfg->slot, cfg->func); 72512623Sphk printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 72688006Sluigi cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 72788006Sluigi cfg->mfdev); 72888006Sluigi printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 72988006Sluigi cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 73088006Sluigi printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 73188006Sluigi cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 73288006Sluigi cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 73388006Sluigi if (cfg->intpin > 0) 73488006Sluigi printf("\tintpin=%c, irq=%d\n", 73588006Sluigi cfg->intpin +'a' -1, cfg->intline); 73688006Sluigi if (cfg->pp.pp_cap) { 73788006Sluigi uint16_t status; 73888006Sluigi 73988006Sluigi status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 74088006Sluigi printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 74188006Sluigi cfg->pp.pp_cap & PCIM_PCAP_SPEC, 74288006Sluigi cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 74388006Sluigi cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 74412243Sphk status & PCIM_PSTAT_DMASK); 74512623Sphk } 74612623Sphk if (cfg->msi.msi_data) { 74712623Sphk int ctrl; 74812623Sphk 74942095Sdfr ctrl = cfg->msi.msi_ctrl; 75012243Sphk printf("\tMSI supports %d message%s%s%s\n", 75112243Sphk cfg->msi.msi_msgnum, 75212243Sphk (cfg->msi.msi_msgnum == 1) ? "" : "s", 75312243Sphk (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 75412243Sphk (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 75511865Sphk } 75662573Sphk } 75711863Sphk} 758100833Struckman 75911863Sphkstatic int 760100833Struckmanpci_porten(device_t pcib, int b, int s, int f) 761100833Struckman{ 762100833Struckman return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 76312243Sphk & PCIM_CMD_PORTEN) != 0; 764100833Struckman} 76520506Sbde 766100833Struckmanstatic int 767100833Struckmanpci_memen(device_t pcib, int b, int s, int f) 76811863Sphk{ 76912243Sphk return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 77012243Sphk & PCIM_CMD_MEMEN) != 0; 77111863Sphk} 77212243Sphk 77312243Sphk/* 77412243Sphk * Add a resource based on a pci map register. Return 1 if the map 77512243Sphk * register is a 32bit map register or 2 if it is a 64bit register. 77612243Sphk */ 77711863Sphkstatic int 77811863Sphkpci_add_map(device_t pcib, device_t bus, device_t dev, 77912243Sphk int b, int s, int f, int reg, struct resource_list *rl) 78045140Sphk{ 78138517Sdfr uint32_t map; 78238517Sdfr uint64_t base; 78338517Sdfr uint64_t start, end, count; 78462573Sphk uint8_t ln2size; 78538517Sdfr uint8_t ln2range; 78638517Sdfr uint32_t testval; 787100833Struckman uint16_t cmd; 78838517Sdfr int type; 789100833Struckman int barlen; 790100833Struckman 791100833Struckman map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 79245140Sphk PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 79345140Sphk testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 794100833Struckman PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 795100833Struckman 79638517Sdfr if (pci_maptype(map) & PCI_MAPMEM) 79738517Sdfr type = SYS_RES_MEMORY; 79838517Sdfr else 79938517Sdfr type = SYS_RES_IOPORT; 80045140Sphk ln2size = pci_mapsize(testval); 80138517Sdfr ln2range = pci_maprange(testval); 80238517Sdfr base = pci_mapbase(map); 80338517Sdfr barlen = ln2range == 64 ? 2 : 1; 80438517Sdfr 80512243Sphk /* 80612243Sphk * For I/O registers, if bottom bit is set, and the next bit up 80712243Sphk * isn't clear, we know we have a BAR that doesn't conform to the 80812243Sphk * spec, so ignore it. Also, sanity check the size of the data 80912243Sphk * areas to the type of memory involved. Memory must be at least 81012243Sphk * 32 bytes in size, while I/O ranges must be at least 4. 81111865Sphk */ 81262573Sphk if ((testval & 0x1) == 0x1 && 81311863Sphk (testval & 0x2) != 0) 81412243Sphk return (barlen); 815100833Struckman if ((type == SYS_RES_MEMORY && ln2size < 5) || 816100833Struckman (type == SYS_RES_IOPORT && ln2size < 2)) 81711863Sphk return (barlen); 818100833Struckman 819100833Struckman if (ln2range == 64) 820100833Struckman /* Read the other half of a 64bit map register */ 821100833Struckman base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 822100833Struckman 823100833Struckman if (bootverbose) { 824100833Struckman printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 825100833Struckman reg, pci_maptype(map), ln2range, 826100833Struckman (unsigned int) base, ln2size); 827100833Struckman if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 828100833Struckman printf(", port disabled\n"); 829100833Struckman else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 830100833Struckman printf(", memory disabled\n"); 831100833Struckman else 83211863Sphk printf(", enabled\n"); 83345140Sphk } 83412243Sphk 83511863Sphk /* 83645140Sphk * If base is 0, then we have problems. It is best to ignore 83745140Sphk * such entries for the moment. These will be allocated later if 83812243Sphk * the driver specifically requests them. 83912243Sphk * 84012243Sphk * Similarly treat maps whose values is the same as the test value 84112243Sphk * read back. These maps have had all f's written to them by the 84211863Sphk * BIOS in an attempt to disable the resources. 84312131Sphk */ 84412131Sphk if (base == 0 || map == testval) 84511863Sphk return (barlen); 84611863Sphk 84712243Sphk /* 84812243Sphk * This code theoretically does the right thing, but has 84912243Sphk * undesirable side effects in some cases where peripherals 85012243Sphk * respond oddly to having these bits enabled. Let the user 85112243Sphk * be able to turn them off (since pci_enable_io_modes is 1 by 85211865Sphk * default). 85362573Sphk */ 85411863Sphk if (pci_enable_io_modes) { 85512243Sphk /* Turn on resources that have been left off by a lazy BIOS */ 856100833Struckman if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 85712243Sphk cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 858100833Struckman cmd |= PCIM_CMD_PORTEN; 859100833Struckman PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 860100833Struckman } 861100833Struckman if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 862100833Struckman cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 863100833Struckman cmd |= PCIM_CMD_MEMEN; 864100833Struckman PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 865100833Struckman } 866100833Struckman } else { 867100833Struckman if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 868100833Struckman return (barlen); 869100833Struckman if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 870100833Struckman return (barlen); 871100833Struckman } 87212243Sphk 87312243Sphk start = base; 87412243Sphk end = base + (1 << ln2size) - 1; 87512243Sphk count = 1 << ln2size; 87612243Sphk resource_list_add(rl, type, reg, start, end, count); 87712243Sphk 87812243Sphk /* 87912243Sphk * Not quite sure what to do on failure of allocating the resource 88012243Sphk * since I can postulate several right answers. 88112260Sphk */ 88212260Sphk resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 88312260Sphk return (barlen); 88412260Sphk} 88512260Sphk 88638517Sdfr/* 88712243Sphk * For ATA devices we need to decide early what addressing mode to use. 88838517Sdfr * Legacy demands that the primary and secondary ATA ports sits on the 88912260Sphk * same addresses that old ISA hardware did. This dictates that we use 89012260Sphk * those addresses and ignore the BAR's if we cannot set PCI native 89138517Sdfr * addressing mode. 89273971Stmm */ 89373971Stmmstatic void 89473971Stmmpci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 89573971Stmm int s, int f, struct resource_list *rl) 89673971Stmm{ 89712260Sphk int rid, type, progif; 89817971Sbde#if 0 89912243Sphk /* if this device supports PCI native addressing use it */ 90012260Sphk progif = pci_read_config(dev, PCIR_PROGIF, 1); 90116282Snate if ((progif & 0x8a) == 0x8a) { 90211863Sphk if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 90312260Sphk pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 90412243Sphk printf("Trying ATA native PCI addressing mode\n"); 90512243Sphk pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 90612260Sphk } 90738517Sdfr } 90812243Sphk#endif 90912260Sphk progif = pci_read_config(dev, PCIR_PROGIF, 1); 91012260Sphk type = SYS_RES_IOPORT; 91112260Sphk if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 91211863Sphk pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 91317971Sbde pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 91412243Sphk } 91512131Sphk else { 91611863Sphk rid = PCIR_BAR(0); 91711863Sphk resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 91816282Snate resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 91983366Sjulian rid = PCIR_BAR(1); 92076834Sjlemon resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 92116282Snate resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 92216282Snate } 92316282Snate if (progif & PCIP_STORAGE_IDE_MODESEC) { 92416282Snate pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 92516282Snate pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 92616282Snate } 92786183Srwatson else { 92816282Snate rid = PCIR_BAR(2); 92916282Snate resource_list_add(rl, type, rid, 0x170, 0x177, 8); 93016282Snate resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 93116282Snate rid = PCIR_BAR(3); 93216282Snate resource_list_add(rl, type, rid, 0x376, 0x376, 1); 93316282Snate resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 93416282Snate } 93516282Snate pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 93616282Snate pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl); 93777646Sdd} 93816282Snate 93916282Snatestatic void 94016282Snatepci_add_resources(device_t pcib, device_t bus, device_t dev) 94116282Snate{ 94216282Snate struct pci_devinfo *dinfo = device_get_ivars(dev); 94316282Snate pcicfgregs *cfg = &dinfo->cfg; 94416282Snate struct resource_list *rl = &dinfo->resources; 94516282Snate struct pci_quirk *q; 94693625Srwatson int b, i, irq, f, s; 94716282Snate 94816282Snate b = cfg->bus; 94916282Snate s = cfg->slot; 95016282Snate f = cfg->func; 95157975Sphk 95216282Snate /* ATA devices needs special map treatment */ 95393625Srwatson if ((pci_get_class(dev) == PCIC_STORAGE) && 95416282Snate (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 95516282Snate (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 95616282Snate pci_ata_maps(pcib, bus, dev, b, s, f, rl); 95716282Snate else 95816282Snate for (i = 0; i < cfg->nummaps;) 95916282Snate i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 96016282Snate rl); 96116282Snate 96216282Snate for (q = &pci_quirks[0]; q->devid; q++) { 96316282Snate if (q->devid == ((cfg->device << 16) | cfg->vendor) 96416282Snate && q->type == PCI_QUIRK_MAP_REG) 96516282Snate pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 96616282Snate } 96776834Sjlemon 96883366Sjulian if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 96976834Sjlemon#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 97076834Sjlemon defined(__arm__) || defined(__alpha__) 97176834Sjlemon /* 97278620Smjacob * Try to re-route interrupts. Sometimes the BIOS or 97378620Smjacob * firmware may leave bogus values in these registers. 97476834Sjlemon * If the re-route fails, then just stick with what we 97576834Sjlemon * have. 97676834Sjlemon */ 97776834Sjlemon irq = PCI_ASSIGN_INTERRUPT(bus, dev); 97876834Sjlemon if (PCI_INTERRUPT_VALID(irq)) { 97983366Sjulian pci_write_config(dev, PCIR_INTLINE, irq, 1); 98076834Sjlemon cfg->intline = irq; 98176834Sjlemon } else 98276834Sjlemon#endif 98376834Sjlemon irq = cfg->intline; 98483366Sjulian resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 98576834Sjlemon } 98676834Sjlemon} 98776834Sjlemon 98876834Sjlemonvoid 98912260Sphkpci_add_children(device_t dev, int busno, size_t dinfo_size) 99012260Sphk{ 99112260Sphk#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 99212260Sphk device_t pcib = device_get_parent(dev); 99338517Sdfr struct pci_devinfo *dinfo; 99412243Sphk int maxslots; 99538517Sdfr int s, f, pcifunchigh; 99638517Sdfr uint8_t hdrtype; 99712243Sphk 998101422Struckman KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 999101422Struckman ("dinfo_size too small")); 100012260Sphk maxslots = PCIB_MAXSLOTS(pcib); 100138517Sdfr for (s = 0; s <= maxslots; s++) { 100273971Stmm pcifunchigh = 0; 100373971Stmm f = 0; 100473971Stmm hdrtype = REG(PCIR_HDRTYPE, 1); 100573971Stmm if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 100673971Stmm continue; 100712260Sphk if (hdrtype & PCIM_MFDEV) 100817971Sbde pcifunchigh = PCI_FUNCMAX; 100917971Sbde for (f = 0; f <= pcifunchigh; f++) { 101012260Sphk dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 101112260Sphk if (dinfo != NULL) { 101212243Sphk pci_add_child(dev, dinfo); 101312243Sphk } 101412260Sphk } 101512243Sphk } 101612260Sphk#undef REG 101712243Sphk} 101812243Sphk 101912260Sphkvoid 102038517Sdfrpci_add_child(device_t bus, struct pci_devinfo *dinfo) 102112243Sphk{ 102212285Sphk device_t pcib; 102312260Sphk 102412260Sphk pcib = device_get_parent(bus); 102512260Sphk dinfo->cfg.dev = device_add_child(bus, NULL, -1); 102612260Sphk device_set_ivars(dinfo->cfg.dev, dinfo); 102712243Sphk resource_list_init(&dinfo->resources); 102817971Sbde pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 102912243Sphk pci_cfg_restore(dinfo->cfg.dev, dinfo); 103012243Sphk pci_print_verbose(dinfo); 103112243Sphk pci_add_resources(pcib, bus, dinfo->cfg.dev); 103212243Sphk} 1033100487Struckman 1034100487Struckmanstatic int 1035100487Struckmanpci_probe(device_t dev) 1036100487Struckman{ 1037100487Struckman 1038100487Struckman device_set_desc(dev, "PCI bus"); 1039100487Struckman 1040100487Struckman /* Allow other subclasses to override this driver. */ 1041100487Struckman return (-1000); 1042100487Struckman} 1043100487Struckman 1044100487Struckmanstatic int 1045100487Struckmanpci_attach(device_t dev) 1046100487Struckman{ 1047100487Struckman int busno; 1048100487Struckman 1049100487Struckman /* 10501541Srgrimes * Since there can be multiple independantly numbered PCI 105153977Sgreen * busses on some large alpha systems, we can't use the unit 105253977Sgreen * number to decide what bus we are probing. We ask the parent 105312131Sphk * pcib what our bus number is. 105444078Sdfr */ 105553977Sgreen busno = pcib_get_bus(dev); 105612131Sphk if (bootverbose) 105753977Sgreen device_printf(dev, "physical bus=%d\n", busno); 105812131Sphk 105944078Sdfr pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 106044078Sdfr 106112131Sphk return (bus_generic_attach(dev)); 106244078Sdfr} 106312429Sphk 106444078Sdfrint 106553977Sgreenpci_suspend(device_t dev) 106653977Sgreen{ 106753977Sgreen int dstate, error, i, numdevs; 106853977Sgreen device_t acpi_dev, child, *devlist; 106953977Sgreen struct pci_devinfo *dinfo; 107053977Sgreen 107153977Sgreen /* 107253977Sgreen * Save the PCI configuration space for each child and set the 107353977Sgreen * device in the appropriate power state for this sleep state. 107453977Sgreen */ 107553977Sgreen acpi_dev = NULL; 107653977Sgreen if (pci_do_power_resume) 107753977Sgreen acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 107853977Sgreen device_get_children(dev, &devlist, &numdevs); 107912131Sphk for (i = 0; i < numdevs; i++) { 108053977Sgreen child = devlist[i]; 108112131Sphk dinfo = (struct pci_devinfo *) device_get_ivars(child); 108212131Sphk pci_cfg_save(child, dinfo, 0); 108344078Sdfr } 108412131Sphk 108512131Sphk /* Suspend devices before potentially powering them down. */ 108653977Sgreen error = bus_generic_suspend(dev); 108753977Sgreen if (error) { 108853977Sgreen free(devlist, M_TEMP); 108953977Sgreen return (error); 109053977Sgreen } 109153977Sgreen 109253977Sgreen /* 109353977Sgreen * Always set the device to D3. If ACPI suggests a different 1094104094Sphk * power state, use it instead. If ACPI is not present, the 109562573Sphk * firmware is responsible for managing device power. Skip 109653977Sgreen * children who aren't attached since they are powered down 109753977Sgreen * separately. Only manage type 0 devices for now. 109853977Sgreen */ 109953977Sgreen for (i = 0; acpi_dev && i < numdevs; i++) { 110053977Sgreen child = devlist[i]; 110153977Sgreen dinfo = (struct pci_devinfo *) device_get_ivars(child); 110253977Sgreen if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 110353977Sgreen dstate = PCI_POWERSTATE_D3; 110453977Sgreen ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 110553977Sgreen pci_set_powerstate(child, dstate); 110653977Sgreen } 110753977Sgreen } 110853977Sgreen free(devlist, M_TEMP); 110953977Sgreen return (0); 111053977Sgreen} 111153977Sgreen 111253977Sgreenint 111353977Sgreenpci_resume(device_t dev) 111483968Srwatson{ 111583968Srwatson int i, numdevs; 111612131Sphk device_t acpi_dev, child, *devlist; 111712131Sphk struct pci_devinfo *dinfo; 111892953Srwatson 111992953Srwatson /* 112083968Srwatson * Set each child to D0 and restore its PCI configuration space. 112183968Srwatson */ 112292953Srwatson acpi_dev = NULL; 112392953Srwatson if (pci_do_power_resume) 112492953Srwatson acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 112583968Srwatson device_get_children(dev, &devlist, &numdevs); 112612910Sphk for (i = 0; i < numdevs; i++) { 112783968Srwatson /* 112883968Srwatson * Notify ACPI we're going to D0 but ignore the result. If 112992953Srwatson * ACPI is not present, the firmware is responsible for 113083968Srwatson * managing device power. Only manage type 0 devices for now. 113192953Srwatson */ 113292953Srwatson child = devlist[i]; 113392953Srwatson dinfo = (struct pci_devinfo *) device_get_ivars(child); 113492953Srwatson if (acpi_dev && device_is_attached(child) && 113593593Sjhb dinfo->cfg.hdrtype == 0) { 113692953Srwatson ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 113792953Srwatson pci_set_powerstate(child, PCI_POWERSTATE_D0); 113883968Srwatson } 113983968Srwatson 114044078Sdfr /* Now the device is powered up, restore its config space. */ 114112131Sphk pci_cfg_restore(child, dinfo); 114212131Sphk } 114353977Sgreen free(devlist, M_TEMP); 114453977Sgreen return (bus_generic_resume(dev)); 114553977Sgreen} 114653977Sgreen 114753977Sgreenstatic void 114853977Sgreenpci_load_vendor_data(void) 114953977Sgreen{ 115012131Sphk caddr_t vendordata, info; 115112131Sphk 115212221Sbde if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 115312171Sphk info = preload_search_info(vendordata, MODINFO_ADDR); 115412171Sphk pci_vendordata = *(char **)info; 115512171Sphk info = preload_search_info(vendordata, MODINFO_SIZE); 115612171Sphk pci_vendordata_size = *(size_t *)info; 115712171Sphk /* terminate the database */ 115812171Sphk pci_vendordata[pci_vendordata_size] = '\n'; 115912171Sphk } 116012171Sphk} 116112221Sbde 116212171Sphkvoid 116382746Sdillonpci_driver_added(device_t dev, driver_t *driver) 116482746Sdillon{ 116582746Sdillon int numdevs; 116612131Sphk device_t *devlist; 116783366Sjulian device_t child; 11681541Srgrimes struct pci_devinfo *dinfo; 116982746Sdillon int i; 117038517Sdfr 11711541Srgrimes if (bootverbose) 11721541Srgrimes device_printf(dev, "driver added\n"); 11731541Srgrimes DEVICE_IDENTIFY(driver, dev); 117411863Sphk device_get_children(dev, &devlist, &numdevs); 11753308Sphk for (i = 0; i < numdevs; i++) { 11763308Sphk child = devlist[i]; 11771541Srgrimes if (device_get_state(child) != DS_NOTPRESENT) 11781541Srgrimes continue; 117982746Sdillon dinfo = device_get_ivars(child); 118082746Sdillon pci_print_verbose(dinfo); 118183366Sjulian if (bootverbose) 118212171Sphk printf("pci%d:%d:%d: reprobing on driver added\n", 118312260Sphk dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 118412260Sphk pci_cfg_restore(child, dinfo); 118582746Sdillon if (device_probe_and_attach(child) != 0) 118612260Sphk pci_cfg_save(child, dinfo, 1); 118782746Sdillon } 118812260Sphk free(devlist, M_TEMP); 118982746Sdillon} 119012260Sphk 119182746Sdillonint 119282746Sdillonpci_print_child(device_t dev, device_t child) 119312260Sphk{ 119412171Sphk struct pci_devinfo *dinfo; 119512171Sphk struct resource_list *rl; 119612171Sphk int retval = 0; 119712171Sphk 119812171Sphk dinfo = device_get_ivars(child); 119912171Sphk rl = &dinfo->resources; 120012171Sphk 120183366Sjulian retval += bus_print_child_header(dev, child); 120280338Sroam 120312171Sphk retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 120412429Sphk retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 120516159Sphk retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 120612171Sphk if (device_get_flags(dev)) 120712243Sphk retval += printf(" flags %#x", device_get_flags(dev)); 120812243Sphk 120986183Srwatson retval += printf(" at device %d.%d", pci_get_slot(child), 121012285Sphk pci_get_function(child)); 121112171Sphk 121212171Sphk retval += bus_print_child_footer(dev, child); 121312243Sphk 121412171Sphk return (retval); 121512260Sphk} 121612171Sphk 121712171Sphkstatic struct 121812171Sphk{ 121912171Sphk int class; 122012171Sphk int subclass; 122112243Sphk char *desc; 122252644Sphk} pci_nomatch_tab[] = { 122312243Sphk {PCIC_OLD, -1, "old"}, 122412243Sphk {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 122512243Sphk {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 122612131Sphk {PCIC_STORAGE, -1, "mass storage"}, 122777646Sdd {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 122852644Sphk {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 122912243Sphk {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 123012243Sphk {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 123112243Sphk {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 123211863Sphk {PCIC_NETWORK, -1, "network"}, 123312131Sphk {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 123412243Sphk {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 123512243Sphk {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 123612429Sphk {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 123711863Sphk {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 123893625Srwatson {PCIC_DISPLAY, -1, "display"}, 123912429Sphk {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 124016159Sphk {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 124116159Sphk {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 124216159Sphk {PCIC_MULTIMEDIA, -1, "multimedia"}, 124316159Sphk {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 124412243Sphk {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 124516159Sphk {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 124612429Sphk {PCIC_MEMORY, -1, "memory"}, 124757975Sphk {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 124812429Sphk {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 124993625Srwatson {PCIC_BRIDGE, -1, "bridge"}, 125012429Sphk {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 125112260Sphk {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 125212260Sphk {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 125312260Sphk {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 125412260Sphk {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 125512260Sphk {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 125612243Sphk {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 125712260Sphk {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 125812260Sphk {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 125911863Sphk {PCIC_SIMPLECOMM, -1, "simple comms"}, 126012260Sphk {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 12611541Srgrimes {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 12621541Srgrimes {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 12631541Srgrimes {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 12641541Srgrimes {PCIC_BASEPERIPH, -1, "base peripheral"}, 126515103Sphk {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 126615103Sphk {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 12671541Srgrimes {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 12681541Srgrimes {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 12691541Srgrimes {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 12701541Srgrimes {PCIC_INPUTDEV, -1, "input device"}, 12711541Srgrimes {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 12721541Srgrimes {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 12731541Srgrimes {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 12741541Srgrimes {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 12759455Speter {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 12769455Speter {PCIC_DOCKING, -1, "docking station"}, 12779455Speter {PCIC_PROCESSOR, -1, "processor"}, 12789455Speter {PCIC_SERIALBUS, -1, "serial bus"}, 12799455Speter {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 12809455Speter {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 12819455Speter {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 12829455Speter {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 128312819Sphk {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 12849455Speter {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 12859455Speter {PCIC_WIRELESS, -1, "wireless controller"}, 12869455Speter {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 12879455Speter {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 12889455Speter {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 12899455Speter {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 12909455Speter {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 12919455Speter {PCIC_SATCOM, -1, "satellite communication"}, 12929455Speter {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 12939455Speter {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 12949455Speter {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 12959455Speter {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 12969455Speter {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 12979455Speter {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 12989455Speter {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 12999455Speter {PCIC_DASP, -1, "dasp"}, 13009455Speter {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 13019455Speter {0, 0, NULL} 13029455Speter}; 13039455Speter 13049455Spetervoid 13059455Speterpci_probe_nomatch(device_t dev, device_t child) 13069455Speter{ 13079455Speter int i; 13089455Speter char *cp, *scp, *device; 13099455Speter 13109455Speter /* 13119455Speter * Look for a listing for this device in a loaded device database. 13129455Speter */ 13139455Speter if ((device = pci_describe_device(child)) != NULL) { 13149455Speter device_printf(dev, "<%s>", device); 13159455Speter free(device, M_DEVBUF); 13169455Speter } else { 13179455Speter /* 13189455Speter * Scan the class/subclass descriptions for a general 13199455Speter * description. 132012819Sphk */ 13219455Speter cp = "unknown"; 132212221Sbde scp = NULL; 13231541Srgrimes for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 13241541Srgrimes if (pci_nomatch_tab[i].class == pci_get_class(child)) { 13251541Srgrimes if (pci_nomatch_tab[i].subclass == -1) { 132638864Sbde cp = pci_nomatch_tab[i].desc; 13271541Srgrimes } else if (pci_nomatch_tab[i].subclass == 13281541Srgrimes pci_get_subclass(child)) { 132912221Sbde scp = pci_nomatch_tab[i].desc; 13301541Srgrimes } 133182746Sdillon } 133282746Sdillon } 133382746Sdillon device_printf(dev, "<%s%s%s>", 13341549Srgrimes cp ? cp : "", 133583366Sjulian ((cp != NULL) && (scp != NULL)) ? ", " : "", 13361541Srgrimes scp ? scp : ""); 133712171Sphk } 133838517Sdfr printf(" at device %d.%d (no driver attached)\n", 133982494Speter pci_get_slot(child), pci_get_function(child)); 13401541Srgrimes if (pci_do_power_nodriver) 134182746Sdillon pci_cfg_save(child, 134282746Sdillon (struct pci_devinfo *) device_get_ivars(child), 1); 13431541Srgrimes return; 13441541Srgrimes} 13451541Srgrimes 134612171Sphk/* 134712171Sphk * Parse the PCI device database, if loaded, and return a pointer to a 134812171Sphk * description of the device. 134912171Sphk * 135012171Sphk * The database is flat text formatted as follows: 135112171Sphk * 135283366Sjulian * Any line not in a valid format is ignored. 135312429Sphk * Lines are terminated with newline '\n' characters. 13541541Srgrimes * 13551541Srgrimes * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 13561541Srgrimes * the vendor name. 135712171Sphk * 135812171Sphk * A DEVICE line is entered immediately below the corresponding VENDOR ID. 135983366Sjulian * - devices cannot be listed without a corresponding VENDOR line. 136012429Sphk * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 13611541Srgrimes * another TAB, then the device name. 13621541Srgrimes */ 13631541Srgrimes 136412171Sphk/* 136512171Sphk * Assuming (ptr) points to the beginning of a line in the database, 136612171Sphk * return the vendor or device and description of the next entry. 136712171Sphk * The value of (vendor) or (device) inappropriate for the entry type 136883366Sjulian * is set to -1. Returns nonzero at the end of the database. 136912429Sphk * 13701541Srgrimes * Note that this is slightly unrobust in the face of corrupt data; 13711541Srgrimes * we attempt to safeguard against this by spamming the end of the 13721541Srgrimes * database with a newline when we initialise. 137312171Sphk */ 137412171Sphkstatic int 137583366Sjulianpci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 137612429Sphk{ 13771541Srgrimes char *cp = *ptr; 13781541Srgrimes int left; 13791541Srgrimes 138012171Sphk *device = -1; 138112171Sphk *vendor = -1; 138283366Sjulian **desc = '\0'; 138312429Sphk for (;;) { 13841541Srgrimes left = pci_vendordata_size - (cp - pci_vendordata); 13851541Srgrimes if (left <= 0) { 13861541Srgrimes *ptr = cp; 138712171Sphk return(1); 138812171Sphk } 138983366Sjulian 139012429Sphk /* vendor entry? */ 13911541Srgrimes if (*cp != '\t' && 13921541Srgrimes sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 13931541Srgrimes break; 139412171Sphk /* device entry? */ 139512171Sphk if (*cp == '\t' && 139683366Sjulian sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 139712429Sphk break; 13981541Srgrimes 13991541Srgrimes /* skip to next line */ 14009455Speter while (*cp != '\n' && left > 0) { 14019455Speter cp++; 14029455Speter left--; 14039455Speter } 14049455Speter if (*cp == '\n') { 140582494Speter cp++; 140682494Speter left--; 140782494Speter } 140882494Speter } 140982494Speter /* skip to next line */ 141082494Speter while (*cp != '\n' && left > 0) { 141182494Speter cp++; 14129455Speter left--; 14139455Speter } 14149455Speter if (*cp == '\n' && left > 0) 14159455Speter cp++; 14169455Speter *ptr = cp; 14179455Speter return(0); 14189455Speter} 14199455Speter 14209455Speterstatic char * 14219455Speterpci_describe_device(device_t dev) 14229455Speter{ 14239455Speter int vendor, device; 14249455Speter char *desc, *vp, *dp, *line; 14259455Speter 14269455Speter desc = vp = dp = NULL; 14279455Speter 14289455Speter /* 14299455Speter * If we have no vendor data, we can't do anything. 14309455Speter */ 14319455Speter if (pci_vendordata == NULL) 14329455Speter goto out; 14339455Speter 14349455Speter /* 14359455Speter * Scan the vendor data looking for this device 143682494Speter */ 14379455Speter line = pci_vendordata; 14389455Speter if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 14399455Speter goto out; 14409455Speter for (;;) { 14419455Speter if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 14429455Speter goto out; 144382494Speter if (vendor == pci_get_vendor(dev)) 144482494Speter break; 14459455Speter } 14469455Speter if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 14479455Speter goto out; 14489455Speter for (;;) { 14499455Speter if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 14509455Speter *dp = 0; 14519455Speter break; 14529455Speter } 14539455Speter if (vendor != -1) { 14549455Speter *dp = 0; 14559455Speter break; 14569455Speter } 14579455Speter if (device == pci_get_device(dev)) 14589455Speter break; 14599455Speter } 14609455Speter if (dp[0] == '\0') 14619455Speter snprintf(dp, 80, "0x%x", pci_get_device(dev)); 14629455Speter if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 14639455Speter NULL) 14649455Speter sprintf(desc, "%s, %s", vp, dp); 14651541Srgrimes out: 146682746Sdillon if (vp != NULL) 146782746Sdillon free(vp, M_DEVBUF); 14681541Srgrimes if (dp != NULL) 146982746Sdillon free(dp, M_DEVBUF); 147083366Sjulian return(desc); 147182746Sdillon} 147299012Salfred 147382746Sdillonint 147482746Sdillonpci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 147582746Sdillon{ 14761541Srgrimes struct pci_devinfo *dinfo; 14771541Srgrimes pcicfgregs *cfg; 14781541Srgrimes 1479 dinfo = device_get_ivars(child); 1480 cfg = &dinfo->cfg; 1481 1482 switch (which) { 1483 case PCI_IVAR_ETHADDR: 1484 /* 1485 * The generic accessor doesn't deal with failure, so 1486 * we set the return value, then return an error. 1487 */ 1488 *((uint8_t **) result) = NULL; 1489 return (EINVAL); 1490 case PCI_IVAR_SUBVENDOR: 1491 *result = cfg->subvendor; 1492 break; 1493 case PCI_IVAR_SUBDEVICE: 1494 *result = cfg->subdevice; 1495 break; 1496 case PCI_IVAR_VENDOR: 1497 *result = cfg->vendor; 1498 break; 1499 case PCI_IVAR_DEVICE: 1500 *result = cfg->device; 1501 break; 1502 case PCI_IVAR_DEVID: 1503 *result = (cfg->device << 16) | cfg->vendor; 1504 break; 1505 case PCI_IVAR_CLASS: 1506 *result = cfg->baseclass; 1507 break; 1508 case PCI_IVAR_SUBCLASS: 1509 *result = cfg->subclass; 1510 break; 1511 case PCI_IVAR_PROGIF: 1512 *result = cfg->progif; 1513 break; 1514 case PCI_IVAR_REVID: 1515 *result = cfg->revid; 1516 break; 1517 case PCI_IVAR_INTPIN: 1518 *result = cfg->intpin; 1519 break; 1520 case PCI_IVAR_IRQ: 1521 *result = cfg->intline; 1522 break; 1523 case PCI_IVAR_BUS: 1524 *result = cfg->bus; 1525 break; 1526 case PCI_IVAR_SLOT: 1527 *result = cfg->slot; 1528 break; 1529 case PCI_IVAR_FUNCTION: 1530 *result = cfg->func; 1531 break; 1532 case PCI_IVAR_CMDREG: 1533 *result = cfg->cmdreg; 1534 break; 1535 case PCI_IVAR_CACHELNSZ: 1536 *result = cfg->cachelnsz; 1537 break; 1538 case PCI_IVAR_MINGNT: 1539 *result = cfg->mingnt; 1540 break; 1541 case PCI_IVAR_MAXLAT: 1542 *result = cfg->maxlat; 1543 break; 1544 case PCI_IVAR_LATTIMER: 1545 *result = cfg->lattimer; 1546 break; 1547 default: 1548 return (ENOENT); 1549 } 1550 return (0); 1551} 1552 1553int 1554pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1555{ 1556 struct pci_devinfo *dinfo; 1557 1558 dinfo = device_get_ivars(child); 1559 1560 switch (which) { 1561 case PCI_IVAR_INTPIN: 1562 dinfo->cfg.intpin = value; 1563 return (0); 1564 case PCI_IVAR_ETHADDR: 1565 case PCI_IVAR_SUBVENDOR: 1566 case PCI_IVAR_SUBDEVICE: 1567 case PCI_IVAR_VENDOR: 1568 case PCI_IVAR_DEVICE: 1569 case PCI_IVAR_DEVID: 1570 case PCI_IVAR_CLASS: 1571 case PCI_IVAR_SUBCLASS: 1572 case PCI_IVAR_PROGIF: 1573 case PCI_IVAR_REVID: 1574 case PCI_IVAR_IRQ: 1575 case PCI_IVAR_BUS: 1576 case PCI_IVAR_SLOT: 1577 case PCI_IVAR_FUNCTION: 1578 return (EINVAL); /* disallow for now */ 1579 1580 default: 1581 return (ENOENT); 1582 } 1583} 1584 1585 1586#include "opt_ddb.h" 1587#ifdef DDB 1588#include <ddb/ddb.h> 1589#include <sys/cons.h> 1590 1591/* 1592 * List resources based on pci map registers, used for within ddb 1593 */ 1594 1595DB_SHOW_COMMAND(pciregs, db_pci_dump) 1596{ 1597 struct pci_devinfo *dinfo; 1598 struct devlist *devlist_head; 1599 struct pci_conf *p; 1600 const char *name; 1601 int i, error, none_count, quit; 1602 1603 none_count = 0; 1604 /* get the head of the device queue */ 1605 devlist_head = &pci_devq; 1606 1607 /* 1608 * Go through the list of devices and print out devices 1609 */ 1610 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1611 for (error = 0, i = 0, quit = 0, 1612 dinfo = STAILQ_FIRST(devlist_head); 1613 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1614 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1615 1616 /* Populate pd_name and pd_unit */ 1617 name = NULL; 1618 if (dinfo->cfg.dev) 1619 name = device_get_name(dinfo->cfg.dev); 1620 1621 p = &dinfo->conf; 1622 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1623 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1624 (name && *name) ? name : "none", 1625 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1626 none_count++, 1627 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1628 p->pc_sel.pc_func, (p->pc_class << 16) | 1629 (p->pc_subclass << 8) | p->pc_progif, 1630 (p->pc_subdevice << 16) | p->pc_subvendor, 1631 (p->pc_device << 16) | p->pc_vendor, 1632 p->pc_revid, p->pc_hdr); 1633 } 1634} 1635#endif /* DDB */ 1636 1637static struct resource * 1638pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1639 u_long start, u_long end, u_long count, u_int flags) 1640{ 1641 struct pci_devinfo *dinfo = device_get_ivars(child); 1642 struct resource_list *rl = &dinfo->resources; 1643 struct resource_list_entry *rle; 1644 struct resource *res; 1645 uint32_t map, testval; 1646 int mapsize; 1647 1648 /* 1649 * Weed out the bogons, and figure out how large the BAR/map 1650 * is. Bars that read back 0 here are bogus and unimplemented. 1651 * Note: atapci in legacy mode are special and handled elsewhere 1652 * in the code. If you have a atapci device in legacy mode and 1653 * it fails here, that other code is broken. 1654 */ 1655 res = NULL; 1656 map = pci_read_config(child, *rid, 4); 1657 pci_write_config(child, *rid, 0xffffffff, 4); 1658 testval = pci_read_config(child, *rid, 4); 1659 if (pci_mapbase(testval) == 0) 1660 goto out; 1661 if (pci_maptype(testval) & PCI_MAPMEM) { 1662 if (type != SYS_RES_MEMORY) { 1663 if (bootverbose) 1664 device_printf(dev, 1665 "child %s requested type %d for rid %#x," 1666 " but the BAR says it is an memio\n", 1667 device_get_nameunit(child), type, *rid); 1668 goto out; 1669 } 1670 } else { 1671 if (type != SYS_RES_IOPORT) { 1672 if (bootverbose) 1673 device_printf(dev, 1674 "child %s requested type %d for rid %#x," 1675 " but the BAR says it is an ioport\n", 1676 device_get_nameunit(child), type, *rid); 1677 goto out; 1678 } 1679 } 1680 /* 1681 * For real BARs, we need to override the size that 1682 * the driver requests, because that's what the BAR 1683 * actually uses and we would otherwise have a 1684 * situation where we might allocate the excess to 1685 * another driver, which won't work. 1686 */ 1687 mapsize = pci_mapsize(testval); 1688 count = 1 << mapsize; 1689 if (RF_ALIGNMENT(flags) < mapsize) 1690 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1691 1692 /* 1693 * Allocate enough resource, and then write back the 1694 * appropriate bar for that resource. 1695 */ 1696 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1697 start, end, count, flags); 1698 if (res == NULL) { 1699 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1700 count, *rid, type); 1701 goto out; 1702 } 1703 resource_list_add(rl, type, *rid, start, end, count); 1704 rle = resource_list_find(rl, type, *rid); 1705 if (rle == NULL) 1706 panic("pci_alloc_map: unexpectedly can't find resource."); 1707 rle->res = res; 1708 if (bootverbose) 1709 device_printf(child, 1710 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1711 count, *rid, type, rman_get_start(res)); 1712 map = rman_get_start(res); 1713out:; 1714 pci_write_config(child, *rid, map, 4); 1715 return (res); 1716} 1717 1718 1719struct resource * 1720pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1721 u_long start, u_long end, u_long count, u_int flags) 1722{ 1723 struct pci_devinfo *dinfo = device_get_ivars(child); 1724 struct resource_list *rl = &dinfo->resources; 1725 struct resource_list_entry *rle; 1726 pcicfgregs *cfg = &dinfo->cfg; 1727 1728 /* 1729 * Perform lazy resource allocation 1730 */ 1731 if (device_get_parent(child) == dev) { 1732 switch (type) { 1733 case SYS_RES_IRQ: 1734 /* 1735 * If the child device doesn't have an 1736 * interrupt routed and is deserving of an 1737 * interrupt, try to assign it one. 1738 */ 1739 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1740 (cfg->intpin != 0)) { 1741 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1742 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1743 pci_write_config(child, PCIR_INTLINE, 1744 cfg->intline, 1); 1745 resource_list_add(rl, SYS_RES_IRQ, 0, 1746 cfg->intline, cfg->intline, 1); 1747 } 1748 } 1749 break; 1750 case SYS_RES_IOPORT: 1751 case SYS_RES_MEMORY: 1752 if (*rid < PCIR_BAR(cfg->nummaps)) { 1753 /* 1754 * Enable the I/O mode. We should 1755 * also be assigning resources too 1756 * when none are present. The 1757 * resource_list_alloc kind of sorta does 1758 * this... 1759 */ 1760 if (PCI_ENABLE_IO(dev, child, type)) 1761 return (NULL); 1762 } 1763 rle = resource_list_find(rl, type, *rid); 1764 if (rle == NULL) 1765 return (pci_alloc_map(dev, child, type, rid, 1766 start, end, count, flags)); 1767 break; 1768 } 1769 /* 1770 * If we've already allocated the resource, then 1771 * return it now. But first we may need to activate 1772 * it, since we don't allocate the resource as active 1773 * above. Normally this would be done down in the 1774 * nexus, but since we short-circuit that path we have 1775 * to do its job here. Not sure if we should free the 1776 * resource if it fails to activate. 1777 */ 1778 rle = resource_list_find(rl, type, *rid); 1779 if (rle != NULL && rle->res != NULL) { 1780 if (bootverbose) 1781 device_printf(child, 1782 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1783 rman_get_size(rle->res), *rid, type, 1784 rman_get_start(rle->res)); 1785 if ((flags & RF_ACTIVE) && 1786 bus_generic_activate_resource(dev, child, type, 1787 *rid, rle->res) != 0) 1788 return NULL; 1789 return (rle->res); 1790 } 1791 } 1792 return (resource_list_alloc(rl, dev, child, type, rid, 1793 start, end, count, flags)); 1794} 1795 1796void 1797pci_delete_resource(device_t dev, device_t child, int type, int rid) 1798{ 1799 struct pci_devinfo *dinfo; 1800 struct resource_list *rl; 1801 struct resource_list_entry *rle; 1802 1803 if (device_get_parent(child) != dev) 1804 return; 1805 1806 dinfo = device_get_ivars(child); 1807 rl = &dinfo->resources; 1808 rle = resource_list_find(rl, type, rid); 1809 if (rle) { 1810 if (rle->res) { 1811 if (rman_get_device(rle->res) != dev || 1812 rman_get_flags(rle->res) & RF_ACTIVE) { 1813 device_printf(dev, "delete_resource: " 1814 "Resource still owned by child, oops. " 1815 "(type=%d, rid=%d, addr=%lx)\n", 1816 rle->type, rle->rid, 1817 rman_get_start(rle->res)); 1818 return; 1819 } 1820 bus_release_resource(dev, type, rid, rle->res); 1821 } 1822 resource_list_delete(rl, type, rid); 1823 } 1824 /* 1825 * Why do we turn off the PCI configuration BAR when we delete a 1826 * resource? -- imp 1827 */ 1828 pci_write_config(child, rid, 0, 4); 1829 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1830} 1831 1832struct resource_list * 1833pci_get_resource_list (device_t dev, device_t child) 1834{ 1835 struct pci_devinfo *dinfo = device_get_ivars(child); 1836 1837 return (&dinfo->resources); 1838} 1839 1840uint32_t 1841pci_read_config_method(device_t dev, device_t child, int reg, int width) 1842{ 1843 struct pci_devinfo *dinfo = device_get_ivars(child); 1844 pcicfgregs *cfg = &dinfo->cfg; 1845 1846 return (PCIB_READ_CONFIG(device_get_parent(dev), 1847 cfg->bus, cfg->slot, cfg->func, reg, width)); 1848} 1849 1850void 1851pci_write_config_method(device_t dev, device_t child, int reg, 1852 uint32_t val, int width) 1853{ 1854 struct pci_devinfo *dinfo = device_get_ivars(child); 1855 pcicfgregs *cfg = &dinfo->cfg; 1856 1857 PCIB_WRITE_CONFIG(device_get_parent(dev), 1858 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1859} 1860 1861int 1862pci_child_location_str_method(device_t dev, device_t child, char *buf, 1863 size_t buflen) 1864{ 1865 1866 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1867 pci_get_function(child)); 1868 return (0); 1869} 1870 1871int 1872pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1873 size_t buflen) 1874{ 1875 struct pci_devinfo *dinfo; 1876 pcicfgregs *cfg; 1877 1878 dinfo = device_get_ivars(child); 1879 cfg = &dinfo->cfg; 1880 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1881 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1882 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1883 cfg->progif); 1884 return (0); 1885} 1886 1887int 1888pci_assign_interrupt_method(device_t dev, device_t child) 1889{ 1890 struct pci_devinfo *dinfo = device_get_ivars(child); 1891 pcicfgregs *cfg = &dinfo->cfg; 1892 1893 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1894 cfg->intpin)); 1895} 1896 1897static int 1898pci_modevent(module_t mod, int what, void *arg) 1899{ 1900 static struct cdev *pci_cdev; 1901 1902 switch (what) { 1903 case MOD_LOAD: 1904 STAILQ_INIT(&pci_devq); 1905 pci_generation = 0; 1906 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1907 "pci"); 1908 pci_load_vendor_data(); 1909 break; 1910 1911 case MOD_UNLOAD: 1912 destroy_dev(pci_cdev); 1913 break; 1914 } 1915 1916 return (0); 1917} 1918 1919void 1920pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1921{ 1922 int i; 1923 1924 /* 1925 * Only do header type 0 devices. Type 1 devices are bridges, 1926 * which we know need special treatment. Type 2 devices are 1927 * cardbus bridges which also require special treatment. 1928 * Other types are unknown, and we err on the side of safety 1929 * by ignoring them. 1930 */ 1931 if (dinfo->cfg.hdrtype != 0) 1932 return; 1933 1934 /* 1935 * Restore the device to full power mode. We must do this 1936 * before we restore the registers because moving from D3 to 1937 * D0 will cause the chip's BARs and some other registers to 1938 * be reset to some unknown power on reset values. Cut down 1939 * the noise on boot by doing nothing if we are already in 1940 * state D0. 1941 */ 1942 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1943 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1944 } 1945 for (i = 0; i < dinfo->cfg.nummaps; i++) 1946 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1947 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1948 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1949 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1950 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1951 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1952 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1953 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1954 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1955 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1956 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1957} 1958 1959void 1960pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1961{ 1962 int i; 1963 uint32_t cls; 1964 int ps; 1965 1966 /* 1967 * Only do header type 0 devices. Type 1 devices are bridges, which 1968 * we know need special treatment. Type 2 devices are cardbus bridges 1969 * which also require special treatment. Other types are unknown, and 1970 * we err on the side of safety by ignoring them. Powering down 1971 * bridges should not be undertaken lightly. 1972 */ 1973 if (dinfo->cfg.hdrtype != 0) 1974 return; 1975 for (i = 0; i < dinfo->cfg.nummaps; i++) 1976 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1977 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1978 1979 /* 1980 * Some drivers apparently write to these registers w/o updating our 1981 * cached copy. No harm happens if we update the copy, so do so here 1982 * so we can restore them. The COMMAND register is modified by the 1983 * bus w/o updating the cache. This should represent the normally 1984 * writable portion of the 'defined' part of type 0 headers. In 1985 * theory we also need to save/restore the PCI capability structures 1986 * we know about, but apart from power we don't know any that are 1987 * writable. 1988 */ 1989 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1990 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1991 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1992 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1993 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1994 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1995 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1996 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1997 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1998 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1999 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2000 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2001 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2002 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2003 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2004 2005 /* 2006 * don't set the state for display devices, base peripherals and 2007 * memory devices since bad things happen when they are powered down. 2008 * We should (a) have drivers that can easily detach and (b) use 2009 * generic drivers for these devices so that some device actually 2010 * attaches. We need to make sure that when we implement (a) we don't 2011 * power the device down on a reattach. 2012 */ 2013 cls = pci_get_class(dev); 2014 if (!setstate) 2015 return; 2016 switch (pci_do_power_nodriver) 2017 { 2018 case 0: /* NO powerdown at all */ 2019 return; 2020 case 1: /* Conservative about what to power down */ 2021 if (cls == PCIC_STORAGE) 2022 return; 2023 /*FALLTHROUGH*/ 2024 case 2: /* Agressive about what to power down */ 2025 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2026 cls == PCIC_BASEPERIPH) 2027 return; 2028 /*FALLTHROUGH*/ 2029 case 3: /* Power down everything */ 2030 break; 2031 } 2032 /* 2033 * PCI spec says we can only go into D3 state from D0 state. 2034 * Transition from D[12] into D0 before going to D3 state. 2035 */ 2036 ps = pci_get_powerstate(dev); 2037 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2038 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2039 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2040 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2041} 2042