pci.c revision 149776
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 149776 2005-09-03 23:15:46Z imp $"); 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63#if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65#include <contrib/dev/acpica/acpi.h> 66#include "acpi_if.h" 67#else 68#define ACPI_PWR_FOR_SLEEP(x, y, z) 69#endif 70 71static uint32_t pci_mapbase(unsigned mapreg); 72static int pci_maptype(unsigned mapreg); 73static int pci_mapsize(unsigned testval); 74static int pci_maprange(unsigned mapreg); 75static void pci_fixancient(pcicfgregs *cfg); 76 77static int pci_porten(device_t pcib, int b, int s, int f); 78static int pci_memen(device_t pcib, int b, int s, int f); 79static int pci_add_map(device_t pcib, device_t bus, device_t dev, 80 int b, int s, int f, int reg, 81 struct resource_list *rl); 82static void pci_add_resources(device_t pcib, device_t bus, 83 device_t dev); 84static int pci_probe(device_t dev); 85static int pci_attach(device_t dev); 86static void pci_load_vendor_data(void); 87static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89static char *pci_describe_device(device_t dev); 90static int pci_modevent(module_t mod, int what, void *arg); 91static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 95static device_method_t pci_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pci_probe), 98 DEVMETHOD(device_attach, pci_attach), 99 DEVMETHOD(device_detach, bus_generic_detach), 100 DEVMETHOD(device_shutdown, bus_generic_shutdown), 101 DEVMETHOD(device_suspend, pci_suspend), 102 DEVMETHOD(device_resume, pci_resume), 103 104 /* Bus interface */ 105 DEVMETHOD(bus_print_child, pci_print_child), 106 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 107 DEVMETHOD(bus_read_ivar, pci_read_ivar), 108 DEVMETHOD(bus_write_ivar, pci_write_ivar), 109 DEVMETHOD(bus_driver_added, pci_driver_added), 110 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 111 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 112 113 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 114 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 115 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 116 DEVMETHOD(bus_delete_resource, pci_delete_resource), 117 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 118 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 119 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 120 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 121 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 122 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 123 124 /* PCI interface */ 125 DEVMETHOD(pci_read_config, pci_read_config_method), 126 DEVMETHOD(pci_write_config, pci_write_config_method), 127 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 128 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 129 DEVMETHOD(pci_enable_io, pci_enable_io_method), 130 DEVMETHOD(pci_disable_io, pci_disable_io_method), 131 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 132 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 133 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 134 135 { 0, 0 } 136}; 137 138DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 139 140devclass_t pci_devclass; 141DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 142MODULE_VERSION(pci, 1); 143 144static char *pci_vendordata; 145static size_t pci_vendordata_size; 146 147 148struct pci_quirk { 149 uint32_t devid; /* Vendor/device of the card */ 150 int type; 151#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 152 int arg1; 153 int arg2; 154}; 155 156struct pci_quirk pci_quirks[] = { 157 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 158 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 159 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 160 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 161 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 163 { 0 } 164}; 165 166/* map register information */ 167#define PCI_MAPMEM 0x01 /* memory map */ 168#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 169#define PCI_MAPPORT 0x04 /* port map */ 170 171struct devlist pci_devq; 172uint32_t pci_generation; 173uint32_t pci_numdevs = 0; 174 175/* sysctl vars */ 176SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 177 178static int pci_enable_io_modes = 1; 179TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 180SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 181 &pci_enable_io_modes, 1, 182 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 183enable these bits correctly. We'd like to do this all the time, but there\n\ 184are some peripherals that this causes problems with."); 185 186static int pci_do_powerstate = 1; 187TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 188SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 189 &pci_do_powerstate, 1, 190 "Power down devices into D3 state when no driver attaches to them.\n\ 191Otherwise, leave the device in D0 state when no driver attaches."); 192 193/* Find a device_t by bus/slot/function */ 194 195device_t 196pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 197{ 198 struct pci_devinfo *dinfo; 199 200 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 201 if ((dinfo->cfg.bus == bus) && 202 (dinfo->cfg.slot == slot) && 203 (dinfo->cfg.func == func)) { 204 return (dinfo->cfg.dev); 205 } 206 } 207 208 return (NULL); 209} 210 211/* Find a device_t by vendor/device ID */ 212 213device_t 214pci_find_device(uint16_t vendor, uint16_t device) 215{ 216 struct pci_devinfo *dinfo; 217 218 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 219 if ((dinfo->cfg.vendor == vendor) && 220 (dinfo->cfg.device == device)) { 221 return (dinfo->cfg.dev); 222 } 223 } 224 225 return (NULL); 226} 227 228/* return base address of memory or port map */ 229 230static uint32_t 231pci_mapbase(unsigned mapreg) 232{ 233 int mask = 0x03; 234 if ((mapreg & 0x01) == 0) 235 mask = 0x0f; 236 return (mapreg & ~mask); 237} 238 239/* return map type of memory or port map */ 240 241static int 242pci_maptype(unsigned mapreg) 243{ 244 static uint8_t maptype[0x10] = { 245 PCI_MAPMEM, PCI_MAPPORT, 246 PCI_MAPMEM, 0, 247 PCI_MAPMEM, PCI_MAPPORT, 248 0, 0, 249 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 250 PCI_MAPMEM|PCI_MAPMEMP, 0, 251 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 252 0, 0, 253 }; 254 255 return maptype[mapreg & 0x0f]; 256} 257 258/* return log2 of map size decoded for memory or port map */ 259 260static int 261pci_mapsize(unsigned testval) 262{ 263 int ln2size; 264 265 testval = pci_mapbase(testval); 266 ln2size = 0; 267 if (testval != 0) { 268 while ((testval & 1) == 0) 269 { 270 ln2size++; 271 testval >>= 1; 272 } 273 } 274 return (ln2size); 275} 276 277/* return log2 of address range supported by map register */ 278 279static int 280pci_maprange(unsigned mapreg) 281{ 282 int ln2range = 0; 283 switch (mapreg & 0x07) { 284 case 0x00: 285 case 0x01: 286 case 0x05: 287 ln2range = 32; 288 break; 289 case 0x02: 290 ln2range = 20; 291 break; 292 case 0x04: 293 ln2range = 64; 294 break; 295 } 296 return (ln2range); 297} 298 299/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 300 301static void 302pci_fixancient(pcicfgregs *cfg) 303{ 304 if (cfg->hdrtype != 0) 305 return; 306 307 /* PCI to PCI bridges use header type 1 */ 308 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 309 cfg->hdrtype = 1; 310} 311 312/* extract header type specific config data */ 313 314static void 315pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 316{ 317#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 318 switch (cfg->hdrtype) { 319 case 0: 320 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 321 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 322 cfg->nummaps = PCI_MAXMAPS_0; 323 break; 324 case 1: 325 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 326 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 327 cfg->nummaps = PCI_MAXMAPS_1; 328 break; 329 case 2: 330 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 331 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 332 cfg->nummaps = PCI_MAXMAPS_2; 333 break; 334 } 335#undef REG 336} 337 338/* read configuration header into pcicfgregs structure */ 339 340struct pci_devinfo * 341pci_read_device(device_t pcib, int b, int s, int f, size_t size) 342{ 343#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 344 pcicfgregs *cfg = NULL; 345 struct pci_devinfo *devlist_entry; 346 struct devlist *devlist_head; 347 348 devlist_head = &pci_devq; 349 350 devlist_entry = NULL; 351 352 if (REG(PCIR_DEVVENDOR, 4) != -1) { 353 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 354 if (devlist_entry == NULL) 355 return (NULL); 356 357 cfg = &devlist_entry->cfg; 358 359 cfg->bus = b; 360 cfg->slot = s; 361 cfg->func = f; 362 cfg->vendor = REG(PCIR_VENDOR, 2); 363 cfg->device = REG(PCIR_DEVICE, 2); 364 cfg->cmdreg = REG(PCIR_COMMAND, 2); 365 cfg->statreg = REG(PCIR_STATUS, 2); 366 cfg->baseclass = REG(PCIR_CLASS, 1); 367 cfg->subclass = REG(PCIR_SUBCLASS, 1); 368 cfg->progif = REG(PCIR_PROGIF, 1); 369 cfg->revid = REG(PCIR_REVID, 1); 370 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 371 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 372 cfg->lattimer = REG(PCIR_LATTIMER, 1); 373 cfg->intpin = REG(PCIR_INTPIN, 1); 374 cfg->intline = REG(PCIR_INTLINE, 1); 375 376 cfg->mingnt = REG(PCIR_MINGNT, 1); 377 cfg->maxlat = REG(PCIR_MAXLAT, 1); 378 379 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 380 cfg->hdrtype &= ~PCIM_MFDEV; 381 382 pci_fixancient(cfg); 383 pci_hdrtypedata(pcib, b, s, f, cfg); 384 385 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 386 pci_read_extcap(pcib, cfg); 387 388 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 389 390 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 391 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 392 devlist_entry->conf.pc_sel.pc_func = cfg->func; 393 devlist_entry->conf.pc_hdr = cfg->hdrtype; 394 395 devlist_entry->conf.pc_subvendor = cfg->subvendor; 396 devlist_entry->conf.pc_subdevice = cfg->subdevice; 397 devlist_entry->conf.pc_vendor = cfg->vendor; 398 devlist_entry->conf.pc_device = cfg->device; 399 400 devlist_entry->conf.pc_class = cfg->baseclass; 401 devlist_entry->conf.pc_subclass = cfg->subclass; 402 devlist_entry->conf.pc_progif = cfg->progif; 403 devlist_entry->conf.pc_revid = cfg->revid; 404 405 pci_numdevs++; 406 pci_generation++; 407 } 408 return (devlist_entry); 409#undef REG 410} 411 412static void 413pci_read_extcap(device_t pcib, pcicfgregs *cfg) 414{ 415#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 416 int ptr, nextptr, ptrptr; 417 418 switch (cfg->hdrtype & PCIM_HDRTYPE) { 419 case 0: 420 ptrptr = PCIR_CAP_PTR; 421 break; 422 case 2: 423 ptrptr = 0x14; 424 break; 425 default: 426 return; /* no extended capabilities support */ 427 } 428 nextptr = REG(ptrptr, 1); /* sanity check? */ 429 430 /* 431 * Read capability entries. 432 */ 433 while (nextptr != 0) { 434 /* Sanity check */ 435 if (nextptr > 255) { 436 printf("illegal PCI extended capability offset %d\n", 437 nextptr); 438 return; 439 } 440 /* Find the next entry */ 441 ptr = nextptr; 442 nextptr = REG(ptr + 1, 1); 443 444 /* Process this entry */ 445 switch (REG(ptr, 1)) { 446 case PCIY_PMG: /* PCI power management */ 447 if (cfg->pp.pp_cap == 0) { 448 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 449 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 450 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 451 if ((nextptr - ptr) > PCIR_POWER_DATA) 452 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 453 } 454 break; 455 case PCIY_MSI: /* PCI MSI */ 456 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 457 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 458 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 459 else 460 cfg->msi.msi_data = PCIR_MSI_DATA; 461 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 462 PCIM_MSICTRL_MMC_MASK)>>1); 463 default: 464 break; 465 } 466 } 467#undef REG 468} 469 470/* free pcicfgregs structure and all depending data structures */ 471 472int 473pci_freecfg(struct pci_devinfo *dinfo) 474{ 475 struct devlist *devlist_head; 476 477 devlist_head = &pci_devq; 478 479 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 480 free(dinfo, M_DEVBUF); 481 482 /* increment the generation count */ 483 pci_generation++; 484 485 /* we're losing one device */ 486 pci_numdevs--; 487 return (0); 488} 489 490/* 491 * PCI power manangement 492 */ 493int 494pci_set_powerstate_method(device_t dev, device_t child, int state) 495{ 496 struct pci_devinfo *dinfo = device_get_ivars(child); 497 pcicfgregs *cfg = &dinfo->cfg; 498 uint16_t status; 499 int result, oldstate, highest, delay; 500 501 if (cfg->pp.pp_cap == 0) 502 return (EOPNOTSUPP); 503 504 /* 505 * Optimize a no state change request away. While it would be OK to 506 * write to the hardware in theory, some devices have shown odd 507 * behavior when going from D3 -> D3. 508 */ 509 oldstate = pci_get_powerstate(child); 510 if (oldstate == state) 511 return (0); 512 513 /* 514 * The PCI power management specification states that after a state 515 * transition between PCI power states, system software must 516 * guarantee a minimal delay before the function accesses the device. 517 * Compute the worst case delay that we need to guarantee before we 518 * access the device. Many devices will be responsive much more 519 * quickly than this delay, but there are some that don't respond 520 * instantly to state changes. Transitions to/from D3 state require 521 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 522 * is done below with DELAY rather than a sleeper function because 523 * this function can be called from contexts where we cannot sleep. 524 */ 525 highest = (oldstate > state) ? oldstate : state; 526 if (highest == PCI_POWERSTATE_D3) 527 delay = 10000; 528 else if (highest == PCI_POWERSTATE_D2) 529 delay = 200; 530 else 531 delay = 0; 532 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 533 & ~PCIM_PSTAT_DMASK; 534 result = 0; 535 switch (state) { 536 case PCI_POWERSTATE_D0: 537 status |= PCIM_PSTAT_D0; 538 break; 539 case PCI_POWERSTATE_D1: 540 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 541 return (EOPNOTSUPP); 542 status |= PCIM_PSTAT_D1; 543 break; 544 case PCI_POWERSTATE_D2: 545 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 546 return (EOPNOTSUPP); 547 status |= PCIM_PSTAT_D2; 548 break; 549 case PCI_POWERSTATE_D3: 550 status |= PCIM_PSTAT_D3; 551 break; 552 default: 553 return (EINVAL); 554 } 555 556 if (bootverbose) 557 printf( 558 "pci%d:%d:%d: Transition from D%d to D%d\n", 559 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 560 oldstate, state); 561 562 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 563 if (delay) 564 DELAY(delay); 565 return (0); 566} 567 568int 569pci_get_powerstate_method(device_t dev, device_t child) 570{ 571 struct pci_devinfo *dinfo = device_get_ivars(child); 572 pcicfgregs *cfg = &dinfo->cfg; 573 uint16_t status; 574 int result; 575 576 if (cfg->pp.pp_cap != 0) { 577 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 578 switch (status & PCIM_PSTAT_DMASK) { 579 case PCIM_PSTAT_D0: 580 result = PCI_POWERSTATE_D0; 581 break; 582 case PCIM_PSTAT_D1: 583 result = PCI_POWERSTATE_D1; 584 break; 585 case PCIM_PSTAT_D2: 586 result = PCI_POWERSTATE_D2; 587 break; 588 case PCIM_PSTAT_D3: 589 result = PCI_POWERSTATE_D3; 590 break; 591 default: 592 result = PCI_POWERSTATE_UNKNOWN; 593 break; 594 } 595 } else { 596 /* No support, device is always at D0 */ 597 result = PCI_POWERSTATE_D0; 598 } 599 return (result); 600} 601 602/* 603 * Some convenience functions for PCI device drivers. 604 */ 605 606static __inline void 607pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 608{ 609 uint16_t command; 610 611 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 612 command |= bit; 613 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 614} 615 616static __inline void 617pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 618{ 619 uint16_t command; 620 621 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 622 command &= ~bit; 623 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 624} 625 626int 627pci_enable_busmaster_method(device_t dev, device_t child) 628{ 629 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 630 return (0); 631} 632 633int 634pci_disable_busmaster_method(device_t dev, device_t child) 635{ 636 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 637 return (0); 638} 639 640int 641pci_enable_io_method(device_t dev, device_t child, int space) 642{ 643 uint16_t command; 644 uint16_t bit; 645 char *error; 646 647 bit = 0; 648 error = NULL; 649 650 switch(space) { 651 case SYS_RES_IOPORT: 652 bit = PCIM_CMD_PORTEN; 653 error = "port"; 654 break; 655 case SYS_RES_MEMORY: 656 bit = PCIM_CMD_MEMEN; 657 error = "memory"; 658 break; 659 default: 660 return (EINVAL); 661 } 662 pci_set_command_bit(dev, child, bit); 663 /* Some devices seem to need a brief stall here, what do to? */ 664 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 665 if (command & bit) 666 return (0); 667 device_printf(child, "failed to enable %s mapping!\n", error); 668 return (ENXIO); 669} 670 671int 672pci_disable_io_method(device_t dev, device_t child, int space) 673{ 674 uint16_t command; 675 uint16_t bit; 676 char *error; 677 678 bit = 0; 679 error = NULL; 680 681 switch(space) { 682 case SYS_RES_IOPORT: 683 bit = PCIM_CMD_PORTEN; 684 error = "port"; 685 break; 686 case SYS_RES_MEMORY: 687 bit = PCIM_CMD_MEMEN; 688 error = "memory"; 689 break; 690 default: 691 return (EINVAL); 692 } 693 pci_clear_command_bit(dev, child, bit); 694 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 695 if (command & bit) { 696 device_printf(child, "failed to disable %s mapping!\n", error); 697 return (ENXIO); 698 } 699 return (0); 700} 701 702/* 703 * New style pci driver. Parent device is either a pci-host-bridge or a 704 * pci-pci-bridge. Both kinds are represented by instances of pcib. 705 */ 706 707void 708pci_print_verbose(struct pci_devinfo *dinfo) 709{ 710 if (bootverbose) { 711 pcicfgregs *cfg = &dinfo->cfg; 712 713 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 714 cfg->vendor, cfg->device, cfg->revid); 715 printf("\tbus=%d, slot=%d, func=%d\n", 716 cfg->bus, cfg->slot, cfg->func); 717 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 718 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 719 cfg->mfdev); 720 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 721 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 722 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 723 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 724 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 725 if (cfg->intpin > 0) 726 printf("\tintpin=%c, irq=%d\n", 727 cfg->intpin +'a' -1, cfg->intline); 728 if (cfg->pp.pp_cap) { 729 uint16_t status; 730 731 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 732 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 733 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 734 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 735 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 736 status & PCIM_PSTAT_DMASK); 737 } 738 if (cfg->msi.msi_data) { 739 int ctrl; 740 741 ctrl = cfg->msi.msi_ctrl; 742 printf("\tMSI supports %d message%s%s%s\n", 743 cfg->msi.msi_msgnum, 744 (cfg->msi.msi_msgnum == 1) ? "" : "s", 745 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 746 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 747 } 748 } 749} 750 751static int 752pci_porten(device_t pcib, int b, int s, int f) 753{ 754 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 755 & PCIM_CMD_PORTEN) != 0; 756} 757 758static int 759pci_memen(device_t pcib, int b, int s, int f) 760{ 761 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 762 & PCIM_CMD_MEMEN) != 0; 763} 764 765/* 766 * Add a resource based on a pci map register. Return 1 if the map 767 * register is a 32bit map register or 2 if it is a 64bit register. 768 */ 769static int 770pci_add_map(device_t pcib, device_t bus, device_t dev, 771 int b, int s, int f, int reg, struct resource_list *rl) 772{ 773 uint32_t map; 774 uint64_t base; 775 uint64_t start, end, count; 776 uint8_t ln2size; 777 uint8_t ln2range; 778 uint32_t testval; 779 uint16_t cmd; 780 int type; 781 int barlen; 782 783 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 784 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 785 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 786 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 787 788 if (pci_maptype(map) & PCI_MAPMEM) 789 type = SYS_RES_MEMORY; 790 else 791 type = SYS_RES_IOPORT; 792 ln2size = pci_mapsize(testval); 793 ln2range = pci_maprange(testval); 794 base = pci_mapbase(map); 795 barlen = ln2range == 64 ? 2 : 1; 796 797 /* 798 * For I/O registers, if bottom bit is set, and the next bit up 799 * isn't clear, we know we have a BAR that doesn't conform to the 800 * spec, so ignore it. Also, sanity check the size of the data 801 * areas to the type of memory involved. Memory must be at least 802 * 32 bytes in size, while I/O ranges must be at least 4. 803 */ 804 if ((testval & 0x1) == 0x1 && 805 (testval & 0x2) != 0) 806 return (barlen); 807 if ((type == SYS_RES_MEMORY && ln2size < 5) || 808 (type == SYS_RES_IOPORT && ln2size < 2)) 809 return (barlen); 810 811 if (ln2range == 64) 812 /* Read the other half of a 64bit map register */ 813 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 814 815 if (bootverbose) { 816 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 817 reg, pci_maptype(map), ln2range, 818 (unsigned int) base, ln2size); 819 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 820 printf(", port disabled\n"); 821 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 822 printf(", memory disabled\n"); 823 else 824 printf(", enabled\n"); 825 } 826 827 /* 828 * If base is 0, then we have problems. It is best to ignore 829 * such entries for the moment. These will be allocated later if 830 * the driver specifically requests them. 831 * 832 * Similarly treat maps whose values is the same as the test value 833 * read back. These maps have had all f's written to them by the 834 * BIOS in an attempt to disable the resources. 835 */ 836 if (base == 0 || map == testval) 837 return (barlen); 838 839 /* 840 * This code theoretically does the right thing, but has 841 * undesirable side effects in some cases where peripherals 842 * respond oddly to having these bits enabled. Let the user 843 * be able to turn them off (since pci_enable_io_modes is 1 by 844 * default). 845 */ 846 if (pci_enable_io_modes) { 847 /* Turn on resources that have been left off by a lazy BIOS */ 848 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 849 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 850 cmd |= PCIM_CMD_PORTEN; 851 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 852 } 853 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 854 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 855 cmd |= PCIM_CMD_MEMEN; 856 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 857 } 858 } else { 859 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 860 return (barlen); 861 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 862 return (barlen); 863 } 864 865 start = base; 866 end = base + (1 << ln2size) - 1; 867 count = 1 << ln2size; 868 resource_list_add(rl, type, reg, start, end, count); 869 870 /* 871 * Not quite sure what to do on failure of allocating the resource 872 * since I can postulate several right answers. 873 */ 874 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 875 return (barlen); 876} 877 878/* 879 * For ATA devices we need to decide early what addressing mode to use. 880 * Legacy demands that the primary and secondary ATA ports sits on the 881 * same addresses that old ISA hardware did. This dictates that we use 882 * those addresses and ignore the BAR's if we cannot set PCI native 883 * addressing mode. 884 */ 885static void 886pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 887 int s, int f, struct resource_list *rl) 888{ 889 int rid, type, progif; 890#if 0 891 /* if this device supports PCI native addressing use it */ 892 progif = pci_read_config(dev, PCIR_PROGIF, 1); 893 if ((progif & 0x8a) == 0x8a) { 894 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 895 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 896 printf("Trying ATA native PCI addressing mode\n"); 897 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 898 } 899 } 900#endif 901 progif = pci_read_config(dev, PCIR_PROGIF, 1); 902 type = SYS_RES_IOPORT; 903 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 904 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 905 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 906 } 907 else { 908 rid = PCIR_BAR(0); 909 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 910 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 911 rid = PCIR_BAR(1); 912 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 913 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 914 } 915 if (progif & PCIP_STORAGE_IDE_MODESEC) { 916 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 917 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 918 } 919 else { 920 rid = PCIR_BAR(2); 921 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 922 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 923 rid = PCIR_BAR(3); 924 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 925 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 926 } 927 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 928 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl); 929} 930 931static void 932pci_add_resources(device_t pcib, device_t bus, device_t dev) 933{ 934 struct pci_devinfo *dinfo = device_get_ivars(dev); 935 pcicfgregs *cfg = &dinfo->cfg; 936 struct resource_list *rl = &dinfo->resources; 937 struct pci_quirk *q; 938 int b, i, irq, f, s; 939 940 b = cfg->bus; 941 s = cfg->slot; 942 f = cfg->func; 943 944 /* ATA devices needs special map treatment */ 945 if ((pci_get_class(dev) == PCIC_STORAGE) && 946 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 947 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 948 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 949 else 950 for (i = 0; i < cfg->nummaps;) 951 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 952 rl); 953 954 for (q = &pci_quirks[0]; q->devid; q++) { 955 if (q->devid == ((cfg->device << 16) | cfg->vendor) 956 && q->type == PCI_QUIRK_MAP_REG) 957 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 958 } 959 960 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 961#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 962 defined(__arm__) || defined(__alpha__) 963 /* 964 * Try to re-route interrupts. Sometimes the BIOS or 965 * firmware may leave bogus values in these registers. 966 * If the re-route fails, then just stick with what we 967 * have. 968 */ 969 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 970 if (PCI_INTERRUPT_VALID(irq)) { 971 pci_write_config(dev, PCIR_INTLINE, irq, 1); 972 cfg->intline = irq; 973 } else 974#endif 975 irq = cfg->intline; 976 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 977 } 978} 979 980void 981pci_add_children(device_t dev, int busno, size_t dinfo_size) 982{ 983#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 984 device_t pcib = device_get_parent(dev); 985 struct pci_devinfo *dinfo; 986 int maxslots; 987 int s, f, pcifunchigh; 988 uint8_t hdrtype; 989 990 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 991 ("dinfo_size too small")); 992 maxslots = PCIB_MAXSLOTS(pcib); 993 for (s = 0; s <= maxslots; s++) { 994 pcifunchigh = 0; 995 f = 0; 996 hdrtype = REG(PCIR_HDRTYPE, 1); 997 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 998 continue; 999 if (hdrtype & PCIM_MFDEV) 1000 pcifunchigh = PCI_FUNCMAX; 1001 for (f = 0; f <= pcifunchigh; f++) { 1002 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1003 if (dinfo != NULL) { 1004 pci_add_child(dev, dinfo); 1005 } 1006 } 1007 } 1008#undef REG 1009} 1010 1011void 1012pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1013{ 1014 device_t pcib; 1015 1016 pcib = device_get_parent(bus); 1017 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1018 device_set_ivars(dinfo->cfg.dev, dinfo); 1019 resource_list_init(&dinfo->resources); 1020 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1021 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1022 pci_print_verbose(dinfo); 1023 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1024} 1025 1026static int 1027pci_probe(device_t dev) 1028{ 1029 1030 device_set_desc(dev, "PCI bus"); 1031 1032 /* Allow other subclasses to override this driver. */ 1033 return (-1000); 1034} 1035 1036static int 1037pci_attach(device_t dev) 1038{ 1039 int busno; 1040 1041 /* 1042 * Since there can be multiple independantly numbered PCI 1043 * busses on some large alpha systems, we can't use the unit 1044 * number to decide what bus we are probing. We ask the parent 1045 * pcib what our bus number is. 1046 */ 1047 busno = pcib_get_bus(dev); 1048 if (bootverbose) 1049 device_printf(dev, "physical bus=%d\n", busno); 1050 1051 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1052 1053 return (bus_generic_attach(dev)); 1054} 1055 1056int 1057pci_suspend(device_t dev) 1058{ 1059 int dstate, error, i, numdevs; 1060 device_t acpi_dev, child, *devlist; 1061 struct pci_devinfo *dinfo; 1062 1063 /* 1064 * Save the PCI configuration space for each child and set the 1065 * device in the appropriate power state for this sleep state. 1066 */ 1067 acpi_dev = NULL; 1068 if (pci_do_powerstate) 1069 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1070 device_get_children(dev, &devlist, &numdevs); 1071 for (i = 0; i < numdevs; i++) { 1072 child = devlist[i]; 1073 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1074 pci_cfg_save(child, dinfo, 0); 1075 } 1076 1077 /* Suspend devices before potentially powering them down. */ 1078 error = bus_generic_suspend(dev); 1079 if (error) { 1080 free(devlist, M_TEMP); 1081 return (error); 1082 } 1083 1084 /* 1085 * Always set the device to D3. If ACPI suggests a different 1086 * power state, use it instead. If ACPI is not present, the 1087 * firmware is responsible for managing device power. Skip 1088 * children who aren't attached since they are powered down 1089 * separately. Only manage type 0 devices for now. 1090 */ 1091 for (i = 0; acpi_dev && i < numdevs; i++) { 1092 child = devlist[i]; 1093 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1094 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1095 dstate = PCI_POWERSTATE_D3; 1096 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1097 pci_set_powerstate(child, dstate); 1098 } 1099 } 1100 free(devlist, M_TEMP); 1101 return (0); 1102} 1103 1104int 1105pci_resume(device_t dev) 1106{ 1107 int i, numdevs; 1108 device_t acpi_dev, child, *devlist; 1109 struct pci_devinfo *dinfo; 1110 1111 /* 1112 * Set each child to D0 and restore its PCI configuration space. 1113 */ 1114 acpi_dev = NULL; 1115 if (pci_do_powerstate) 1116 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1117 device_get_children(dev, &devlist, &numdevs); 1118 for (i = 0; i < numdevs; i++) { 1119 /* 1120 * Notify ACPI we're going to D0 but ignore the result. If 1121 * ACPI is not present, the firmware is responsible for 1122 * managing device power. Only manage type 0 devices for now. 1123 */ 1124 child = devlist[i]; 1125 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1126 if (acpi_dev && device_is_attached(child) && 1127 dinfo->cfg.hdrtype == 0) { 1128 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1129 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1130 } 1131 1132 /* Now the device is powered up, restore its config space. */ 1133 pci_cfg_restore(child, dinfo); 1134 } 1135 free(devlist, M_TEMP); 1136 return (bus_generic_resume(dev)); 1137} 1138 1139static void 1140pci_load_vendor_data(void) 1141{ 1142 caddr_t vendordata, info; 1143 1144 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1145 info = preload_search_info(vendordata, MODINFO_ADDR); 1146 pci_vendordata = *(char **)info; 1147 info = preload_search_info(vendordata, MODINFO_SIZE); 1148 pci_vendordata_size = *(size_t *)info; 1149 /* terminate the database */ 1150 pci_vendordata[pci_vendordata_size] = '\n'; 1151 } 1152} 1153 1154void 1155pci_driver_added(device_t dev, driver_t *driver) 1156{ 1157 int numdevs; 1158 device_t *devlist; 1159 device_t child; 1160 struct pci_devinfo *dinfo; 1161 int i; 1162 1163 if (bootverbose) 1164 device_printf(dev, "driver added\n"); 1165 DEVICE_IDENTIFY(driver, dev); 1166 device_get_children(dev, &devlist, &numdevs); 1167 for (i = 0; i < numdevs; i++) { 1168 child = devlist[i]; 1169 if (device_get_state(child) != DS_NOTPRESENT) 1170 continue; 1171 dinfo = device_get_ivars(child); 1172 pci_print_verbose(dinfo); 1173 if (bootverbose) 1174 printf("pci%d:%d:%d: reprobing on driver added\n", 1175 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1176 pci_cfg_restore(child, dinfo); 1177 if (device_probe_and_attach(child) != 0) 1178 pci_cfg_save(child, dinfo, 1); 1179 } 1180 free(devlist, M_TEMP); 1181} 1182 1183int 1184pci_print_child(device_t dev, device_t child) 1185{ 1186 struct pci_devinfo *dinfo; 1187 struct resource_list *rl; 1188 int retval = 0; 1189 1190 dinfo = device_get_ivars(child); 1191 rl = &dinfo->resources; 1192 1193 retval += bus_print_child_header(dev, child); 1194 1195 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1196 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1197 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1198 if (device_get_flags(dev)) 1199 retval += printf(" flags %#x", device_get_flags(dev)); 1200 1201 retval += printf(" at device %d.%d", pci_get_slot(child), 1202 pci_get_function(child)); 1203 1204 retval += bus_print_child_footer(dev, child); 1205 1206 return (retval); 1207} 1208 1209static struct 1210{ 1211 int class; 1212 int subclass; 1213 char *desc; 1214} pci_nomatch_tab[] = { 1215 {PCIC_OLD, -1, "old"}, 1216 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1217 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1218 {PCIC_STORAGE, -1, "mass storage"}, 1219 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1220 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1221 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1222 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1223 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1224 {PCIC_NETWORK, -1, "network"}, 1225 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1226 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1227 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1228 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1229 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1230 {PCIC_DISPLAY, -1, "display"}, 1231 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1232 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1233 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1234 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1235 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1236 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1237 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1238 {PCIC_MEMORY, -1, "memory"}, 1239 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1240 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1241 {PCIC_BRIDGE, -1, "bridge"}, 1242 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1243 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1244 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1245 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1246 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1247 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1248 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1249 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1250 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1251 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1252 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1253 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1254 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1255 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1256 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1257 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1258 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1259 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1260 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1261 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1262 {PCIC_INPUTDEV, -1, "input device"}, 1263 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1264 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1265 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1266 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1267 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1268 {PCIC_DOCKING, -1, "docking station"}, 1269 {PCIC_PROCESSOR, -1, "processor"}, 1270 {PCIC_SERIALBUS, -1, "serial bus"}, 1271 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1272 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1273 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1274 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1275 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1276 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1277 {PCIC_WIRELESS, -1, "wireless controller"}, 1278 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1279 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1280 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1281 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1282 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1283 {PCIC_SATCOM, -1, "satellite communication"}, 1284 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1285 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1286 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1287 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1288 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1289 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1290 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1291 {PCIC_DASP, -1, "dasp"}, 1292 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1293 {0, 0, NULL} 1294}; 1295 1296void 1297pci_probe_nomatch(device_t dev, device_t child) 1298{ 1299 int i; 1300 char *cp, *scp, *device; 1301 1302 /* 1303 * Look for a listing for this device in a loaded device database. 1304 */ 1305 if ((device = pci_describe_device(child)) != NULL) { 1306 device_printf(dev, "<%s>", device); 1307 free(device, M_DEVBUF); 1308 } else { 1309 /* 1310 * Scan the class/subclass descriptions for a general 1311 * description. 1312 */ 1313 cp = "unknown"; 1314 scp = NULL; 1315 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1316 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1317 if (pci_nomatch_tab[i].subclass == -1) { 1318 cp = pci_nomatch_tab[i].desc; 1319 } else if (pci_nomatch_tab[i].subclass == 1320 pci_get_subclass(child)) { 1321 scp = pci_nomatch_tab[i].desc; 1322 } 1323 } 1324 } 1325 device_printf(dev, "<%s%s%s>", 1326 cp ? cp : "", 1327 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1328 scp ? scp : ""); 1329 } 1330 printf(" at device %d.%d (no driver attached)\n", 1331 pci_get_slot(child), pci_get_function(child)); 1332 if (pci_do_powerstate) 1333 pci_cfg_save(child, 1334 (struct pci_devinfo *) device_get_ivars(child), 1); 1335 return; 1336} 1337 1338/* 1339 * Parse the PCI device database, if loaded, and return a pointer to a 1340 * description of the device. 1341 * 1342 * The database is flat text formatted as follows: 1343 * 1344 * Any line not in a valid format is ignored. 1345 * Lines are terminated with newline '\n' characters. 1346 * 1347 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1348 * the vendor name. 1349 * 1350 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1351 * - devices cannot be listed without a corresponding VENDOR line. 1352 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1353 * another TAB, then the device name. 1354 */ 1355 1356/* 1357 * Assuming (ptr) points to the beginning of a line in the database, 1358 * return the vendor or device and description of the next entry. 1359 * The value of (vendor) or (device) inappropriate for the entry type 1360 * is set to -1. Returns nonzero at the end of the database. 1361 * 1362 * Note that this is slightly unrobust in the face of corrupt data; 1363 * we attempt to safeguard against this by spamming the end of the 1364 * database with a newline when we initialise. 1365 */ 1366static int 1367pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1368{ 1369 char *cp = *ptr; 1370 int left; 1371 1372 *device = -1; 1373 *vendor = -1; 1374 **desc = '\0'; 1375 for (;;) { 1376 left = pci_vendordata_size - (cp - pci_vendordata); 1377 if (left <= 0) { 1378 *ptr = cp; 1379 return(1); 1380 } 1381 1382 /* vendor entry? */ 1383 if (*cp != '\t' && 1384 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1385 break; 1386 /* device entry? */ 1387 if (*cp == '\t' && 1388 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1389 break; 1390 1391 /* skip to next line */ 1392 while (*cp != '\n' && left > 0) { 1393 cp++; 1394 left--; 1395 } 1396 if (*cp == '\n') { 1397 cp++; 1398 left--; 1399 } 1400 } 1401 /* skip to next line */ 1402 while (*cp != '\n' && left > 0) { 1403 cp++; 1404 left--; 1405 } 1406 if (*cp == '\n' && left > 0) 1407 cp++; 1408 *ptr = cp; 1409 return(0); 1410} 1411 1412static char * 1413pci_describe_device(device_t dev) 1414{ 1415 int vendor, device; 1416 char *desc, *vp, *dp, *line; 1417 1418 desc = vp = dp = NULL; 1419 1420 /* 1421 * If we have no vendor data, we can't do anything. 1422 */ 1423 if (pci_vendordata == NULL) 1424 goto out; 1425 1426 /* 1427 * Scan the vendor data looking for this device 1428 */ 1429 line = pci_vendordata; 1430 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1431 goto out; 1432 for (;;) { 1433 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1434 goto out; 1435 if (vendor == pci_get_vendor(dev)) 1436 break; 1437 } 1438 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1439 goto out; 1440 for (;;) { 1441 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1442 *dp = 0; 1443 break; 1444 } 1445 if (vendor != -1) { 1446 *dp = 0; 1447 break; 1448 } 1449 if (device == pci_get_device(dev)) 1450 break; 1451 } 1452 if (dp[0] == '\0') 1453 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1454 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1455 NULL) 1456 sprintf(desc, "%s, %s", vp, dp); 1457 out: 1458 if (vp != NULL) 1459 free(vp, M_DEVBUF); 1460 if (dp != NULL) 1461 free(dp, M_DEVBUF); 1462 return(desc); 1463} 1464 1465int 1466pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1467{ 1468 struct pci_devinfo *dinfo; 1469 pcicfgregs *cfg; 1470 1471 dinfo = device_get_ivars(child); 1472 cfg = &dinfo->cfg; 1473 1474 switch (which) { 1475 case PCI_IVAR_ETHADDR: 1476 /* 1477 * The generic accessor doesn't deal with failure, so 1478 * we set the return value, then return an error. 1479 */ 1480 *((uint8_t **) result) = NULL; 1481 return (EINVAL); 1482 case PCI_IVAR_SUBVENDOR: 1483 *result = cfg->subvendor; 1484 break; 1485 case PCI_IVAR_SUBDEVICE: 1486 *result = cfg->subdevice; 1487 break; 1488 case PCI_IVAR_VENDOR: 1489 *result = cfg->vendor; 1490 break; 1491 case PCI_IVAR_DEVICE: 1492 *result = cfg->device; 1493 break; 1494 case PCI_IVAR_DEVID: 1495 *result = (cfg->device << 16) | cfg->vendor; 1496 break; 1497 case PCI_IVAR_CLASS: 1498 *result = cfg->baseclass; 1499 break; 1500 case PCI_IVAR_SUBCLASS: 1501 *result = cfg->subclass; 1502 break; 1503 case PCI_IVAR_PROGIF: 1504 *result = cfg->progif; 1505 break; 1506 case PCI_IVAR_REVID: 1507 *result = cfg->revid; 1508 break; 1509 case PCI_IVAR_INTPIN: 1510 *result = cfg->intpin; 1511 break; 1512 case PCI_IVAR_IRQ: 1513 *result = cfg->intline; 1514 break; 1515 case PCI_IVAR_BUS: 1516 *result = cfg->bus; 1517 break; 1518 case PCI_IVAR_SLOT: 1519 *result = cfg->slot; 1520 break; 1521 case PCI_IVAR_FUNCTION: 1522 *result = cfg->func; 1523 break; 1524 default: 1525 return (ENOENT); 1526 } 1527 return (0); 1528} 1529 1530int 1531pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1532{ 1533 struct pci_devinfo *dinfo; 1534 1535 dinfo = device_get_ivars(child); 1536 1537 switch (which) { 1538 case PCI_IVAR_INTPIN: 1539 dinfo->cfg.intpin = value; 1540 return (0); 1541 case PCI_IVAR_ETHADDR: 1542 case PCI_IVAR_SUBVENDOR: 1543 case PCI_IVAR_SUBDEVICE: 1544 case PCI_IVAR_VENDOR: 1545 case PCI_IVAR_DEVICE: 1546 case PCI_IVAR_DEVID: 1547 case PCI_IVAR_CLASS: 1548 case PCI_IVAR_SUBCLASS: 1549 case PCI_IVAR_PROGIF: 1550 case PCI_IVAR_REVID: 1551 case PCI_IVAR_IRQ: 1552 case PCI_IVAR_BUS: 1553 case PCI_IVAR_SLOT: 1554 case PCI_IVAR_FUNCTION: 1555 return (EINVAL); /* disallow for now */ 1556 1557 default: 1558 return (ENOENT); 1559 } 1560} 1561 1562 1563#include "opt_ddb.h" 1564#ifdef DDB 1565#include <ddb/ddb.h> 1566#include <sys/cons.h> 1567 1568/* 1569 * List resources based on pci map registers, used for within ddb 1570 */ 1571 1572DB_SHOW_COMMAND(pciregs, db_pci_dump) 1573{ 1574 struct pci_devinfo *dinfo; 1575 struct devlist *devlist_head; 1576 struct pci_conf *p; 1577 const char *name; 1578 int i, error, none_count, quit; 1579 1580 none_count = 0; 1581 /* get the head of the device queue */ 1582 devlist_head = &pci_devq; 1583 1584 /* 1585 * Go through the list of devices and print out devices 1586 */ 1587 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1588 for (error = 0, i = 0, quit = 0, 1589 dinfo = STAILQ_FIRST(devlist_head); 1590 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1591 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1592 1593 /* Populate pd_name and pd_unit */ 1594 name = NULL; 1595 if (dinfo->cfg.dev) 1596 name = device_get_name(dinfo->cfg.dev); 1597 1598 p = &dinfo->conf; 1599 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1600 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1601 (name && *name) ? name : "none", 1602 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1603 none_count++, 1604 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1605 p->pc_sel.pc_func, (p->pc_class << 16) | 1606 (p->pc_subclass << 8) | p->pc_progif, 1607 (p->pc_subdevice << 16) | p->pc_subvendor, 1608 (p->pc_device << 16) | p->pc_vendor, 1609 p->pc_revid, p->pc_hdr); 1610 } 1611} 1612#endif /* DDB */ 1613 1614static struct resource * 1615pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1616 u_long start, u_long end, u_long count, u_int flags) 1617{ 1618 struct pci_devinfo *dinfo = device_get_ivars(child); 1619 struct resource_list *rl = &dinfo->resources; 1620 struct resource_list_entry *rle; 1621 struct resource *res; 1622 uint32_t map, testval; 1623 int mapsize; 1624 1625 /* 1626 * Weed out the bogons, and figure out how large the BAR/map 1627 * is. Bars that read back 0 here are bogus and unimplemented. 1628 * Note: atapci in legacy mode are special and handled elsewhere 1629 * in the code. If you have a atapci device in legacy mode and 1630 * it fails here, that other code is broken. 1631 */ 1632 res = NULL; 1633 map = pci_read_config(child, *rid, 4); 1634 pci_write_config(child, *rid, 0xffffffff, 4); 1635 testval = pci_read_config(child, *rid, 4); 1636 if (pci_mapbase(testval) == 0) 1637 goto out; 1638 if (pci_maptype(testval) & PCI_MAPMEM) { 1639 if (type != SYS_RES_MEMORY) { 1640 if (bootverbose) 1641 device_printf(child, 1642 "rid %#x is memory, requested %d\n", 1643 *rid, type); 1644 goto out; 1645 } 1646 } else { 1647 if (type != SYS_RES_IOPORT) { 1648 if (bootverbose) 1649 device_printf(child, 1650 "rid %#x is ioport, requested %d\n", 1651 *rid, type); 1652 goto out; 1653 } 1654 } 1655 /* 1656 * For real BARs, we need to override the size that 1657 * the driver requests, because that's what the BAR 1658 * actually uses and we would otherwise have a 1659 * situation where we might allocate the excess to 1660 * another driver, which won't work. 1661 */ 1662 mapsize = pci_mapsize(testval); 1663 count = 1 << mapsize; 1664 if (RF_ALIGNMENT(flags) < mapsize) 1665 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1666 1667 /* 1668 * Allocate enough resource, and then write back the 1669 * appropriate bar for that resource. 1670 */ 1671 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1672 start, end, count, flags); 1673 if (res == NULL) { 1674 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1675 count, *rid, type); 1676 goto out; 1677 } 1678 resource_list_add(rl, type, *rid, start, end, count); 1679 rle = resource_list_find(rl, type, *rid); 1680 if (rle == NULL) 1681 panic("pci_alloc_map: unexpectedly can't find resource."); 1682 rle->res = res; 1683 if (bootverbose) 1684 device_printf(child, 1685 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1686 count, *rid, type, rman_get_start(res)); 1687 map = rman_get_start(res); 1688out:; 1689 pci_write_config(child, *rid, map, 4); 1690 return (res); 1691} 1692 1693 1694struct resource * 1695pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1696 u_long start, u_long end, u_long count, u_int flags) 1697{ 1698 struct pci_devinfo *dinfo = device_get_ivars(child); 1699 struct resource_list *rl = &dinfo->resources; 1700 struct resource_list_entry *rle; 1701 pcicfgregs *cfg = &dinfo->cfg; 1702 1703 /* 1704 * Perform lazy resource allocation 1705 */ 1706 if (device_get_parent(child) == dev) { 1707 switch (type) { 1708 case SYS_RES_IRQ: 1709 /* 1710 * If the child device doesn't have an 1711 * interrupt routed and is deserving of an 1712 * interrupt, try to assign it one. 1713 */ 1714 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1715 (cfg->intpin != 0)) { 1716 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1717 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1718 pci_write_config(child, PCIR_INTLINE, 1719 cfg->intline, 1); 1720 resource_list_add(rl, SYS_RES_IRQ, 0, 1721 cfg->intline, cfg->intline, 1); 1722 } 1723 } 1724 break; 1725 case SYS_RES_IOPORT: 1726 case SYS_RES_MEMORY: 1727 if (*rid < PCIR_BAR(cfg->nummaps)) { 1728 /* 1729 * Enable the I/O mode. We should 1730 * also be assigning resources too 1731 * when none are present. The 1732 * resource_list_alloc kind of sorta does 1733 * this... 1734 */ 1735 if (PCI_ENABLE_IO(dev, child, type)) 1736 return (NULL); 1737 } 1738 rle = resource_list_find(rl, type, *rid); 1739 if (rle == NULL) 1740 return (pci_alloc_map(dev, child, type, rid, 1741 start, end, count, flags)); 1742 break; 1743 } 1744 /* 1745 * If we've already allocated the resource, then 1746 * return it now. But first we may need to activate 1747 * it, since we don't allocate the resource as active 1748 * above. Normally this would be done down in the 1749 * nexus, but since we short-circuit that path we have 1750 * to do its job here. Not sure if we should free the 1751 * resource if it fails to activate. 1752 */ 1753 rle = resource_list_find(rl, type, *rid); 1754 if (rle != NULL && rle->res != NULL) { 1755 if (bootverbose) 1756 device_printf(child, 1757 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1758 rman_get_size(rle->res), *rid, type, 1759 rman_get_start(rle->res)); 1760 if ((flags & RF_ACTIVE) && 1761 bus_generic_activate_resource(dev, child, type, 1762 *rid, rle->res) != 0) 1763 return NULL; 1764 return (rle->res); 1765 } 1766 } 1767 return (resource_list_alloc(rl, dev, child, type, rid, 1768 start, end, count, flags)); 1769} 1770 1771void 1772pci_delete_resource(device_t dev, device_t child, int type, int rid) 1773{ 1774 struct pci_devinfo *dinfo; 1775 struct resource_list *rl; 1776 struct resource_list_entry *rle; 1777 1778 if (device_get_parent(child) != dev) 1779 return; 1780 1781 dinfo = device_get_ivars(child); 1782 rl = &dinfo->resources; 1783 rle = resource_list_find(rl, type, rid); 1784 if (rle) { 1785 if (rle->res) { 1786 if (rman_get_device(rle->res) != dev || 1787 rman_get_flags(rle->res) & RF_ACTIVE) { 1788 device_printf(dev, "delete_resource: " 1789 "Resource still owned by child, oops. " 1790 "(type=%d, rid=%d, addr=%lx)\n", 1791 rle->type, rle->rid, 1792 rman_get_start(rle->res)); 1793 return; 1794 } 1795 bus_release_resource(dev, type, rid, rle->res); 1796 } 1797 resource_list_delete(rl, type, rid); 1798 } 1799 /* 1800 * Why do we turn off the PCI configuration BAR when we delete a 1801 * resource? -- imp 1802 */ 1803 pci_write_config(child, rid, 0, 4); 1804 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1805} 1806 1807struct resource_list * 1808pci_get_resource_list (device_t dev, device_t child) 1809{ 1810 struct pci_devinfo *dinfo = device_get_ivars(child); 1811 1812 return (&dinfo->resources); 1813} 1814 1815uint32_t 1816pci_read_config_method(device_t dev, device_t child, int reg, int width) 1817{ 1818 struct pci_devinfo *dinfo = device_get_ivars(child); 1819 pcicfgregs *cfg = &dinfo->cfg; 1820 1821 return (PCIB_READ_CONFIG(device_get_parent(dev), 1822 cfg->bus, cfg->slot, cfg->func, reg, width)); 1823} 1824 1825void 1826pci_write_config_method(device_t dev, device_t child, int reg, 1827 uint32_t val, int width) 1828{ 1829 struct pci_devinfo *dinfo = device_get_ivars(child); 1830 pcicfgregs *cfg = &dinfo->cfg; 1831 1832 PCIB_WRITE_CONFIG(device_get_parent(dev), 1833 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1834} 1835 1836int 1837pci_child_location_str_method(device_t dev, device_t child, char *buf, 1838 size_t buflen) 1839{ 1840 1841 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1842 pci_get_function(child)); 1843 return (0); 1844} 1845 1846int 1847pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1848 size_t buflen) 1849{ 1850 struct pci_devinfo *dinfo; 1851 pcicfgregs *cfg; 1852 1853 dinfo = device_get_ivars(child); 1854 cfg = &dinfo->cfg; 1855 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1856 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1857 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1858 cfg->progif); 1859 return (0); 1860} 1861 1862int 1863pci_assign_interrupt_method(device_t dev, device_t child) 1864{ 1865 struct pci_devinfo *dinfo = device_get_ivars(child); 1866 pcicfgregs *cfg = &dinfo->cfg; 1867 1868 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1869 cfg->intpin)); 1870} 1871 1872static int 1873pci_modevent(module_t mod, int what, void *arg) 1874{ 1875 static struct cdev *pci_cdev; 1876 1877 switch (what) { 1878 case MOD_LOAD: 1879 STAILQ_INIT(&pci_devq); 1880 pci_generation = 0; 1881 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1882 "pci"); 1883 pci_load_vendor_data(); 1884 break; 1885 1886 case MOD_UNLOAD: 1887 destroy_dev(pci_cdev); 1888 break; 1889 } 1890 1891 return (0); 1892} 1893 1894void 1895pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1896{ 1897 int i; 1898 1899 /* 1900 * Only do header type 0 devices. Type 1 devices are bridges, 1901 * which we know need special treatment. Type 2 devices are 1902 * cardbus bridges which also require special treatment. 1903 * Other types are unknown, and we err on the side of safety 1904 * by ignoring them. 1905 */ 1906 if (dinfo->cfg.hdrtype != 0) 1907 return; 1908 1909 /* 1910 * Restore the device to full power mode. We must do this 1911 * before we restore the registers because moving from D3 to 1912 * D0 will cause the chip's BARs and some other registers to 1913 * be reset to some unknown power on reset values. Cut down 1914 * the noise on boot by doing nothing if we are already in 1915 * state D0. 1916 */ 1917 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1918 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1919 } 1920 for (i = 0; i < dinfo->cfg.nummaps; i++) 1921 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1922 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1923 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1924 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1925 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1926 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1927 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1928 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1929 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1930 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1931 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1932} 1933 1934void 1935pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1936{ 1937 int i; 1938 uint32_t cls; 1939 int ps; 1940 1941 /* 1942 * Only do header type 0 devices. Type 1 devices are bridges, which 1943 * we know need special treatment. Type 2 devices are cardbus bridges 1944 * which also require special treatment. Other types are unknown, and 1945 * we err on the side of safety by ignoring them. Powering down 1946 * bridges should not be undertaken lightly. 1947 */ 1948 if (dinfo->cfg.hdrtype != 0) 1949 return; 1950 for (i = 0; i < dinfo->cfg.nummaps; i++) 1951 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1952 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1953 1954 /* 1955 * Some drivers apparently write to these registers w/o updating our 1956 * cached copy. No harm happens if we update the copy, so do so here 1957 * so we can restore them. The COMMAND register is modified by the 1958 * bus w/o updating the cache. This should represent the normally 1959 * writable portion of the 'defined' part of type 0 headers. In 1960 * theory we also need to save/restore the PCI capability structures 1961 * we know about, but apart from power we don't know any that are 1962 * writable. 1963 */ 1964 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1965 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1966 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1967 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1968 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1969 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1970 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1971 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1972 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1973 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1974 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1975 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1976 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1977 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1978 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1979 1980 /* 1981 * don't set the state for display devices, base peripherals and 1982 * memory devices since bad things happen when they are powered down. 1983 * We should (a) have drivers that can easily detach and (b) use 1984 * generic drivers for these devices so that some device actually 1985 * attaches. We need to make sure that when we implement (a) we don't 1986 * power the device down on a reattach. 1987 */ 1988 cls = pci_get_class(dev); 1989 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY && 1990 cls != PCIC_BASEPERIPH) { 1991 /* 1992 * PCI spec says we can only go into D3 state from D0 state. 1993 * Transition from D[12] into D0 before going to D3 state. 1994 */ 1995 ps = pci_get_powerstate(dev); 1996 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1997 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1998 } 1999 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 2000 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2001 } 2002 } 2003} 2004