pci.c revision 149686
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 149686 2005-09-01 02:42:34Z imp $"); 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63#if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65#include <contrib/dev/acpica/acpi.h> 66#include "acpi_if.h" 67#else 68#define ACPI_PWR_FOR_SLEEP(x, y, z) 69#endif 70 71static uint32_t pci_mapbase(unsigned mapreg); 72static int pci_maptype(unsigned mapreg); 73static int pci_mapsize(unsigned testval); 74static int pci_maprange(unsigned mapreg); 75static void pci_fixancient(pcicfgregs *cfg); 76 77static int pci_porten(device_t pcib, int b, int s, int f); 78static int pci_memen(device_t pcib, int b, int s, int f); 79static int pci_add_map(device_t pcib, device_t bus, device_t dev, 80 int b, int s, int f, int reg, 81 struct resource_list *rl); 82static void pci_add_resources(device_t pcib, device_t bus, 83 device_t dev); 84static int pci_probe(device_t dev); 85static int pci_attach(device_t dev); 86static void pci_load_vendor_data(void); 87static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89static char *pci_describe_device(device_t dev); 90static int pci_modevent(module_t mod, int what, void *arg); 91static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 95static device_method_t pci_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pci_probe), 98 DEVMETHOD(device_attach, pci_attach), 99 DEVMETHOD(device_detach, bus_generic_detach), 100 DEVMETHOD(device_shutdown, bus_generic_shutdown), 101 DEVMETHOD(device_suspend, pci_suspend), 102 DEVMETHOD(device_resume, pci_resume), 103 104 /* Bus interface */ 105 DEVMETHOD(bus_print_child, pci_print_child), 106 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 107 DEVMETHOD(bus_read_ivar, pci_read_ivar), 108 DEVMETHOD(bus_write_ivar, pci_write_ivar), 109 DEVMETHOD(bus_driver_added, pci_driver_added), 110 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 111 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 112 113 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 114 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 115 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 116 DEVMETHOD(bus_delete_resource, pci_delete_resource), 117 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 118 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 119 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 120 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 121 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 122 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 123 124 /* PCI interface */ 125 DEVMETHOD(pci_read_config, pci_read_config_method), 126 DEVMETHOD(pci_write_config, pci_write_config_method), 127 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 128 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 129 DEVMETHOD(pci_enable_io, pci_enable_io_method), 130 DEVMETHOD(pci_disable_io, pci_disable_io_method), 131 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 132 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 133 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 134 135 { 0, 0 } 136}; 137 138DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 139 140devclass_t pci_devclass; 141DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 142MODULE_VERSION(pci, 1); 143 144static char *pci_vendordata; 145static size_t pci_vendordata_size; 146 147 148struct pci_quirk { 149 uint32_t devid; /* Vendor/device of the card */ 150 int type; 151#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 152 int arg1; 153 int arg2; 154}; 155 156struct pci_quirk pci_quirks[] = { 157 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 158 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 159 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 160 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 161 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 163 { 0 } 164}; 165 166/* map register information */ 167#define PCI_MAPMEM 0x01 /* memory map */ 168#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 169#define PCI_MAPPORT 0x04 /* port map */ 170 171struct devlist pci_devq; 172uint32_t pci_generation; 173uint32_t pci_numdevs = 0; 174 175/* sysctl vars */ 176SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 177 178static int pci_enable_io_modes = 1; 179TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 180SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 181 &pci_enable_io_modes, 1, 182 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 183enable these bits correctly. We'd like to do this all the time, but there\n\ 184are some peripherals that this causes problems with."); 185 186static int pci_do_powerstate = 1; 187TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 188SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 189 &pci_do_powerstate, 1, 190 "Power down devices into D3 state when no driver attaches to them.\n\ 191Otherwise, leave the device in D0 state when no driver attaches."); 192 193/* Find a device_t by bus/slot/function */ 194 195device_t 196pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 197{ 198 struct pci_devinfo *dinfo; 199 200 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 201 if ((dinfo->cfg.bus == bus) && 202 (dinfo->cfg.slot == slot) && 203 (dinfo->cfg.func == func)) { 204 return (dinfo->cfg.dev); 205 } 206 } 207 208 return (NULL); 209} 210 211/* Find a device_t by vendor/device ID */ 212 213device_t 214pci_find_device(uint16_t vendor, uint16_t device) 215{ 216 struct pci_devinfo *dinfo; 217 218 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 219 if ((dinfo->cfg.vendor == vendor) && 220 (dinfo->cfg.device == device)) { 221 return (dinfo->cfg.dev); 222 } 223 } 224 225 return (NULL); 226} 227 228/* return base address of memory or port map */ 229 230static uint32_t 231pci_mapbase(unsigned mapreg) 232{ 233 int mask = 0x03; 234 if ((mapreg & 0x01) == 0) 235 mask = 0x0f; 236 return (mapreg & ~mask); 237} 238 239/* return map type of memory or port map */ 240 241static int 242pci_maptype(unsigned mapreg) 243{ 244 static uint8_t maptype[0x10] = { 245 PCI_MAPMEM, PCI_MAPPORT, 246 PCI_MAPMEM, 0, 247 PCI_MAPMEM, PCI_MAPPORT, 248 0, 0, 249 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 250 PCI_MAPMEM|PCI_MAPMEMP, 0, 251 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 252 0, 0, 253 }; 254 255 return maptype[mapreg & 0x0f]; 256} 257 258/* return log2 of map size decoded for memory or port map */ 259 260static int 261pci_mapsize(unsigned testval) 262{ 263 int ln2size; 264 265 testval = pci_mapbase(testval); 266 ln2size = 0; 267 if (testval != 0) { 268 while ((testval & 1) == 0) 269 { 270 ln2size++; 271 testval >>= 1; 272 } 273 } 274 return (ln2size); 275} 276 277/* return log2 of address range supported by map register */ 278 279static int 280pci_maprange(unsigned mapreg) 281{ 282 int ln2range = 0; 283 switch (mapreg & 0x07) { 284 case 0x00: 285 case 0x01: 286 case 0x05: 287 ln2range = 32; 288 break; 289 case 0x02: 290 ln2range = 20; 291 break; 292 case 0x04: 293 ln2range = 64; 294 break; 295 } 296 return (ln2range); 297} 298 299/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 300 301static void 302pci_fixancient(pcicfgregs *cfg) 303{ 304 if (cfg->hdrtype != 0) 305 return; 306 307 /* PCI to PCI bridges use header type 1 */ 308 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 309 cfg->hdrtype = 1; 310} 311 312/* extract header type specific config data */ 313 314static void 315pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 316{ 317#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 318 switch (cfg->hdrtype) { 319 case 0: 320 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 321 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 322 cfg->nummaps = PCI_MAXMAPS_0; 323 break; 324 case 1: 325 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 326 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 327 cfg->nummaps = PCI_MAXMAPS_1; 328 break; 329 case 2: 330 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 331 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 332 cfg->nummaps = PCI_MAXMAPS_2; 333 break; 334 } 335#undef REG 336} 337 338/* read configuration header into pcicfgregs structure */ 339 340struct pci_devinfo * 341pci_read_device(device_t pcib, int b, int s, int f, size_t size) 342{ 343#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 344 pcicfgregs *cfg = NULL; 345 struct pci_devinfo *devlist_entry; 346 struct devlist *devlist_head; 347 348 devlist_head = &pci_devq; 349 350 devlist_entry = NULL; 351 352 if (REG(PCIR_DEVVENDOR, 4) != -1) { 353 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 354 if (devlist_entry == NULL) 355 return (NULL); 356 357 cfg = &devlist_entry->cfg; 358 359 cfg->bus = b; 360 cfg->slot = s; 361 cfg->func = f; 362 cfg->vendor = REG(PCIR_VENDOR, 2); 363 cfg->device = REG(PCIR_DEVICE, 2); 364 cfg->cmdreg = REG(PCIR_COMMAND, 2); 365 cfg->statreg = REG(PCIR_STATUS, 2); 366 cfg->baseclass = REG(PCIR_CLASS, 1); 367 cfg->subclass = REG(PCIR_SUBCLASS, 1); 368 cfg->progif = REG(PCIR_PROGIF, 1); 369 cfg->revid = REG(PCIR_REVID, 1); 370 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 371 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 372 cfg->lattimer = REG(PCIR_LATTIMER, 1); 373 cfg->intpin = REG(PCIR_INTPIN, 1); 374 cfg->intline = REG(PCIR_INTLINE, 1); 375 376 cfg->mingnt = REG(PCIR_MINGNT, 1); 377 cfg->maxlat = REG(PCIR_MAXLAT, 1); 378 379 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 380 cfg->hdrtype &= ~PCIM_MFDEV; 381 382 pci_fixancient(cfg); 383 pci_hdrtypedata(pcib, b, s, f, cfg); 384 385 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 386 pci_read_extcap(pcib, cfg); 387 388 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 389 390 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 391 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 392 devlist_entry->conf.pc_sel.pc_func = cfg->func; 393 devlist_entry->conf.pc_hdr = cfg->hdrtype; 394 395 devlist_entry->conf.pc_subvendor = cfg->subvendor; 396 devlist_entry->conf.pc_subdevice = cfg->subdevice; 397 devlist_entry->conf.pc_vendor = cfg->vendor; 398 devlist_entry->conf.pc_device = cfg->device; 399 400 devlist_entry->conf.pc_class = cfg->baseclass; 401 devlist_entry->conf.pc_subclass = cfg->subclass; 402 devlist_entry->conf.pc_progif = cfg->progif; 403 devlist_entry->conf.pc_revid = cfg->revid; 404 405 pci_numdevs++; 406 pci_generation++; 407 } 408 return (devlist_entry); 409#undef REG 410} 411 412static void 413pci_read_extcap(device_t pcib, pcicfgregs *cfg) 414{ 415#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 416 int ptr, nextptr, ptrptr; 417 418 switch (cfg->hdrtype & PCIM_HDRTYPE) { 419 case 0: 420 ptrptr = PCIR_CAP_PTR; 421 break; 422 case 2: 423 ptrptr = 0x14; 424 break; 425 default: 426 return; /* no extended capabilities support */ 427 } 428 nextptr = REG(ptrptr, 1); /* sanity check? */ 429 430 /* 431 * Read capability entries. 432 */ 433 while (nextptr != 0) { 434 /* Sanity check */ 435 if (nextptr > 255) { 436 printf("illegal PCI extended capability offset %d\n", 437 nextptr); 438 return; 439 } 440 /* Find the next entry */ 441 ptr = nextptr; 442 nextptr = REG(ptr + 1, 1); 443 444 /* Process this entry */ 445 switch (REG(ptr, 1)) { 446 case PCIY_PMG: /* PCI power management */ 447 if (cfg->pp.pp_cap == 0) { 448 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 449 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 450 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 451 if ((nextptr - ptr) > PCIR_POWER_DATA) 452 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 453 } 454 break; 455 case PCIY_MSI: /* PCI MSI */ 456 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 457 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 458 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 459 else 460 cfg->msi.msi_data = PCIR_MSI_DATA; 461 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 462 PCIM_MSICTRL_MMC_MASK)>>1); 463 default: 464 break; 465 } 466 } 467#undef REG 468} 469 470/* free pcicfgregs structure and all depending data structures */ 471 472int 473pci_freecfg(struct pci_devinfo *dinfo) 474{ 475 struct devlist *devlist_head; 476 477 devlist_head = &pci_devq; 478 479 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 480 free(dinfo, M_DEVBUF); 481 482 /* increment the generation count */ 483 pci_generation++; 484 485 /* we're losing one device */ 486 pci_numdevs--; 487 return (0); 488} 489 490/* 491 * PCI power manangement 492 */ 493int 494pci_set_powerstate_method(device_t dev, device_t child, int state) 495{ 496 struct pci_devinfo *dinfo = device_get_ivars(child); 497 pcicfgregs *cfg = &dinfo->cfg; 498 uint16_t status; 499 int result, oldstate, highest, delay; 500 501 if (cfg->pp.pp_cap == 0) 502 return (EOPNOTSUPP); 503 504 /* 505 * Optimize a no state change request away. While it would be OK to 506 * write to the hardware in theory, some devices have shown odd 507 * behavior when going from D3 -> D3. 508 */ 509 oldstate = pci_get_powerstate(child); 510 if (oldstate == state) 511 return (0); 512 513 /* 514 * The PCI power management specification states that after a state 515 * transition between PCI power states, system software must 516 * guarantee a minimal delay before the function accesses the device. 517 * Compute the worst case delay that we need to guarantee before we 518 * access the device. Many devices will be responsive much more 519 * quickly than this delay, but there are some that don't respond 520 * instantly to state changes. Transitions to/from D3 state require 521 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 522 * is done below with DELAY rather than a sleeper function because 523 * this function can be called from contexts where we cannot sleep. 524 */ 525 highest = (oldstate > state) ? oldstate : state; 526 if (highest == PCI_POWERSTATE_D3) 527 delay = 10000; 528 else if (highest == PCI_POWERSTATE_D2) 529 delay = 200; 530 else 531 delay = 0; 532 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 533 & ~PCIM_PSTAT_DMASK; 534 result = 0; 535 switch (state) { 536 case PCI_POWERSTATE_D0: 537 status |= PCIM_PSTAT_D0; 538 break; 539 case PCI_POWERSTATE_D1: 540 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 541 return (EOPNOTSUPP); 542 status |= PCIM_PSTAT_D1; 543 break; 544 case PCI_POWERSTATE_D2: 545 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 546 return (EOPNOTSUPP); 547 status |= PCIM_PSTAT_D2; 548 break; 549 case PCI_POWERSTATE_D3: 550 status |= PCIM_PSTAT_D3; 551 break; 552 default: 553 return (EINVAL); 554 } 555 556 if (bootverbose) 557 printf( 558 "pci%d:%d:%d: Transition from D%d to D%d\n", 559 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 560 oldstate, state); 561 562 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 563 if (delay) 564 DELAY(delay); 565 return (0); 566} 567 568int 569pci_get_powerstate_method(device_t dev, device_t child) 570{ 571 struct pci_devinfo *dinfo = device_get_ivars(child); 572 pcicfgregs *cfg = &dinfo->cfg; 573 uint16_t status; 574 int result; 575 576 if (cfg->pp.pp_cap != 0) { 577 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 578 switch (status & PCIM_PSTAT_DMASK) { 579 case PCIM_PSTAT_D0: 580 result = PCI_POWERSTATE_D0; 581 break; 582 case PCIM_PSTAT_D1: 583 result = PCI_POWERSTATE_D1; 584 break; 585 case PCIM_PSTAT_D2: 586 result = PCI_POWERSTATE_D2; 587 break; 588 case PCIM_PSTAT_D3: 589 result = PCI_POWERSTATE_D3; 590 break; 591 default: 592 result = PCI_POWERSTATE_UNKNOWN; 593 break; 594 } 595 } else { 596 /* No support, device is always at D0 */ 597 result = PCI_POWERSTATE_D0; 598 } 599 return (result); 600} 601 602/* 603 * Some convenience functions for PCI device drivers. 604 */ 605 606static __inline void 607pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 608{ 609 uint16_t command; 610 611 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 612 command |= bit; 613 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 614} 615 616static __inline void 617pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 618{ 619 uint16_t command; 620 621 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 622 command &= ~bit; 623 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 624} 625 626int 627pci_enable_busmaster_method(device_t dev, device_t child) 628{ 629 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 630 return (0); 631} 632 633int 634pci_disable_busmaster_method(device_t dev, device_t child) 635{ 636 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 637 return (0); 638} 639 640int 641pci_enable_io_method(device_t dev, device_t child, int space) 642{ 643 uint16_t command; 644 uint16_t bit; 645 char *error; 646 647 bit = 0; 648 error = NULL; 649 650 switch(space) { 651 case SYS_RES_IOPORT: 652 bit = PCIM_CMD_PORTEN; 653 error = "port"; 654 break; 655 case SYS_RES_MEMORY: 656 bit = PCIM_CMD_MEMEN; 657 error = "memory"; 658 break; 659 default: 660 return (EINVAL); 661 } 662 pci_set_command_bit(dev, child, bit); 663 /* Some devices seem to need a brief stall here, what do to? */ 664 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 665 if (command & bit) 666 return (0); 667 device_printf(child, "failed to enable %s mapping!\n", error); 668 return (ENXIO); 669} 670 671int 672pci_disable_io_method(device_t dev, device_t child, int space) 673{ 674 uint16_t command; 675 uint16_t bit; 676 char *error; 677 678 bit = 0; 679 error = NULL; 680 681 switch(space) { 682 case SYS_RES_IOPORT: 683 bit = PCIM_CMD_PORTEN; 684 error = "port"; 685 break; 686 case SYS_RES_MEMORY: 687 bit = PCIM_CMD_MEMEN; 688 error = "memory"; 689 break; 690 default: 691 return (EINVAL); 692 } 693 pci_clear_command_bit(dev, child, bit); 694 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 695 if (command & bit) { 696 device_printf(child, "failed to disable %s mapping!\n", error); 697 return (ENXIO); 698 } 699 return (0); 700} 701 702/* 703 * New style pci driver. Parent device is either a pci-host-bridge or a 704 * pci-pci-bridge. Both kinds are represented by instances of pcib. 705 */ 706 707void 708pci_print_verbose(struct pci_devinfo *dinfo) 709{ 710 if (bootverbose) { 711 pcicfgregs *cfg = &dinfo->cfg; 712 713 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 714 cfg->vendor, cfg->device, cfg->revid); 715 printf("\tbus=%d, slot=%d, func=%d\n", 716 cfg->bus, cfg->slot, cfg->func); 717 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 718 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 719 cfg->mfdev); 720 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 721 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 722 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 723 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 724 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 725 if (cfg->intpin > 0) 726 printf("\tintpin=%c, irq=%d\n", 727 cfg->intpin +'a' -1, cfg->intline); 728 if (cfg->pp.pp_cap) { 729 uint16_t status; 730 731 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 732 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 733 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 734 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 735 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 736 status & PCIM_PSTAT_DMASK); 737 } 738 if (cfg->msi.msi_data) { 739 int ctrl; 740 741 ctrl = cfg->msi.msi_ctrl; 742 printf("\tMSI supports %d message%s%s%s\n", 743 cfg->msi.msi_msgnum, 744 (cfg->msi.msi_msgnum == 1) ? "" : "s", 745 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 746 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 747 } 748 } 749} 750 751static int 752pci_porten(device_t pcib, int b, int s, int f) 753{ 754 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 755 & PCIM_CMD_PORTEN) != 0; 756} 757 758static int 759pci_memen(device_t pcib, int b, int s, int f) 760{ 761 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 762 & PCIM_CMD_MEMEN) != 0; 763} 764 765/* 766 * Add a resource based on a pci map register. Return 1 if the map 767 * register is a 32bit map register or 2 if it is a 64bit register. 768 */ 769static int 770pci_add_map(device_t pcib, device_t bus, device_t dev, 771 int b, int s, int f, int reg, struct resource_list *rl) 772{ 773 uint32_t map; 774 uint64_t base; 775 uint64_t start, end, count; 776 uint8_t ln2size; 777 uint8_t ln2range; 778 uint32_t testval; 779 uint16_t cmd; 780 int type; 781 782 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 783 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 784 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 785 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 786 787 if (pci_maptype(map) & PCI_MAPMEM) 788 type = SYS_RES_MEMORY; 789 else 790 type = SYS_RES_IOPORT; 791 ln2size = pci_mapsize(testval); 792 ln2range = pci_maprange(testval); 793 base = pci_mapbase(map); 794 795 /* 796 * For I/O registers, if bottom bit is set, and the next bit up 797 * isn't clear, we know we have a BAR that doesn't conform to the 798 * spec, so ignore it. Also, sanity check the size of the data 799 * areas to the type of memory involved. Memory must be at least 800 * 32 bytes in size, while I/O ranges must be at least 4. 801 */ 802 if ((testval & 0x1) == 0x1 && 803 (testval & 0x2) != 0) 804 return (1); 805 if ((type == SYS_RES_MEMORY && ln2size < 5) || 806 (type == SYS_RES_IOPORT && ln2size < 2)) 807 return (1); 808 809 if (ln2range == 64) 810 /* Read the other half of a 64bit map register */ 811 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 812 813 if (bootverbose) { 814 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 815 reg, pci_maptype(map), ln2range, 816 (unsigned int) base, ln2size); 817 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 818 printf(", port disabled\n"); 819 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 820 printf(", memory disabled\n"); 821 else 822 printf(", enabled\n"); 823 } 824 825 /* 826 * If base is 0, then we have problems. It is best to ignore 827 * such entries for the moment. These will be allocated later if 828 * the driver specifically requests them. 829 * 830 * Similarlly treat maps whose values is the same as the test value 831 * read back. These maps have had all f's written to them by the 832 * BIOS in an attempt to disable the resources. 833 */ 834 if (base == 0 || map == testval) 835 return 1; 836 837 /* 838 * This code theoretically does the right thing, but has 839 * undesirable side effects in some cases where peripherals 840 * respond oddly to having these bits enabled. Let the user 841 * be able to turn them off (since pci_enable_io_modes is 1 by 842 * default). 843 */ 844 if (pci_enable_io_modes) { 845 /* Turn on resources that have been left off by a lazy BIOS */ 846 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 847 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 848 cmd |= PCIM_CMD_PORTEN; 849 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 850 } 851 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 852 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 853 cmd |= PCIM_CMD_MEMEN; 854 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 855 } 856 } else { 857 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 858 return (1); 859 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 860 return (1); 861 } 862 863 start = base; 864 end = base + (1 << ln2size) - 1; 865 count = 1 << ln2size; 866 resource_list_add(rl, type, reg, start, end, count); 867 868 /* 869 * Not quite sure what to do on failure of allocating the resource 870 * since I can postulate several right answers. 871 */ 872 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 873 return ((ln2range == 64) ? 2 : 1); 874} 875 876/* 877 * For ATA devices we need to decide early what addressing mode to use. 878 * Legacy demands that the primary and secondary ATA ports sits on the 879 * same addresses that old ISA hardware did. This dictates that we use 880 * those addresses and ignore the BAR's if we cannot set PCI native 881 * addressing mode. 882 */ 883static void 884pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 885 int s, int f, struct resource_list *rl) 886{ 887 int rid, type, progif; 888#if 0 889 /* if this device supports PCI native addressing use it */ 890 progif = pci_read_config(dev, PCIR_PROGIF, 1); 891 if ((progif & 0x8a) == 0x8a) { 892 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 893 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 894 printf("Trying ATA native PCI addressing mode\n"); 895 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 896 } 897 } 898#endif 899 progif = pci_read_config(dev, PCIR_PROGIF, 1); 900 type = SYS_RES_IOPORT; 901 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 902 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 903 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 904 } 905 else { 906 rid = PCIR_BAR(0); 907 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 908 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 909 rid = PCIR_BAR(1); 910 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 911 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 912 } 913 if (progif & PCIP_STORAGE_IDE_MODESEC) { 914 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 915 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 916 } 917 else { 918 rid = PCIR_BAR(2); 919 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 920 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 921 rid = PCIR_BAR(3); 922 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 923 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 924 } 925 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 926 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl); 927} 928 929static void 930pci_add_resources(device_t pcib, device_t bus, device_t dev) 931{ 932 struct pci_devinfo *dinfo = device_get_ivars(dev); 933 pcicfgregs *cfg = &dinfo->cfg; 934 struct resource_list *rl = &dinfo->resources; 935 struct pci_quirk *q; 936 int b, i, irq, f, s; 937 938 b = cfg->bus; 939 s = cfg->slot; 940 f = cfg->func; 941 942 /* ATA devices needs special map treatment */ 943 if ((pci_get_class(dev) == PCIC_STORAGE) && 944 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 945 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 946 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 947 else 948 for (i = 0; i < cfg->nummaps;) 949 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 950 rl); 951 952 for (q = &pci_quirks[0]; q->devid; q++) { 953 if (q->devid == ((cfg->device << 16) | cfg->vendor) 954 && q->type == PCI_QUIRK_MAP_REG) 955 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 956 } 957 958 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 959#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 960 defined(__arm__) || defined(__alpha__) 961 /* 962 * Try to re-route interrupts. Sometimes the BIOS or 963 * firmware may leave bogus values in these registers. 964 * If the re-route fails, then just stick with what we 965 * have. 966 */ 967 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 968 if (PCI_INTERRUPT_VALID(irq)) { 969 pci_write_config(dev, PCIR_INTLINE, irq, 1); 970 cfg->intline = irq; 971 } else 972#endif 973 irq = cfg->intline; 974 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 975 } 976} 977 978void 979pci_add_children(device_t dev, int busno, size_t dinfo_size) 980{ 981#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 982 device_t pcib = device_get_parent(dev); 983 struct pci_devinfo *dinfo; 984 int maxslots; 985 int s, f, pcifunchigh; 986 uint8_t hdrtype; 987 988 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 989 ("dinfo_size too small")); 990 maxslots = PCIB_MAXSLOTS(pcib); 991 for (s = 0; s <= maxslots; s++) { 992 pcifunchigh = 0; 993 f = 0; 994 hdrtype = REG(PCIR_HDRTYPE, 1); 995 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 996 continue; 997 if (hdrtype & PCIM_MFDEV) 998 pcifunchigh = PCI_FUNCMAX; 999 for (f = 0; f <= pcifunchigh; f++) { 1000 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1001 if (dinfo != NULL) { 1002 pci_add_child(dev, dinfo); 1003 } 1004 } 1005 } 1006#undef REG 1007} 1008 1009void 1010pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1011{ 1012 device_t pcib; 1013 1014 pcib = device_get_parent(bus); 1015 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1016 device_set_ivars(dinfo->cfg.dev, dinfo); 1017 resource_list_init(&dinfo->resources); 1018 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1019 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1020 pci_print_verbose(dinfo); 1021 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1022} 1023 1024static int 1025pci_probe(device_t dev) 1026{ 1027 1028 device_set_desc(dev, "PCI bus"); 1029 1030 /* Allow other subclasses to override this driver. */ 1031 return (-1000); 1032} 1033 1034static int 1035pci_attach(device_t dev) 1036{ 1037 int busno; 1038 1039 /* 1040 * Since there can be multiple independantly numbered PCI 1041 * busses on some large alpha systems, we can't use the unit 1042 * number to decide what bus we are probing. We ask the parent 1043 * pcib what our bus number is. 1044 */ 1045 busno = pcib_get_bus(dev); 1046 if (bootverbose) 1047 device_printf(dev, "physical bus=%d\n", busno); 1048 1049 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1050 1051 return (bus_generic_attach(dev)); 1052} 1053 1054int 1055pci_suspend(device_t dev) 1056{ 1057 int dstate, error, i, numdevs; 1058 device_t acpi_dev, child, *devlist; 1059 struct pci_devinfo *dinfo; 1060 1061 /* 1062 * Save the PCI configuration space for each child and set the 1063 * device in the appropriate power state for this sleep state. 1064 */ 1065 acpi_dev = NULL; 1066 if (pci_do_powerstate) 1067 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1068 device_get_children(dev, &devlist, &numdevs); 1069 for (i = 0; i < numdevs; i++) { 1070 child = devlist[i]; 1071 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1072 pci_cfg_save(child, dinfo, 0); 1073 } 1074 1075 /* Suspend devices before potentially powering them down. */ 1076 error = bus_generic_suspend(dev); 1077 if (error) { 1078 free(devlist, M_TEMP); 1079 return (error); 1080 } 1081 1082 /* 1083 * Always set the device to D3. If ACPI suggests a different 1084 * power state, use it instead. If ACPI is not present, the 1085 * firmware is responsible for managing device power. Skip 1086 * children who aren't attached since they are powered down 1087 * separately. Only manage type 0 devices for now. 1088 */ 1089 for (i = 0; acpi_dev && i < numdevs; i++) { 1090 child = devlist[i]; 1091 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1092 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1093 dstate = PCI_POWERSTATE_D3; 1094 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1095 pci_set_powerstate(child, dstate); 1096 } 1097 } 1098 free(devlist, M_TEMP); 1099 return (0); 1100} 1101 1102int 1103pci_resume(device_t dev) 1104{ 1105 int i, numdevs; 1106 device_t acpi_dev, child, *devlist; 1107 struct pci_devinfo *dinfo; 1108 1109 /* 1110 * Set each child to D0 and restore its PCI configuration space. 1111 */ 1112 acpi_dev = NULL; 1113 if (pci_do_powerstate) 1114 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1115 device_get_children(dev, &devlist, &numdevs); 1116 for (i = 0; i < numdevs; i++) { 1117 /* 1118 * Notify ACPI we're going to D0 but ignore the result. If 1119 * ACPI is not present, the firmware is responsible for 1120 * managing device power. Only manage type 0 devices for now. 1121 */ 1122 child = devlist[i]; 1123 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1124 if (acpi_dev && device_is_attached(child) && 1125 dinfo->cfg.hdrtype == 0) { 1126 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1127 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1128 } 1129 1130 /* Now the device is powered up, restore its config space. */ 1131 pci_cfg_restore(child, dinfo); 1132 } 1133 free(devlist, M_TEMP); 1134 return (bus_generic_resume(dev)); 1135} 1136 1137static void 1138pci_load_vendor_data(void) 1139{ 1140 caddr_t vendordata, info; 1141 1142 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1143 info = preload_search_info(vendordata, MODINFO_ADDR); 1144 pci_vendordata = *(char **)info; 1145 info = preload_search_info(vendordata, MODINFO_SIZE); 1146 pci_vendordata_size = *(size_t *)info; 1147 /* terminate the database */ 1148 pci_vendordata[pci_vendordata_size] = '\n'; 1149 } 1150} 1151 1152void 1153pci_driver_added(device_t dev, driver_t *driver) 1154{ 1155 int numdevs; 1156 device_t *devlist; 1157 device_t child; 1158 struct pci_devinfo *dinfo; 1159 int i; 1160 1161 if (bootverbose) 1162 device_printf(dev, "driver added\n"); 1163 DEVICE_IDENTIFY(driver, dev); 1164 device_get_children(dev, &devlist, &numdevs); 1165 for (i = 0; i < numdevs; i++) { 1166 child = devlist[i]; 1167 if (device_get_state(child) != DS_NOTPRESENT) 1168 continue; 1169 dinfo = device_get_ivars(child); 1170 pci_print_verbose(dinfo); 1171 if (bootverbose) 1172 printf("pci%d:%d:%d: reprobing on driver added\n", 1173 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1174 pci_cfg_restore(child, dinfo); 1175 if (device_probe_and_attach(child) != 0) 1176 pci_cfg_save(child, dinfo, 1); 1177 } 1178 free(devlist, M_TEMP); 1179} 1180 1181int 1182pci_print_child(device_t dev, device_t child) 1183{ 1184 struct pci_devinfo *dinfo; 1185 struct resource_list *rl; 1186 int retval = 0; 1187 1188 dinfo = device_get_ivars(child); 1189 rl = &dinfo->resources; 1190 1191 retval += bus_print_child_header(dev, child); 1192 1193 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1194 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1195 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1196 if (device_get_flags(dev)) 1197 retval += printf(" flags %#x", device_get_flags(dev)); 1198 1199 retval += printf(" at device %d.%d", pci_get_slot(child), 1200 pci_get_function(child)); 1201 1202 retval += bus_print_child_footer(dev, child); 1203 1204 return (retval); 1205} 1206 1207static struct 1208{ 1209 int class; 1210 int subclass; 1211 char *desc; 1212} pci_nomatch_tab[] = { 1213 {PCIC_OLD, -1, "old"}, 1214 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1215 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1216 {PCIC_STORAGE, -1, "mass storage"}, 1217 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1218 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1219 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1220 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1221 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1222 {PCIC_NETWORK, -1, "network"}, 1223 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1224 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1225 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1226 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1227 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1228 {PCIC_DISPLAY, -1, "display"}, 1229 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1230 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1231 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1232 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1233 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1234 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1235 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1236 {PCIC_MEMORY, -1, "memory"}, 1237 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1238 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1239 {PCIC_BRIDGE, -1, "bridge"}, 1240 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1241 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1242 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1243 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1244 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1245 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1246 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1247 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1248 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1249 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1250 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1251 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1252 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1253 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1254 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1255 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1256 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1257 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1258 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1259 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1260 {PCIC_INPUTDEV, -1, "input device"}, 1261 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1262 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1263 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1264 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1265 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1266 {PCIC_DOCKING, -1, "docking station"}, 1267 {PCIC_PROCESSOR, -1, "processor"}, 1268 {PCIC_SERIALBUS, -1, "serial bus"}, 1269 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1270 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1271 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1272 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1273 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1274 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1275 {PCIC_WIRELESS, -1, "wireless controller"}, 1276 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1277 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1278 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1279 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1280 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1281 {PCIC_SATCOM, -1, "satellite communication"}, 1282 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1283 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1284 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1285 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1286 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1287 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1288 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1289 {PCIC_DASP, -1, "dasp"}, 1290 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1291 {0, 0, NULL} 1292}; 1293 1294void 1295pci_probe_nomatch(device_t dev, device_t child) 1296{ 1297 int i; 1298 char *cp, *scp, *device; 1299 1300 /* 1301 * Look for a listing for this device in a loaded device database. 1302 */ 1303 if ((device = pci_describe_device(child)) != NULL) { 1304 device_printf(dev, "<%s>", device); 1305 free(device, M_DEVBUF); 1306 } else { 1307 /* 1308 * Scan the class/subclass descriptions for a general 1309 * description. 1310 */ 1311 cp = "unknown"; 1312 scp = NULL; 1313 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1314 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1315 if (pci_nomatch_tab[i].subclass == -1) { 1316 cp = pci_nomatch_tab[i].desc; 1317 } else if (pci_nomatch_tab[i].subclass == 1318 pci_get_subclass(child)) { 1319 scp = pci_nomatch_tab[i].desc; 1320 } 1321 } 1322 } 1323 device_printf(dev, "<%s%s%s>", 1324 cp ? cp : "", 1325 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1326 scp ? scp : ""); 1327 } 1328 printf(" at device %d.%d (no driver attached)\n", 1329 pci_get_slot(child), pci_get_function(child)); 1330 if (pci_do_powerstate) 1331 pci_cfg_save(child, 1332 (struct pci_devinfo *) device_get_ivars(child), 1); 1333 return; 1334} 1335 1336/* 1337 * Parse the PCI device database, if loaded, and return a pointer to a 1338 * description of the device. 1339 * 1340 * The database is flat text formatted as follows: 1341 * 1342 * Any line not in a valid format is ignored. 1343 * Lines are terminated with newline '\n' characters. 1344 * 1345 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1346 * the vendor name. 1347 * 1348 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1349 * - devices cannot be listed without a corresponding VENDOR line. 1350 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1351 * another TAB, then the device name. 1352 */ 1353 1354/* 1355 * Assuming (ptr) points to the beginning of a line in the database, 1356 * return the vendor or device and description of the next entry. 1357 * The value of (vendor) or (device) inappropriate for the entry type 1358 * is set to -1. Returns nonzero at the end of the database. 1359 * 1360 * Note that this is slightly unrobust in the face of corrupt data; 1361 * we attempt to safeguard against this by spamming the end of the 1362 * database with a newline when we initialise. 1363 */ 1364static int 1365pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1366{ 1367 char *cp = *ptr; 1368 int left; 1369 1370 *device = -1; 1371 *vendor = -1; 1372 **desc = '\0'; 1373 for (;;) { 1374 left = pci_vendordata_size - (cp - pci_vendordata); 1375 if (left <= 0) { 1376 *ptr = cp; 1377 return(1); 1378 } 1379 1380 /* vendor entry? */ 1381 if (*cp != '\t' && 1382 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1383 break; 1384 /* device entry? */ 1385 if (*cp == '\t' && 1386 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1387 break; 1388 1389 /* skip to next line */ 1390 while (*cp != '\n' && left > 0) { 1391 cp++; 1392 left--; 1393 } 1394 if (*cp == '\n') { 1395 cp++; 1396 left--; 1397 } 1398 } 1399 /* skip to next line */ 1400 while (*cp != '\n' && left > 0) { 1401 cp++; 1402 left--; 1403 } 1404 if (*cp == '\n' && left > 0) 1405 cp++; 1406 *ptr = cp; 1407 return(0); 1408} 1409 1410static char * 1411pci_describe_device(device_t dev) 1412{ 1413 int vendor, device; 1414 char *desc, *vp, *dp, *line; 1415 1416 desc = vp = dp = NULL; 1417 1418 /* 1419 * If we have no vendor data, we can't do anything. 1420 */ 1421 if (pci_vendordata == NULL) 1422 goto out; 1423 1424 /* 1425 * Scan the vendor data looking for this device 1426 */ 1427 line = pci_vendordata; 1428 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1429 goto out; 1430 for (;;) { 1431 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1432 goto out; 1433 if (vendor == pci_get_vendor(dev)) 1434 break; 1435 } 1436 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1437 goto out; 1438 for (;;) { 1439 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1440 *dp = 0; 1441 break; 1442 } 1443 if (vendor != -1) { 1444 *dp = 0; 1445 break; 1446 } 1447 if (device == pci_get_device(dev)) 1448 break; 1449 } 1450 if (dp[0] == '\0') 1451 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1452 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1453 NULL) 1454 sprintf(desc, "%s, %s", vp, dp); 1455 out: 1456 if (vp != NULL) 1457 free(vp, M_DEVBUF); 1458 if (dp != NULL) 1459 free(dp, M_DEVBUF); 1460 return(desc); 1461} 1462 1463int 1464pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1465{ 1466 struct pci_devinfo *dinfo; 1467 pcicfgregs *cfg; 1468 1469 dinfo = device_get_ivars(child); 1470 cfg = &dinfo->cfg; 1471 1472 switch (which) { 1473 case PCI_IVAR_ETHADDR: 1474 /* 1475 * The generic accessor doesn't deal with failure, so 1476 * we set the return value, then return an error. 1477 */ 1478 *((uint8_t **) result) = NULL; 1479 return (EINVAL); 1480 case PCI_IVAR_SUBVENDOR: 1481 *result = cfg->subvendor; 1482 break; 1483 case PCI_IVAR_SUBDEVICE: 1484 *result = cfg->subdevice; 1485 break; 1486 case PCI_IVAR_VENDOR: 1487 *result = cfg->vendor; 1488 break; 1489 case PCI_IVAR_DEVICE: 1490 *result = cfg->device; 1491 break; 1492 case PCI_IVAR_DEVID: 1493 *result = (cfg->device << 16) | cfg->vendor; 1494 break; 1495 case PCI_IVAR_CLASS: 1496 *result = cfg->baseclass; 1497 break; 1498 case PCI_IVAR_SUBCLASS: 1499 *result = cfg->subclass; 1500 break; 1501 case PCI_IVAR_PROGIF: 1502 *result = cfg->progif; 1503 break; 1504 case PCI_IVAR_REVID: 1505 *result = cfg->revid; 1506 break; 1507 case PCI_IVAR_INTPIN: 1508 *result = cfg->intpin; 1509 break; 1510 case PCI_IVAR_IRQ: 1511 *result = cfg->intline; 1512 break; 1513 case PCI_IVAR_BUS: 1514 *result = cfg->bus; 1515 break; 1516 case PCI_IVAR_SLOT: 1517 *result = cfg->slot; 1518 break; 1519 case PCI_IVAR_FUNCTION: 1520 *result = cfg->func; 1521 break; 1522 default: 1523 return (ENOENT); 1524 } 1525 return (0); 1526} 1527 1528int 1529pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1530{ 1531 struct pci_devinfo *dinfo; 1532 1533 dinfo = device_get_ivars(child); 1534 1535 switch (which) { 1536 case PCI_IVAR_INTPIN: 1537 dinfo->cfg.intpin = value; 1538 return (0); 1539 case PCI_IVAR_ETHADDR: 1540 case PCI_IVAR_SUBVENDOR: 1541 case PCI_IVAR_SUBDEVICE: 1542 case PCI_IVAR_VENDOR: 1543 case PCI_IVAR_DEVICE: 1544 case PCI_IVAR_DEVID: 1545 case PCI_IVAR_CLASS: 1546 case PCI_IVAR_SUBCLASS: 1547 case PCI_IVAR_PROGIF: 1548 case PCI_IVAR_REVID: 1549 case PCI_IVAR_IRQ: 1550 case PCI_IVAR_BUS: 1551 case PCI_IVAR_SLOT: 1552 case PCI_IVAR_FUNCTION: 1553 return (EINVAL); /* disallow for now */ 1554 1555 default: 1556 return (ENOENT); 1557 } 1558} 1559 1560 1561#include "opt_ddb.h" 1562#ifdef DDB 1563#include <ddb/ddb.h> 1564#include <sys/cons.h> 1565 1566/* 1567 * List resources based on pci map registers, used for within ddb 1568 */ 1569 1570DB_SHOW_COMMAND(pciregs, db_pci_dump) 1571{ 1572 struct pci_devinfo *dinfo; 1573 struct devlist *devlist_head; 1574 struct pci_conf *p; 1575 const char *name; 1576 int i, error, none_count, quit; 1577 1578 none_count = 0; 1579 /* get the head of the device queue */ 1580 devlist_head = &pci_devq; 1581 1582 /* 1583 * Go through the list of devices and print out devices 1584 */ 1585 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1586 for (error = 0, i = 0, quit = 0, 1587 dinfo = STAILQ_FIRST(devlist_head); 1588 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1589 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1590 1591 /* Populate pd_name and pd_unit */ 1592 name = NULL; 1593 if (dinfo->cfg.dev) 1594 name = device_get_name(dinfo->cfg.dev); 1595 1596 p = &dinfo->conf; 1597 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1598 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1599 (name && *name) ? name : "none", 1600 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1601 none_count++, 1602 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1603 p->pc_sel.pc_func, (p->pc_class << 16) | 1604 (p->pc_subclass << 8) | p->pc_progif, 1605 (p->pc_subdevice << 16) | p->pc_subvendor, 1606 (p->pc_device << 16) | p->pc_vendor, 1607 p->pc_revid, p->pc_hdr); 1608 } 1609} 1610#endif /* DDB */ 1611 1612static struct resource * 1613pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1614 u_long start, u_long end, u_long count, u_int flags) 1615{ 1616 struct pci_devinfo *dinfo = device_get_ivars(child); 1617 struct resource_list *rl = &dinfo->resources; 1618 struct resource_list_entry *rle; 1619 struct resource *res; 1620 uint32_t map, testval; 1621 int mapsize; 1622 1623 /* 1624 * Weed out the bogons, and figure out how large the BAR/map 1625 * is. Bars that read back 0 here are bogus and unimplemented. 1626 * Note: atapci in legacy mode are special and handled elsewhere 1627 * in the code. If you have a atapci device in legacy mode and 1628 * it fails here, that other code is broken. 1629 */ 1630 res = NULL; 1631 map = pci_read_config(child, *rid, 4); 1632 pci_write_config(child, *rid, 0xffffffff, 4); 1633 testval = pci_read_config(child, *rid, 4); 1634 if (pci_mapbase(testval) == 0) 1635 goto out; 1636 if (pci_maptype(testval) & PCI_MAPMEM) { 1637 if (type != SYS_RES_MEMORY) { 1638 if (bootverbose) 1639 device_printf(child, 1640 "rid %#x is memory, requested %d\n", 1641 *rid, type); 1642 goto out; 1643 } 1644 } else { 1645 if (type != SYS_RES_IOPORT) { 1646 if (bootverbose) 1647 device_printf(child, 1648 "rid %#x is ioport, requested %d\n", 1649 *rid, type); 1650 goto out; 1651 } 1652 } 1653 /* 1654 * For real BARs, we need to override the size that 1655 * the driver requests, because that's what the BAR 1656 * actually uses and we would otherwise have a 1657 * situation where we might allocate the excess to 1658 * another driver, which won't work. 1659 */ 1660 mapsize = pci_mapsize(testval); 1661 count = 1 << mapsize; 1662 if (RF_ALIGNMENT(flags) < mapsize) 1663 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1664 1665 /* 1666 * Allocate enough resource, and then write back the 1667 * appropriate bar for that resource. 1668 */ 1669 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1670 start, end, count, flags); 1671 if (res == NULL) { 1672 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1673 count, *rid, type); 1674 goto out; 1675 } 1676 resource_list_add(rl, type, *rid, start, end, count); 1677 rle = resource_list_find(rl, type, *rid); 1678 if (rle == NULL) 1679 panic("pci_alloc_map: unexpectedly can't find resource."); 1680 rle->res = res; 1681 if (bootverbose) 1682 device_printf(child, 1683 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1684 count, *rid, type, rman_get_start(res)); 1685 map = rman_get_start(res); 1686out:; 1687 pci_write_config(child, *rid, map, 4); 1688 return (res); 1689} 1690 1691 1692struct resource * 1693pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1694 u_long start, u_long end, u_long count, u_int flags) 1695{ 1696 struct pci_devinfo *dinfo = device_get_ivars(child); 1697 struct resource_list *rl = &dinfo->resources; 1698 struct resource_list_entry *rle; 1699 pcicfgregs *cfg = &dinfo->cfg; 1700 1701 /* 1702 * Perform lazy resource allocation 1703 */ 1704 if (device_get_parent(child) == dev) { 1705 switch (type) { 1706 case SYS_RES_IRQ: 1707 /* 1708 * If the child device doesn't have an 1709 * interrupt routed and is deserving of an 1710 * interrupt, try to assign it one. 1711 */ 1712 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1713 (cfg->intpin != 0)) { 1714 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1715 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1716 pci_write_config(child, PCIR_INTLINE, 1717 cfg->intline, 1); 1718 resource_list_add(rl, SYS_RES_IRQ, 0, 1719 cfg->intline, cfg->intline, 1); 1720 } 1721 } 1722 break; 1723 case SYS_RES_IOPORT: 1724 case SYS_RES_MEMORY: 1725 if (*rid < PCIR_BAR(cfg->nummaps)) { 1726 /* 1727 * Enable the I/O mode. We should 1728 * also be assigning resources too 1729 * when none are present. The 1730 * resource_list_alloc kind of sorta does 1731 * this... 1732 */ 1733 if (PCI_ENABLE_IO(dev, child, type)) 1734 return (NULL); 1735 } 1736 rle = resource_list_find(rl, type, *rid); 1737 if (rle == NULL) 1738 return (pci_alloc_map(dev, child, type, rid, 1739 start, end, count, flags)); 1740 break; 1741 } 1742 /* 1743 * If we've already allocated the resource, then 1744 * return it now. But first we may need to activate 1745 * it, since we don't allocate the resource as active 1746 * above. Normally this would be done down in the 1747 * nexus, but since we short-circuit that path we have 1748 * to do its job here. Not sure if we should free the 1749 * resource if it fails to activate. 1750 */ 1751 rle = resource_list_find(rl, type, *rid); 1752 if (rle != NULL && rle->res != NULL) { 1753 if (bootverbose) 1754 device_printf(child, 1755 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1756 rman_get_size(rle->res), *rid, type, 1757 rman_get_start(rle->res)); 1758 if ((flags & RF_ACTIVE) && 1759 bus_generic_activate_resource(dev, child, type, 1760 *rid, rle->res) != 0) 1761 return NULL; 1762 return (rle->res); 1763 } 1764 } 1765 return (resource_list_alloc(rl, dev, child, type, rid, 1766 start, end, count, flags)); 1767} 1768 1769void 1770pci_delete_resource(device_t dev, device_t child, int type, int rid) 1771{ 1772 struct pci_devinfo *dinfo; 1773 struct resource_list *rl; 1774 struct resource_list_entry *rle; 1775 1776 if (device_get_parent(child) != dev) 1777 return; 1778 1779 dinfo = device_get_ivars(child); 1780 rl = &dinfo->resources; 1781 rle = resource_list_find(rl, type, rid); 1782 if (rle) { 1783 if (rle->res) { 1784 if (rman_get_device(rle->res) != dev || 1785 rman_get_flags(rle->res) & RF_ACTIVE) { 1786 device_printf(dev, "delete_resource: " 1787 "Resource still owned by child, oops. " 1788 "(type=%d, rid=%d, addr=%lx)\n", 1789 rle->type, rle->rid, 1790 rman_get_start(rle->res)); 1791 return; 1792 } 1793 bus_release_resource(dev, type, rid, rle->res); 1794 } 1795 resource_list_delete(rl, type, rid); 1796 } 1797 /* 1798 * Why do we turn off the PCI configuration BAR when we delete a 1799 * resource? -- imp 1800 */ 1801 pci_write_config(child, rid, 0, 4); 1802 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1803} 1804 1805struct resource_list * 1806pci_get_resource_list (device_t dev, device_t child) 1807{ 1808 struct pci_devinfo *dinfo = device_get_ivars(child); 1809 1810 return (&dinfo->resources); 1811} 1812 1813uint32_t 1814pci_read_config_method(device_t dev, device_t child, int reg, int width) 1815{ 1816 struct pci_devinfo *dinfo = device_get_ivars(child); 1817 pcicfgregs *cfg = &dinfo->cfg; 1818 1819 return (PCIB_READ_CONFIG(device_get_parent(dev), 1820 cfg->bus, cfg->slot, cfg->func, reg, width)); 1821} 1822 1823void 1824pci_write_config_method(device_t dev, device_t child, int reg, 1825 uint32_t val, int width) 1826{ 1827 struct pci_devinfo *dinfo = device_get_ivars(child); 1828 pcicfgregs *cfg = &dinfo->cfg; 1829 1830 PCIB_WRITE_CONFIG(device_get_parent(dev), 1831 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1832} 1833 1834int 1835pci_child_location_str_method(device_t dev, device_t child, char *buf, 1836 size_t buflen) 1837{ 1838 1839 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1840 pci_get_function(child)); 1841 return (0); 1842} 1843 1844int 1845pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1846 size_t buflen) 1847{ 1848 struct pci_devinfo *dinfo; 1849 pcicfgregs *cfg; 1850 1851 dinfo = device_get_ivars(child); 1852 cfg = &dinfo->cfg; 1853 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1854 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1855 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1856 cfg->progif); 1857 return (0); 1858} 1859 1860int 1861pci_assign_interrupt_method(device_t dev, device_t child) 1862{ 1863 struct pci_devinfo *dinfo = device_get_ivars(child); 1864 pcicfgregs *cfg = &dinfo->cfg; 1865 1866 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1867 cfg->intpin)); 1868} 1869 1870static int 1871pci_modevent(module_t mod, int what, void *arg) 1872{ 1873 static struct cdev *pci_cdev; 1874 1875 switch (what) { 1876 case MOD_LOAD: 1877 STAILQ_INIT(&pci_devq); 1878 pci_generation = 0; 1879 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1880 "pci"); 1881 pci_load_vendor_data(); 1882 break; 1883 1884 case MOD_UNLOAD: 1885 destroy_dev(pci_cdev); 1886 break; 1887 } 1888 1889 return (0); 1890} 1891 1892void 1893pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1894{ 1895 int i; 1896 1897 /* 1898 * Only do header type 0 devices. Type 1 devices are bridges, 1899 * which we know need special treatment. Type 2 devices are 1900 * cardbus bridges which also require special treatment. 1901 * Other types are unknown, and we err on the side of safety 1902 * by ignoring them. 1903 */ 1904 if (dinfo->cfg.hdrtype != 0) 1905 return; 1906 1907 /* 1908 * Restore the device to full power mode. We must do this 1909 * before we restore the registers because moving from D3 to 1910 * D0 will cause the chip's BARs and some other registers to 1911 * be reset to some unknown power on reset values. Cut down 1912 * the noise on boot by doing nothing if we are already in 1913 * state D0. 1914 */ 1915 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1916 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1917 } 1918 for (i = 0; i < dinfo->cfg.nummaps; i++) 1919 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1920 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1921 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1922 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1923 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1924 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1925 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1926 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1927 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1928 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1929 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1930} 1931 1932void 1933pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1934{ 1935 int i; 1936 uint32_t cls; 1937 int ps; 1938 1939 /* 1940 * Only do header type 0 devices. Type 1 devices are bridges, which 1941 * we know need special treatment. Type 2 devices are cardbus bridges 1942 * which also require special treatment. Other types are unknown, and 1943 * we err on the side of safety by ignoring them. Powering down 1944 * bridges should not be undertaken lightly. 1945 */ 1946 if (dinfo->cfg.hdrtype != 0) 1947 return; 1948 for (i = 0; i < dinfo->cfg.nummaps; i++) 1949 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1950 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1951 1952 /* 1953 * Some drivers apparently write to these registers w/o updating our 1954 * cached copy. No harm happens if we update the copy, so do so here 1955 * so we can restore them. The COMMAND register is modified by the 1956 * bus w/o updating the cache. This should represent the normally 1957 * writable portion of the 'defined' part of type 0 headers. In 1958 * theory we also need to save/restore the PCI capability structures 1959 * we know about, but apart from power we don't know any that are 1960 * writable. 1961 */ 1962 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1963 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1964 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1965 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1966 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1967 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1968 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1969 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1970 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1971 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1972 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1973 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1974 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1975 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1976 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1977 1978 /* 1979 * don't set the state for display devices, base peripherals and 1980 * memory devices since bad things happen when they are powered down. 1981 * We should (a) have drivers that can easily detach and (b) use 1982 * generic drivers for these devices so that some device actually 1983 * attaches. We need to make sure that when we implement (a) we don't 1984 * power the device down on a reattach. 1985 */ 1986 cls = pci_get_class(dev); 1987 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY && 1988 cls != PCIC_BASEPERIPH) { 1989 /* 1990 * PCI spec says we can only go into D3 state from D0 state. 1991 * Transition from D[12] into D0 before going to D3 state. 1992 */ 1993 ps = pci_get_powerstate(dev); 1994 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1995 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1996 } 1997 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1998 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1999 } 2000 } 2001} 2002