pci.c revision 142735
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 142735 2005-02-28 01:14:15Z imp $"); 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63#if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65#include <contrib/dev/acpica/acpi.h> 66#include "acpi_if.h" 67#else 68#define ACPI_PWR_FOR_SLEEP(x, y, z) 69#endif 70 71static uint32_t pci_mapbase(unsigned mapreg); 72static int pci_maptype(unsigned mapreg); 73static int pci_mapsize(unsigned testval); 74static int pci_maprange(unsigned mapreg); 75static void pci_fixancient(pcicfgregs *cfg); 76 77static int pci_porten(device_t pcib, int b, int s, int f); 78static int pci_memen(device_t pcib, int b, int s, int f); 79static int pci_add_map(device_t pcib, device_t bus, device_t dev, 80 int b, int s, int f, int reg, 81 struct resource_list *rl); 82static void pci_add_resources(device_t pcib, device_t bus, 83 device_t dev); 84static int pci_probe(device_t dev); 85static int pci_attach(device_t dev); 86static void pci_load_vendor_data(void); 87static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89static char *pci_describe_device(device_t dev); 90static int pci_modevent(module_t mod, int what, void *arg); 91static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 95static device_method_t pci_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pci_probe), 98 DEVMETHOD(device_attach, pci_attach), 99 DEVMETHOD(device_shutdown, bus_generic_shutdown), 100 DEVMETHOD(device_suspend, pci_suspend), 101 DEVMETHOD(device_resume, pci_resume), 102 103 /* Bus interface */ 104 DEVMETHOD(bus_print_child, pci_print_child), 105 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 106 DEVMETHOD(bus_read_ivar, pci_read_ivar), 107 DEVMETHOD(bus_write_ivar, pci_write_ivar), 108 DEVMETHOD(bus_driver_added, pci_driver_added), 109 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 110 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 111 112 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 113 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 114 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 115 DEVMETHOD(bus_delete_resource, pci_delete_resource), 116 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 117 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 118 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 119 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 120 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 121 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 122 123 /* PCI interface */ 124 DEVMETHOD(pci_read_config, pci_read_config_method), 125 DEVMETHOD(pci_write_config, pci_write_config_method), 126 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 127 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 128 DEVMETHOD(pci_enable_io, pci_enable_io_method), 129 DEVMETHOD(pci_disable_io, pci_disable_io_method), 130 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 131 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 132 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 133 134 { 0, 0 } 135}; 136 137DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 138 139devclass_t pci_devclass; 140DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 141MODULE_VERSION(pci, 1); 142 143static char *pci_vendordata; 144static size_t pci_vendordata_size; 145 146 147struct pci_quirk { 148 uint32_t devid; /* Vendor/device of the card */ 149 int type; 150#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 151 int arg1; 152 int arg2; 153}; 154 155struct pci_quirk pci_quirks[] = { 156 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 157 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 158 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 159 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 160 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 161 162 { 0 } 163}; 164 165/* map register information */ 166#define PCI_MAPMEM 0x01 /* memory map */ 167#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 168#define PCI_MAPPORT 0x04 /* port map */ 169 170struct devlist pci_devq; 171uint32_t pci_generation; 172uint32_t pci_numdevs = 0; 173 174/* sysctl vars */ 175SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 176 177static int pci_enable_io_modes = 1; 178TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 179SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 180 &pci_enable_io_modes, 1, 181 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 182enable these bits correctly. We'd like to do this all the time, but there\n\ 183are some peripherals that this causes problems with."); 184 185static int pci_do_powerstate = 1; 186TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 187SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 188 &pci_do_powerstate, 1, 189 "Power down devices into D3 state when no driver attaches to them.\n\ 190Otherwise, leave the device in D0 state when no driver attaches."); 191 192/* Find a device_t by bus/slot/function */ 193 194device_t 195pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 196{ 197 struct pci_devinfo *dinfo; 198 199 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 200 if ((dinfo->cfg.bus == bus) && 201 (dinfo->cfg.slot == slot) && 202 (dinfo->cfg.func == func)) { 203 return (dinfo->cfg.dev); 204 } 205 } 206 207 return (NULL); 208} 209 210/* Find a device_t by vendor/device ID */ 211 212device_t 213pci_find_device(uint16_t vendor, uint16_t device) 214{ 215 struct pci_devinfo *dinfo; 216 217 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 218 if ((dinfo->cfg.vendor == vendor) && 219 (dinfo->cfg.device == device)) { 220 return (dinfo->cfg.dev); 221 } 222 } 223 224 return (NULL); 225} 226 227/* return base address of memory or port map */ 228 229static uint32_t 230pci_mapbase(unsigned mapreg) 231{ 232 int mask = 0x03; 233 if ((mapreg & 0x01) == 0) 234 mask = 0x0f; 235 return (mapreg & ~mask); 236} 237 238/* return map type of memory or port map */ 239 240static int 241pci_maptype(unsigned mapreg) 242{ 243 static uint8_t maptype[0x10] = { 244 PCI_MAPMEM, PCI_MAPPORT, 245 PCI_MAPMEM, 0, 246 PCI_MAPMEM, PCI_MAPPORT, 247 0, 0, 248 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 249 PCI_MAPMEM|PCI_MAPMEMP, 0, 250 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 251 0, 0, 252 }; 253 254 return maptype[mapreg & 0x0f]; 255} 256 257/* return log2 of map size decoded for memory or port map */ 258 259static int 260pci_mapsize(unsigned testval) 261{ 262 int ln2size; 263 264 testval = pci_mapbase(testval); 265 ln2size = 0; 266 if (testval != 0) { 267 while ((testval & 1) == 0) 268 { 269 ln2size++; 270 testval >>= 1; 271 } 272 } 273 return (ln2size); 274} 275 276/* return log2 of address range supported by map register */ 277 278static int 279pci_maprange(unsigned mapreg) 280{ 281 int ln2range = 0; 282 switch (mapreg & 0x07) { 283 case 0x00: 284 case 0x01: 285 case 0x05: 286 ln2range = 32; 287 break; 288 case 0x02: 289 ln2range = 20; 290 break; 291 case 0x04: 292 ln2range = 64; 293 break; 294 } 295 return (ln2range); 296} 297 298/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 299 300static void 301pci_fixancient(pcicfgregs *cfg) 302{ 303 if (cfg->hdrtype != 0) 304 return; 305 306 /* PCI to PCI bridges use header type 1 */ 307 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 308 cfg->hdrtype = 1; 309} 310 311/* extract header type specific config data */ 312 313static void 314pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 315{ 316#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 317 switch (cfg->hdrtype) { 318 case 0: 319 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 320 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 321 cfg->nummaps = PCI_MAXMAPS_0; 322 break; 323 case 1: 324 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 325 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 326 cfg->nummaps = PCI_MAXMAPS_1; 327 break; 328 case 2: 329 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 330 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 331 cfg->nummaps = PCI_MAXMAPS_2; 332 break; 333 } 334#undef REG 335} 336 337/* read configuration header into pcicfgregs structure */ 338 339struct pci_devinfo * 340pci_read_device(device_t pcib, int b, int s, int f, size_t size) 341{ 342#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 343 pcicfgregs *cfg = NULL; 344 struct pci_devinfo *devlist_entry; 345 struct devlist *devlist_head; 346 347 devlist_head = &pci_devq; 348 349 devlist_entry = NULL; 350 351 if (REG(PCIR_DEVVENDOR, 4) != -1) { 352 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 353 if (devlist_entry == NULL) 354 return (NULL); 355 356 cfg = &devlist_entry->cfg; 357 358 cfg->bus = b; 359 cfg->slot = s; 360 cfg->func = f; 361 cfg->vendor = REG(PCIR_VENDOR, 2); 362 cfg->device = REG(PCIR_DEVICE, 2); 363 cfg->cmdreg = REG(PCIR_COMMAND, 2); 364 cfg->statreg = REG(PCIR_STATUS, 2); 365 cfg->baseclass = REG(PCIR_CLASS, 1); 366 cfg->subclass = REG(PCIR_SUBCLASS, 1); 367 cfg->progif = REG(PCIR_PROGIF, 1); 368 cfg->revid = REG(PCIR_REVID, 1); 369 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 370 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 371 cfg->lattimer = REG(PCIR_LATTIMER, 1); 372 cfg->intpin = REG(PCIR_INTPIN, 1); 373 cfg->intline = REG(PCIR_INTLINE, 1); 374 375 cfg->mingnt = REG(PCIR_MINGNT, 1); 376 cfg->maxlat = REG(PCIR_MAXLAT, 1); 377 378 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 379 cfg->hdrtype &= ~PCIM_MFDEV; 380 381 pci_fixancient(cfg); 382 pci_hdrtypedata(pcib, b, s, f, cfg); 383 384 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 385 pci_read_extcap(pcib, cfg); 386 387 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 388 389 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 390 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 391 devlist_entry->conf.pc_sel.pc_func = cfg->func; 392 devlist_entry->conf.pc_hdr = cfg->hdrtype; 393 394 devlist_entry->conf.pc_subvendor = cfg->subvendor; 395 devlist_entry->conf.pc_subdevice = cfg->subdevice; 396 devlist_entry->conf.pc_vendor = cfg->vendor; 397 devlist_entry->conf.pc_device = cfg->device; 398 399 devlist_entry->conf.pc_class = cfg->baseclass; 400 devlist_entry->conf.pc_subclass = cfg->subclass; 401 devlist_entry->conf.pc_progif = cfg->progif; 402 devlist_entry->conf.pc_revid = cfg->revid; 403 404 pci_numdevs++; 405 pci_generation++; 406 } 407 return (devlist_entry); 408#undef REG 409} 410 411static void 412pci_read_extcap(device_t pcib, pcicfgregs *cfg) 413{ 414#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 415 int ptr, nextptr, ptrptr; 416 417 switch (cfg->hdrtype & PCIM_HDRTYPE) { 418 case 0: 419 ptrptr = PCIR_CAP_PTR; 420 break; 421 case 2: 422 ptrptr = 0x14; 423 break; 424 default: 425 return; /* no extended capabilities support */ 426 } 427 nextptr = REG(ptrptr, 1); /* sanity check? */ 428 429 /* 430 * Read capability entries. 431 */ 432 while (nextptr != 0) { 433 /* Sanity check */ 434 if (nextptr > 255) { 435 printf("illegal PCI extended capability offset %d\n", 436 nextptr); 437 return; 438 } 439 /* Find the next entry */ 440 ptr = nextptr; 441 nextptr = REG(ptr + 1, 1); 442 443 /* Process this entry */ 444 switch (REG(ptr, 1)) { 445 case PCIY_PMG: /* PCI power management */ 446 if (cfg->pp.pp_cap == 0) { 447 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 448 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 449 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 450 if ((nextptr - ptr) > PCIR_POWER_DATA) 451 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 452 } 453 break; 454 case PCIY_MSI: /* PCI MSI */ 455 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 456 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 457 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 458 else 459 cfg->msi.msi_data = PCIR_MSI_DATA; 460 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 461 PCIM_MSICTRL_MMC_MASK)>>1); 462 default: 463 break; 464 } 465 } 466#undef REG 467} 468 469/* free pcicfgregs structure and all depending data structures */ 470 471int 472pci_freecfg(struct pci_devinfo *dinfo) 473{ 474 struct devlist *devlist_head; 475 476 devlist_head = &pci_devq; 477 478 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 479 free(dinfo, M_DEVBUF); 480 481 /* increment the generation count */ 482 pci_generation++; 483 484 /* we're losing one device */ 485 pci_numdevs--; 486 return (0); 487} 488 489/* 490 * PCI power manangement 491 */ 492int 493pci_set_powerstate_method(device_t dev, device_t child, int state) 494{ 495 struct pci_devinfo *dinfo = device_get_ivars(child); 496 pcicfgregs *cfg = &dinfo->cfg; 497 uint16_t status; 498 int result, oldstate, highest, delay; 499 500 if (cfg->pp.pp_cap == 0) 501 return (EOPNOTSUPP); 502 503 /* 504 * Optimize a no state change request away. While it would be OK to 505 * write to the hardware in theory, some devices have shown odd 506 * behavior when going from D3 -> D3. 507 */ 508 oldstate = pci_get_powerstate(child); 509 if (oldstate == state) 510 return (0); 511 512 /* 513 * The PCI power management specification states that after a state 514 * transition between PCI power states, system software must 515 * guarantee a minimal delay before the function accesses the device. 516 * Compute the worst case delay that we need to guarantee before we 517 * access the device. Many devices will be responsive much more 518 * quickly than this delay, but there are some that don't respond 519 * instantly to state changes. Transitions to/from D3 state require 520 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 521 * is done below with DELAY rather than a sleeper function because 522 * this function can be called from contexts where we cannot sleep. 523 */ 524 highest = (oldstate > state) ? oldstate : state; 525 if (highest == PCI_POWERSTATE_D3) 526 delay = 10000; 527 else if (highest == PCI_POWERSTATE_D2) 528 delay = 200; 529 else 530 delay = 0; 531 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 532 & ~PCIM_PSTAT_DMASK; 533 result = 0; 534 switch (state) { 535 case PCI_POWERSTATE_D0: 536 status |= PCIM_PSTAT_D0; 537 break; 538 case PCI_POWERSTATE_D1: 539 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 540 return (EOPNOTSUPP); 541 status |= PCIM_PSTAT_D1; 542 break; 543 case PCI_POWERSTATE_D2: 544 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 545 return (EOPNOTSUPP); 546 status |= PCIM_PSTAT_D2; 547 break; 548 case PCI_POWERSTATE_D3: 549 status |= PCIM_PSTAT_D3; 550 break; 551 default: 552 return (EINVAL); 553 } 554 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 555 if (delay) 556 DELAY(delay); 557 return (0); 558} 559 560int 561pci_get_powerstate_method(device_t dev, device_t child) 562{ 563 struct pci_devinfo *dinfo = device_get_ivars(child); 564 pcicfgregs *cfg = &dinfo->cfg; 565 uint16_t status; 566 int result; 567 568 if (cfg->pp.pp_cap != 0) { 569 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 570 switch (status & PCIM_PSTAT_DMASK) { 571 case PCIM_PSTAT_D0: 572 result = PCI_POWERSTATE_D0; 573 break; 574 case PCIM_PSTAT_D1: 575 result = PCI_POWERSTATE_D1; 576 break; 577 case PCIM_PSTAT_D2: 578 result = PCI_POWERSTATE_D2; 579 break; 580 case PCIM_PSTAT_D3: 581 result = PCI_POWERSTATE_D3; 582 break; 583 default: 584 result = PCI_POWERSTATE_UNKNOWN; 585 break; 586 } 587 } else { 588 /* No support, device is always at D0 */ 589 result = PCI_POWERSTATE_D0; 590 } 591 return (result); 592} 593 594/* 595 * Some convenience functions for PCI device drivers. 596 */ 597 598static __inline void 599pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 600{ 601 uint16_t command; 602 603 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 604 command |= bit; 605 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 606} 607 608static __inline void 609pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 610{ 611 uint16_t command; 612 613 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 614 command &= ~bit; 615 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 616} 617 618int 619pci_enable_busmaster_method(device_t dev, device_t child) 620{ 621 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 622 return (0); 623} 624 625int 626pci_disable_busmaster_method(device_t dev, device_t child) 627{ 628 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 629 return (0); 630} 631 632int 633pci_enable_io_method(device_t dev, device_t child, int space) 634{ 635 uint16_t command; 636 uint16_t bit; 637 char *error; 638 639 bit = 0; 640 error = NULL; 641 642 switch(space) { 643 case SYS_RES_IOPORT: 644 bit = PCIM_CMD_PORTEN; 645 error = "port"; 646 break; 647 case SYS_RES_MEMORY: 648 bit = PCIM_CMD_MEMEN; 649 error = "memory"; 650 break; 651 default: 652 return (EINVAL); 653 } 654 pci_set_command_bit(dev, child, bit); 655 /* Some devices seem to need a brief stall here, what do to? */ 656 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 657 if (command & bit) 658 return (0); 659 device_printf(child, "failed to enable %s mapping!\n", error); 660 return (ENXIO); 661} 662 663int 664pci_disable_io_method(device_t dev, device_t child, int space) 665{ 666 uint16_t command; 667 uint16_t bit; 668 char *error; 669 670 bit = 0; 671 error = NULL; 672 673 switch(space) { 674 case SYS_RES_IOPORT: 675 bit = PCIM_CMD_PORTEN; 676 error = "port"; 677 break; 678 case SYS_RES_MEMORY: 679 bit = PCIM_CMD_MEMEN; 680 error = "memory"; 681 break; 682 default: 683 return (EINVAL); 684 } 685 pci_clear_command_bit(dev, child, bit); 686 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 687 if (command & bit) { 688 device_printf(child, "failed to disable %s mapping!\n", error); 689 return (ENXIO); 690 } 691 return (0); 692} 693 694/* 695 * New style pci driver. Parent device is either a pci-host-bridge or a 696 * pci-pci-bridge. Both kinds are represented by instances of pcib. 697 */ 698 699void 700pci_print_verbose(struct pci_devinfo *dinfo) 701{ 702 if (bootverbose) { 703 pcicfgregs *cfg = &dinfo->cfg; 704 705 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 706 cfg->vendor, cfg->device, cfg->revid); 707 printf("\tbus=%d, slot=%d, func=%d\n", 708 cfg->bus, cfg->slot, cfg->func); 709 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 710 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 711 cfg->mfdev); 712 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 713 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 714 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 715 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 716 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 717 if (cfg->intpin > 0) 718 printf("\tintpin=%c, irq=%d\n", 719 cfg->intpin +'a' -1, cfg->intline); 720 if (cfg->pp.pp_cap) { 721 uint16_t status; 722 723 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 724 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 725 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 726 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 727 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 728 status & PCIM_PSTAT_DMASK); 729 } 730 if (cfg->msi.msi_data) { 731 int ctrl; 732 733 ctrl = cfg->msi.msi_ctrl; 734 printf("\tMSI supports %d message%s%s%s\n", 735 cfg->msi.msi_msgnum, 736 (cfg->msi.msi_msgnum == 1) ? "" : "s", 737 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 738 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 739 } 740 } 741} 742 743static int 744pci_porten(device_t pcib, int b, int s, int f) 745{ 746 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 747 & PCIM_CMD_PORTEN) != 0; 748} 749 750static int 751pci_memen(device_t pcib, int b, int s, int f) 752{ 753 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 754 & PCIM_CMD_MEMEN) != 0; 755} 756 757/* 758 * Add a resource based on a pci map register. Return 1 if the map 759 * register is a 32bit map register or 2 if it is a 64bit register. 760 */ 761static int 762pci_add_map(device_t pcib, device_t bus, device_t dev, 763 int b, int s, int f, int reg, struct resource_list *rl) 764{ 765 uint32_t map; 766 uint64_t base; 767 uint64_t start, end, count; 768 uint8_t ln2size; 769 uint8_t ln2range; 770 uint32_t testval; 771 uint16_t cmd; 772 int type; 773 774 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 775 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 776 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 777 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 778 779 if (pci_maptype(map) & PCI_MAPMEM) 780 type = SYS_RES_MEMORY; 781 else 782 type = SYS_RES_IOPORT; 783 ln2size = pci_mapsize(testval); 784 ln2range = pci_maprange(testval); 785 base = pci_mapbase(map); 786 787 /* 788 * For I/O registers, if bottom bit is set, and the next bit up 789 * isn't clear, we know we have a BAR that doesn't conform to the 790 * spec, so ignore it. Also, sanity check the size of the data 791 * areas to the type of memory involved. Memory must be at least 792 * 32 bytes in size, while I/O ranges must be at least 4. 793 */ 794 if ((testval & 0x1) == 0x1 && 795 (testval & 0x2) != 0) 796 return (1); 797 if ((type == SYS_RES_MEMORY && ln2size < 5) || 798 (type == SYS_RES_IOPORT && ln2size < 2)) 799 return (1); 800 801 if (ln2range == 64) 802 /* Read the other half of a 64bit map register */ 803 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 804 805 if (bootverbose) { 806 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 807 reg, pci_maptype(map), ln2range, 808 (unsigned int) base, ln2size); 809 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 810 printf(", port disabled\n"); 811 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 812 printf(", memory disabled\n"); 813 else 814 printf(", enabled\n"); 815 } 816 817 /* 818 * This code theoretically does the right thing, but has 819 * undesirable side effects in some cases where peripherals 820 * respond oddly to having these bits enabled. Let the user 821 * be able to turn them off (since pci_enable_io_modes is 1 by 822 * default). 823 */ 824 if (pci_enable_io_modes) { 825 /* Turn on resources that have been left off by a lazy BIOS */ 826 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 827 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 828 cmd |= PCIM_CMD_PORTEN; 829 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 830 } 831 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 832 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 833 cmd |= PCIM_CMD_MEMEN; 834 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 835 } 836 } else { 837 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 838 return (1); 839 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 840 return (1); 841 } 842 /* 843 * If base is 0, then we have problems. It is best to ignore 844 * such entires for the moment. These will be allocated later if 845 * the driver specifically requests them. 846 */ 847 if (base == 0) 848 return 1; 849 850 start = base; 851 end = base + (1 << ln2size) - 1; 852 count = 1 << ln2size; 853 resource_list_add(rl, type, reg, start, end, count); 854 855 /* 856 * Not quite sure what to do on failure of allocating the resource 857 * since I can postulate several right answers. 858 */ 859 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 860 return ((ln2range == 64) ? 2 : 1); 861} 862 863/* 864 * For ATA devices we need to decide early what addressing mode to use. 865 * Legacy demands that the primary and secondary ATA ports sits on the 866 * same addresses that old ISA hardware did. This dictates that we use 867 * those addresses and ignore the BAR's if we cannot set PCI native 868 * addressing mode. 869 */ 870static void 871pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 872 int s, int f, struct resource_list *rl) 873{ 874 int rid, type, progif; 875#if 0 876 /* if this device supports PCI native addressing use it */ 877 progif = pci_read_config(dev, PCIR_PROGIF, 1); 878 if ((progif & 0x8a) == 0x8a) { 879 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 880 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 881 printf("Trying ATA native PCI addressing mode\n"); 882 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 883 } 884 } 885#endif 886 progif = pci_read_config(dev, PCIR_PROGIF, 1); 887 type = SYS_RES_IOPORT; 888 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 889 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 890 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 891 } 892 else { 893 rid = PCIR_BAR(0); 894 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 895 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 896 rid = PCIR_BAR(1); 897 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 898 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 899 } 900 if (progif & PCIP_STORAGE_IDE_MODESEC) { 901 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 902 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 903 } 904 else { 905 rid = PCIR_BAR(2); 906 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 907 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 908 rid = PCIR_BAR(3); 909 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 910 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 911 } 912 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 913} 914 915static void 916pci_add_resources(device_t pcib, device_t bus, device_t dev) 917{ 918 struct pci_devinfo *dinfo = device_get_ivars(dev); 919 pcicfgregs *cfg = &dinfo->cfg; 920 struct resource_list *rl = &dinfo->resources; 921 struct pci_quirk *q; 922 int b, i, irq, f, s; 923 924 b = cfg->bus; 925 s = cfg->slot; 926 f = cfg->func; 927 928 /* ATA devices needs special map treatment */ 929 if ((pci_get_class(dev) == PCIC_STORAGE) && 930 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 931 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 932 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 933 else 934 for (i = 0; i < cfg->nummaps;) 935 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 936 rl); 937 938 for (q = &pci_quirks[0]; q->devid; q++) { 939 if (q->devid == ((cfg->device << 16) | cfg->vendor) 940 && q->type == PCI_QUIRK_MAP_REG) 941 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 942 } 943 944 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 945#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 946 defined(__arm__) || defined(__alpha__) 947 /* 948 * Try to re-route interrupts. Sometimes the BIOS or 949 * firmware may leave bogus values in these registers. 950 * If the re-route fails, then just stick with what we 951 * have. 952 */ 953 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 954 if (PCI_INTERRUPT_VALID(irq)) { 955 pci_write_config(dev, PCIR_INTLINE, irq, 1); 956 cfg->intline = irq; 957 } else 958#endif 959 irq = cfg->intline; 960 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 961 } 962} 963 964void 965pci_add_children(device_t dev, int busno, size_t dinfo_size) 966{ 967#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 968 device_t pcib = device_get_parent(dev); 969 struct pci_devinfo *dinfo; 970 int maxslots; 971 int s, f, pcifunchigh; 972 uint8_t hdrtype; 973 974 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 975 ("dinfo_size too small")); 976 maxslots = PCIB_MAXSLOTS(pcib); 977 for (s = 0; s <= maxslots; s++) { 978 pcifunchigh = 0; 979 f = 0; 980 hdrtype = REG(PCIR_HDRTYPE, 1); 981 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 982 continue; 983 if (hdrtype & PCIM_MFDEV) 984 pcifunchigh = PCI_FUNCMAX; 985 for (f = 0; f <= pcifunchigh; f++) { 986 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 987 if (dinfo != NULL) { 988 pci_add_child(dev, dinfo); 989 } 990 } 991 } 992#undef REG 993} 994 995void 996pci_add_child(device_t bus, struct pci_devinfo *dinfo) 997{ 998 device_t pcib; 999 1000 pcib = device_get_parent(bus); 1001 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1002 device_set_ivars(dinfo->cfg.dev, dinfo); 1003 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1004 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1005 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1006 pci_print_verbose(dinfo); 1007} 1008 1009static int 1010pci_probe(device_t dev) 1011{ 1012 1013 device_set_desc(dev, "PCI bus"); 1014 1015 /* Allow other subclasses to override this driver. */ 1016 return (-1000); 1017} 1018 1019static int 1020pci_attach(device_t dev) 1021{ 1022 int busno; 1023 1024 /* 1025 * Since there can be multiple independantly numbered PCI 1026 * busses on some large alpha systems, we can't use the unit 1027 * number to decide what bus we are probing. We ask the parent 1028 * pcib what our bus number is. 1029 */ 1030 busno = pcib_get_bus(dev); 1031 if (bootverbose) 1032 device_printf(dev, "physical bus=%d\n", busno); 1033 1034 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1035 1036 return (bus_generic_attach(dev)); 1037} 1038 1039int 1040pci_suspend(device_t dev) 1041{ 1042 int dstate, error, i, numdevs; 1043 device_t acpi_dev, child, *devlist; 1044 struct pci_devinfo *dinfo; 1045 1046 /* 1047 * Save the PCI configuration space for each child and set the 1048 * device in the appropriate power state for this sleep state. 1049 */ 1050 acpi_dev = NULL; 1051 if (pci_do_powerstate) 1052 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1053 device_get_children(dev, &devlist, &numdevs); 1054 for (i = 0; i < numdevs; i++) { 1055 child = devlist[i]; 1056 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1057 pci_cfg_save(child, dinfo, 0); 1058 } 1059 1060 /* Suspend devices before potentially powering them down. */ 1061 error = bus_generic_suspend(dev); 1062 if (error) 1063 return (error); 1064 1065 /* 1066 * Always set the device to D3. If ACPI suggests a different 1067 * power state, use it instead. If ACPI is not present, the 1068 * firmware is responsible for managing device power. Skip 1069 * children who aren't attached since they are powered down 1070 * separately. Only manage type 0 devices for now. 1071 */ 1072 for (i = 0; acpi_dev && i < numdevs; i++) { 1073 child = devlist[i]; 1074 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1075 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1076 dstate = PCI_POWERSTATE_D3; 1077 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1078 pci_set_powerstate(child, dstate); 1079 } 1080 } 1081 free(devlist, M_TEMP); 1082 return (0); 1083} 1084 1085int 1086pci_resume(device_t dev) 1087{ 1088 int i, numdevs; 1089 device_t acpi_dev, child, *devlist; 1090 struct pci_devinfo *dinfo; 1091 1092 /* 1093 * Set each child to D0 and restore its PCI configuration space. 1094 */ 1095 acpi_dev = NULL; 1096 if (pci_do_powerstate) 1097 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1098 device_get_children(dev, &devlist, &numdevs); 1099 for (i = 0; i < numdevs; i++) { 1100 /* 1101 * Notify ACPI we're going to D0 but ignore the result. If 1102 * ACPI is not present, the firmware is responsible for 1103 * managing device power. Only manage type 0 devices for now. 1104 */ 1105 child = devlist[i]; 1106 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1107 if (acpi_dev && device_is_attached(child) && 1108 dinfo->cfg.hdrtype == 0) { 1109 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1110 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1111 } 1112 1113 /* Now the device is powered up, restore its config space. */ 1114 pci_cfg_restore(child, dinfo); 1115 } 1116 free(devlist, M_TEMP); 1117 return (bus_generic_resume(dev)); 1118} 1119 1120static void 1121pci_load_vendor_data(void) 1122{ 1123 caddr_t vendordata, info; 1124 1125 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1126 info = preload_search_info(vendordata, MODINFO_ADDR); 1127 pci_vendordata = *(char **)info; 1128 info = preload_search_info(vendordata, MODINFO_SIZE); 1129 pci_vendordata_size = *(size_t *)info; 1130 /* terminate the database */ 1131 pci_vendordata[pci_vendordata_size] = '\n'; 1132 } 1133} 1134 1135void 1136pci_driver_added(device_t dev, driver_t *driver) 1137{ 1138 int numdevs; 1139 device_t *devlist; 1140 device_t child; 1141 struct pci_devinfo *dinfo; 1142 int i; 1143 1144 if (bootverbose) 1145 device_printf(dev, "driver added\n"); 1146 DEVICE_IDENTIFY(driver, dev); 1147 device_get_children(dev, &devlist, &numdevs); 1148 for (i = 0; i < numdevs; i++) { 1149 child = devlist[i]; 1150 if (device_get_state(child) != DS_NOTPRESENT) 1151 continue; 1152 dinfo = device_get_ivars(child); 1153 pci_print_verbose(dinfo); 1154/*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */ 1155 if (bootverbose) 1156 printf("pci%d:%d:%d: reprobing on driver added\n", 1157 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1158 pci_cfg_restore(child, dinfo); 1159 if (device_probe_and_attach(child) != 0) 1160 pci_cfg_save(child, dinfo, 1); 1161 } 1162 free(devlist, M_TEMP); 1163} 1164 1165int 1166pci_print_child(device_t dev, device_t child) 1167{ 1168 struct pci_devinfo *dinfo; 1169 struct resource_list *rl; 1170 int retval = 0; 1171 1172 dinfo = device_get_ivars(child); 1173 rl = &dinfo->resources; 1174 1175 retval += bus_print_child_header(dev, child); 1176 1177 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1178 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1179 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1180 if (device_get_flags(dev)) 1181 retval += printf(" flags %#x", device_get_flags(dev)); 1182 1183 retval += printf(" at device %d.%d", pci_get_slot(child), 1184 pci_get_function(child)); 1185 1186 retval += bus_print_child_footer(dev, child); 1187 1188 return (retval); 1189} 1190 1191static struct 1192{ 1193 int class; 1194 int subclass; 1195 char *desc; 1196} pci_nomatch_tab[] = { 1197 {PCIC_OLD, -1, "old"}, 1198 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1199 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1200 {PCIC_STORAGE, -1, "mass storage"}, 1201 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1202 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1203 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1204 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1205 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1206 {PCIC_NETWORK, -1, "network"}, 1207 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1208 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1209 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1210 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1211 {PCIC_DISPLAY, -1, "display"}, 1212 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1213 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1214 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1215 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1216 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1217 {PCIC_MEMORY, -1, "memory"}, 1218 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1219 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1220 {PCIC_BRIDGE, -1, "bridge"}, 1221 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1222 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1223 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1224 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1225 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1226 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1227 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1228 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1229 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1230 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1231 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1232 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1233 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1234 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1235 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1236 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1237 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1238 {PCIC_INPUTDEV, -1, "input device"}, 1239 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1240 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1241 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1242 {PCIC_DOCKING, -1, "docking station"}, 1243 {PCIC_PROCESSOR, -1, "processor"}, 1244 {PCIC_SERIALBUS, -1, "serial bus"}, 1245 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1246 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1247 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1248 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1249 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1250 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1251 {0, 0, NULL} 1252}; 1253 1254void 1255pci_probe_nomatch(device_t dev, device_t child) 1256{ 1257 int i; 1258 char *cp, *scp, *device; 1259 1260 /* 1261 * Look for a listing for this device in a loaded device database. 1262 */ 1263 if ((device = pci_describe_device(child)) != NULL) { 1264 device_printf(dev, "<%s>", device); 1265 free(device, M_DEVBUF); 1266 } else { 1267 /* 1268 * Scan the class/subclass descriptions for a general 1269 * description. 1270 */ 1271 cp = "unknown"; 1272 scp = NULL; 1273 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1274 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1275 if (pci_nomatch_tab[i].subclass == -1) { 1276 cp = pci_nomatch_tab[i].desc; 1277 } else if (pci_nomatch_tab[i].subclass == 1278 pci_get_subclass(child)) { 1279 scp = pci_nomatch_tab[i].desc; 1280 } 1281 } 1282 } 1283 device_printf(dev, "<%s%s%s>", 1284 cp ? cp : "", 1285 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1286 scp ? scp : ""); 1287 } 1288 printf(" at device %d.%d (no driver attached)\n", 1289 pci_get_slot(child), pci_get_function(child)); 1290 if (pci_do_powerstate) 1291 pci_cfg_save(child, 1292 (struct pci_devinfo *) device_get_ivars(child), 1); 1293 return; 1294} 1295 1296/* 1297 * Parse the PCI device database, if loaded, and return a pointer to a 1298 * description of the device. 1299 * 1300 * The database is flat text formatted as follows: 1301 * 1302 * Any line not in a valid format is ignored. 1303 * Lines are terminated with newline '\n' characters. 1304 * 1305 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1306 * the vendor name. 1307 * 1308 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1309 * - devices cannot be listed without a corresponding VENDOR line. 1310 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1311 * another TAB, then the device name. 1312 */ 1313 1314/* 1315 * Assuming (ptr) points to the beginning of a line in the database, 1316 * return the vendor or device and description of the next entry. 1317 * The value of (vendor) or (device) inappropriate for the entry type 1318 * is set to -1. Returns nonzero at the end of the database. 1319 * 1320 * Note that this is slightly unrobust in the face of corrupt data; 1321 * we attempt to safeguard against this by spamming the end of the 1322 * database with a newline when we initialise. 1323 */ 1324static int 1325pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1326{ 1327 char *cp = *ptr; 1328 int left; 1329 1330 *device = -1; 1331 *vendor = -1; 1332 **desc = '\0'; 1333 for (;;) { 1334 left = pci_vendordata_size - (cp - pci_vendordata); 1335 if (left <= 0) { 1336 *ptr = cp; 1337 return(1); 1338 } 1339 1340 /* vendor entry? */ 1341 if (*cp != '\t' && 1342 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1343 break; 1344 /* device entry? */ 1345 if (*cp == '\t' && 1346 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1347 break; 1348 1349 /* skip to next line */ 1350 while (*cp != '\n' && left > 0) { 1351 cp++; 1352 left--; 1353 } 1354 if (*cp == '\n') { 1355 cp++; 1356 left--; 1357 } 1358 } 1359 /* skip to next line */ 1360 while (*cp != '\n' && left > 0) { 1361 cp++; 1362 left--; 1363 } 1364 if (*cp == '\n' && left > 0) 1365 cp++; 1366 *ptr = cp; 1367 return(0); 1368} 1369 1370static char * 1371pci_describe_device(device_t dev) 1372{ 1373 int vendor, device; 1374 char *desc, *vp, *dp, *line; 1375 1376 desc = vp = dp = NULL; 1377 1378 /* 1379 * If we have no vendor data, we can't do anything. 1380 */ 1381 if (pci_vendordata == NULL) 1382 goto out; 1383 1384 /* 1385 * Scan the vendor data looking for this device 1386 */ 1387 line = pci_vendordata; 1388 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1389 goto out; 1390 for (;;) { 1391 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1392 goto out; 1393 if (vendor == pci_get_vendor(dev)) 1394 break; 1395 } 1396 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1397 goto out; 1398 for (;;) { 1399 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1400 *dp = 0; 1401 break; 1402 } 1403 if (vendor != -1) { 1404 *dp = 0; 1405 break; 1406 } 1407 if (device == pci_get_device(dev)) 1408 break; 1409 } 1410 if (dp[0] == '\0') 1411 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1412 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1413 NULL) 1414 sprintf(desc, "%s, %s", vp, dp); 1415 out: 1416 if (vp != NULL) 1417 free(vp, M_DEVBUF); 1418 if (dp != NULL) 1419 free(dp, M_DEVBUF); 1420 return(desc); 1421} 1422 1423int 1424pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1425{ 1426 struct pci_devinfo *dinfo; 1427 pcicfgregs *cfg; 1428 1429 dinfo = device_get_ivars(child); 1430 cfg = &dinfo->cfg; 1431 1432 switch (which) { 1433 case PCI_IVAR_ETHADDR: 1434 /* 1435 * The generic accessor doesn't deal with failure, so 1436 * we set the return value, then return an error. 1437 */ 1438 *((uint8_t **) result) = NULL; 1439 return (EINVAL); 1440 case PCI_IVAR_SUBVENDOR: 1441 *result = cfg->subvendor; 1442 break; 1443 case PCI_IVAR_SUBDEVICE: 1444 *result = cfg->subdevice; 1445 break; 1446 case PCI_IVAR_VENDOR: 1447 *result = cfg->vendor; 1448 break; 1449 case PCI_IVAR_DEVICE: 1450 *result = cfg->device; 1451 break; 1452 case PCI_IVAR_DEVID: 1453 *result = (cfg->device << 16) | cfg->vendor; 1454 break; 1455 case PCI_IVAR_CLASS: 1456 *result = cfg->baseclass; 1457 break; 1458 case PCI_IVAR_SUBCLASS: 1459 *result = cfg->subclass; 1460 break; 1461 case PCI_IVAR_PROGIF: 1462 *result = cfg->progif; 1463 break; 1464 case PCI_IVAR_REVID: 1465 *result = cfg->revid; 1466 break; 1467 case PCI_IVAR_INTPIN: 1468 *result = cfg->intpin; 1469 break; 1470 case PCI_IVAR_IRQ: 1471 *result = cfg->intline; 1472 break; 1473 case PCI_IVAR_BUS: 1474 *result = cfg->bus; 1475 break; 1476 case PCI_IVAR_SLOT: 1477 *result = cfg->slot; 1478 break; 1479 case PCI_IVAR_FUNCTION: 1480 *result = cfg->func; 1481 break; 1482 default: 1483 return (ENOENT); 1484 } 1485 return (0); 1486} 1487 1488int 1489pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1490{ 1491 struct pci_devinfo *dinfo; 1492 1493 dinfo = device_get_ivars(child); 1494 1495 switch (which) { 1496 case PCI_IVAR_INTPIN: 1497 dinfo->cfg.intpin = value; 1498 return (0); 1499 case PCI_IVAR_ETHADDR: 1500 case PCI_IVAR_SUBVENDOR: 1501 case PCI_IVAR_SUBDEVICE: 1502 case PCI_IVAR_VENDOR: 1503 case PCI_IVAR_DEVICE: 1504 case PCI_IVAR_DEVID: 1505 case PCI_IVAR_CLASS: 1506 case PCI_IVAR_SUBCLASS: 1507 case PCI_IVAR_PROGIF: 1508 case PCI_IVAR_REVID: 1509 case PCI_IVAR_IRQ: 1510 case PCI_IVAR_BUS: 1511 case PCI_IVAR_SLOT: 1512 case PCI_IVAR_FUNCTION: 1513 return (EINVAL); /* disallow for now */ 1514 1515 default: 1516 return (ENOENT); 1517 } 1518} 1519 1520 1521#include "opt_ddb.h" 1522#ifdef DDB 1523#include <ddb/ddb.h> 1524#include <sys/cons.h> 1525 1526/* 1527 * List resources based on pci map registers, used for within ddb 1528 */ 1529 1530DB_SHOW_COMMAND(pciregs, db_pci_dump) 1531{ 1532 struct pci_devinfo *dinfo; 1533 struct devlist *devlist_head; 1534 struct pci_conf *p; 1535 const char *name; 1536 int i, error, none_count, quit; 1537 1538 none_count = 0; 1539 /* get the head of the device queue */ 1540 devlist_head = &pci_devq; 1541 1542 /* 1543 * Go through the list of devices and print out devices 1544 */ 1545 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1546 for (error = 0, i = 0, quit = 0, 1547 dinfo = STAILQ_FIRST(devlist_head); 1548 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1549 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1550 1551 /* Populate pd_name and pd_unit */ 1552 name = NULL; 1553 if (dinfo->cfg.dev) 1554 name = device_get_name(dinfo->cfg.dev); 1555 1556 p = &dinfo->conf; 1557 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1558 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1559 (name && *name) ? name : "none", 1560 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1561 none_count++, 1562 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1563 p->pc_sel.pc_func, (p->pc_class << 16) | 1564 (p->pc_subclass << 8) | p->pc_progif, 1565 (p->pc_subdevice << 16) | p->pc_subvendor, 1566 (p->pc_device << 16) | p->pc_vendor, 1567 p->pc_revid, p->pc_hdr); 1568 } 1569} 1570#endif /* DDB */ 1571 1572static struct resource * 1573pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1574 u_long start, u_long end, u_long count, u_int flags) 1575{ 1576 struct pci_devinfo *dinfo = device_get_ivars(child); 1577 struct resource_list *rl = &dinfo->resources; 1578 struct resource_list_entry *rle; 1579 struct resource *res; 1580 uint32_t map, testval; 1581 int mapsize; 1582 1583 /* 1584 * Weed out the bogons, and figure out how large the BAR/map 1585 * is. Bars that read back 0 here are bogus and unimplemented. 1586 * Note: atapci in legacy mode are special and handled elsewhere 1587 * in the code. If you have a atapci device in legacy mode and 1588 * it fails here, that other code is broken. 1589 */ 1590 res = NULL; 1591 map = pci_read_config(child, *rid, 4); 1592 pci_write_config(child, *rid, 0xffffffff, 4); 1593 testval = pci_read_config(child, *rid, 4); 1594 if (testval == 0) 1595 return (NULL); 1596 if (pci_maptype(testval) & PCI_MAPMEM) { 1597 if (type != SYS_RES_MEMORY) { 1598 device_printf(child, 1599 "failed: rid %#x is memory, requested %d\n", 1600 *rid, type); 1601 goto out; 1602 } 1603 } else { 1604 if (type != SYS_RES_IOPORT) { 1605 device_printf(child, 1606 "failed: rid %#x is ioport, requested %d\n", 1607 *rid, type); 1608 goto out; 1609 } 1610 } 1611 /* 1612 * For real BARs, we need to override the size that 1613 * the driver requests, because that's what the BAR 1614 * actually uses and we would otherwise have a 1615 * situation where we might allocate the excess to 1616 * another driver, which won't work. 1617 */ 1618 mapsize = pci_mapsize(testval); 1619 count = 1 << mapsize; 1620 if (RF_ALIGNMENT(flags) < mapsize) 1621 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1622 1623 /* 1624 * Allocate enough resource, and then write back the 1625 * appropriate bar for that resource. 1626 */ 1627 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1628 start, end, count, flags); 1629 if (res == NULL) { 1630 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1631 count, *rid, type); 1632 goto out; 1633 } 1634 resource_list_add(rl, type, *rid, start, end, count); 1635 rle = resource_list_find(rl, type, *rid); 1636 if (rle == NULL) 1637 panic("pci_alloc_map: unexpectedly can't find resource."); 1638 rle->res = res; 1639 if (bootverbose) 1640 device_printf(child, 1641 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1642 count, *rid, type, rman_get_start(res)); 1643 map = rman_get_start(res); 1644out:; 1645 pci_write_config(child, *rid, map, 4); 1646 return (res); 1647} 1648 1649 1650struct resource * 1651pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1652 u_long start, u_long end, u_long count, u_int flags) 1653{ 1654 struct pci_devinfo *dinfo = device_get_ivars(child); 1655 struct resource_list *rl = &dinfo->resources; 1656 struct resource_list_entry *rle; 1657 pcicfgregs *cfg = &dinfo->cfg; 1658 1659 /* 1660 * Perform lazy resource allocation 1661 */ 1662 if (device_get_parent(child) == dev) { 1663 switch (type) { 1664 case SYS_RES_IRQ: 1665 /* 1666 * If the child device doesn't have an 1667 * interrupt routed and is deserving of an 1668 * interrupt, try to assign it one. 1669 */ 1670 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1671 (cfg->intpin != 0)) { 1672 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1673 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1674 pci_write_config(child, PCIR_INTLINE, 1675 cfg->intline, 1); 1676 resource_list_add(rl, SYS_RES_IRQ, 0, 1677 cfg->intline, cfg->intline, 1); 1678 } 1679 } 1680 break; 1681 case SYS_RES_IOPORT: 1682 case SYS_RES_MEMORY: 1683 if (*rid < PCIR_BAR(cfg->nummaps)) { 1684 /* 1685 * Enable the I/O mode. We should 1686 * also be assigning resources too 1687 * when none are present. The 1688 * resource_list_alloc kind of sorta does 1689 * this... 1690 */ 1691 if (PCI_ENABLE_IO(dev, child, type)) 1692 return (NULL); 1693 } 1694 rle = resource_list_find(rl, type, *rid); 1695 if (rle == NULL) 1696 return (pci_alloc_map(dev, child, type, rid, 1697 start, end, count, flags)); 1698 break; 1699 } 1700 /* 1701 * If we've already allocated the resource, then 1702 * return it now. But first we may need to activate 1703 * it, since we don't allocate the resource as active 1704 * above. Normally this would be done down in the 1705 * nexus, but since we short-circuit that path we have 1706 * to do its job here. Not sure if we should free the 1707 * resource if it fails to activate. 1708 */ 1709 rle = resource_list_find(rl, type, *rid); 1710 if (rle != NULL && rle->res != NULL) { 1711 if (bootverbose) 1712 device_printf(child, 1713 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1714 rman_get_size(rle->res), *rid, type, 1715 rman_get_start(rle->res)); 1716 if ((flags & RF_ACTIVE) && 1717 bus_generic_activate_resource(dev, child, type, 1718 *rid, rle->res) != 0) 1719 return NULL; 1720 return (rle->res); 1721 } 1722 } 1723 return (resource_list_alloc(rl, dev, child, type, rid, 1724 start, end, count, flags)); 1725} 1726 1727void 1728pci_delete_resource(device_t dev, device_t child, int type, int rid) 1729{ 1730 struct pci_devinfo *dinfo; 1731 struct resource_list *rl; 1732 struct resource_list_entry *rle; 1733 1734 if (device_get_parent(child) != dev) 1735 return; 1736 1737 dinfo = device_get_ivars(child); 1738 rl = &dinfo->resources; 1739 rle = resource_list_find(rl, type, rid); 1740 if (rle) { 1741 if (rle->res) { 1742 if (rman_get_device(rle->res) != dev || 1743 rman_get_flags(rle->res) & RF_ACTIVE) { 1744 device_printf(dev, "delete_resource: " 1745 "Resource still owned by child, oops. " 1746 "(type=%d, rid=%d, addr=%lx)\n", 1747 rle->type, rle->rid, 1748 rman_get_start(rle->res)); 1749 return; 1750 } 1751 bus_release_resource(dev, type, rid, rle->res); 1752 } 1753 resource_list_delete(rl, type, rid); 1754 } 1755 /* 1756 * Why do we turn off the PCI configuration BAR when we delete a 1757 * resource? -- imp 1758 */ 1759 pci_write_config(child, rid, 0, 4); 1760 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1761} 1762 1763struct resource_list * 1764pci_get_resource_list (device_t dev, device_t child) 1765{ 1766 struct pci_devinfo *dinfo = device_get_ivars(child); 1767 1768 return (&dinfo->resources); 1769} 1770 1771uint32_t 1772pci_read_config_method(device_t dev, device_t child, int reg, int width) 1773{ 1774 struct pci_devinfo *dinfo = device_get_ivars(child); 1775 pcicfgregs *cfg = &dinfo->cfg; 1776 1777 return (PCIB_READ_CONFIG(device_get_parent(dev), 1778 cfg->bus, cfg->slot, cfg->func, reg, width)); 1779} 1780 1781void 1782pci_write_config_method(device_t dev, device_t child, int reg, 1783 uint32_t val, int width) 1784{ 1785 struct pci_devinfo *dinfo = device_get_ivars(child); 1786 pcicfgregs *cfg = &dinfo->cfg; 1787 1788 PCIB_WRITE_CONFIG(device_get_parent(dev), 1789 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1790} 1791 1792int 1793pci_child_location_str_method(device_t dev, device_t child, char *buf, 1794 size_t buflen) 1795{ 1796 1797 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1798 pci_get_function(child)); 1799 return (0); 1800} 1801 1802int 1803pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1804 size_t buflen) 1805{ 1806 struct pci_devinfo *dinfo; 1807 pcicfgregs *cfg; 1808 1809 dinfo = device_get_ivars(child); 1810 cfg = &dinfo->cfg; 1811 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1812 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1813 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1814 cfg->progif); 1815 return (0); 1816} 1817 1818int 1819pci_assign_interrupt_method(device_t dev, device_t child) 1820{ 1821 struct pci_devinfo *dinfo = device_get_ivars(child); 1822 pcicfgregs *cfg = &dinfo->cfg; 1823 1824 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1825 cfg->intpin)); 1826} 1827 1828static int 1829pci_modevent(module_t mod, int what, void *arg) 1830{ 1831 static struct cdev *pci_cdev; 1832 1833 switch (what) { 1834 case MOD_LOAD: 1835 STAILQ_INIT(&pci_devq); 1836 pci_generation = 0; 1837 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1838 "pci"); 1839 pci_load_vendor_data(); 1840 break; 1841 1842 case MOD_UNLOAD: 1843 destroy_dev(pci_cdev); 1844 break; 1845 } 1846 1847 return (0); 1848} 1849 1850void 1851pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1852{ 1853 int i; 1854 1855 /* 1856 * Only do header type 0 devices. Type 1 devices are bridges, 1857 * which we know need special treatment. Type 2 devices are 1858 * cardbus bridges which also require special treatment. 1859 * Other types are unknown, and we err on the side of safety 1860 * by ignoring them. 1861 */ 1862 if (dinfo->cfg.hdrtype != 0) 1863 return; 1864 1865 /* 1866 * Restore the device to full power mode. We must do this 1867 * before we restore the registers because moving from D3 to 1868 * D0 will cause the chip's BARs and some other registers to 1869 * be reset to some unknown power on reset values. Cut down 1870 * the noise on boot by doing nothing if we are already in 1871 * state D0. 1872 */ 1873 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1874 if (bootverbose) 1875 printf( 1876 "pci%d:%d:%d: Transition from D%d to D0\n", 1877 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1878 pci_get_powerstate(dev)); 1879 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1880 } 1881 for (i = 0; i < dinfo->cfg.nummaps; i++) 1882 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1883 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1884 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1885 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1886 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1887 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1888 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1889 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1890 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1891 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1892 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1893} 1894 1895void 1896pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1897{ 1898 int i; 1899 uint32_t cls; 1900 int ps; 1901 1902 /* 1903 * Only do header type 0 devices. Type 1 devices are bridges, which 1904 * we know need special treatment. Type 2 devices are cardbus bridges 1905 * which also require special treatment. Other types are unknown, and 1906 * we err on the side of safety by ignoring them. Powering down 1907 * bridges should not be undertaken lightly. 1908 */ 1909 if (dinfo->cfg.hdrtype != 0) 1910 return; 1911 for (i = 0; i < dinfo->cfg.nummaps; i++) 1912 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1913 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1914 1915 /* 1916 * Some drivers apparently write to these registers w/o updating our 1917 * cached copy. No harm happens if we update the copy, so do so here 1918 * so we can restore them. The COMMAND register is modified by the 1919 * bus w/o updating the cache. This should represent the normally 1920 * writable portion of the 'defined' part of type 0 headers. In 1921 * theory we also need to save/restore the PCI capability structures 1922 * we know about, but apart from power we don't know any that are 1923 * writable. 1924 */ 1925 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1926 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1927 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1928 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1929 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1930 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1931 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1932 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1933 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1934 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1935 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1936 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1937 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1938 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1939 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1940 1941 /* 1942 * don't set the state for display devices, base peripherals and 1943 * memory devices since bad things happen when they are powered down. 1944 * We should (a) have drivers that can easily detach and (b) use 1945 * generic drivers for these devices so that some device actually 1946 * attaches. We need to make sure that when we implement (a) we don't 1947 * power the device down on a reattach. 1948 */ 1949 cls = pci_get_class(dev); 1950 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY && 1951 cls != PCIC_BASEPERIPH) { 1952 /* 1953 * PCI spec says we can only go into D3 state from D0 state. 1954 * Transition from D[12] into D0 before going to D3 state. 1955 */ 1956 ps = pci_get_powerstate(dev); 1957 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1958 if (bootverbose) 1959 printf( 1960 "pci%d:%d:%d: Transition from D%d to D0\n", 1961 dinfo->cfg.bus, dinfo->cfg.slot, 1962 dinfo->cfg.func, ps); 1963 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1964 } 1965 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1966 if (bootverbose) 1967 printf( 1968 "pci%d:%d:%d: Transition from D0 to D3\n", 1969 dinfo->cfg.bus, dinfo->cfg.slot, 1970 dinfo->cfg.func); 1971 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1972 } 1973 } 1974} 1975