pci.c revision 138336
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/pci/pci.c 138336 2004-12-03 08:13:08Z njl $"); 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63#if defined(__i386__) || defined(__amd64__) || defined (__ia64__) 64#include <contrib/dev/acpica/acpi.h> 65#include <dev/acpica/acpivar.h> 66#include "acpi_if.h" 67#else 68#define ACPI_PWR_FOR_SLEEP(x, y, z) 69#endif 70 71static uint32_t pci_mapbase(unsigned mapreg); 72static int pci_maptype(unsigned mapreg); 73static int pci_mapsize(unsigned testval); 74static int pci_maprange(unsigned mapreg); 75static void pci_fixancient(pcicfgregs *cfg); 76 77static int pci_porten(device_t pcib, int b, int s, int f); 78static int pci_memen(device_t pcib, int b, int s, int f); 79static int pci_add_map(device_t pcib, device_t bus, device_t dev, 80 int b, int s, int f, int reg, 81 struct resource_list *rl); 82static void pci_add_resources(device_t pcib, device_t bus, 83 device_t dev); 84static int pci_probe(device_t dev); 85static int pci_attach(device_t dev); 86static void pci_load_vendor_data(void); 87static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89static char *pci_describe_device(device_t dev); 90static int pci_modevent(module_t mod, int what, void *arg); 91static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94static void pci_cfg_restore(device_t, struct pci_devinfo *); 95static void pci_cfg_save(device_t, struct pci_devinfo *, int); 96 97static device_method_t pci_methods[] = { 98 /* Device interface */ 99 DEVMETHOD(device_probe, pci_probe), 100 DEVMETHOD(device_attach, pci_attach), 101 DEVMETHOD(device_shutdown, bus_generic_shutdown), 102 DEVMETHOD(device_suspend, pci_suspend), 103 DEVMETHOD(device_resume, pci_resume), 104 105 /* Bus interface */ 106 DEVMETHOD(bus_print_child, pci_print_child), 107 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 108 DEVMETHOD(bus_read_ivar, pci_read_ivar), 109 DEVMETHOD(bus_write_ivar, pci_write_ivar), 110 DEVMETHOD(bus_driver_added, pci_driver_added), 111 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 112 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 113 114 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 115 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 116 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 117 DEVMETHOD(bus_delete_resource, pci_delete_resource), 118 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 119 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 120 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 121 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 122 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 123 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 124 125 /* PCI interface */ 126 DEVMETHOD(pci_read_config, pci_read_config_method), 127 DEVMETHOD(pci_write_config, pci_write_config_method), 128 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 129 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 130 DEVMETHOD(pci_enable_io, pci_enable_io_method), 131 DEVMETHOD(pci_disable_io, pci_disable_io_method), 132 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 133 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 134 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 135 136 { 0, 0 } 137}; 138 139DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 140 141devclass_t pci_devclass; 142DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 143MODULE_VERSION(pci, 1); 144 145static char *pci_vendordata; 146static size_t pci_vendordata_size; 147 148 149struct pci_quirk { 150 uint32_t devid; /* Vendor/device of the card */ 151 int type; 152#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 153 int arg1; 154 int arg2; 155}; 156 157struct pci_quirk pci_quirks[] = { 158 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 159 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 160 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 161 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 162 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 163 164 { 0 } 165}; 166 167/* map register information */ 168#define PCI_MAPMEM 0x01 /* memory map */ 169#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 170#define PCI_MAPPORT 0x04 /* port map */ 171 172struct devlist pci_devq; 173uint32_t pci_generation; 174uint32_t pci_numdevs = 0; 175 176/* sysctl vars */ 177SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 178 179static int pci_enable_io_modes = 1; 180TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 181SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 182 &pci_enable_io_modes, 1, 183 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 184enable these bits correctly. We'd like to do this all the time, but there\n\ 185are some peripherals that this causes problems with."); 186 187static int pci_do_powerstate = 1; 188TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 189SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 190 &pci_do_powerstate, 1, 191 "Power down devices into D3 state when no driver attaches to them.\n\ 192Otherwise, leave the device in D0 state when no driver attaches."); 193 194/* Find a device_t by bus/slot/function */ 195 196device_t 197pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 198{ 199 struct pci_devinfo *dinfo; 200 201 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 202 if ((dinfo->cfg.bus == bus) && 203 (dinfo->cfg.slot == slot) && 204 (dinfo->cfg.func == func)) { 205 return (dinfo->cfg.dev); 206 } 207 } 208 209 return (NULL); 210} 211 212/* Find a device_t by vendor/device ID */ 213 214device_t 215pci_find_device(uint16_t vendor, uint16_t device) 216{ 217 struct pci_devinfo *dinfo; 218 219 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 220 if ((dinfo->cfg.vendor == vendor) && 221 (dinfo->cfg.device == device)) { 222 return (dinfo->cfg.dev); 223 } 224 } 225 226 return (NULL); 227} 228 229/* return base address of memory or port map */ 230 231static uint32_t 232pci_mapbase(unsigned mapreg) 233{ 234 int mask = 0x03; 235 if ((mapreg & 0x01) == 0) 236 mask = 0x0f; 237 return (mapreg & ~mask); 238} 239 240/* return map type of memory or port map */ 241 242static int 243pci_maptype(unsigned mapreg) 244{ 245 static uint8_t maptype[0x10] = { 246 PCI_MAPMEM, PCI_MAPPORT, 247 PCI_MAPMEM, 0, 248 PCI_MAPMEM, PCI_MAPPORT, 249 0, 0, 250 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 251 PCI_MAPMEM|PCI_MAPMEMP, 0, 252 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 253 0, 0, 254 }; 255 256 return maptype[mapreg & 0x0f]; 257} 258 259/* return log2 of map size decoded for memory or port map */ 260 261static int 262pci_mapsize(unsigned testval) 263{ 264 int ln2size; 265 266 testval = pci_mapbase(testval); 267 ln2size = 0; 268 if (testval != 0) { 269 while ((testval & 1) == 0) 270 { 271 ln2size++; 272 testval >>= 1; 273 } 274 } 275 return (ln2size); 276} 277 278/* return log2 of address range supported by map register */ 279 280static int 281pci_maprange(unsigned mapreg) 282{ 283 int ln2range = 0; 284 switch (mapreg & 0x07) { 285 case 0x00: 286 case 0x01: 287 case 0x05: 288 ln2range = 32; 289 break; 290 case 0x02: 291 ln2range = 20; 292 break; 293 case 0x04: 294 ln2range = 64; 295 break; 296 } 297 return (ln2range); 298} 299 300/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 301 302static void 303pci_fixancient(pcicfgregs *cfg) 304{ 305 if (cfg->hdrtype != 0) 306 return; 307 308 /* PCI to PCI bridges use header type 1 */ 309 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 310 cfg->hdrtype = 1; 311} 312 313/* extract header type specific config data */ 314 315static void 316pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 317{ 318#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 319 switch (cfg->hdrtype) { 320 case 0: 321 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 322 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 323 cfg->nummaps = PCI_MAXMAPS_0; 324 break; 325 case 1: 326 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 327 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 328 cfg->nummaps = PCI_MAXMAPS_1; 329 break; 330 case 2: 331 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 332 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 333 cfg->nummaps = PCI_MAXMAPS_2; 334 break; 335 } 336#undef REG 337} 338 339/* read configuration header into pcicfgregs structure */ 340 341struct pci_devinfo * 342pci_read_device(device_t pcib, int b, int s, int f, size_t size) 343{ 344#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 345 pcicfgregs *cfg = NULL; 346 struct pci_devinfo *devlist_entry; 347 struct devlist *devlist_head; 348 349 devlist_head = &pci_devq; 350 351 devlist_entry = NULL; 352 353 if (REG(PCIR_DEVVENDOR, 4) != -1) { 354 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 355 if (devlist_entry == NULL) 356 return (NULL); 357 358 cfg = &devlist_entry->cfg; 359 360 cfg->bus = b; 361 cfg->slot = s; 362 cfg->func = f; 363 cfg->vendor = REG(PCIR_VENDOR, 2); 364 cfg->device = REG(PCIR_DEVICE, 2); 365 cfg->cmdreg = REG(PCIR_COMMAND, 2); 366 cfg->statreg = REG(PCIR_STATUS, 2); 367 cfg->baseclass = REG(PCIR_CLASS, 1); 368 cfg->subclass = REG(PCIR_SUBCLASS, 1); 369 cfg->progif = REG(PCIR_PROGIF, 1); 370 cfg->revid = REG(PCIR_REVID, 1); 371 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 372 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 373 cfg->lattimer = REG(PCIR_LATTIMER, 1); 374 cfg->intpin = REG(PCIR_INTPIN, 1); 375 cfg->intline = REG(PCIR_INTLINE, 1); 376 377 cfg->mingnt = REG(PCIR_MINGNT, 1); 378 cfg->maxlat = REG(PCIR_MAXLAT, 1); 379 380 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 381 cfg->hdrtype &= ~PCIM_MFDEV; 382 383 pci_fixancient(cfg); 384 pci_hdrtypedata(pcib, b, s, f, cfg); 385 386 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 387 pci_read_extcap(pcib, cfg); 388 389 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 390 391 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 392 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 393 devlist_entry->conf.pc_sel.pc_func = cfg->func; 394 devlist_entry->conf.pc_hdr = cfg->hdrtype; 395 396 devlist_entry->conf.pc_subvendor = cfg->subvendor; 397 devlist_entry->conf.pc_subdevice = cfg->subdevice; 398 devlist_entry->conf.pc_vendor = cfg->vendor; 399 devlist_entry->conf.pc_device = cfg->device; 400 401 devlist_entry->conf.pc_class = cfg->baseclass; 402 devlist_entry->conf.pc_subclass = cfg->subclass; 403 devlist_entry->conf.pc_progif = cfg->progif; 404 devlist_entry->conf.pc_revid = cfg->revid; 405 406 pci_numdevs++; 407 pci_generation++; 408 } 409 return (devlist_entry); 410#undef REG 411} 412 413static void 414pci_read_extcap(device_t pcib, pcicfgregs *cfg) 415{ 416#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 417 int ptr, nextptr, ptrptr; 418 419 switch (cfg->hdrtype & PCIM_HDRTYPE) { 420 case 0: 421 ptrptr = PCIR_CAP_PTR; 422 break; 423 case 2: 424 ptrptr = 0x14; 425 break; 426 default: 427 return; /* no extended capabilities support */ 428 } 429 nextptr = REG(ptrptr, 1); /* sanity check? */ 430 431 /* 432 * Read capability entries. 433 */ 434 while (nextptr != 0) { 435 /* Sanity check */ 436 if (nextptr > 255) { 437 printf("illegal PCI extended capability offset %d\n", 438 nextptr); 439 return; 440 } 441 /* Find the next entry */ 442 ptr = nextptr; 443 nextptr = REG(ptr + 1, 1); 444 445 /* Process this entry */ 446 switch (REG(ptr, 1)) { 447 case PCIY_PMG: /* PCI power management */ 448 if (cfg->pp.pp_cap == 0) { 449 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 450 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 451 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 452 if ((nextptr - ptr) > PCIR_POWER_DATA) 453 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 454 } 455 break; 456 case PCIY_MSI: /* PCI MSI */ 457 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 458 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 459 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 460 else 461 cfg->msi.msi_data = PCIR_MSI_DATA; 462 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 463 PCIM_MSICTRL_MMC_MASK)>>1); 464 default: 465 break; 466 } 467 } 468#undef REG 469} 470 471/* free pcicfgregs structure and all depending data structures */ 472 473int 474pci_freecfg(struct pci_devinfo *dinfo) 475{ 476 struct devlist *devlist_head; 477 478 devlist_head = &pci_devq; 479 480 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 481 free(dinfo, M_DEVBUF); 482 483 /* increment the generation count */ 484 pci_generation++; 485 486 /* we're losing one device */ 487 pci_numdevs--; 488 return (0); 489} 490 491/* 492 * PCI power manangement 493 */ 494int 495pci_set_powerstate_method(device_t dev, device_t child, int state) 496{ 497 struct pci_devinfo *dinfo = device_get_ivars(child); 498 pcicfgregs *cfg = &dinfo->cfg; 499 uint16_t status; 500 int result; 501 502 /* 503 * Dx -> Dx is a nop always. 504 */ 505 if (pci_get_powerstate(child) == state) 506 return (0); 507 508 if (cfg->pp.pp_cap != 0) { 509 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 510 & ~PCIM_PSTAT_DMASK; 511 result = 0; 512 switch (state) { 513 case PCI_POWERSTATE_D0: 514 status |= PCIM_PSTAT_D0; 515 break; 516 case PCI_POWERSTATE_D1: 517 if (cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) { 518 status |= PCIM_PSTAT_D1; 519 } else { 520 result = EOPNOTSUPP; 521 } 522 break; 523 case PCI_POWERSTATE_D2: 524 if (cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) { 525 status |= PCIM_PSTAT_D2; 526 } else { 527 result = EOPNOTSUPP; 528 } 529 break; 530 case PCI_POWERSTATE_D3: 531 status |= PCIM_PSTAT_D3; 532 break; 533 default: 534 result = EINVAL; 535 } 536 if (result == 0) 537 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 538 2); 539 } else { 540 result = ENXIO; 541 } 542 return(result); 543} 544 545int 546pci_get_powerstate_method(device_t dev, device_t child) 547{ 548 struct pci_devinfo *dinfo = device_get_ivars(child); 549 pcicfgregs *cfg = &dinfo->cfg; 550 uint16_t status; 551 int result; 552 553 if (cfg->pp.pp_cap != 0) { 554 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 555 switch (status & PCIM_PSTAT_DMASK) { 556 case PCIM_PSTAT_D0: 557 result = PCI_POWERSTATE_D0; 558 break; 559 case PCIM_PSTAT_D1: 560 result = PCI_POWERSTATE_D1; 561 break; 562 case PCIM_PSTAT_D2: 563 result = PCI_POWERSTATE_D2; 564 break; 565 case PCIM_PSTAT_D3: 566 result = PCI_POWERSTATE_D3; 567 break; 568 default: 569 result = PCI_POWERSTATE_UNKNOWN; 570 break; 571 } 572 } else { 573 /* No support, device is always at D0 */ 574 result = PCI_POWERSTATE_D0; 575 } 576 return(result); 577} 578 579/* 580 * Some convenience functions for PCI device drivers. 581 */ 582 583static __inline void 584pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 585{ 586 uint16_t command; 587 588 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 589 command |= bit; 590 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 591} 592 593static __inline void 594pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 595{ 596 uint16_t command; 597 598 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 599 command &= ~bit; 600 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 601} 602 603int 604pci_enable_busmaster_method(device_t dev, device_t child) 605{ 606 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 607 return (0); 608} 609 610int 611pci_disable_busmaster_method(device_t dev, device_t child) 612{ 613 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 614 return (0); 615} 616 617int 618pci_enable_io_method(device_t dev, device_t child, int space) 619{ 620 uint16_t command; 621 uint16_t bit; 622 char *error; 623 624 bit = 0; 625 error = NULL; 626 627 switch(space) { 628 case SYS_RES_IOPORT: 629 bit = PCIM_CMD_PORTEN; 630 error = "port"; 631 break; 632 case SYS_RES_MEMORY: 633 bit = PCIM_CMD_MEMEN; 634 error = "memory"; 635 break; 636 default: 637 return (EINVAL); 638 } 639 pci_set_command_bit(dev, child, bit); 640 /* Some devices seem to need a brief stall here, what do to? */ 641 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 642 if (command & bit) 643 return (0); 644 device_printf(child, "failed to enable %s mapping!\n", error); 645 return (ENXIO); 646} 647 648int 649pci_disable_io_method(device_t dev, device_t child, int space) 650{ 651 uint16_t command; 652 uint16_t bit; 653 char *error; 654 655 bit = 0; 656 error = NULL; 657 658 switch(space) { 659 case SYS_RES_IOPORT: 660 bit = PCIM_CMD_PORTEN; 661 error = "port"; 662 break; 663 case SYS_RES_MEMORY: 664 bit = PCIM_CMD_MEMEN; 665 error = "memory"; 666 break; 667 default: 668 return (EINVAL); 669 } 670 pci_clear_command_bit(dev, child, bit); 671 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 672 if (command & bit) { 673 device_printf(child, "failed to disable %s mapping!\n", error); 674 return (ENXIO); 675 } 676 return (0); 677} 678 679/* 680 * New style pci driver. Parent device is either a pci-host-bridge or a 681 * pci-pci-bridge. Both kinds are represented by instances of pcib. 682 */ 683 684void 685pci_print_verbose(struct pci_devinfo *dinfo) 686{ 687 if (bootverbose) { 688 pcicfgregs *cfg = &dinfo->cfg; 689 690 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 691 cfg->vendor, cfg->device, cfg->revid); 692 printf("\tbus=%d, slot=%d, func=%d\n", 693 cfg->bus, cfg->slot, cfg->func); 694 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 695 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 696 cfg->mfdev); 697 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 698 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 699 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 700 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 701 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 702 if (cfg->intpin > 0) 703 printf("\tintpin=%c, irq=%d\n", 704 cfg->intpin +'a' -1, cfg->intline); 705 if (cfg->pp.pp_cap) { 706 uint16_t status; 707 708 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 709 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 710 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 711 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 712 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 713 status & PCIM_PSTAT_DMASK); 714 } 715 if (cfg->msi.msi_data) { 716 int ctrl; 717 718 ctrl = cfg->msi.msi_ctrl; 719 printf("\tMSI supports %d message%s%s%s\n", 720 cfg->msi.msi_msgnum, 721 (cfg->msi.msi_msgnum == 1) ? "" : "s", 722 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 723 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 724 } 725 } 726} 727 728static int 729pci_porten(device_t pcib, int b, int s, int f) 730{ 731 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 732 & PCIM_CMD_PORTEN) != 0; 733} 734 735static int 736pci_memen(device_t pcib, int b, int s, int f) 737{ 738 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 739 & PCIM_CMD_MEMEN) != 0; 740} 741 742/* 743 * Add a resource based on a pci map register. Return 1 if the map 744 * register is a 32bit map register or 2 if it is a 64bit register. 745 */ 746static int 747pci_add_map(device_t pcib, device_t bus, device_t dev, 748 int b, int s, int f, int reg, struct resource_list *rl) 749{ 750 uint32_t map; 751 uint64_t base; 752 uint64_t start, end, count; 753 uint8_t ln2size; 754 uint8_t ln2range; 755 uint32_t testval; 756 uint16_t cmd; 757 int type; 758 759 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 760 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 761 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 762 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 763 764 if (pci_maptype(map) & PCI_MAPMEM) 765 type = SYS_RES_MEMORY; 766 else 767 type = SYS_RES_IOPORT; 768 ln2size = pci_mapsize(testval); 769 ln2range = pci_maprange(testval); 770 base = pci_mapbase(map); 771 772 /* 773 * For I/O registers, if bottom bit is set, and the next bit up 774 * isn't clear, we know we have a BAR that doesn't conform to the 775 * spec, so ignore it. Also, sanity check the size of the data 776 * areas to the type of memory involved. Memory must be at least 777 * 32 bytes in size, while I/O ranges must be at least 4. 778 */ 779 if ((testval & 0x1) == 0x1 && 780 (testval & 0x2) != 0) 781 return (1); 782 if ((type == SYS_RES_MEMORY && ln2size < 5) || 783 (type == SYS_RES_IOPORT && ln2size < 2)) 784 return (1); 785 786 if (ln2range == 64) 787 /* Read the other half of a 64bit map register */ 788 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 789 790 if (bootverbose) { 791 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 792 reg, pci_maptype(map), ln2range, 793 (unsigned int) base, ln2size); 794 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 795 printf(", port disabled\n"); 796 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 797 printf(", memory disabled\n"); 798 else 799 printf(", enabled\n"); 800 } 801 802 /* 803 * This code theoretically does the right thing, but has 804 * undesirable side effects in some cases where peripherals 805 * respond oddly to having these bits enabled. Let the user 806 * be able to turn them off (since pci_enable_io_modes is 1 by 807 * default). 808 */ 809 if (pci_enable_io_modes) { 810 /* Turn on resources that have been left off by a lazy BIOS */ 811 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 812 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 813 cmd |= PCIM_CMD_PORTEN; 814 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 815 } 816 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 817 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 818 cmd |= PCIM_CMD_MEMEN; 819 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 820 } 821 } else { 822 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 823 return (1); 824 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 825 return (1); 826 } 827 /* 828 * If base is 0, then we have problems. It is best to ignore 829 * such entires for the moment. These will be allocated later if 830 * the driver specifically requests them. 831 */ 832 if (base == 0) 833 return 1; 834 835 start = base; 836 end = base + (1 << ln2size) - 1; 837 count = 1 << ln2size; 838 resource_list_add(rl, type, reg, start, end, count); 839 840 /* 841 * Not quite sure what to do on failure of allocating the resource 842 * since I can postulate several right answers. 843 */ 844 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 845 return ((ln2range == 64) ? 2 : 1); 846} 847 848/* 849 * For ATA devices we need to decide early what addressing mode to use. 850 * Legacy demands that the primary and secondary ATA ports sits on the 851 * same addresses that old ISA hardware did. This dictates that we use 852 * those addresses and ignore the BAR's if we cannot set PCI native 853 * addressing mode. 854 */ 855static void 856pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 857 int s, int f, struct resource_list *rl) 858{ 859 int rid, type, progif; 860#if 0 861 /* if this device supports PCI native addressing use it */ 862 progif = pci_read_config(dev, PCIR_PROGIF, 1); 863 if ((progif & 0x8a) == 0x8a) { 864 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 865 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 866 printf("Trying ATA native PCI addressing mode\n"); 867 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 868 } 869 } 870#endif 871 progif = pci_read_config(dev, PCIR_PROGIF, 1); 872 type = SYS_RES_IOPORT; 873 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 874 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 875 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 876 } 877 else { 878 rid = PCIR_BAR(0); 879 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 880 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 881 rid = PCIR_BAR(1); 882 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 883 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 884 } 885 if (progif & PCIP_STORAGE_IDE_MODESEC) { 886 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 887 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 888 } 889 else { 890 rid = PCIR_BAR(2); 891 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 892 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 893 rid = PCIR_BAR(3); 894 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 895 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 896 } 897 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 898} 899 900static void 901pci_add_resources(device_t pcib, device_t bus, device_t dev) 902{ 903 struct pci_devinfo *dinfo = device_get_ivars(dev); 904 pcicfgregs *cfg = &dinfo->cfg; 905 struct resource_list *rl = &dinfo->resources; 906 struct pci_quirk *q; 907 int b, i, irq, f, s; 908 909 b = cfg->bus; 910 s = cfg->slot; 911 f = cfg->func; 912 913 /* ATA devices needs special map treatment */ 914 if ((pci_get_class(dev) == PCIC_STORAGE) && 915 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 916 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 917 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 918 else 919 for (i = 0; i < cfg->nummaps;) 920 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 921 rl); 922 923 for (q = &pci_quirks[0]; q->devid; q++) { 924 if (q->devid == ((cfg->device << 16) | cfg->vendor) 925 && q->type == PCI_QUIRK_MAP_REG) 926 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 927 } 928 929 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 930#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 931 defined(__arm__) 932 /* 933 * Try to re-route interrupts. Sometimes the BIOS or 934 * firmware may leave bogus values in these registers. 935 * If the re-route fails, then just stick with what we 936 * have. 937 */ 938 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 939 if (PCI_INTERRUPT_VALID(irq)) { 940 pci_write_config(dev, PCIR_INTLINE, irq, 1); 941 cfg->intline = irq; 942 } else 943#endif 944 irq = cfg->intline; 945 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 946 } 947} 948 949void 950pci_add_children(device_t dev, int busno, size_t dinfo_size) 951{ 952#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 953 device_t pcib = device_get_parent(dev); 954 struct pci_devinfo *dinfo; 955 int maxslots; 956 int s, f, pcifunchigh; 957 uint8_t hdrtype; 958 959 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 960 ("dinfo_size too small")); 961 maxslots = PCIB_MAXSLOTS(pcib); 962 for (s = 0; s <= maxslots; s++) { 963 pcifunchigh = 0; 964 f = 0; 965 hdrtype = REG(PCIR_HDRTYPE, 1); 966 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 967 continue; 968 if (hdrtype & PCIM_MFDEV) 969 pcifunchigh = PCI_FUNCMAX; 970 for (f = 0; f <= pcifunchigh; f++) { 971 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 972 if (dinfo != NULL) { 973 pci_add_child(dev, dinfo); 974 } 975 } 976 } 977#undef REG 978} 979 980void 981pci_add_child(device_t bus, struct pci_devinfo *dinfo) 982{ 983 device_t pcib; 984 985 pcib = device_get_parent(bus); 986 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 987 device_set_ivars(dinfo->cfg.dev, dinfo); 988 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 989 pci_cfg_restore(dinfo->cfg.dev, dinfo); 990 pci_add_resources(pcib, bus, dinfo->cfg.dev); 991 pci_print_verbose(dinfo); 992} 993 994static int 995pci_probe(device_t dev) 996{ 997 998 device_set_desc(dev, "PCI bus"); 999 1000 /* Allow other subclasses to override this driver. */ 1001 return (-1000); 1002} 1003 1004static int 1005pci_attach(device_t dev) 1006{ 1007 int busno; 1008 1009 /* 1010 * Since there can be multiple independantly numbered PCI 1011 * busses on some large alpha systems, we can't use the unit 1012 * number to decide what bus we are probing. We ask the parent 1013 * pcib what our bus number is. 1014 */ 1015 busno = pcib_get_bus(dev); 1016 if (bootverbose) 1017 device_printf(dev, "physical bus=%d\n", busno); 1018 1019 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1020 1021 return (bus_generic_attach(dev)); 1022} 1023 1024int 1025pci_suspend(device_t dev) 1026{ 1027 int dstate, error, i, numdevs; 1028 device_t acpi_dev, child, *devlist; 1029 struct pci_devinfo *dinfo; 1030 1031 /* 1032 * Save the PCI configuration space for each child and set the 1033 * device in the appropriate power state for this sleep state. 1034 */ 1035 acpi_dev = NULL; 1036 if (pci_do_powerstate) 1037 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1038 device_get_children(dev, &devlist, &numdevs); 1039 for (i = 0; i < numdevs; i++) { 1040 child = devlist[i]; 1041 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1042 pci_cfg_save(child, dinfo, 0); 1043 } 1044 1045 /* Suspend devices before potentially powering them down. */ 1046 error = bus_generic_suspend(dev); 1047 if (error) 1048 return (error); 1049 1050 /* 1051 * Always set the device to D3. If ACPI suggests a different 1052 * power state, use it instead. If ACPI is not present, the 1053 * firmware is responsible for managing device power. Skip 1054 * children who aren't attached since they are powered down 1055 * separately. Only manage type 0 devices for now. 1056 */ 1057 for (i = 0; acpi_dev && i < numdevs; i++) { 1058 child = devlist[i]; 1059 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1060 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1061 dstate = PCI_POWERSTATE_D3; 1062 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1063 pci_set_powerstate(child, dstate); 1064 } 1065 } 1066 free(devlist, M_TEMP); 1067 return (0); 1068} 1069 1070int 1071pci_resume(device_t dev) 1072{ 1073 int i, numdevs; 1074 device_t acpi_dev, child, *devlist; 1075 struct pci_devinfo *dinfo; 1076 1077 /* 1078 * Set each child to D0 and restore its PCI configuration space. 1079 */ 1080 acpi_dev = NULL; 1081 if (pci_do_powerstate) 1082 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1083 device_get_children(dev, &devlist, &numdevs); 1084 for (i = 0; i < numdevs; i++) { 1085 /* 1086 * Notify ACPI we're going to D0 but ignore the result. If 1087 * ACPI is not present, the firmware is responsible for 1088 * managing device power. Only manage type 0 devices for now. 1089 */ 1090 child = devlist[i]; 1091 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1092 if (acpi_dev && device_is_attached(child) && 1093 dinfo->cfg.hdrtype == 0) { 1094 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1095 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1096 } 1097 1098 /* Now the device is powered up, restore its config space. */ 1099 pci_cfg_restore(child, dinfo); 1100 } 1101 free(devlist, M_TEMP); 1102 return (bus_generic_resume(dev)); 1103} 1104 1105static void 1106pci_load_vendor_data(void) 1107{ 1108 caddr_t vendordata, info; 1109 1110 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1111 info = preload_search_info(vendordata, MODINFO_ADDR); 1112 pci_vendordata = *(char **)info; 1113 info = preload_search_info(vendordata, MODINFO_SIZE); 1114 pci_vendordata_size = *(size_t *)info; 1115 /* terminate the database */ 1116 pci_vendordata[pci_vendordata_size] = '\n'; 1117 } 1118} 1119 1120void 1121pci_driver_added(device_t dev, driver_t *driver) 1122{ 1123 int numdevs; 1124 device_t *devlist; 1125 device_t child; 1126 struct pci_devinfo *dinfo; 1127 int i; 1128 1129 if (bootverbose) 1130 device_printf(dev, "driver added\n"); 1131 DEVICE_IDENTIFY(driver, dev); 1132 device_get_children(dev, &devlist, &numdevs); 1133 for (i = 0; i < numdevs; i++) { 1134 child = devlist[i]; 1135 if (device_get_state(child) != DS_NOTPRESENT) 1136 continue; 1137 dinfo = device_get_ivars(child); 1138 pci_print_verbose(dinfo); 1139/*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */ 1140 if (bootverbose) 1141 printf("pci%d:%d:%d: reprobing on driver added\n", 1142 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1143 pci_cfg_restore(child, dinfo); 1144 if (device_probe_and_attach(child) != 0) 1145 pci_cfg_save(child, dinfo, 1); 1146 } 1147 free(devlist, M_TEMP); 1148} 1149 1150int 1151pci_print_child(device_t dev, device_t child) 1152{ 1153 struct pci_devinfo *dinfo; 1154 struct resource_list *rl; 1155 int retval = 0; 1156 1157 dinfo = device_get_ivars(child); 1158 rl = &dinfo->resources; 1159 1160 retval += bus_print_child_header(dev, child); 1161 1162 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1163 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1164 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1165 if (device_get_flags(dev)) 1166 retval += printf(" flags %#x", device_get_flags(dev)); 1167 1168 retval += printf(" at device %d.%d", pci_get_slot(child), 1169 pci_get_function(child)); 1170 1171 retval += bus_print_child_footer(dev, child); 1172 1173 return (retval); 1174} 1175 1176static struct 1177{ 1178 int class; 1179 int subclass; 1180 char *desc; 1181} pci_nomatch_tab[] = { 1182 {PCIC_OLD, -1, "old"}, 1183 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1184 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1185 {PCIC_STORAGE, -1, "mass storage"}, 1186 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1187 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1188 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1189 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1190 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1191 {PCIC_NETWORK, -1, "network"}, 1192 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1193 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1194 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1195 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1196 {PCIC_DISPLAY, -1, "display"}, 1197 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1198 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1199 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1200 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1201 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1202 {PCIC_MEMORY, -1, "memory"}, 1203 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1204 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1205 {PCIC_BRIDGE, -1, "bridge"}, 1206 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1207 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1208 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1209 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1210 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1211 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1212 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1213 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1214 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1215 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1216 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1217 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1218 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1219 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1220 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1221 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1222 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1223 {PCIC_INPUTDEV, -1, "input device"}, 1224 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1225 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1226 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1227 {PCIC_DOCKING, -1, "docking station"}, 1228 {PCIC_PROCESSOR, -1, "processor"}, 1229 {PCIC_SERIALBUS, -1, "serial bus"}, 1230 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1231 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1232 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1233 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1234 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1235 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1236 {0, 0, NULL} 1237}; 1238 1239void 1240pci_probe_nomatch(device_t dev, device_t child) 1241{ 1242 int i; 1243 char *cp, *scp, *device; 1244 1245 /* 1246 * Look for a listing for this device in a loaded device database. 1247 */ 1248 if ((device = pci_describe_device(child)) != NULL) { 1249 device_printf(dev, "<%s>", device); 1250 free(device, M_DEVBUF); 1251 } else { 1252 /* 1253 * Scan the class/subclass descriptions for a general 1254 * description. 1255 */ 1256 cp = "unknown"; 1257 scp = NULL; 1258 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1259 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1260 if (pci_nomatch_tab[i].subclass == -1) { 1261 cp = pci_nomatch_tab[i].desc; 1262 } else if (pci_nomatch_tab[i].subclass == 1263 pci_get_subclass(child)) { 1264 scp = pci_nomatch_tab[i].desc; 1265 } 1266 } 1267 } 1268 device_printf(dev, "<%s%s%s>", 1269 cp ? cp : "", 1270 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1271 scp ? scp : ""); 1272 } 1273 printf(" at device %d.%d (no driver attached)\n", 1274 pci_get_slot(child), pci_get_function(child)); 1275 if (pci_do_powerstate) 1276 pci_cfg_save(child, 1277 (struct pci_devinfo *) device_get_ivars(child), 1); 1278 return; 1279} 1280 1281/* 1282 * Parse the PCI device database, if loaded, and return a pointer to a 1283 * description of the device. 1284 * 1285 * The database is flat text formatted as follows: 1286 * 1287 * Any line not in a valid format is ignored. 1288 * Lines are terminated with newline '\n' characters. 1289 * 1290 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1291 * the vendor name. 1292 * 1293 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1294 * - devices cannot be listed without a corresponding VENDOR line. 1295 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1296 * another TAB, then the device name. 1297 */ 1298 1299/* 1300 * Assuming (ptr) points to the beginning of a line in the database, 1301 * return the vendor or device and description of the next entry. 1302 * The value of (vendor) or (device) inappropriate for the entry type 1303 * is set to -1. Returns nonzero at the end of the database. 1304 * 1305 * Note that this is slightly unrobust in the face of corrupt data; 1306 * we attempt to safeguard against this by spamming the end of the 1307 * database with a newline when we initialise. 1308 */ 1309static int 1310pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1311{ 1312 char *cp = *ptr; 1313 int left; 1314 1315 *device = -1; 1316 *vendor = -1; 1317 **desc = '\0'; 1318 for (;;) { 1319 left = pci_vendordata_size - (cp - pci_vendordata); 1320 if (left <= 0) { 1321 *ptr = cp; 1322 return(1); 1323 } 1324 1325 /* vendor entry? */ 1326 if (*cp != '\t' && 1327 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1328 break; 1329 /* device entry? */ 1330 if (*cp == '\t' && 1331 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1332 break; 1333 1334 /* skip to next line */ 1335 while (*cp != '\n' && left > 0) { 1336 cp++; 1337 left--; 1338 } 1339 if (*cp == '\n') { 1340 cp++; 1341 left--; 1342 } 1343 } 1344 /* skip to next line */ 1345 while (*cp != '\n' && left > 0) { 1346 cp++; 1347 left--; 1348 } 1349 if (*cp == '\n' && left > 0) 1350 cp++; 1351 *ptr = cp; 1352 return(0); 1353} 1354 1355static char * 1356pci_describe_device(device_t dev) 1357{ 1358 int vendor, device; 1359 char *desc, *vp, *dp, *line; 1360 1361 desc = vp = dp = NULL; 1362 1363 /* 1364 * If we have no vendor data, we can't do anything. 1365 */ 1366 if (pci_vendordata == NULL) 1367 goto out; 1368 1369 /* 1370 * Scan the vendor data looking for this device 1371 */ 1372 line = pci_vendordata; 1373 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1374 goto out; 1375 for (;;) { 1376 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1377 goto out; 1378 if (vendor == pci_get_vendor(dev)) 1379 break; 1380 } 1381 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1382 goto out; 1383 for (;;) { 1384 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1385 *dp = 0; 1386 break; 1387 } 1388 if (vendor != -1) { 1389 *dp = 0; 1390 break; 1391 } 1392 if (device == pci_get_device(dev)) 1393 break; 1394 } 1395 if (dp[0] == '\0') 1396 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1397 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1398 NULL) 1399 sprintf(desc, "%s, %s", vp, dp); 1400 out: 1401 if (vp != NULL) 1402 free(vp, M_DEVBUF); 1403 if (dp != NULL) 1404 free(dp, M_DEVBUF); 1405 return(desc); 1406} 1407 1408int 1409pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1410{ 1411 struct pci_devinfo *dinfo; 1412 pcicfgregs *cfg; 1413 1414 dinfo = device_get_ivars(child); 1415 cfg = &dinfo->cfg; 1416 1417 switch (which) { 1418 case PCI_IVAR_ETHADDR: 1419 /* 1420 * The generic accessor doesn't deal with failure, so 1421 * we set the return value, then return an error. 1422 */ 1423 *((uint8_t **) result) = NULL; 1424 return (EINVAL); 1425 case PCI_IVAR_SUBVENDOR: 1426 *result = cfg->subvendor; 1427 break; 1428 case PCI_IVAR_SUBDEVICE: 1429 *result = cfg->subdevice; 1430 break; 1431 case PCI_IVAR_VENDOR: 1432 *result = cfg->vendor; 1433 break; 1434 case PCI_IVAR_DEVICE: 1435 *result = cfg->device; 1436 break; 1437 case PCI_IVAR_DEVID: 1438 *result = (cfg->device << 16) | cfg->vendor; 1439 break; 1440 case PCI_IVAR_CLASS: 1441 *result = cfg->baseclass; 1442 break; 1443 case PCI_IVAR_SUBCLASS: 1444 *result = cfg->subclass; 1445 break; 1446 case PCI_IVAR_PROGIF: 1447 *result = cfg->progif; 1448 break; 1449 case PCI_IVAR_REVID: 1450 *result = cfg->revid; 1451 break; 1452 case PCI_IVAR_INTPIN: 1453 *result = cfg->intpin; 1454 break; 1455 case PCI_IVAR_IRQ: 1456 *result = cfg->intline; 1457 break; 1458 case PCI_IVAR_BUS: 1459 *result = cfg->bus; 1460 break; 1461 case PCI_IVAR_SLOT: 1462 *result = cfg->slot; 1463 break; 1464 case PCI_IVAR_FUNCTION: 1465 *result = cfg->func; 1466 break; 1467 default: 1468 return (ENOENT); 1469 } 1470 return (0); 1471} 1472 1473int 1474pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1475{ 1476 struct pci_devinfo *dinfo; 1477 1478 dinfo = device_get_ivars(child); 1479 1480 switch (which) { 1481 case PCI_IVAR_INTPIN: 1482 dinfo->cfg.intpin = value; 1483 return (0); 1484 case PCI_IVAR_ETHADDR: 1485 case PCI_IVAR_SUBVENDOR: 1486 case PCI_IVAR_SUBDEVICE: 1487 case PCI_IVAR_VENDOR: 1488 case PCI_IVAR_DEVICE: 1489 case PCI_IVAR_DEVID: 1490 case PCI_IVAR_CLASS: 1491 case PCI_IVAR_SUBCLASS: 1492 case PCI_IVAR_PROGIF: 1493 case PCI_IVAR_REVID: 1494 case PCI_IVAR_IRQ: 1495 case PCI_IVAR_BUS: 1496 case PCI_IVAR_SLOT: 1497 case PCI_IVAR_FUNCTION: 1498 return (EINVAL); /* disallow for now */ 1499 1500 default: 1501 return (ENOENT); 1502 } 1503} 1504 1505 1506#include "opt_ddb.h" 1507#ifdef DDB 1508#include <ddb/ddb.h> 1509#include <sys/cons.h> 1510 1511/* 1512 * List resources based on pci map registers, used for within ddb 1513 */ 1514 1515DB_SHOW_COMMAND(pciregs, db_pci_dump) 1516{ 1517 struct pci_devinfo *dinfo; 1518 struct devlist *devlist_head; 1519 struct pci_conf *p; 1520 const char *name; 1521 int i, error, none_count, quit; 1522 1523 none_count = 0; 1524 /* get the head of the device queue */ 1525 devlist_head = &pci_devq; 1526 1527 /* 1528 * Go through the list of devices and print out devices 1529 */ 1530 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1531 for (error = 0, i = 0, quit = 0, 1532 dinfo = STAILQ_FIRST(devlist_head); 1533 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1534 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1535 1536 /* Populate pd_name and pd_unit */ 1537 name = NULL; 1538 if (dinfo->cfg.dev) 1539 name = device_get_name(dinfo->cfg.dev); 1540 1541 p = &dinfo->conf; 1542 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1543 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1544 (name && *name) ? name : "none", 1545 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1546 none_count++, 1547 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1548 p->pc_sel.pc_func, (p->pc_class << 16) | 1549 (p->pc_subclass << 8) | p->pc_progif, 1550 (p->pc_subdevice << 16) | p->pc_subvendor, 1551 (p->pc_device << 16) | p->pc_vendor, 1552 p->pc_revid, p->pc_hdr); 1553 } 1554} 1555#endif /* DDB */ 1556 1557static struct resource * 1558pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1559 u_long start, u_long end, u_long count, u_int flags) 1560{ 1561 struct pci_devinfo *dinfo = device_get_ivars(child); 1562 struct resource_list *rl = &dinfo->resources; 1563 struct resource_list_entry *rle; 1564 struct resource *res; 1565 uint32_t map, testval; 1566 int mapsize; 1567 1568 /* 1569 * Weed out the bogons, and figure out how large the BAR/map 1570 * is. Bars that read back 0 here are bogus and unimplemented. 1571 * Note: atapci in legacy mode are special and handled elsewhere 1572 * in the code. If you have a atapci device in legacy mode and 1573 * it fails here, that other code is broken. 1574 */ 1575 res = NULL; 1576 map = pci_read_config(child, *rid, 4); 1577 pci_write_config(child, *rid, 0xffffffff, 4); 1578 testval = pci_read_config(child, *rid, 4); 1579 if (testval == 0) 1580 return (NULL); 1581 if (pci_maptype(testval) & PCI_MAPMEM) { 1582 if (type != SYS_RES_MEMORY) { 1583 device_printf(child, 1584 "failed: rid %#x is memory, requested %d\n", 1585 *rid, type); 1586 goto out; 1587 } 1588 } else { 1589 if (type != SYS_RES_IOPORT) { 1590 device_printf(child, 1591 "failed: rid %#x is ioport, requested %d\n", 1592 *rid, type); 1593 goto out; 1594 } 1595 } 1596 /* 1597 * For real BARs, we need to override the size that 1598 * the driver requests, because that's what the BAR 1599 * actually uses and we would otherwise have a 1600 * situation where we might allocate the excess to 1601 * another driver, which won't work. 1602 */ 1603 mapsize = pci_mapsize(testval); 1604 count = 1 << mapsize; 1605 if (RF_ALIGNMENT(flags) < mapsize) 1606 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1607 1608 /* 1609 * Allocate enough resource, and then write back the 1610 * appropriate bar for that resource. 1611 */ 1612 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1613 start, end, count, flags); 1614 if (res == NULL) { 1615 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1616 count, *rid, type); 1617 goto out; 1618 } 1619 resource_list_add(rl, type, *rid, start, end, count); 1620 rle = resource_list_find(rl, type, *rid); 1621 if (rle == NULL) 1622 panic("pci_alloc_map: unexpectedly can't find resource."); 1623 rle->res = res; 1624 if (bootverbose) 1625 device_printf(child, 1626 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1627 count, *rid, type, rman_get_start(res)); 1628 map = rman_get_start(res); 1629out:; 1630 pci_write_config(child, *rid, map, 4); 1631 return (res); 1632} 1633 1634 1635struct resource * 1636pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1637 u_long start, u_long end, u_long count, u_int flags) 1638{ 1639 struct pci_devinfo *dinfo = device_get_ivars(child); 1640 struct resource_list *rl = &dinfo->resources; 1641 struct resource_list_entry *rle; 1642 pcicfgregs *cfg = &dinfo->cfg; 1643 1644 /* 1645 * Perform lazy resource allocation 1646 */ 1647 if (device_get_parent(child) == dev) { 1648 switch (type) { 1649 case SYS_RES_IRQ: 1650 /* 1651 * If the child device doesn't have an 1652 * interrupt routed and is deserving of an 1653 * interrupt, try to assign it one. 1654 */ 1655 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1656 (cfg->intpin != 0)) { 1657 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1658 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1659 pci_write_config(child, PCIR_INTLINE, 1660 cfg->intline, 1); 1661 resource_list_add(rl, SYS_RES_IRQ, 0, 1662 cfg->intline, cfg->intline, 1); 1663 } 1664 } 1665 break; 1666 case SYS_RES_IOPORT: 1667 case SYS_RES_MEMORY: 1668 if (*rid < PCIR_BAR(cfg->nummaps)) { 1669 /* 1670 * Enable the I/O mode. We should 1671 * also be assigning resources too 1672 * when none are present. The 1673 * resource_list_alloc kind of sorta does 1674 * this... 1675 */ 1676 if (PCI_ENABLE_IO(dev, child, type)) 1677 return (NULL); 1678 } 1679 rle = resource_list_find(rl, type, *rid); 1680 if (rle == NULL) 1681 return (pci_alloc_map(dev, child, type, rid, 1682 start, end, count, flags)); 1683 break; 1684 } 1685 /* 1686 * If we've already allocated the resource, then 1687 * return it now. But first we may need to activate 1688 * it, since we don't allocate the resource as active 1689 * above. Normally this would be done down in the 1690 * nexus, but since we short-circuit that path we have 1691 * to do its job here. Not sure if we should free the 1692 * resource if it fails to activate. 1693 */ 1694 rle = resource_list_find(rl, type, *rid); 1695 if (rle != NULL && rle->res != NULL) { 1696 if (bootverbose) 1697 device_printf(child, 1698 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1699 rman_get_size(rle->res), *rid, type, 1700 rman_get_start(rle->res)); 1701 if ((flags & RF_ACTIVE) && 1702 bus_generic_activate_resource(dev, child, type, 1703 *rid, rle->res) != 0) 1704 return NULL; 1705 return (rle->res); 1706 } 1707 } 1708 return (resource_list_alloc(rl, dev, child, type, rid, 1709 start, end, count, flags)); 1710} 1711 1712void 1713pci_delete_resource(device_t dev, device_t child, int type, int rid) 1714{ 1715 struct pci_devinfo *dinfo; 1716 struct resource_list *rl; 1717 struct resource_list_entry *rle; 1718 1719 if (device_get_parent(child) != dev) 1720 return; 1721 1722 dinfo = device_get_ivars(child); 1723 rl = &dinfo->resources; 1724 rle = resource_list_find(rl, type, rid); 1725 if (rle) { 1726 if (rle->res) { 1727 if (rman_get_device(rle->res) != dev || 1728 rman_get_flags(rle->res) & RF_ACTIVE) { 1729 device_printf(dev, "delete_resource: " 1730 "Resource still owned by child, oops. " 1731 "(type=%d, rid=%d, addr=%lx)\n", 1732 rle->type, rle->rid, 1733 rman_get_start(rle->res)); 1734 return; 1735 } 1736 bus_release_resource(dev, type, rid, rle->res); 1737 } 1738 resource_list_delete(rl, type, rid); 1739 } 1740 /* 1741 * Why do we turn off the PCI configuration BAR when we delete a 1742 * resource? -- imp 1743 */ 1744 pci_write_config(child, rid, 0, 4); 1745 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1746} 1747 1748struct resource_list * 1749pci_get_resource_list (device_t dev, device_t child) 1750{ 1751 struct pci_devinfo *dinfo = device_get_ivars(child); 1752 1753 return (&dinfo->resources); 1754} 1755 1756uint32_t 1757pci_read_config_method(device_t dev, device_t child, int reg, int width) 1758{ 1759 struct pci_devinfo *dinfo = device_get_ivars(child); 1760 pcicfgregs *cfg = &dinfo->cfg; 1761 1762 return (PCIB_READ_CONFIG(device_get_parent(dev), 1763 cfg->bus, cfg->slot, cfg->func, reg, width)); 1764} 1765 1766void 1767pci_write_config_method(device_t dev, device_t child, int reg, 1768 uint32_t val, int width) 1769{ 1770 struct pci_devinfo *dinfo = device_get_ivars(child); 1771 pcicfgregs *cfg = &dinfo->cfg; 1772 1773 PCIB_WRITE_CONFIG(device_get_parent(dev), 1774 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1775} 1776 1777int 1778pci_child_location_str_method(device_t dev, device_t child, char *buf, 1779 size_t buflen) 1780{ 1781 struct pci_devinfo *dinfo; 1782 1783 dinfo = device_get_ivars(child); 1784 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1785 pci_get_function(child)); 1786 return (0); 1787} 1788 1789int 1790pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1791 size_t buflen) 1792{ 1793 struct pci_devinfo *dinfo; 1794 pcicfgregs *cfg; 1795 1796 dinfo = device_get_ivars(child); 1797 cfg = &dinfo->cfg; 1798 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1799 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1800 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1801 cfg->progif); 1802 return (0); 1803} 1804 1805int 1806pci_assign_interrupt_method(device_t dev, device_t child) 1807{ 1808 struct pci_devinfo *dinfo = device_get_ivars(child); 1809 pcicfgregs *cfg = &dinfo->cfg; 1810 1811 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1812 cfg->intpin)); 1813} 1814 1815static int 1816pci_modevent(module_t mod, int what, void *arg) 1817{ 1818 static struct cdev *pci_cdev; 1819 1820 switch (what) { 1821 case MOD_LOAD: 1822 STAILQ_INIT(&pci_devq); 1823 pci_generation = 0; 1824 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1825 "pci"); 1826 pci_load_vendor_data(); 1827 break; 1828 1829 case MOD_UNLOAD: 1830 destroy_dev(pci_cdev); 1831 break; 1832 } 1833 1834 return (0); 1835} 1836 1837static void 1838pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1839{ 1840 int i; 1841 1842 /* 1843 * Only do header type 0 devices. Type 1 devices are bridges, 1844 * which we know need special treatment. Type 2 devices are 1845 * cardbus bridges which also require special treatment. 1846 * Other types are unknown, and we err on the side of safety 1847 * by ignoring them. 1848 */ 1849 if (dinfo->cfg.hdrtype != 0) 1850 return; 1851 1852 /* 1853 * Restore the device to full power mode. We must do this 1854 * before we restore the registers because moving from D3 to 1855 * D0 will cause the chip's BARs and some other registers to 1856 * be reset to some unknown power on reset values. Cut down 1857 * the noise on boot by doing nothing if we are already in 1858 * state D0. 1859 */ 1860 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1861 if (bootverbose) 1862 printf( 1863 "pci%d:%d:%d: Transition from D%d to D0\n", 1864 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1865 pci_get_powerstate(dev)); 1866 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1867 } 1868 for (i = 0; i < dinfo->cfg.nummaps; i++) 1869 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1870 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1871 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1872 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1873 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1874 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1875 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1876 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1877 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1878 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1879 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1880} 1881 1882static void 1883pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1884{ 1885 int i; 1886 uint32_t cls; 1887 int ps; 1888 1889 /* 1890 * Only do header type 0 devices. Type 1 devices are bridges, which 1891 * we know need special treatment. Type 2 devices are cardbus bridges 1892 * which also require special treatment. Other types are unknown, and 1893 * we err on the side of safety by ignoring them. Powering down 1894 * bridges should not be undertaken lightly. 1895 */ 1896 if (dinfo->cfg.hdrtype != 0) 1897 return; 1898 for (i = 0; i < dinfo->cfg.nummaps; i++) 1899 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1900 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1901 1902 /* 1903 * Some drivers apparently write to these registers w/o 1904 * updating our cahced copy. No harm happens if we update the 1905 * copy, so do so here so we can restore them. The COMMAND 1906 * register is modified by the bus w/o updating the cache. This 1907 * should represent the normally writable portion of the 'defined' 1908 * part of type 0 headers. In theory we also need to save/restore 1909 * the PCI capability structures we know about, but apart from power 1910 * we don't know any that are writable. 1911 */ 1912 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1913 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1914 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1915 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1916 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1917 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1918 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1919 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1920 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1921 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1922 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1923 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1924 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1925 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1926 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1927 1928 /* 1929 * don't set the state for display devices and for memory devices 1930 * since bad things happen. we should (a) have drivers that can easily 1931 * detach and (b) use generic drivers for these devices so that some 1932 * device actually attaches. We need to make sure that when we 1933 * implement (a) we don't power the device down on a reattach. 1934 */ 1935 cls = pci_get_class(dev); 1936 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY) { 1937 /* 1938 * PCI spec is clear that we can only go into D3 state from 1939 * D0 state. Transition from D[12] into D0 before going 1940 * to D3 state. 1941 */ 1942 ps = pci_get_powerstate(dev); 1943 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1944 if (bootverbose) 1945 printf( 1946 "pci%d:%d:%d: Transition from D%d to D0\n", 1947 dinfo->cfg.bus, dinfo->cfg.slot, 1948 dinfo->cfg.func, ps); 1949 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1950 } 1951 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1952 if (bootverbose) 1953 printf( 1954 "pci%d:%d:%d: Transition from D0 to D3\n", 1955 dinfo->cfg.bus, dinfo->cfg.slot, 1956 dinfo->cfg.func); 1957 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1958 } 1959 } 1960} 1961