pci.c revision 13656
1/************************************************************************** 2** 3** $Id: pci.c,v 1.42 1996/01/25 18:31:58 se Exp $ 4** 5** General subroutines for the PCI bus. 6** pci_configure () 7** 8** FreeBSD 9** 10**------------------------------------------------------------------------- 11** 12** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 13** 14** Redistribution and use in source and binary forms, with or without 15** modification, are permitted provided that the following conditions 16** are met: 17** 1. Redistributions of source code must retain the above copyright 18** notice, this list of conditions and the following disclaimer. 19** 2. Redistributions in binary form must reproduce the above copyright 20** notice, this list of conditions and the following disclaimer in the 21** documentation and/or other materials provided with the distribution. 22** 3. The name of the author may not be used to endorse or promote products 23** derived from this software without specific prior written permission. 24** 25** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35** 36*************************************************************************** 37*/ 38 39#include "pci.h" 40#if NPCI > 0 41 42/*======================================================== 43** 44** #includes and declarations 45** 46**======================================================== 47*/ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/malloc.h> 52#include <sys/errno.h> 53#include <sys/kernel.h> 54#include <sys/sysctl.h> 55#include <sys/proc.h> /* declaration of wakeup(), used by vm.h */ 56#include <sys/devconf.h> 57 58#include <machine/cpu.h> /* bootverbose */ 59 60#include <vm/vm.h> 61#include <vm/vm_param.h> 62#include <vm/pmap.h> 63 64#include <sys/devconf.h> 65 66#include <i386/isa/isa_device.h> /* XXX inthand2_t */ 67 68#include <pci/pcivar.h> 69#include <pci/pcireg.h> 70#include <pci/pcibus.h> 71 72#define PCI_MAX_IRQ (16) 73 74 75/*======================================================== 76** 77** Structs and Functions 78** 79**======================================================== 80*/ 81 82struct pci_devconf { 83 struct kern_devconf pdc_kdc; 84 struct pci_info pdc_pi; 85}; 86 87struct pcicb { 88 struct pcicb *pcicb_next; 89 struct pcicb *pcicb_up; 90 struct pcicb *pcicb_down; 91 pcici_t pcicb_bridge; 92 93 u_long pcicb_seen; 94 u_char pcicb_bus; 95 u_char pcicb_subordinate; 96 u_char pcicb_flags; 97#define PCICB_ISAMEM 0x01 98 u_int pcicb_mfrom; 99 u_int pcicb_mupto; 100 u_int pcicb_mamount; 101 u_short pcicb_pfrom; 102 u_short pcicb_pupto; 103 u_short pcicb_pamount; 104 u_char pcicb_bfrom; 105 u_char pcicb_bupto; 106 107 u_long pcicb_iobase; 108 u_long pcicb_iolimit; 109 u_long pcicb_membase; 110 u_long pcicb_memlimit; 111 u_long pcicb_p_membase; 112 u_long pcicb_p_memlimit; 113}; 114 115static int pci_externalize (struct kern_devconf *, struct sysctl_req *); 116 117static int pci_internalize (struct kern_devconf *, struct sysctl_req *); 118 119static void 120not_supported (pcici_t tag, u_long type); 121 122static void 123pci_bus_config (void); 124 125static void 126pci_bridge_config (void); 127 128/*======================================================== 129** 130** Variables 131** 132**======================================================== 133*/ 134 135/* 136** log2 of safe burst len (in words) 137*/ 138 139unsigned pci_max_burst_len = 3; /* 2=16Byte, 3=32Byte, 4=64Byte, ... */ 140unsigned pci_mechanism = 0; 141unsigned pci_maxdevice = 0; 142static struct pcibus* pcibus; 143 144/*-------------------------------------------------------- 145** 146** Local variables. 147** 148**-------------------------------------------------------- 149*/ 150 151static int pci_conf_count; 152static int pci_info_done; 153static struct pcicb pcibus0 = { 154 NULL, NULL, NULL, 155 { 0 }, 156 0, 0, 0, 0, 157 0, 0, 0, 0, 0, 0, 0, 0, /* real allocation */ 158 0, 0xFFFF, /* iobase/limit */ 159 0x2000000, 0xFFFFFFFFu, /* nonprefetch membase/limit */ 160 0x2000000, 0xFFFFFFFFu /* prefetch membase/limit */ 161}; 162static struct pcicb *pcicb; 163 164/*======================================================== 165** 166** pci_configure () 167** 168** Autoconfiguration of pci devices. 169** 170** May be called more than once. 171** Any device is attached only once. 172** 173** Has to take care of mirrored devices, which are 174** entailed by incomplete decoding of pci address lines. 175** 176**======================================================== 177*/ 178 179void pci_configure() 180{ 181 struct pcibus **pbp = (struct pcibus**) pcibus_set.ls_items; 182 183 /* 184 ** check pci bus present 185 */ 186 187 while (!pci_maxdevice && (pcibus = *pbp++)) { 188 (*pcibus->pb_setup)(); 189 } 190 191 if (!pci_maxdevice) return; 192 193 /* 194 ** hello world .. 195 */ 196 197 for (pcicb = &pcibus0; pcicb != NULL;) { 198 pci_bus_config (); 199 200 if (pcicb->pcicb_down) { 201 pcicb = pcicb->pcicb_down; 202 continue; 203 }; 204 205 while (pcicb && !pcicb->pcicb_next) 206 pcicb = pcicb->pcicb_up; 207 208 if (pcicb) 209 pcicb = pcicb->pcicb_next; 210 } 211 pci_conf_count++; 212} 213 214/*======================================================== 215** 216** Subroutines for configuration. 217** 218**======================================================== 219*/ 220 221static void 222pci_register_io (struct pcicb * cb, u_int base, u_int limit) 223{ 224#ifdef PCI_BRIDGE_DEBUG 225 if (bootverbose) 226 printf ("register_io: bus=%d base=%x limit=%x\n", 227 cb->pcicb_bus, base, limit); 228#endif 229 230 if (!cb->pcicb_pfrom || base < cb->pcicb_pfrom) 231 cb->pcicb_pfrom = base; 232 if (limit > cb->pcicb_pupto) 233 cb->pcicb_pupto = limit; 234 235 /* 236 ** XXX should set bridge io mapping here 237 ** but it can be mapped in 4k blocks only, 238 ** leading to conflicts with isa/eisa .. 239 */ 240} 241 242static void 243pci_register_memory (struct pcicb * cb, u_int base, u_int limit) 244{ 245#ifdef PCI_BRIDGE_DEBUG 246 if (bootverbose) 247 printf ("register_mem: bus=%d base=%x limit=%x\n", 248 cb->pcicb_bus, base, limit); 249#endif 250 251 if (!cb->pcicb_mfrom || base < cb->pcicb_mfrom) 252 cb->pcicb_mfrom = base; 253 if (limit > cb->pcicb_mupto) 254 cb->pcicb_mupto = limit; 255 /* 256 ** set the bridges mapping 257 ** 258 ** XXX should handle the 1Mb granularity. 259 */ 260 if (cb->pcicb_bridge.tag) { 261 pci_conf_write(cb->pcicb_bridge, 262 PCI_PCI_BRIDGE_MEM_REG, 263 (cb->pcicb_memlimit & 0xffff0000) | 264 (cb->pcicb_membase >> 16)); 265 if (bootverbose) 266 printf ("\t[pci%d uses memory from %x to %x]\n", 267 cb->pcicb_bus, 268 (unsigned) cb->pcicb_membase, 269 (unsigned) cb->pcicb_memlimit); 270 } 271} 272 273/* 274** XXX This function is neither complete nor tested. 275** It's only used if the bios hasn't done it's job 276** of mapping the pci devices in the physical memory. 277*/ 278 279static u_int 280pci_memalloc (struct pcicb * cb, u_int addr, u_int size) 281{ 282 u_int result = 0, limit=0, newbase=0; 283#ifdef PCI_BRIDGE_DEBUG 284 if (bootverbose) 285 printf ("memalloc: bus=%d addr=%x size=%x ..\n", 286 cb->pcicb_bus, addr, size); 287#endif 288 289 if (!cb) goto done; 290 291 if (!cb->pcicb_membase) { 292 printf ("memalloc: bus%d: membase not set.\n", 293 cb->pcicb_bus); 294 goto done; 295 } 296 297 /* 298 ** get upper allocation limit 299 */ 300 limit = cb->pcicb_memlimit; 301 if (cb->pcicb_mfrom && cb->pcicb_mfrom <= limit) 302 limit = cb->pcicb_mfrom-1; 303 304 /* 305 ** address fixed, and impossible to allocate ? 306 */ 307 if (addr && addr+size-1 > limit) 308 goto done; 309 310 /* 311 ** get possible address 312 */ 313 314 result = addr; 315 if (!result) result = ((limit + 1) / size - 1) * size; 316 317 /* 318 ** if not local available, request from parent. 319 */ 320 321 if (result < cb->pcicb_membase) { 322 newbase = pci_memalloc (cb->pcicb_up, result, size); 323 if (newbase) cb->pcicb_membase = result; 324 else result=0; 325 } 326done: 327 if (result) 328 pci_register_memory (cb, result, result+size-1); 329 330#ifdef PCI_BRIDGE_DEBUG 331 printf ("memalloc: bus=%d addr=%x size=%x --> %x (limit=%x).\n", 332 cb->pcicb_bus, addr, size, result, limit); 333#endif 334 335 return (result); 336} 337 338/*======================================================== 339** 340** pci_bus_config() 341** 342** Autoconfiguration of one pci bus. 343** 344**======================================================== 345*/ 346 347static void 348pci_bus_config (void) 349{ 350 u_char device; 351 u_char reg; 352 pcici_t tag, mtag; 353 pcidi_t type; 354 u_long data; 355 int unit; 356 int pciint; 357 int irq; 358 359 struct pci_device *dvp; 360 361 struct pci_devconf *pdcp; 362 363 /* 364 ** first initialize the bridge (bus controller chip) 365 */ 366 pci_bridge_config (); 367 368 printf ("Probing for devices on PCI bus %d:\n", pcicb->pcicb_bus); 369#ifndef PCI_QUIET 370 if (bootverbose && !pci_info_done) { 371 pci_info_done=1; 372 printf ("\tconfiguration mode %d allows %d devices.\n", 373 pci_mechanism, pci_maxdevice); 374 }; 375#endif 376 for (device=0; device<pci_maxdevice; device ++) { 377 char *name = NULL; 378 struct pci_device **dvpp; 379 int func, maxfunc = 0; 380 381 if ((pcicb->pcicb_seen >> device) & 1) 382 continue; 383 384 for (func=0; func <= maxfunc; func++) { 385 tag = pcibus->pb_tag (pcicb->pcicb_bus, device, func); 386 type = pcibus->pb_read (tag, PCI_ID_REG); 387 388 if ((!type) || (type==0xfffffffful)) continue; 389 390 /* 391 ** lookup device in ioconfiguration: 392 */ 393 394 dvpp = (struct pci_device **)pcidevice_set.ls_items; 395 396 while (dvp = *dvpp++) { 397 if (dvp->pd_probe) { 398 if (name=(*dvp->pd_probe)(tag, type)) 399 break; 400 } 401 }; 402 /* 403 ** check for mirrored devices. 404 */ 405 if (func != 0) { 406 goto real_device; 407 } 408 if (device & 0x10) { 409 mtag=pcibus->pb_tag (pcicb->pcicb_bus, 410 (u_char)(device & ~0x10), 0); 411 } else if (device & 0x08) { 412 mtag=pcibus->pb_tag (pcicb->pcicb_bus, 413 (u_char)(device & ~0x08), 0); 414 } else goto real_device; 415 416 if (type!=pcibus->pb_read (mtag, PCI_ID_REG)) 417 goto real_device; 418 419 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) 420 if (pcibus->pb_read(tag,reg)!=pcibus->pb_read(mtag,reg)) 421 goto real_device; 422 423#ifndef PCI_QUIET 424 if (dvp==NULL) continue; 425 if (bootverbose) 426 printf ("%s? <%s> mirrored on pci%d:%d\n", 427 dvp->pd_name, name, pcicb->pcicb_bus, device); 428#endif 429 continue; 430 431 real_device: 432 /* 433 * Ack. The Triton PIIX doesn't correctly set 434 * the multifunction bit. Fake it. 435 */ 436 if (type == 0x122e8086) { 437 maxfunc = 1; 438 } 439 440 if (func == 0 && (pcibus->pb_read (tag, PCI_HEADER_MISC) 441 & PCI_HEADER_MULTIFUNCTION)) { 442 maxfunc = 7; 443 } 444 445 if (dvp==NULL) { 446#ifndef PCI_QUIET 447 if (pci_conf_count) 448 continue; 449 printf("%s%d:%d: ", pcibus->pb_name, 450 pcicb->pcicb_bus, device); 451 not_supported (tag, type); 452#endif 453 continue; 454 }; 455 456 pcicb->pcicb_seen |= (1ul << device); 457 458 /* 459 ** Get and increment the unit. 460 */ 461 462 unit = (*dvp->pd_count)++; 463 464 /* 465 ** ignore device ? 466 */ 467 468 if (!*name) continue; 469 470 /* 471 ** Announce this device 472 */ 473 474 printf ("%s%d <%s> rev %d", dvp->pd_name, unit, name, 475 (unsigned) pci_conf_read (tag, PCI_CLASS_REG) & 0xff); 476 477 /* 478 ** Get the int pin number (pci interrupt number a-d) 479 ** from the pci configuration space. 480 */ 481 482 data = pcibus->pb_read (tag, PCI_INTERRUPT_REG); 483 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 484 485 if (pciint) { 486 487 printf (" int %c irq ", 0x60+pciint); 488 489 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 490 491 /* 492 ** If it's zero, the isa irq number is unknown, 493 ** and we cannot bind the pci interrupt. 494 */ 495 496 if (irq) 497 printf ("%d", irq); 498 else 499 printf ("??"); 500 }; 501 502 printf (" on pci%d:%d\n", pcicb->pcicb_bus, device); 503 504 /* 505 ** Read the current mapping, 506 ** and update the pcicb fields. 507 */ 508 509 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) { 510 u_int map, addr, size; 511 512 data = pci_conf_read(tag, PCI_CLASS_REG); 513 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 514 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 515 continue; 516 }; 517 518 map = pcibus->pb_read (tag, reg); 519 if (!(map & PCI_MAP_MEMORY_ADDRESS_MASK)) 520 continue; 521 522 pcibus->pb_write (tag, reg, 0xffffffff); 523 data = pcibus->pb_read (tag, reg); 524 pcibus->pb_write (tag, reg, map); 525 526 switch (data & 7) { 527 528 default: 529 continue; 530 case 1: 531 case 5: 532 size = -(data & PCI_MAP_IO_ADDRESS_MASK); 533 addr = map & PCI_MAP_IO_ADDRESS_MASK; 534 535 pci_register_io (pcicb, addr, addr+size-1); 536 pcicb->pcicb_pamount += size; 537 break; 538 539 case 0: 540 case 2: 541 case 4: 542 size = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 543 addr = map & PCI_MAP_MEMORY_ADDRESS_MASK; 544 if (addr >= 0x100000) { 545 pci_register_memory 546 (pcicb, addr, addr+size-1); 547 pcicb->pcicb_mamount += size; 548 } else { 549 pcicb->pcicb_flags |= PCICB_ISAMEM; 550 }; 551 break; 552 }; 553 if (bootverbose) 554 printf ("\tmapreg[%02x] type=%d addr=%08x size=%04x.\n", 555 reg, map&7, addr, size); 556 }; 557 558 /* 559 ** Allocate a devconf structure 560 ** We should, and eventually will, set the 561 ** parent pointer to a pci bus devconf structure, 562 ** and arrange to set the state field dynamically. 563 */ 564 565 pdcp = (struct pci_devconf *) 566 malloc (sizeof (struct pci_devconf),M_DEVBUF,M_WAITOK); 567 bzero(pdcp, sizeof(struct pci_devconf)); 568 569 pdcp -> pdc_pi.pi_bus = pcicb->pcicb_bus; 570 pdcp -> pdc_pi.pi_device = device; 571 pdcp -> pdc_pi.pi_func = func; 572 573 pdcp -> pdc_kdc.kdc_name = dvp->pd_name; 574 pdcp -> pdc_kdc.kdc_unit = unit; 575 576 pdcp -> pdc_kdc.kdc_md.mddc_devtype = MDDT_PCI; 577 578 pdcp -> pdc_kdc.kdc_externalize = pci_externalize; 579 pdcp -> pdc_kdc.kdc_internalize = pci_internalize; 580 581 pdcp -> pdc_kdc.kdc_datalen = PCI_EXTERNAL_LEN; 582 pdcp -> pdc_kdc.kdc_parentdata = &pdcp->pdc_pi; 583 pdcp -> pdc_kdc.kdc_state = DC_UNKNOWN; 584 pdcp -> pdc_kdc.kdc_description = name; 585 pdcp -> pdc_kdc.kdc_shutdown = dvp->pd_shutdown; 586 587 /* 588 ** And register this device 589 */ 590 591 dev_attach (&pdcp->pdc_kdc); 592 593 /* 594 ** attach device 595 ** may produce additional log messages, 596 ** i.e. when installing subdevices. 597 */ 598 599 (*dvp->pd_attach) (tag, unit); 600 601 /* 602 ** Special processing of certain classes 603 */ 604 605 data = pci_conf_read(tag, PCI_CLASS_REG); 606 607 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 608 struct pcicb *this, **link; 609 unsigned char primary, secondary, subordinate; 610 u_int command; 611 612 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 613 614 /* 615 ** get current configuration of the bridge. 616 */ 617 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 618 primary = PCI_PRIMARY_BUS_EXTRACT (data); 619 secondary = PCI_SECONDARY_BUS_EXTRACT(data); 620 subordinate = PCI_SUBORDINATE_BUS_EXTRACT(data); 621#ifndef PCI_QUIET 622 if (bootverbose) { 623 printf ("\tbridge from pci%d to pci%d through %d.\n", 624 primary, secondary, subordinate); 625 printf ("\tmapping regs: io:%08lx mem:%08lx pmem:%08lx\n", 626 pci_conf_read (tag, PCI_PCI_BRIDGE_IO_REG), 627 pci_conf_read (tag, PCI_PCI_BRIDGE_MEM_REG), 628 pci_conf_read (tag, PCI_PCI_BRIDGE_PMEM_REG)); 629 } 630#endif 631 /* 632 ** check for uninitialized bridge. 633 */ 634 if (secondary == 0 || secondary < primary || 635 pcicb->pcicb_bus != primary) 636 { 637 printf ("\tINCORRECTLY or NEVER CONFIGURED.\n"); 638 /* 639 ** disable this bridge 640 */ 641 pcibus->pb_write (tag, PCI_COMMAND_STATUS_REG, 642 0xffff0000); 643 secondary = 0; 644 subordinate = 0; 645 }; 646 647 /* 648 ** allocate bus descriptor for bus behind the bridge 649 */ 650 link = &pcicb->pcicb_down; 651 while (*link) link = &(*link)->pcicb_next; 652 653 this = malloc (sizeof (*this), M_DEVBUF, M_WAITOK); 654 655 /* 656 ** Initialize this descriptor so far. 657 ** (the initialization is completed just before 658 ** scanning the bus behind the bridge. 659 */ 660 bzero (this, sizeof(*this)); 661 this->pcicb_up = pcicb; 662 this->pcicb_bridge = tag; 663 this->pcicb_bus = secondary; 664 this->pcicb_subordinate = subordinate; 665 666 command = pci_conf_read(tag,PCI_COMMAND_STATUS_REG); 667 668 if (command & PCI_COMMAND_IO_ENABLE){ 669 /* 670 ** Bridge was configured by the bios. 671 ** Read out the mapped io region. 672 */ 673 u_int reg, data, mask; 674 675 reg = pci_conf_read (tag, 676 PCI_PCI_BRIDGE_IO_REG); 677 pci_conf_write(tag, 678 PCI_PCI_BRIDGE_IO_REG, 0xFFFF); 679 data = pci_conf_read (tag, 680 PCI_PCI_BRIDGE_IO_REG); 681 pci_conf_write(tag, 682 PCI_PCI_BRIDGE_IO_REG, reg & 0xffff); 683 684 mask = (0xFF00 ^ (data & 0xFF00)) | 0xFF; 685 686 this->pcicb_iobase = 687 PCI_PPB_IOBASE_EXTRACT (reg); 688 this->pcicb_iolimit = 689 PCI_PPB_IOLIMIT_EXTRACT(reg) | mask; 690 691 /* 692 ** Note the used io space. 693 */ 694 pci_register_io (pcicb, this->pcicb_iobase, 695 this->pcicb_iolimit); 696 697 }; 698 699 if (command & PCI_COMMAND_MEM_ENABLE) { 700 /* 701 ** Bridge was configured by the bios. 702 ** Read out the mapped memory regions. 703 */ 704 u_int reg, data, mask; 705 706 /* 707 ** non prefetchable memory 708 */ 709 reg = pci_conf_read (tag, 710 PCI_PCI_BRIDGE_MEM_REG); 711 pci_conf_write(tag, 712 PCI_PCI_BRIDGE_MEM_REG, 0xFFFFFFFF); 713 data = pci_conf_read (tag, 714 PCI_PCI_BRIDGE_MEM_REG); 715 pci_conf_write(tag, 716 PCI_PCI_BRIDGE_MEM_REG, reg); 717 718 mask = 0xFFFFFFFF ^ (data & 0xFFFF0000); 719 this->pcicb_membase = 720 PCI_PPB_MEMBASE_EXTRACT (reg); 721 this->pcicb_memlimit = 722 PCI_PPB_MEMLIMIT_EXTRACT(reg) | mask; 723 724 /* 725 ** Register used memory space. 726 */ 727 pci_register_memory (pcicb, 728 this->pcicb_membase, 729 this->pcicb_memlimit); 730 731 /* 732 ** prefetchable memory 733 */ 734 reg = pci_conf_read (tag, 735 PCI_PCI_BRIDGE_PMEM_REG); 736 pci_conf_write(tag, 737 PCI_PCI_BRIDGE_PMEM_REG, 0xFFFFFFFF); 738 data = pci_conf_read (tag, 739 PCI_PCI_BRIDGE_PMEM_REG); 740 pci_conf_write(tag, 741 PCI_PCI_BRIDGE_PMEM_REG, reg); 742 743 mask = 0xFFFFFFFF ^ (data & 0xFFFF0000); 744 this->pcicb_p_membase= 745 PCI_PPB_MEMBASE_EXTRACT (reg); 746 this->pcicb_p_memlimit= 747 PCI_PPB_MEMLIMIT_EXTRACT(reg) | mask; 748 749 /* 750 ** Register used memory space. 751 */ 752 pci_register_memory (pcicb, 753 this->pcicb_p_membase, 754 this->pcicb_p_memlimit); 755 } 756 757 /* 758 ** Link it in chain. 759 */ 760 *link=this; 761 762 /* 763 ** Update mapping info of parent bus. 764 */ 765 if (!pcicb->pcicb_bfrom||secondary< pcicb->pcicb_bfrom) 766 pcicb->pcicb_bfrom = secondary; 767 if (subordinate > pcicb->pcicb_bupto) 768 pcicb->pcicb_bupto = subordinate; 769 770 break; 771 } 772 } 773 } 774 775#ifndef PCI_QUIET 776 if (bootverbose) { 777 if (pcicb->pcicb_mamount) 778 printf ("%s%d: uses %d bytes of memory from %x upto %x.\n", 779 pcibus->pb_name, pcicb->pcicb_bus, 780 pcicb->pcicb_mamount, 781 pcicb->pcicb_mfrom, pcicb->pcicb_mupto); 782 if (pcicb->pcicb_pamount) 783 printf ("%s%d: uses %d bytes of I/O space from %x upto %x.\n", 784 pcibus->pb_name, pcicb->pcicb_bus, 785 pcicb->pcicb_pamount, 786 pcicb->pcicb_pfrom, pcicb->pcicb_pupto); 787 if (pcicb->pcicb_bfrom) 788 printf ("%s%d: subordinate busses from %x upto %x.\n", 789 pcibus->pb_name, pcicb->pcicb_bus, 790 pcicb->pcicb_bfrom, pcicb->pcicb_bupto); 791 } 792#endif 793} 794 795/*======================================================== 796** 797** pci_bridge_config() 798** 799** Configuration of a pci bridge. 800** 801**======================================================== 802*/ 803 804static void 805pci_bridge_config (void) 806{ 807 pcici_t tag; 808 struct pcicb* parent; 809 810 tag = pcicb->pcicb_bridge; 811 if (!tag.tag) return; 812 813 if (!pcicb->pcicb_bus) { 814 u_int data; 815 /* 816 ** Get the lowest available bus number. 817 */ 818 pcicb->pcicb_bus = ++pcibus0.pcicb_subordinate; 819 820 /* 821 ** and configure the bridge 822 */ 823 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 824 data = PCI_PRIMARY_BUS_INSERT(data, pcicb->pcicb_up->pcicb_bus); 825 data = PCI_SECONDARY_BUS_INSERT(data, pcicb->pcicb_bus); 826 data = PCI_SUBORDINATE_BUS_INSERT(data, pcicb->pcicb_bus); 827 pci_conf_write (tag, PCI_PCI_BRIDGE_BUS_REG, data); 828 829 /* 830 ** Propagate the new upper bus number limit. 831 */ 832 for (parent = pcicb->pcicb_up; parent != NULL; 833 parent = parent->pcicb_up) 834 { 835 if (parent->pcicb_subordinate >= pcicb->pcicb_bus) 836 continue; 837 parent->pcicb_subordinate = pcicb->pcicb_bus; 838 if (!parent->pcicb_bridge.tag) 839 continue; 840 data = pci_conf_read 841 (parent->pcicb_bridge, PCI_PCI_BRIDGE_BUS_REG); 842 data = PCI_SUBORDINATE_BUS_INSERT 843 (data, pcicb->pcicb_bus); 844 pci_conf_write (parent->pcicb_bridge, 845 PCI_PCI_BRIDGE_BUS_REG, data); 846 } 847 } 848 849 if (!pcicb->pcicb_membase) { 850 u_int size = 0x100000; 851 pcicb->pcicb_membase = pci_memalloc (pcicb->pcicb_up, 0, size); 852 if (pcicb->pcicb_membase) 853 pcicb->pcicb_memlimit = pcicb->pcicb_membase+size-1; 854 } 855} 856 857/*----------------------------------------------------------------- 858** 859** The following functions are provided for the device driver 860** to read/write the configuration space. 861** 862** pci_conf_read(): 863** Read a long word from the pci configuration space. 864** Requires a tag (from pcitag) and the register 865** number (should be a long word alligned one). 866** 867** pci_conf_write(): 868** Writes a long word to the pci configuration space. 869** Requires a tag (from pcitag), the register number 870** (should be a long word alligned one), and a value. 871** 872**----------------------------------------------------------------- 873*/ 874 875u_long 876pci_conf_read (pcici_t tag, u_long reg) 877{ 878 return (pcibus->pb_read (tag, reg)); 879} 880 881void 882pci_conf_write (pcici_t tag, u_long reg, u_long data) 883{ 884 pcibus->pb_write (tag, reg, data); 885} 886 887/*----------------------------------------------------------------------- 888** 889** Map device into port space. 890** 891** Actually the device should have been mapped by the bios. 892** This function only reads and verifies the value. 893** 894** PCI-Specification: 6.2.5.1: address maps 895** 896**----------------------------------------------------------------------- 897*/ 898 899int pci_map_port (pcici_t tag, u_long reg, u_short* pa) 900{ 901 unsigned data, ioaddr, iosize; 902 struct pcicb *link = pcicb; 903 904 /* 905 ** sanity check 906 */ 907 908 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 909 printf ("pci_map_port failed: bad register=0x%x\n", 910 (unsigned)reg); 911 return (0); 912 }; 913 914 /*if (pcicb->pcicb_flags & PCICB_NOIOSET) { 915 printf ("pci_map_port failed: pci%d has not been configured for I/O access\n", 916 pcicb->pcicb_bus); 917 return (0); 918 }*/ 919 920 /* 921 ** get size and type of port 922 ** 923 ** type is in the lowest two bits. 924 ** If device requires 2^n bytes, the next 925 ** n-2 bits are hardwired as 0. 926 */ 927 928 ioaddr = pcibus->pb_read (tag, reg) & PCI_MAP_IO_ADDRESS_MASK; 929 if (!ioaddr || ioaddr > 0xfffful) { 930 printf ("pci_map_port failed: not configured by bios.\n"); 931 return (0); 932 }; 933 934 pcibus->pb_write (tag, reg, 0xfffffffful); 935 data = pcibus->pb_read (tag, reg); 936 pcibus->pb_write (tag, reg, ioaddr); 937 938 if ((data & 0x03) != PCI_MAP_IO) { 939 printf ("pci_map_port failed: bad port type=0x%x\n", 940 (unsigned) data); 941 return (0); 942 }; 943 iosize = -(data & PCI_MAP_IO_ADDRESS_MASK); 944 if (ioaddr < pcicb->pcicb_iobase 945 || ioaddr + iosize -1 > pcicb->pcicb_iolimit) { 946 printf ("pci_map_port failed: device's iorange 0x%x-0x%x " 947 "is incompatible with its bridge's range 0x%x-0x%x\n", 948 (unsigned) ioaddr, (unsigned) ioaddr + iosize - 1, 949 (unsigned) pcicb->pcicb_iobase, 950 (unsigned) pcicb->pcicb_iolimit); 951 return (0); 952 } 953 954#ifndef PCI_QUIET 955 if (bootverbose) 956 printf ("\treg%d: ioaddr=0x%x size=0x%x\n", 957 (unsigned) reg, (unsigned) ioaddr, (unsigned) iosize); 958#endif 959 /* 960 ** set the configuration register of and 961 ** return the address to the driver. 962 ** Make sure to enable each upstream bridge 963 ** so I/O and DMA can go all the way. 964 */ 965 966 for (;;) { 967 data = pcibus->pb_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 968 data |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 969 (void) pcibus->pb_write(tag, PCI_COMMAND_STATUS_REG, data); 970 if ((link = link->pcicb_up) == NULL) 971 break; 972 tag = link->pcicb_bridge; 973 } 974 975 *pa = ioaddr; 976 977 return (1); 978} 979 980/*----------------------------------------------------------------------- 981** 982** Map device into virtual and physical space 983** 984** Actually the device should have been mapped by the bios. 985** This function only reads and verifies the value. 986** 987** PCI-Specification: 6.2.5.1: address maps 988** 989**----------------------------------------------------------------------- 990*/ 991 992int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa) 993{ 994 struct pcicb *link = pcicb; 995 unsigned data ,paddr; 996 vm_size_t psize, poffs; 997 vm_offset_t vaddr; 998 999 /* 1000 ** sanity check 1001 */ 1002 1003 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 1004 printf ("pci_map_mem failed: bad register=0x%x\n", 1005 (unsigned)reg); 1006 return (0); 1007 }; 1008 1009 /* 1010 ** save old mapping, get size and type of memory 1011 ** 1012 ** type is in the lowest four bits. 1013 ** If device requires 2^n bytes, the next 1014 ** n-4 bits are read as 0. 1015 */ 1016 1017 paddr = pcibus->pb_read (tag, reg) & PCI_MAP_MEMORY_ADDRESS_MASK; 1018 pcibus->pb_write (tag, reg, 0xfffffffful); 1019 data = pcibus->pb_read (tag, reg); 1020 pcibus->pb_write (tag, reg, paddr); 1021 1022 /* 1023 ** check the type 1024 */ 1025 1026 if ((data & PCI_MAP_MEMORY_TYPE_MASK) != PCI_MAP_MEMORY_TYPE_32BIT) { 1027 printf ("pci_map_mem failed: bad memory type=0x%x\n", 1028 (unsigned) data); 1029 return (0); 1030 }; 1031 1032 /* 1033 ** get the size. 1034 */ 1035 1036 psize = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 1037 1038 if (!paddr || paddr == PCI_MAP_MEMORY_ADDRESS_MASK) { 1039 paddr = pci_memalloc (pcicb, 0, psize); 1040 if (!paddr) { 1041 printf ("pci_map_mem: not configured by bios.\n"); 1042 return (0); 1043 }; 1044 pci_register_memory (pcicb, paddr, paddr+psize-1); 1045 }; 1046 1047 if (paddr < pcicb->pcicb_membase || 1048 paddr + psize - 1 > pcicb->pcicb_memlimit) { 1049 printf ("pci_map_mem failed: device's memrange 0x%x-0x%x is " 1050 "incompatible with its bridge's memrange 0x%x-0x%x\n", 1051 (unsigned) paddr, 1052 (unsigned) (paddr + psize - 1), 1053 (unsigned) pcicb->pcicb_membase, 1054 (unsigned) pcicb->pcicb_memlimit); 1055/* return (0);*/ 1056/* ACHTUNG: Ist der Code richtig, wenn eine PCI-PCI-Bridge fuer 1057 * die PCI-Slots verwendet wird, aber die Onboard-Devices direkt 1058 * an der CPU-PCI-Bridge haengen (Siehe Compaq Prolinea Problem) ??? 1059 */ 1060 } 1061 pcibus->pb_write (tag, reg, paddr); 1062 1063 /* 1064 ** Truncate paddr to page boundary. 1065 ** (Or does pmap_mapdev the job?) 1066 */ 1067 1068 poffs = paddr - trunc_page (paddr); 1069 vaddr = (vm_offset_t) pmap_mapdev (paddr-poffs, psize+poffs); 1070 1071 if (!vaddr) return (0); 1072 1073 vaddr += poffs; 1074 1075#ifndef PCI_QUIET 1076 /* 1077 ** display values. 1078 */ 1079 1080 if (bootverbose) 1081 printf ("\treg%d: virtual=0x%lx physical=0x%lx size=0x%lx\n", 1082 (unsigned) reg, (u_long)vaddr, (u_long)paddr, (u_long)psize); 1083#endif 1084 /* 1085 ** set the configuration register and 1086 ** return the address to the driver 1087 ** Make sure to enable each upstream bridge 1088 ** so memory and DMA can go all the way. 1089 */ 1090 1091 for (;;) { 1092 data = pcibus->pb_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 1093 data |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1094 (void) pcibus->pb_write(tag, PCI_COMMAND_STATUS_REG, data); 1095 if ((link = link->pcicb_up) == NULL) 1096 break; 1097 tag = link->pcicb_bridge; 1098 } 1099 1100 *va = vaddr; 1101 *pa = paddr; 1102 1103 return (1); 1104} 1105 1106/*------------------------------------------------------------ 1107** 1108** Interface functions for the devconf module. 1109** 1110**------------------------------------------------------------ 1111*/ 1112 1113static int 1114pci_externalize (struct kern_devconf *kdcp, struct sysctl_req *req) 1115{ 1116 struct pci_externalize_buffer buffer; 1117 struct pci_info * pip = kdcp->kdc_parentdata; 1118 pcici_t tag; 1119 int i; 1120 1121 tag = pcibus->pb_tag (pip->pi_bus, pip->pi_device, pip->pi_func); 1122 1123 buffer.peb_pci_info = *pip; 1124 1125 for (i=0; i<PCI_EXT_CONF_LEN; i++) { 1126 buffer.peb_config[i] = pcibus->pb_read (tag, i*4); 1127 }; 1128 1129 return SYSCTL_OUT(req, &buffer, sizeof buffer); 1130} 1131 1132 1133static int 1134pci_internalize (struct kern_devconf *kdcp, struct sysctl_req *re) 1135{ 1136 return EOPNOTSUPP; 1137} 1138 1139/*----------------------------------------------------------------------- 1140** 1141** Pci meta interrupt handler 1142** 1143** This handler assumes level triggered interrupts. 1144** It's possible to build a kernel which handles shared 1145** edge triggered interrupts by the options "PCI_EDGE_INT". 1146** But there is a performance penalty. 1147** 1148** (Of course you can delete the #ifdef PCI_EDGE_INT bracketed 1149** code at all :-) :-) :-) 1150** 1151**----------------------------------------------------------------------- 1152*/ 1153 1154static struct pci_int_desc* 1155 pci_int_desc [PCI_MAX_IRQ]; 1156 1157#ifndef NO_SHARED_IRQ 1158 1159static inline unsigned 1160splq (unsigned mask) 1161{ 1162 unsigned temp=cpl; 1163 cpl |= mask; 1164 return temp; 1165} 1166 1167static void 1168pci_int (int irq) 1169{ 1170 struct pci_int_desc * p; 1171 int s; 1172 1173 if (irq<0 || irq >= PCI_MAX_IRQ) { 1174 printf ("pci_int: irq %d out of range, ignored\n", irq); 1175 return; 1176 }; 1177 for (p = pci_int_desc[irq]; p!=NULL; p=p->pcid_next) { 1178 s = splq (*p->pcid_maskptr); 1179 (*p->pcid_handler) (p->pcid_argument); 1180 p-> pcid_tally++; 1181 splx (s); 1182#if 0 1183 if (p->pcid_tally<20) 1184 printf ("PCI_INT: irq=%d h=%p cpl o=%x n=%x val=%d\n", 1185 irq, p->pcid_handler, s, cpl, c); 1186#endif 1187 }; 1188} 1189#endif 1190 1191/*----------------------------------------------------------------------- 1192** 1193** Auxiliary function for interrupt (un)mapping. 1194** 1195**----------------------------------------------------------------------- 1196*/ 1197 1198static u_int 1199getirq (pcici_t tag) 1200{ 1201 u_int irq; 1202 1203 irq = PCI_INTERRUPT_LINE_EXTRACT( 1204 pcibus->pb_read (tag, PCI_INTERRUPT_REG)); 1205 1206 if (irq <= 0) { 1207 printf ("\tint line register not set by bios\n"); 1208 return (0); 1209 } 1210 1211 if (irq >= pcibus->pb_maxirq || irq >= PCI_MAX_IRQ) { 1212 printf ("\tirq %d invalid.\n", irq); 1213 return (0); 1214 } 1215 1216 return (irq); 1217} 1218 1219static struct pci_int_desc ** 1220getintdescbytag (u_int irq, pcici_t tag) 1221{ 1222 struct pci_int_desc *p, **pp; 1223 1224 pp=&pci_int_desc[irq]; 1225 while (((p=*pp)) && !sametag(p->pcid_tag,tag)) 1226 pp=&p->pcid_next; 1227 1228 if (!p) return (NULL); 1229 1230 return (pp); 1231} 1232 1233static struct pci_int_desc * 1234getintdescbymptr (u_int irq, unsigned * mptr) 1235{ 1236 struct pci_int_desc *p; 1237 1238 for (p=pci_int_desc[irq];p;p=p->pcid_next) 1239 if (p->pcid_maskptr == mptr) break; 1240 return (p); 1241} 1242 1243/*----------------------------------------------------------------------- 1244** 1245** Map pci interrupt. 1246** 1247**----------------------------------------------------------------------- 1248*/ 1249 1250static unsigned pci_mask0 = 0; 1251 1252int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr) 1253{ 1254 u_int irq; 1255 int result, oldspl; 1256 unsigned mask; 1257 struct pci_int_desc *tail, *mdp=NULL, *new=NULL; 1258 1259 /* 1260 ** Get irq line from configuration space, 1261 ** and check for consistency. 1262 */ 1263 1264 irq = getirq (tag); 1265 if (irq >= PCI_MAX_IRQ) { 1266 printf ("\tillegal irq %d.\n", irq); 1267 return (0); 1268 }; 1269 mask= 1ul << irq; 1270 1271 /* 1272 ** disable this interrupt. 1273 */ 1274 1275 oldspl = splq (mask); 1276 1277 /* 1278 ** If handler for this tag already installed, 1279 ** remove it first. 1280 */ 1281 1282 if (getintdescbytag (irq, tag) != NULL) 1283 pci_unmap_int (tag); 1284 1285 /* 1286 ** If this irq not yet included in the mask, include it. 1287 */ 1288 1289 mdp = getintdescbymptr (irq, maskptr); 1290 if (!mdp) { 1291 result = pcibus->pb_imaskinc (irq, maskptr); 1292 if (result) 1293 goto conflict; 1294 }; 1295 1296 /* 1297 ** Allocate descriptor and initialize it. 1298 */ 1299 1300 tail = pci_int_desc[irq]; 1301 1302 new = malloc (sizeof (*new), M_DEVBUF, M_WAITOK); 1303 bzero (new, sizeof (*new)); 1304 1305 new->pcid_next = tail; 1306 new->pcid_tag = tag; 1307 new->pcid_handler = func; 1308 new->pcid_argument = arg; 1309 new->pcid_maskptr = maskptr; 1310 new->pcid_tally = 0; 1311 new->pcid_mask = mask; 1312 1313 /* 1314 ** If first handler: install it. 1315 ** If second handler: install shared-int-handler. 1316 */ 1317 1318 if (!tail) { 1319 /* 1320 ** first handler for this irq. 1321 */ 1322 1323 result = pcibus->pb_iattach 1324 /* 1325 * XXX if we get here, then `func' must be pci_int 1326 * so the bogus casts are almost OK since they just 1327 * undo the bogus casts that were needed to pass 1328 * pci_int and its arg to pci_map_int(). 1329 */ 1330 (irq, (inthand2_t *) func, (int) arg, maskptr); 1331 if (result) goto conflict; 1332 1333#ifdef NO_SHARED_IRQ 1334 } else goto conflict; 1335#else 1336 } else if (!tail->pcid_next) { 1337 /* 1338 ** Second handler for this irq. 1339 */ 1340 1341 if (bootverbose) 1342 printf ("\tusing shared irq %d.\n", irq); 1343 1344 /* 1345 ** replace old handler by shared-int-handler. 1346 */ 1347 1348 result = pcibus->pb_idetach (irq, 1349 (inthand2_t *) tail->pcid_handler); 1350 if (result) 1351 printf ("\tCANNOT DETACH INT HANDLER.\n"); 1352 1353 result = pcibus->pb_iattach (irq, pci_int, irq, &pci_mask0); 1354 if (result) { 1355 printf ("\tCANNOT ATTACH SHARED INT HANDLER.\n"); 1356 goto fail; 1357 }; 1358 } 1359#endif 1360 /* 1361 ** Link new descriptor, reenable ints and done. 1362 */ 1363 1364 pci_int_desc[irq] = new; 1365 splx (oldspl); 1366 return (1); 1367 1368 /* 1369 ** Handle some problems. 1370 */ 1371 1372conflict: 1373 printf ("\tirq %d already in use.\n", irq); 1374fail: 1375 /* 1376 ** If descriptor allocated, free it. 1377 ** If included in mask, remove it. 1378 */ 1379 1380 if (new) free(new, M_DEVBUF); 1381 if (!mdp) (void) pcibus->pb_imaskexc (irq, maskptr); 1382 splx (oldspl); 1383 return (0); 1384} 1385 1386/*----------------------------------------------------------------------- 1387** 1388** Unmap pci interrupt. 1389** 1390**----------------------------------------------------------------------- 1391*/ 1392 1393int pci_unmap_int (pcici_t tag) 1394{ 1395 int result, oldspl; 1396 struct pci_int_desc *this, **hook, *tail; 1397 unsigned irq; 1398 1399 /* 1400 ** Get irq line from configuration space, 1401 ** and check for consistency. 1402 */ 1403 1404 irq = getirq (tag); 1405 if (irq >= PCI_MAX_IRQ) { 1406 printf ("\tillegal irq %d.\n", irq); 1407 return (0); 1408 }; 1409 1410 /* 1411 ** Search and unlink interrupt descriptor. 1412 */ 1413 1414 hook = getintdescbytag (irq, tag); 1415 if (hook == NULL) { 1416 printf ("\tno irq %d handler for pci %x\n", 1417 irq, tag.tag); 1418 return (0); 1419 }; 1420 1421 this = *hook; 1422 *hook= this->pcid_next; 1423 1424 /* 1425 ** Message 1426 */ 1427 1428 printf ("\tirq %d handler %p(%p) unmapped for pci %x after %d ints.\n", 1429 irq, this->pcid_handler, this->pcid_argument, 1430 this->pcid_tag.tag, this->pcid_tally); 1431 1432 /* 1433 ** If this irq no longer included in the mask, remove it. 1434 */ 1435 1436 if (!getintdescbymptr (irq, this->pcid_maskptr)) 1437 (void) pcibus->pb_imaskexc (irq, this->pcid_maskptr); 1438 1439 tail = pci_int_desc[irq]; 1440 1441 if (tail == NULL) { 1442 1443 /* 1444 ** Remove the old handler. 1445 */ 1446 1447 result = pcibus->pb_idetach (irq, 1448 (inthand2_t *) this->pcid_handler); 1449 if (result) 1450 printf ("\tirq %d: cannot remove handler.\n", irq); 1451 1452 } else if (tail->pcid_next == NULL) { 1453 1454 /* 1455 ** Remove the shared int handler. 1456 ** Install the last remaining handler. 1457 */ 1458 1459 oldspl = splq (1ul << irq); 1460 1461 result = pcibus->pb_idetach (irq, pci_int); 1462 if (result) 1463 printf ("\tirq %d: cannot remove handler.\n", irq); 1464 1465 result = pcibus->pb_iattach (irq, 1466 (inthand2_t *) tail->pcid_handler, 1467 (int) tail->pcid_argument, 1468 tail->pcid_maskptr); 1469 1470 if (result) 1471 printf ("\tirq %d: cannot install handler.\n", irq); 1472 1473 splx (oldspl); 1474 }; 1475 1476 free (this, M_DEVBUF); 1477 return (1); 1478} 1479 1480/*----------------------------------------------------------- 1481** 1482** Display of unknown devices. 1483** 1484**----------------------------------------------------------- 1485*/ 1486struct vt { 1487 u_short ident; 1488 char* name; 1489}; 1490 1491static struct vt VendorTable[] = { 1492 {0x0e11, "Compaq"}, 1493 {0x1000, "NCR/Symbios"}, 1494 {0x1002, "ATI Technologies Inc."}, 1495 {0x1004, "VLSI"}, 1496 {0x100B, "National Semiconductor"}, 1497 {0x100E, "Weitek"}, 1498 {0x1011, "Digital Equipment Corporation"}, 1499 {0x1013, "Cirrus Logic"}, 1500 {0x101A, "NCR"}, 1501 {0x1022, "AMD"}, 1502 {0x102B, "Matrox"}, 1503 {0x102C, "Chips & Technologies"}, 1504 {0x1039, "Silicon Integrated Systems"}, 1505 {0x1042, "SMC"}, 1506 {0x1044, "DPT"}, 1507 {0x1045, "OPTI"}, 1508 {0x104B, "Bus Logic"}, 1509 {0x1060, "UMC"}, 1510 {0x1080, "Contaq"}, 1511 {0x1095, "CMD"}, 1512 {0x10b9, "ACER Labs"}, 1513 {0x1106, "VIA Technologies"}, 1514 {0x5333, "S3 Inc."}, 1515 {0x8086, "Intel Corporation"}, 1516 {0x9004, "Adaptec"}, 1517 {0,0} 1518}; 1519 1520typedef struct { 1521 const char subclass; 1522 const char *name; 1523} subclass_name; 1524 1525/* 0x00 prehistoric subclasses */ 1526static const subclass_name old_subclasses[] = 1527{ 1528 { 0x00, "misc" }, 1529 { 0x01, "vga" }, 1530 { 0x00, NULL } 1531}; 1532 1533/* 0x01 mass storage subclasses */ 1534static const subclass_name storage_subclasses[] = 1535{ 1536 { 0x00, "scsi" }, 1537 { 0x01, "ide" }, 1538 { 0x02, "floppy"}, 1539 { 0x03, "ipi" }, 1540 { 0x80, "misc" }, 1541 { 0x00, NULL } 1542}; 1543 1544/* 0x02 network subclasses */ 1545static const subclass_name network_subclasses[] = 1546{ 1547 { 0x00, "ethernet" }, 1548 { 0x01, "tokenring" }, 1549 { 0x02, "fddi" }, 1550 { 0x80, "misc" }, 1551 { 0x00, NULL } 1552}; 1553 1554/* 0x03 display subclasses */ 1555static const subclass_name display_subclasses[] = 1556{ 1557 { 0x00, "vga" }, 1558 { 0x01, "xga" }, 1559 { 0x80, "misc" }, 1560 { 0x00, NULL } 1561}; 1562 1563/* 0x04 multimedia subclasses */ 1564static const subclass_name multimedia_subclasses[] = 1565{ 1566 { 0x00, "video" }, 1567 { 0x01, "audio" }, 1568 { 0x80, "misc" }, 1569 { 0x00, NULL } 1570}; 1571 1572/* 0x05 memory subclasses */ 1573static const subclass_name memory_subclasses[] = 1574{ 1575 { 0x00, "ram" }, 1576 { 0x01, "flash" }, 1577 { 0x80, "misc" }, 1578 { 0x00, NULL } 1579}; 1580 1581/* 0x06 bridge subclasses */ 1582static const subclass_name bridge_subclasses[] = 1583{ 1584 { 0x00, "host" }, 1585 { 0x01, "isa" }, 1586 { 0x02, "eisa" }, 1587 { 0x03, "mc" }, 1588 { 0x04, "pci" }, 1589 { 0x05, "pcmcia"}, 1590 { 0x80, "misc" }, 1591 { 0x00, NULL } 1592}; 1593 1594static const subclass_name *const subclasses[] = { 1595 old_subclasses, 1596 storage_subclasses, 1597 network_subclasses, 1598 display_subclasses, 1599 multimedia_subclasses, 1600 memory_subclasses, 1601 bridge_subclasses, 1602}; 1603 1604static const char *const majclasses[] = { 1605 "old", 1606 "storage", 1607 "network", 1608 "display", 1609 "multimedia", 1610 "memory", 1611 "bridge" 1612}; 1613 1614 1615void not_supported (pcici_t tag, u_long type) 1616{ 1617 u_char reg; 1618 u_long data; 1619 struct vt * vp; 1620 1621 /* 1622 ** lookup the names. 1623 */ 1624 1625 for (vp=VendorTable; vp->ident; vp++) 1626 if (vp->ident == (type & 0xffff)) 1627 break; 1628 1629 /* 1630 ** and display them. 1631 */ 1632 1633 if (vp->ident) printf (vp->name); 1634 else printf ("vendor=0x%04lx", type & 0xffff); 1635 1636 printf (", device=0x%04lx", type >> 16); 1637 1638 data = (pcibus->pb_read(tag, PCI_CLASS_REG) >> 24) & 0xff; 1639 if (data < sizeof(majclasses) / sizeof(majclasses[0])) 1640 printf(", class=%s", majclasses[data]); 1641 if (data < sizeof(subclasses) / sizeof(subclasses[0])) { 1642 const subclass_name *p = subclasses[data]; 1643 1644 data = (pcibus->pb_read(tag, PCI_CLASS_REG) >> 16) & 0xff; 1645 while (p->name && (p->subclass != data)) 1646 p++; 1647 if (p->name) { 1648 printf(" (%s)", p->name); 1649 } else { 1650 printf(" (unknown subclass 0x%02lx)", data); 1651 } 1652 } 1653 1654 printf (" [no driver assigned]\n"); 1655 1656 if (bootverbose) { 1657 for (reg=PCI_MAP_REG_START; reg<PCI_MAP_REG_END; reg+=4) { 1658 data = pcibus->pb_read (tag, reg); 1659 if ((data&~7)==0) continue; 1660 switch (data&7) { 1661 1662 case 1: 1663 case 5: 1664 printf (" map(%x): io(%lx)\n", 1665 reg, data & ~3); 1666 break; 1667 case 0: 1668 printf (" map(%x): mem32(%lx)\n", 1669 reg, data & ~7); 1670 break; 1671 case 2: 1672 printf (" map(%x): mem20(%lx)\n", 1673 reg, data & ~7); 1674 break; 1675 case 4: 1676 printf (" map(%x): mem64(%lx)\n", 1677 reg, data & ~7); 1678 break; 1679 } 1680 } 1681 } 1682} 1683#endif /* NPCI */ 1684