pci.c revision 130585
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 130585 2004-06-16 09:47:26Z phk $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static uint32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68 69static int pci_porten(device_t pcib, int b, int s, int f); 70static int pci_memen(device_t pcib, int b, int s, int f); 71static int pci_add_map(device_t pcib, device_t bus, device_t dev, 72 int b, int s, int f, int reg, 73 struct resource_list *rl); 74static void pci_add_resources(device_t pcib, device_t bus, 75 device_t dev); 76static int pci_probe(device_t dev); 77static int pci_attach(device_t dev); 78static void pci_load_vendor_data(void); 79static int pci_describe_parse_line(char **ptr, int *vendor, 80 int *device, char **desc); 81static char *pci_describe_device(device_t dev); 82static int pci_modevent(module_t mod, int what, void *arg); 83static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 84 pcicfgregs *cfg); 85static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 86static void pci_cfg_restore(device_t, struct pci_devinfo *); 87static void pci_cfg_save(device_t, struct pci_devinfo *, int); 88 89static device_method_t pci_methods[] = { 90 /* Device interface */ 91 DEVMETHOD(device_probe, pci_probe), 92 DEVMETHOD(device_attach, pci_attach), 93 DEVMETHOD(device_shutdown, bus_generic_shutdown), 94 DEVMETHOD(device_suspend, pci_suspend), 95 DEVMETHOD(device_resume, pci_resume), 96 97 /* Bus interface */ 98 DEVMETHOD(bus_print_child, pci_print_child), 99 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 100 DEVMETHOD(bus_read_ivar, pci_read_ivar), 101 DEVMETHOD(bus_write_ivar, pci_write_ivar), 102 DEVMETHOD(bus_driver_added, pci_driver_added), 103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 105 106 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 107 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 108 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 109 DEVMETHOD(bus_delete_resource, pci_delete_resource), 110 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 111 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 112 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 113 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 114 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 115 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 116 117 /* PCI interface */ 118 DEVMETHOD(pci_read_config, pci_read_config_method), 119 DEVMETHOD(pci_write_config, pci_write_config_method), 120 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 121 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 122 DEVMETHOD(pci_enable_io, pci_enable_io_method), 123 DEVMETHOD(pci_disable_io, pci_disable_io_method), 124 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 125 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 126 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 127 128 { 0, 0 } 129}; 130 131DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 132 133devclass_t pci_devclass; 134DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 135MODULE_VERSION(pci, 1); 136 137static char *pci_vendordata; 138static size_t pci_vendordata_size; 139 140 141struct pci_quirk { 142 uint32_t devid; /* Vendor/device of the card */ 143 int type; 144#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 145 int arg1; 146 int arg2; 147}; 148 149struct pci_quirk pci_quirks[] = { 150 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 151 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 153 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 154 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 155 156 { 0 } 157}; 158 159/* map register information */ 160#define PCI_MAPMEM 0x01 /* memory map */ 161#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 162#define PCI_MAPPORT 0x04 /* port map */ 163 164struct devlist pci_devq; 165uint32_t pci_generation; 166uint32_t pci_numdevs = 0; 167 168/* sysctl vars */ 169SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 170 171static int pci_enable_io_modes = 1; 172TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 173SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 174 &pci_enable_io_modes, 1, 175 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 176enable these bits correctly. We'd like to do this all the time, but there\n\ 177are some peripherals that this causes problems with."); 178 179static int pci_do_powerstate = 0; 180TUNABLE_INT("hw.pci.do_powerstate", (int *)&pci_do_powerstate); 181SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 182 &pci_do_powerstate, 0, 183 "Power down devices into D3 state when no driver attaches to them.\n\ 184Otherwise, leave the device in D0 state when no driver attaches."); 185 186/* Find a device_t by bus/slot/function */ 187 188device_t 189pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 190{ 191 struct pci_devinfo *dinfo; 192 193 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 194 if ((dinfo->cfg.bus == bus) && 195 (dinfo->cfg.slot == slot) && 196 (dinfo->cfg.func == func)) { 197 return (dinfo->cfg.dev); 198 } 199 } 200 201 return (NULL); 202} 203 204/* Find a device_t by vendor/device ID */ 205 206device_t 207pci_find_device(uint16_t vendor, uint16_t device) 208{ 209 struct pci_devinfo *dinfo; 210 211 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 212 if ((dinfo->cfg.vendor == vendor) && 213 (dinfo->cfg.device == device)) { 214 return (dinfo->cfg.dev); 215 } 216 } 217 218 return (NULL); 219} 220 221/* return base address of memory or port map */ 222 223static uint32_t 224pci_mapbase(unsigned mapreg) 225{ 226 int mask = 0x03; 227 if ((mapreg & 0x01) == 0) 228 mask = 0x0f; 229 return (mapreg & ~mask); 230} 231 232/* return map type of memory or port map */ 233 234static int 235pci_maptype(unsigned mapreg) 236{ 237 static uint8_t maptype[0x10] = { 238 PCI_MAPMEM, PCI_MAPPORT, 239 PCI_MAPMEM, 0, 240 PCI_MAPMEM, PCI_MAPPORT, 241 0, 0, 242 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 243 PCI_MAPMEM|PCI_MAPMEMP, 0, 244 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 245 0, 0, 246 }; 247 248 return maptype[mapreg & 0x0f]; 249} 250 251/* return log2 of map size decoded for memory or port map */ 252 253static int 254pci_mapsize(unsigned testval) 255{ 256 int ln2size; 257 258 testval = pci_mapbase(testval); 259 ln2size = 0; 260 if (testval != 0) { 261 while ((testval & 1) == 0) 262 { 263 ln2size++; 264 testval >>= 1; 265 } 266 } 267 return (ln2size); 268} 269 270/* return log2 of address range supported by map register */ 271 272static int 273pci_maprange(unsigned mapreg) 274{ 275 int ln2range = 0; 276 switch (mapreg & 0x07) { 277 case 0x00: 278 case 0x01: 279 case 0x05: 280 ln2range = 32; 281 break; 282 case 0x02: 283 ln2range = 20; 284 break; 285 case 0x04: 286 ln2range = 64; 287 break; 288 } 289 return (ln2range); 290} 291 292/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 293 294static void 295pci_fixancient(pcicfgregs *cfg) 296{ 297 if (cfg->hdrtype != 0) 298 return; 299 300 /* PCI to PCI bridges use header type 1 */ 301 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 302 cfg->hdrtype = 1; 303} 304 305/* extract header type specific config data */ 306 307static void 308pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 309{ 310#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 311 switch (cfg->hdrtype) { 312 case 0: 313 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 314 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 315 cfg->nummaps = PCI_MAXMAPS_0; 316 break; 317 case 1: 318 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 319 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 320 cfg->nummaps = PCI_MAXMAPS_1; 321 break; 322 case 2: 323 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 324 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 325 cfg->nummaps = PCI_MAXMAPS_2; 326 break; 327 } 328#undef REG 329} 330 331/* read configuration header into pcicfgregs structure */ 332 333struct pci_devinfo * 334pci_read_device(device_t pcib, int b, int s, int f, size_t size) 335{ 336#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 337 pcicfgregs *cfg = NULL; 338 struct pci_devinfo *devlist_entry; 339 struct devlist *devlist_head; 340 341 devlist_head = &pci_devq; 342 343 devlist_entry = NULL; 344 345 if (REG(PCIR_DEVVENDOR, 4) != -1) { 346 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 347 if (devlist_entry == NULL) 348 return (NULL); 349 350 cfg = &devlist_entry->cfg; 351 352 cfg->bus = b; 353 cfg->slot = s; 354 cfg->func = f; 355 cfg->vendor = REG(PCIR_VENDOR, 2); 356 cfg->device = REG(PCIR_DEVICE, 2); 357 cfg->cmdreg = REG(PCIR_COMMAND, 2); 358 cfg->statreg = REG(PCIR_STATUS, 2); 359 cfg->baseclass = REG(PCIR_CLASS, 1); 360 cfg->subclass = REG(PCIR_SUBCLASS, 1); 361 cfg->progif = REG(PCIR_PROGIF, 1); 362 cfg->revid = REG(PCIR_REVID, 1); 363 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 364 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 365 cfg->lattimer = REG(PCIR_LATTIMER, 1); 366 cfg->intpin = REG(PCIR_INTPIN, 1); 367 cfg->intline = REG(PCIR_INTLINE, 1); 368 369 cfg->mingnt = REG(PCIR_MINGNT, 1); 370 cfg->maxlat = REG(PCIR_MAXLAT, 1); 371 372 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 373 cfg->hdrtype &= ~PCIM_MFDEV; 374 375 pci_fixancient(cfg); 376 pci_hdrtypedata(pcib, b, s, f, cfg); 377 378 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 379 pci_read_extcap(pcib, cfg); 380 381 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 382 383 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 384 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 385 devlist_entry->conf.pc_sel.pc_func = cfg->func; 386 devlist_entry->conf.pc_hdr = cfg->hdrtype; 387 388 devlist_entry->conf.pc_subvendor = cfg->subvendor; 389 devlist_entry->conf.pc_subdevice = cfg->subdevice; 390 devlist_entry->conf.pc_vendor = cfg->vendor; 391 devlist_entry->conf.pc_device = cfg->device; 392 393 devlist_entry->conf.pc_class = cfg->baseclass; 394 devlist_entry->conf.pc_subclass = cfg->subclass; 395 devlist_entry->conf.pc_progif = cfg->progif; 396 devlist_entry->conf.pc_revid = cfg->revid; 397 398 pci_numdevs++; 399 pci_generation++; 400 } 401 return (devlist_entry); 402#undef REG 403} 404 405static void 406pci_read_extcap(device_t pcib, pcicfgregs *cfg) 407{ 408#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 409 int ptr, nextptr, ptrptr; 410 411 switch (cfg->hdrtype & PCIM_HDRTYPE) { 412 case 0: 413 ptrptr = PCIR_CAP_PTR; 414 break; 415 case 2: 416 ptrptr = 0x14; 417 break; 418 default: 419 return; /* no extended capabilities support */ 420 } 421 nextptr = REG(ptrptr, 1); /* sanity check? */ 422 423 /* 424 * Read capability entries. 425 */ 426 while (nextptr != 0) { 427 /* Sanity check */ 428 if (nextptr > 255) { 429 printf("illegal PCI extended capability offset %d\n", 430 nextptr); 431 return; 432 } 433 /* Find the next entry */ 434 ptr = nextptr; 435 nextptr = REG(ptr + 1, 1); 436 437 /* Process this entry */ 438 switch (REG(ptr, 1)) { 439 case PCIY_PMG: /* PCI power management */ 440 if (cfg->pp.pp_cap == 0) { 441 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 442 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 443 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 444 if ((nextptr - ptr) > PCIR_POWER_DATA) 445 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 446 } 447 break; 448 case PCIY_MSI: /* PCI MSI */ 449 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 450 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 451 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 452 else 453 cfg->msi.msi_data = PCIR_MSI_DATA; 454 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 455 PCIM_MSICTRL_MMC_MASK)>>1); 456 default: 457 break; 458 } 459 } 460#undef REG 461} 462 463/* free pcicfgregs structure and all depending data structures */ 464 465int 466pci_freecfg(struct pci_devinfo *dinfo) 467{ 468 struct devlist *devlist_head; 469 470 devlist_head = &pci_devq; 471 472 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 473 free(dinfo, M_DEVBUF); 474 475 /* increment the generation count */ 476 pci_generation++; 477 478 /* we're losing one device */ 479 pci_numdevs--; 480 return (0); 481} 482 483/* 484 * PCI power manangement 485 */ 486int 487pci_set_powerstate_method(device_t dev, device_t child, int state) 488{ 489 struct pci_devinfo *dinfo = device_get_ivars(child); 490 pcicfgregs *cfg = &dinfo->cfg; 491 uint16_t status; 492 int result; 493 494 /* 495 * Dx -> Dx is a nop always. 496 */ 497 if (pci_get_powerstate(child) == state) 498 return (0); 499 500 if (cfg->pp.pp_cap != 0) { 501 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 502 & ~PCIM_PSTAT_DMASK; 503 result = 0; 504 switch (state) { 505 case PCI_POWERSTATE_D0: 506 status |= PCIM_PSTAT_D0; 507 break; 508 case PCI_POWERSTATE_D1: 509 if (cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) { 510 status |= PCIM_PSTAT_D1; 511 } else { 512 result = EOPNOTSUPP; 513 } 514 break; 515 case PCI_POWERSTATE_D2: 516 if (cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) { 517 status |= PCIM_PSTAT_D2; 518 } else { 519 result = EOPNOTSUPP; 520 } 521 break; 522 case PCI_POWERSTATE_D3: 523 status |= PCIM_PSTAT_D3; 524 break; 525 default: 526 result = EINVAL; 527 } 528 if (result == 0) 529 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 530 2); 531 } else { 532 result = ENXIO; 533 } 534 return(result); 535} 536 537int 538pci_get_powerstate_method(device_t dev, device_t child) 539{ 540 struct pci_devinfo *dinfo = device_get_ivars(child); 541 pcicfgregs *cfg = &dinfo->cfg; 542 uint16_t status; 543 int result; 544 545 if (cfg->pp.pp_cap != 0) { 546 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 547 switch (status & PCIM_PSTAT_DMASK) { 548 case PCIM_PSTAT_D0: 549 result = PCI_POWERSTATE_D0; 550 break; 551 case PCIM_PSTAT_D1: 552 result = PCI_POWERSTATE_D1; 553 break; 554 case PCIM_PSTAT_D2: 555 result = PCI_POWERSTATE_D2; 556 break; 557 case PCIM_PSTAT_D3: 558 result = PCI_POWERSTATE_D3; 559 break; 560 default: 561 result = PCI_POWERSTATE_UNKNOWN; 562 break; 563 } 564 } else { 565 /* No support, device is always at D0 */ 566 result = PCI_POWERSTATE_D0; 567 } 568 return(result); 569} 570 571/* 572 * Some convenience functions for PCI device drivers. 573 */ 574 575static __inline void 576pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 577{ 578 uint16_t command; 579 580 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 581 command |= bit; 582 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 583} 584 585static __inline void 586pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 587{ 588 uint16_t command; 589 590 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 591 command &= ~bit; 592 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 593} 594 595int 596pci_enable_busmaster_method(device_t dev, device_t child) 597{ 598 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 599 return (0); 600} 601 602int 603pci_disable_busmaster_method(device_t dev, device_t child) 604{ 605 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 606 return (0); 607} 608 609int 610pci_enable_io_method(device_t dev, device_t child, int space) 611{ 612 uint16_t command; 613 uint16_t bit; 614 char *error; 615 616 bit = 0; 617 error = NULL; 618 619 switch(space) { 620 case SYS_RES_IOPORT: 621 bit = PCIM_CMD_PORTEN; 622 error = "port"; 623 break; 624 case SYS_RES_MEMORY: 625 bit = PCIM_CMD_MEMEN; 626 error = "memory"; 627 break; 628 default: 629 return (EINVAL); 630 } 631 pci_set_command_bit(dev, child, bit); 632 /* Some devices seem to need a brief stall here, what do to? */ 633 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 634 if (command & bit) 635 return (0); 636 device_printf(child, "failed to enable %s mapping!\n", error); 637 return (ENXIO); 638} 639 640int 641pci_disable_io_method(device_t dev, device_t child, int space) 642{ 643 uint16_t command; 644 uint16_t bit; 645 char *error; 646 647 bit = 0; 648 error = NULL; 649 650 switch(space) { 651 case SYS_RES_IOPORT: 652 bit = PCIM_CMD_PORTEN; 653 error = "port"; 654 break; 655 case SYS_RES_MEMORY: 656 bit = PCIM_CMD_MEMEN; 657 error = "memory"; 658 break; 659 default: 660 return (EINVAL); 661 } 662 pci_clear_command_bit(dev, child, bit); 663 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 664 if (command & bit) { 665 device_printf(child, "failed to disable %s mapping!\n", error); 666 return (ENXIO); 667 } 668 return (0); 669} 670 671/* 672 * New style pci driver. Parent device is either a pci-host-bridge or a 673 * pci-pci-bridge. Both kinds are represented by instances of pcib. 674 */ 675 676void 677pci_print_verbose(struct pci_devinfo *dinfo) 678{ 679 if (bootverbose) { 680 pcicfgregs *cfg = &dinfo->cfg; 681 682 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 683 cfg->vendor, cfg->device, cfg->revid); 684 printf("\tbus=%d, slot=%d, func=%d\n", 685 cfg->bus, cfg->slot, cfg->func); 686 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 687 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 688 cfg->mfdev); 689 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 690 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 691 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 692 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 693 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 694 if (cfg->intpin > 0) 695 printf("\tintpin=%c, irq=%d\n", 696 cfg->intpin +'a' -1, cfg->intline); 697 if (cfg->pp.pp_cap) { 698 uint16_t status; 699 700 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 701 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 702 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 703 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 704 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 705 status & PCIM_PSTAT_DMASK); 706 } 707 if (cfg->msi.msi_data) { 708 int ctrl; 709 710 ctrl = cfg->msi.msi_ctrl; 711 printf("\tMSI supports %d message%s%s%s\n", 712 cfg->msi.msi_msgnum, 713 (cfg->msi.msi_msgnum == 1) ? "" : "s", 714 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 715 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 716 } 717 } 718} 719 720static int 721pci_porten(device_t pcib, int b, int s, int f) 722{ 723 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 724 & PCIM_CMD_PORTEN) != 0; 725} 726 727static int 728pci_memen(device_t pcib, int b, int s, int f) 729{ 730 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 731 & PCIM_CMD_MEMEN) != 0; 732} 733 734/* 735 * Add a resource based on a pci map register. Return 1 if the map 736 * register is a 32bit map register or 2 if it is a 64bit register. 737 */ 738static int 739pci_add_map(device_t pcib, device_t bus, device_t dev, 740 int b, int s, int f, int reg, struct resource_list *rl) 741{ 742 uint32_t map; 743 uint64_t base; 744 uint64_t start, end, count; 745 uint8_t ln2size; 746 uint8_t ln2range; 747 uint32_t testval; 748 uint16_t cmd; 749 int type; 750 751 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 752 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 753 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 754 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 755 756 if (pci_maptype(map) & PCI_MAPMEM) 757 type = SYS_RES_MEMORY; 758 else 759 type = SYS_RES_IOPORT; 760 ln2size = pci_mapsize(testval); 761 ln2range = pci_maprange(testval); 762 base = pci_mapbase(map); 763 764 /* 765 * For I/O registers, if bottom bit is set, and the next bit up 766 * isn't clear, we know we have a BAR that doesn't conform to the 767 * spec, so ignore it. Also, sanity check the size of the data 768 * areas to the type of memory involved. Memory must be at least 769 * 32 bytes in size, while I/O ranges must be at least 4. 770 */ 771 if ((testval & 0x1) == 0x1 && 772 (testval & 0x2) != 0) 773 return (1); 774 if ((type == SYS_RES_MEMORY && ln2size < 5) || 775 (type == SYS_RES_IOPORT && ln2size < 2)) 776 return (1); 777 778 if (ln2range == 64) 779 /* Read the other half of a 64bit map register */ 780 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 781 782 if (bootverbose) { 783 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 784 reg, pci_maptype(map), ln2range, 785 (unsigned int) base, ln2size); 786 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 787 printf(", port disabled\n"); 788 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 789 printf(", memory disabled\n"); 790 else 791 printf(", enabled\n"); 792 } 793 794 /* 795 * This code theoretically does the right thing, but has 796 * undesirable side effects in some cases where peripherals 797 * respond oddly to having these bits enabled. Let the user 798 * be able to turn them off (since pci_enable_io_modes is 1 by 799 * default). 800 */ 801 if (pci_enable_io_modes) { 802 /* Turn on resources that have been left off by a lazy BIOS */ 803 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 804 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 805 cmd |= PCIM_CMD_PORTEN; 806 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 807 } 808 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 809 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 810 cmd |= PCIM_CMD_MEMEN; 811 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 812 } 813 } else { 814 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 815 return (1); 816 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 817 return (1); 818 } 819 /* 820 * If base is 0, then we have problems. It is best to ignore 821 * such entires for the moment. These will be allocated later if 822 * the driver specifically requests them. 823 */ 824 if (base == 0) 825 return 1; 826 827 start = base; 828 end = base + (1 << ln2size) - 1; 829 count = 1 << ln2size; 830 resource_list_add(rl, type, reg, start, end, count); 831 832 /* 833 * Not quite sure what to do on failure of allocating the resource 834 * since I can postulate several right answers. 835 */ 836 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 837 return ((ln2range == 64) ? 2 : 1); 838} 839 840static int 841pci_is_ata_legacy(device_t dev) 842{ 843 /* 844 * ATA PCI in compatibility mode are hard wired to certain 845 * compatibility addresses. Such entries does not contain 846 * valid resources as they are at fixed positions to be 847 * compatible with old ISA requirements. 848 */ 849 if ((pci_get_class(dev) == PCIC_STORAGE) && 850 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 851 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 852 return 1; 853 return 0; 854} 855 856/* 857 * The ATA PCI spec specifies that in legacy mode, the device shall 858 * decode the resources listed below. The ata driver allocates 859 * resources in this order, and many atapci devices actually have 860 * values similar to these in the actual underlying bars. Part of the 861 * problem is that the floppy controller and ata overlap for 1 byte, 862 * which makes it difficult to properly allocate things. 863 * 864 * My reading of the pci spec is such that this appears to be the only 865 * allowed exception to the rule that devices only decode the addresses 866 * presented in their BARs. We also ensure that the bits that take 867 * the device out of legacy mode are set to 0 before making this 868 * reservation. 869 */ 870static void 871pci_add_ata_legacy_maps(device_t pcib, device_t bus, device_t dev, int b, 872 int s, int f, struct resource_list *rl) 873{ 874 int rid; 875 int type; 876 877 type = SYS_RES_IOPORT; 878 if ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MODEPRIM) == 0) { 879 rid = PCIR_BAR(0); 880 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 881 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 882 0); 883 rid = PCIR_BAR(1); 884 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 885 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 886 0); 887 } else { 888 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 889 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 890 } 891 if ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MODESEC) == 0) { 892 rid = PCIR_BAR(2); 893 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 894 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 895 0); 896 rid = PCIR_BAR(3); 897 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 898 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 899 0); 900 } else { 901 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 902 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 903 } 904 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 905} 906 907static void 908pci_add_resources(device_t pcib, device_t bus, device_t dev) 909{ 910 struct pci_devinfo *dinfo = device_get_ivars(dev); 911 pcicfgregs *cfg = &dinfo->cfg; 912 struct resource_list *rl = &dinfo->resources; 913 struct pci_quirk *q; 914 int b, i, irq, f, s; 915 916 b = cfg->bus; 917 s = cfg->slot; 918 f = cfg->func; 919 920 if (pci_is_ata_legacy(dev)) 921 pci_add_ata_legacy_maps(pcib, bus, dev, b, s, f, rl); 922 else 923 for (i = 0; i < cfg->nummaps;) 924 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 925 rl); 926 927 for (q = &pci_quirks[0]; q->devid; q++) { 928 if (q->devid == ((cfg->device << 16) | cfg->vendor) 929 && q->type == PCI_QUIRK_MAP_REG) 930 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 931 } 932 933 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 934#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) 935 /* 936 * Try to re-route interrupts. Sometimes the BIOS or 937 * firmware may leave bogus values in these registers. 938 * If the re-route fails, then just stick with what we 939 * have. 940 */ 941 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 942 if (PCI_INTERRUPT_VALID(irq)) { 943 pci_write_config(dev, PCIR_INTLINE, irq, 1); 944 cfg->intline = irq; 945 } else 946#endif 947 irq = cfg->intline; 948 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 949 } 950} 951 952void 953pci_add_children(device_t dev, int busno, size_t dinfo_size) 954{ 955#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 956 device_t pcib = device_get_parent(dev); 957 struct pci_devinfo *dinfo; 958 int maxslots; 959 int s, f, pcifunchigh; 960 uint8_t hdrtype; 961 962 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 963 ("dinfo_size too small")); 964 maxslots = PCIB_MAXSLOTS(pcib); 965 for (s = 0; s <= maxslots; s++) { 966 pcifunchigh = 0; 967 f = 0; 968 hdrtype = REG(PCIR_HDRTYPE, 1); 969 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 970 continue; 971 if (hdrtype & PCIM_MFDEV) 972 pcifunchigh = PCI_FUNCMAX; 973 for (f = 0; f <= pcifunchigh; f++) { 974 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 975 if (dinfo != NULL) { 976 pci_add_child(dev, dinfo); 977 } 978 } 979 } 980#undef REG 981} 982 983void 984pci_add_child(device_t bus, struct pci_devinfo *dinfo) 985{ 986 device_t pcib; 987 988 pcib = device_get_parent(bus); 989 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 990 device_set_ivars(dinfo->cfg.dev, dinfo); 991 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 992 pci_cfg_restore(dinfo->cfg.dev, dinfo); 993 pci_add_resources(pcib, bus, dinfo->cfg.dev); 994 pci_print_verbose(dinfo); 995} 996 997static int 998pci_probe(device_t dev) 999{ 1000 1001 device_set_desc(dev, "PCI bus"); 1002 1003 /* Allow other subclasses to override this driver. */ 1004 return (-1000); 1005} 1006 1007static int 1008pci_attach(device_t dev) 1009{ 1010 int busno; 1011 1012 /* 1013 * Since there can be multiple independantly numbered PCI 1014 * busses on some large alpha systems, we can't use the unit 1015 * number to decide what bus we are probing. We ask the parent 1016 * pcib what our bus number is. 1017 */ 1018 busno = pcib_get_bus(dev); 1019 if (bootverbose) 1020 device_printf(dev, "physical bus=%d\n", busno); 1021 1022 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1023 1024 return (bus_generic_attach(dev)); 1025} 1026 1027int 1028pci_suspend(device_t dev) 1029{ 1030 int numdevs; 1031 device_t *devlist; 1032 device_t child; 1033 struct pci_devinfo *dinfo; 1034 int i; 1035 1036 /* 1037 * Save the pci configuration space for each child. We don't need 1038 * to do this, unless the BIOS suspend code powers down the bus and 1039 * the devices on the bus. 1040 */ 1041 device_get_children(dev, &devlist, &numdevs); 1042 for (i = 0; i < numdevs; i++) { 1043 child = devlist[i]; 1044 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1045 pci_cfg_save(child, dinfo, 0); 1046 } 1047 free(devlist, M_TEMP); 1048 return (bus_generic_suspend(dev)); 1049} 1050 1051int 1052pci_resume(device_t dev) 1053{ 1054 int numdevs; 1055 device_t *devlist; 1056 device_t child; 1057 struct pci_devinfo *dinfo; 1058 int i; 1059 1060 /* 1061 * Restore the pci configuration space for each child. 1062 */ 1063 device_get_children(dev, &devlist, &numdevs); 1064 for (i = 0; i < numdevs; i++) { 1065 child = devlist[i]; 1066 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1067 pci_cfg_restore(child, dinfo); 1068 } 1069 free(devlist, M_TEMP); 1070 return (bus_generic_resume(dev)); 1071} 1072 1073static void 1074pci_load_vendor_data(void) 1075{ 1076 caddr_t vendordata, info; 1077 1078 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1079 info = preload_search_info(vendordata, MODINFO_ADDR); 1080 pci_vendordata = *(char **)info; 1081 info = preload_search_info(vendordata, MODINFO_SIZE); 1082 pci_vendordata_size = *(size_t *)info; 1083 /* terminate the database */ 1084 pci_vendordata[pci_vendordata_size] = '\n'; 1085 } 1086} 1087 1088void 1089pci_driver_added(device_t dev, driver_t *driver) 1090{ 1091 int numdevs; 1092 device_t *devlist; 1093 device_t child; 1094 struct pci_devinfo *dinfo; 1095 int i; 1096 1097 if (bootverbose) 1098 device_printf(dev, "driver added\n"); 1099 DEVICE_IDENTIFY(driver, dev); 1100 device_get_children(dev, &devlist, &numdevs); 1101 for (i = 0; i < numdevs; i++) { 1102 child = devlist[i]; 1103 if (device_get_state(child) != DS_NOTPRESENT) 1104 continue; 1105 dinfo = device_get_ivars(child); 1106 pci_print_verbose(dinfo); 1107/*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */ 1108 if (bootverbose) 1109 printf("pci%d:%d:%d: reprobing on driver added\n", 1110 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1111 pci_cfg_restore(child, dinfo); 1112 if (device_probe_and_attach(child) != 0) 1113 pci_cfg_save(child, dinfo, 1); 1114 } 1115 free(devlist, M_TEMP); 1116} 1117 1118int 1119pci_print_child(device_t dev, device_t child) 1120{ 1121 struct pci_devinfo *dinfo; 1122 struct resource_list *rl; 1123 int retval = 0; 1124 1125 dinfo = device_get_ivars(child); 1126 rl = &dinfo->resources; 1127 1128 retval += bus_print_child_header(dev, child); 1129 1130 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1131 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1132 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1133 if (device_get_flags(dev)) 1134 retval += printf(" flags %#x", device_get_flags(dev)); 1135 1136 retval += printf(" at device %d.%d", pci_get_slot(child), 1137 pci_get_function(child)); 1138 1139 retval += bus_print_child_footer(dev, child); 1140 1141 return (retval); 1142} 1143 1144static struct 1145{ 1146 int class; 1147 int subclass; 1148 char *desc; 1149} pci_nomatch_tab[] = { 1150 {PCIC_OLD, -1, "old"}, 1151 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1152 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1153 {PCIC_STORAGE, -1, "mass storage"}, 1154 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1155 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1156 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1157 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1158 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1159 {PCIC_NETWORK, -1, "network"}, 1160 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1161 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1162 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1163 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1164 {PCIC_DISPLAY, -1, "display"}, 1165 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1166 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1167 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1168 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1169 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1170 {PCIC_MEMORY, -1, "memory"}, 1171 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1172 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1173 {PCIC_BRIDGE, -1, "bridge"}, 1174 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1175 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1176 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1177 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1178 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1179 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1180 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1181 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1182 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1183 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1184 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1185 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1186 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1187 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1188 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1189 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1190 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1191 {PCIC_INPUTDEV, -1, "input device"}, 1192 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1193 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1194 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1195 {PCIC_DOCKING, -1, "docking station"}, 1196 {PCIC_PROCESSOR, -1, "processor"}, 1197 {PCIC_SERIALBUS, -1, "serial bus"}, 1198 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1199 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1200 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1201 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1202 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1203 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1204 {0, 0, NULL} 1205}; 1206 1207void 1208pci_probe_nomatch(device_t dev, device_t child) 1209{ 1210 int i; 1211 char *cp, *scp, *device; 1212 1213 /* 1214 * Look for a listing for this device in a loaded device database. 1215 */ 1216 if ((device = pci_describe_device(child)) != NULL) { 1217 device_printf(dev, "<%s>", device); 1218 free(device, M_DEVBUF); 1219 } else { 1220 /* 1221 * Scan the class/subclass descriptions for a general 1222 * description. 1223 */ 1224 cp = "unknown"; 1225 scp = NULL; 1226 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1227 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1228 if (pci_nomatch_tab[i].subclass == -1) { 1229 cp = pci_nomatch_tab[i].desc; 1230 } else if (pci_nomatch_tab[i].subclass == 1231 pci_get_subclass(child)) { 1232 scp = pci_nomatch_tab[i].desc; 1233 } 1234 } 1235 } 1236 device_printf(dev, "<%s%s%s>", 1237 cp ? cp : "", 1238 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1239 scp ? scp : ""); 1240 } 1241 printf(" at device %d.%d (no driver attached)\n", 1242 pci_get_slot(child), pci_get_function(child)); 1243 if (pci_do_powerstate) 1244 pci_cfg_save(child, 1245 (struct pci_devinfo *) device_get_ivars(child), 1); 1246 return; 1247} 1248 1249/* 1250 * Parse the PCI device database, if loaded, and return a pointer to a 1251 * description of the device. 1252 * 1253 * The database is flat text formatted as follows: 1254 * 1255 * Any line not in a valid format is ignored. 1256 * Lines are terminated with newline '\n' characters. 1257 * 1258 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1259 * the vendor name. 1260 * 1261 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1262 * - devices cannot be listed without a corresponding VENDOR line. 1263 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1264 * another TAB, then the device name. 1265 */ 1266 1267/* 1268 * Assuming (ptr) points to the beginning of a line in the database, 1269 * return the vendor or device and description of the next entry. 1270 * The value of (vendor) or (device) inappropriate for the entry type 1271 * is set to -1. Returns nonzero at the end of the database. 1272 * 1273 * Note that this is slightly unrobust in the face of corrupt data; 1274 * we attempt to safeguard against this by spamming the end of the 1275 * database with a newline when we initialise. 1276 */ 1277static int 1278pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1279{ 1280 char *cp = *ptr; 1281 int left; 1282 1283 *device = -1; 1284 *vendor = -1; 1285 **desc = '\0'; 1286 for (;;) { 1287 left = pci_vendordata_size - (cp - pci_vendordata); 1288 if (left <= 0) { 1289 *ptr = cp; 1290 return(1); 1291 } 1292 1293 /* vendor entry? */ 1294 if (*cp != '\t' && 1295 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1296 break; 1297 /* device entry? */ 1298 if (*cp == '\t' && 1299 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1300 break; 1301 1302 /* skip to next line */ 1303 while (*cp != '\n' && left > 0) { 1304 cp++; 1305 left--; 1306 } 1307 if (*cp == '\n') { 1308 cp++; 1309 left--; 1310 } 1311 } 1312 /* skip to next line */ 1313 while (*cp != '\n' && left > 0) { 1314 cp++; 1315 left--; 1316 } 1317 if (*cp == '\n' && left > 0) 1318 cp++; 1319 *ptr = cp; 1320 return(0); 1321} 1322 1323static char * 1324pci_describe_device(device_t dev) 1325{ 1326 int vendor, device; 1327 char *desc, *vp, *dp, *line; 1328 1329 desc = vp = dp = NULL; 1330 1331 /* 1332 * If we have no vendor data, we can't do anything. 1333 */ 1334 if (pci_vendordata == NULL) 1335 goto out; 1336 1337 /* 1338 * Scan the vendor data looking for this device 1339 */ 1340 line = pci_vendordata; 1341 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1342 goto out; 1343 for (;;) { 1344 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1345 goto out; 1346 if (vendor == pci_get_vendor(dev)) 1347 break; 1348 } 1349 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1350 goto out; 1351 for (;;) { 1352 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1353 *dp = 0; 1354 break; 1355 } 1356 if (vendor != -1) { 1357 *dp = 0; 1358 break; 1359 } 1360 if (device == pci_get_device(dev)) 1361 break; 1362 } 1363 if (dp[0] == '\0') 1364 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1365 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1366 NULL) 1367 sprintf(desc, "%s, %s", vp, dp); 1368 out: 1369 if (vp != NULL) 1370 free(vp, M_DEVBUF); 1371 if (dp != NULL) 1372 free(dp, M_DEVBUF); 1373 return(desc); 1374} 1375 1376int 1377pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1378{ 1379 struct pci_devinfo *dinfo; 1380 pcicfgregs *cfg; 1381 1382 dinfo = device_get_ivars(child); 1383 cfg = &dinfo->cfg; 1384 1385 switch (which) { 1386 case PCI_IVAR_ETHADDR: 1387 /* 1388 * The generic accessor doesn't deal with failure, so 1389 * we set the return value, then return an error. 1390 */ 1391 *((uint8_t **) result) = NULL; 1392 return (EINVAL); 1393 case PCI_IVAR_SUBVENDOR: 1394 *result = cfg->subvendor; 1395 break; 1396 case PCI_IVAR_SUBDEVICE: 1397 *result = cfg->subdevice; 1398 break; 1399 case PCI_IVAR_VENDOR: 1400 *result = cfg->vendor; 1401 break; 1402 case PCI_IVAR_DEVICE: 1403 *result = cfg->device; 1404 break; 1405 case PCI_IVAR_DEVID: 1406 *result = (cfg->device << 16) | cfg->vendor; 1407 break; 1408 case PCI_IVAR_CLASS: 1409 *result = cfg->baseclass; 1410 break; 1411 case PCI_IVAR_SUBCLASS: 1412 *result = cfg->subclass; 1413 break; 1414 case PCI_IVAR_PROGIF: 1415 *result = cfg->progif; 1416 break; 1417 case PCI_IVAR_REVID: 1418 *result = cfg->revid; 1419 break; 1420 case PCI_IVAR_INTPIN: 1421 *result = cfg->intpin; 1422 break; 1423 case PCI_IVAR_IRQ: 1424 *result = cfg->intline; 1425 break; 1426 case PCI_IVAR_BUS: 1427 *result = cfg->bus; 1428 break; 1429 case PCI_IVAR_SLOT: 1430 *result = cfg->slot; 1431 break; 1432 case PCI_IVAR_FUNCTION: 1433 *result = cfg->func; 1434 break; 1435 default: 1436 return (ENOENT); 1437 } 1438 return (0); 1439} 1440 1441int 1442pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1443{ 1444 struct pci_devinfo *dinfo; 1445 1446 dinfo = device_get_ivars(child); 1447 1448 switch (which) { 1449 case PCI_IVAR_INTPIN: 1450 dinfo->cfg.intpin = value; 1451 return (0); 1452 case PCI_IVAR_ETHADDR: 1453 case PCI_IVAR_SUBVENDOR: 1454 case PCI_IVAR_SUBDEVICE: 1455 case PCI_IVAR_VENDOR: 1456 case PCI_IVAR_DEVICE: 1457 case PCI_IVAR_DEVID: 1458 case PCI_IVAR_CLASS: 1459 case PCI_IVAR_SUBCLASS: 1460 case PCI_IVAR_PROGIF: 1461 case PCI_IVAR_REVID: 1462 case PCI_IVAR_IRQ: 1463 case PCI_IVAR_BUS: 1464 case PCI_IVAR_SLOT: 1465 case PCI_IVAR_FUNCTION: 1466 return (EINVAL); /* disallow for now */ 1467 1468 default: 1469 return (ENOENT); 1470 } 1471} 1472 1473 1474#include "opt_ddb.h" 1475#ifdef DDB 1476#include <ddb/ddb.h> 1477#include <sys/cons.h> 1478 1479/* 1480 * List resources based on pci map registers, used for within ddb 1481 */ 1482 1483DB_SHOW_COMMAND(pciregs, db_pci_dump) 1484{ 1485 struct pci_devinfo *dinfo; 1486 struct devlist *devlist_head; 1487 struct pci_conf *p; 1488 const char *name; 1489 int i, error, none_count, quit; 1490 1491 none_count = 0; 1492 /* get the head of the device queue */ 1493 devlist_head = &pci_devq; 1494 1495 /* 1496 * Go through the list of devices and print out devices 1497 */ 1498 db_setup_paging(db_simple_pager, &quit, DB_LINES_PER_PAGE); 1499 for (error = 0, i = 0, quit = 0, 1500 dinfo = STAILQ_FIRST(devlist_head); 1501 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1502 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1503 1504 /* Populate pd_name and pd_unit */ 1505 name = NULL; 1506 if (dinfo->cfg.dev) 1507 name = device_get_name(dinfo->cfg.dev); 1508 1509 p = &dinfo->conf; 1510 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1511 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1512 (name && *name) ? name : "none", 1513 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1514 none_count++, 1515 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1516 p->pc_sel.pc_func, (p->pc_class << 16) | 1517 (p->pc_subclass << 8) | p->pc_progif, 1518 (p->pc_subdevice << 16) | p->pc_subvendor, 1519 (p->pc_device << 16) | p->pc_vendor, 1520 p->pc_revid, p->pc_hdr); 1521 } 1522} 1523#endif /* DDB */ 1524 1525static struct resource * 1526pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1527 u_long start, u_long end, u_long count, u_int flags) 1528{ 1529 struct pci_devinfo *dinfo = device_get_ivars(child); 1530 struct resource_list *rl = &dinfo->resources; 1531 struct resource_list_entry *rle; 1532 struct resource *res; 1533 uint32_t map, testval; 1534 int mapsize; 1535 1536 /* 1537 * Weed out the bogons, and figure out how large the BAR/map 1538 * is. Bars that read back 0 here are bogus and unimplemented. 1539 * Note: atapci in legacy mode are special and handled elsewhere 1540 * in the code. If you have a atapci device in legacy mode and 1541 * it fails here, that other code is broken. 1542 */ 1543 res = NULL; 1544 map = pci_read_config(child, *rid, 4); 1545 pci_write_config(child, *rid, 0xffffffff, 4); 1546 testval = pci_read_config(child, *rid, 4); 1547 if (testval == 0) 1548 return (NULL); 1549 if (pci_maptype(testval) & PCI_MAPMEM) { 1550 if (type != SYS_RES_MEMORY) { 1551 device_printf(child, 1552 "failed: rid %#x is memory, requested %d\n", 1553 *rid, type); 1554 goto out; 1555 } 1556 } else { 1557 if (type != SYS_RES_IOPORT) { 1558 device_printf(child, 1559 "failed: rid %#x is ioport, requested %d\n", 1560 *rid, type); 1561 goto out; 1562 } 1563 } 1564 /* 1565 * For real BARs, we need to override the size that 1566 * the driver requests, because that's what the BAR 1567 * actually uses and we would otherwise have a 1568 * situation where we might allocate the excess to 1569 * another driver, which won't work. 1570 */ 1571 mapsize = pci_mapsize(testval); 1572 count = 1 << mapsize; 1573 if (RF_ALIGNMENT(flags) < mapsize) 1574 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1575 1576 /* 1577 * Allocate enough resource, and then write back the 1578 * appropriate bar for that resource. 1579 */ 1580 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1581 start, end, count, flags); 1582 if (res == NULL) { 1583 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1584 count, *rid, type); 1585 goto out; 1586 } 1587 resource_list_add(rl, type, *rid, start, end, count); 1588 rle = resource_list_find(rl, type, *rid); 1589 if (rle == NULL) 1590 panic("pci_alloc_map: unexpedly can't find resource."); 1591 rle->res = res; 1592 if (bootverbose) 1593 device_printf(child, 1594 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1595 count, *rid, type, rman_get_start(res)); 1596 map = rman_get_start(res); 1597out:; 1598 pci_write_config(child, *rid, map, 4); 1599 return (res); 1600} 1601 1602 1603struct resource * 1604pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1605 u_long start, u_long end, u_long count, u_int flags) 1606{ 1607 struct pci_devinfo *dinfo = device_get_ivars(child); 1608 struct resource_list *rl = &dinfo->resources; 1609 struct resource_list_entry *rle; 1610 pcicfgregs *cfg = &dinfo->cfg; 1611 1612 /* 1613 * Perform lazy resource allocation 1614 */ 1615 if (device_get_parent(child) == dev) { 1616 switch (type) { 1617 case SYS_RES_IRQ: 1618 /* 1619 * If the child device doesn't have an 1620 * interrupt routed and is deserving of an 1621 * interrupt, try to assign it one. 1622 */ 1623 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1624 (cfg->intpin != 0)) { 1625 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1626 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1627 pci_write_config(child, PCIR_INTLINE, 1628 cfg->intline, 1); 1629 resource_list_add(rl, SYS_RES_IRQ, 0, 1630 cfg->intline, cfg->intline, 1); 1631 } 1632 } 1633 break; 1634 case SYS_RES_IOPORT: 1635 case SYS_RES_MEMORY: 1636 if (*rid < PCIR_BAR(cfg->nummaps)) { 1637 /* 1638 * Enable the I/O mode. We should 1639 * also be assigning resources too 1640 * when none are present. The 1641 * resource_list_alloc kind of sorta does 1642 * this... 1643 */ 1644 if (PCI_ENABLE_IO(dev, child, type)) 1645 return (NULL); 1646 } 1647 rle = resource_list_find(rl, type, *rid); 1648 if (rle == NULL) 1649 return (pci_alloc_map(dev, child, type, rid, 1650 start, end, count, flags)); 1651 break; 1652 } 1653 /* 1654 * If we've already allocated the resource, then 1655 * return it now. But first we may need to activate 1656 * it, since we don't allocate the resource as active 1657 * above. Normally this would be done down in the 1658 * nexus, but since we short-circuit that path we have 1659 * to do its job here. Not sure if we should free the 1660 * resource if it fails to activate. 1661 */ 1662 rle = resource_list_find(rl, type, *rid); 1663 if (rle != NULL && rle->res != NULL) { 1664 if (bootverbose) 1665 device_printf(child, 1666 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1667 rman_get_size(rle->res), *rid, type, 1668 rman_get_start(rle->res)); 1669 if ((flags & RF_ACTIVE) && 1670 bus_generic_activate_resource(dev, child, type, 1671 *rid, rle->res) != 0) 1672 return NULL; 1673 return (rle->res); 1674 } 1675 } 1676 return (resource_list_alloc(rl, dev, child, type, rid, 1677 start, end, count, flags)); 1678} 1679 1680void 1681pci_delete_resource(device_t dev, device_t child, int type, int rid) 1682{ 1683 struct pci_devinfo *dinfo; 1684 struct resource_list *rl; 1685 struct resource_list_entry *rle; 1686 1687 if (device_get_parent(child) != dev) 1688 return; 1689 1690 dinfo = device_get_ivars(child); 1691 rl = &dinfo->resources; 1692 rle = resource_list_find(rl, type, rid); 1693 if (rle) { 1694 if (rle->res) { 1695 if (rman_get_device(rle->res) != dev || 1696 rman_get_flags(rle->res) & RF_ACTIVE) { 1697 device_printf(dev, "delete_resource: " 1698 "Resource still owned by child, oops. " 1699 "(type=%d, rid=%d, addr=%lx)\n", 1700 rle->type, rle->rid, 1701 rman_get_start(rle->res)); 1702 return; 1703 } 1704 bus_release_resource(dev, type, rid, rle->res); 1705 } 1706 resource_list_delete(rl, type, rid); 1707 } 1708 /* 1709 * Why do we turn off the PCI configuration BAR when we delete a 1710 * resource? -- imp 1711 */ 1712 pci_write_config(child, rid, 0, 4); 1713 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1714} 1715 1716struct resource_list * 1717pci_get_resource_list (device_t dev, device_t child) 1718{ 1719 struct pci_devinfo *dinfo = device_get_ivars(child); 1720 1721 return (&dinfo->resources); 1722} 1723 1724uint32_t 1725pci_read_config_method(device_t dev, device_t child, int reg, int width) 1726{ 1727 struct pci_devinfo *dinfo = device_get_ivars(child); 1728 pcicfgregs *cfg = &dinfo->cfg; 1729 1730 return (PCIB_READ_CONFIG(device_get_parent(dev), 1731 cfg->bus, cfg->slot, cfg->func, reg, width)); 1732} 1733 1734void 1735pci_write_config_method(device_t dev, device_t child, int reg, 1736 uint32_t val, int width) 1737{ 1738 struct pci_devinfo *dinfo = device_get_ivars(child); 1739 pcicfgregs *cfg = &dinfo->cfg; 1740 1741 PCIB_WRITE_CONFIG(device_get_parent(dev), 1742 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1743} 1744 1745int 1746pci_child_location_str_method(device_t dev, device_t child, char *buf, 1747 size_t buflen) 1748{ 1749 struct pci_devinfo *dinfo; 1750 1751 dinfo = device_get_ivars(child); 1752 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1753 pci_get_function(child)); 1754 return (0); 1755} 1756 1757int 1758pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1759 size_t buflen) 1760{ 1761 struct pci_devinfo *dinfo; 1762 pcicfgregs *cfg; 1763 1764 dinfo = device_get_ivars(child); 1765 cfg = &dinfo->cfg; 1766 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1767 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1768 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1769 cfg->progif); 1770 return (0); 1771} 1772 1773int 1774pci_assign_interrupt_method(device_t dev, device_t child) 1775{ 1776 struct pci_devinfo *dinfo = device_get_ivars(child); 1777 pcicfgregs *cfg = &dinfo->cfg; 1778 1779 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1780 cfg->intpin)); 1781} 1782 1783static int 1784pci_modevent(module_t mod, int what, void *arg) 1785{ 1786 static struct cdev *pci_cdev; 1787 1788 switch (what) { 1789 case MOD_LOAD: 1790 STAILQ_INIT(&pci_devq); 1791 pci_generation = 0; 1792 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1793 "pci"); 1794 pci_load_vendor_data(); 1795 break; 1796 1797 case MOD_UNLOAD: 1798 destroy_dev(pci_cdev); 1799 break; 1800 } 1801 1802 return (0); 1803} 1804 1805static void 1806pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1807{ 1808 int i; 1809 1810 /* 1811 * Only do header type 0 devices. Type 1 devices are bridges, 1812 * which we know need special treatment. Type 2 devices are 1813 * cardbus bridges which also require special treatment. 1814 * Other types are unknown, and we err on the side of safety 1815 * by ignoring them. 1816 */ 1817 if (dinfo->cfg.hdrtype != 0) 1818 return; 1819 1820 /* 1821 * Restore the device to full power mode. We must do this 1822 * before we restore the registers because moving from D3 to 1823 * D0 will cause the chip's BARs and some other registers to 1824 * be reset to some unknown power on reset values. Cut down 1825 * the noise on boot by doing nothing if we are already in 1826 * state D0. 1827 */ 1828 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1829 if (bootverbose) 1830 printf( 1831 "pci%d:%d:%d: Transition from D%d to D0\n", 1832 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1833 pci_get_powerstate(dev)); 1834 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1835 } 1836 for (i = 0; i < dinfo->cfg.nummaps; i++) 1837 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1838 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1839 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1840 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1841 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1842 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1843 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1844 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1845 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1846 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1847 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1848} 1849 1850static void 1851pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1852{ 1853 int i; 1854 uint32_t cls; 1855 int ps; 1856 1857 /* 1858 * Only do header type 0 devices. Type 1 devices are bridges, which 1859 * we know need special treatment. Type 2 devices are cardbus bridges 1860 * which also require special treatment. Other types are unknown, and 1861 * we err on the side of safety by ignoring them. Powering down 1862 * bridges should not be undertaken lightly. 1863 */ 1864 if (dinfo->cfg.hdrtype != 0) 1865 return; 1866 for (i = 0; i < dinfo->cfg.nummaps; i++) 1867 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1868 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1869 1870 /* 1871 * Some drivers apparently write to these registers w/o 1872 * updating our cahced copy. No harm happens if we update the 1873 * copy, so do so here so we can restore them. The COMMAND 1874 * register is modified by the bus w/o updating the cache. This 1875 * should represent the normally writable portion of the 'defined' 1876 * part of type 0 headers. In theory we also need to save/restore 1877 * the PCI capability structures we know about, but apart from power 1878 * we don't know any that are writable. 1879 */ 1880 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1881 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1882 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1883 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1884 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1885 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1886 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1887 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1888 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1889 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1890 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1891 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1892 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1893 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1894 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1895 1896 /* 1897 * don't set the state for display devices and for memory devices 1898 * since bad things happen. we should (a) have drivers that can easily 1899 * detach and (b) use generic drivers for these devices so that some 1900 * device actually attaches. We need to make sure that when we 1901 * implement (a) we don't power the device down on a reattach. 1902 */ 1903 cls = pci_get_class(dev); 1904 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY) { 1905 /* 1906 * PCI spec is clear that we can only go into D3 state from 1907 * D0 state. Transition from D[12] into D0 before going 1908 * to D3 state. 1909 */ 1910 ps = pci_get_powerstate(dev); 1911 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1912 if (bootverbose) 1913 printf( 1914 "pci%d:%d:%d: Transition from D%d to D0\n", 1915 dinfo->cfg.bus, dinfo->cfg.slot, 1916 dinfo->cfg.func, ps); 1917 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1918 } 1919 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1920 if (bootverbose) 1921 printf( 1922 "pci%d:%d:%d: Transition from D0 to D3\n", 1923 dinfo->cfg.bus, dinfo->cfg.slot, 1924 dinfo->cfg.func); 1925 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1926 } 1927 } 1928} 1929