pci.c revision 129533
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 129533 2004-05-21 06:36:36Z imp $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static uint32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68 69static int pci_porten(device_t pcib, int b, int s, int f); 70static int pci_memen(device_t pcib, int b, int s, int f); 71static int pci_add_map(device_t pcib, device_t bus, device_t dev, 72 int b, int s, int f, int reg, 73 struct resource_list *rl); 74static void pci_add_resources(device_t pcib, device_t bus, 75 device_t dev); 76static int pci_probe(device_t dev); 77static int pci_attach(device_t dev); 78static void pci_load_vendor_data(void); 79static int pci_describe_parse_line(char **ptr, int *vendor, 80 int *device, char **desc); 81static char *pci_describe_device(device_t dev); 82static int pci_modevent(module_t mod, int what, void *arg); 83static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 84 pcicfgregs *cfg); 85static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 86static void pci_cfg_restore(device_t, struct pci_devinfo *); 87static void pci_cfg_save(device_t, struct pci_devinfo *, int); 88 89static device_method_t pci_methods[] = { 90 /* Device interface */ 91 DEVMETHOD(device_probe, pci_probe), 92 DEVMETHOD(device_attach, pci_attach), 93 DEVMETHOD(device_shutdown, bus_generic_shutdown), 94 DEVMETHOD(device_suspend, pci_suspend), 95 DEVMETHOD(device_resume, pci_resume), 96 97 /* Bus interface */ 98 DEVMETHOD(bus_print_child, pci_print_child), 99 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 100 DEVMETHOD(bus_read_ivar, pci_read_ivar), 101 DEVMETHOD(bus_write_ivar, pci_write_ivar), 102 DEVMETHOD(bus_driver_added, pci_driver_added), 103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 105 106 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 107 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 108 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 109 DEVMETHOD(bus_delete_resource, pci_delete_resource), 110 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 111 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 112 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 113 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 114 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 115 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 116 117 /* PCI interface */ 118 DEVMETHOD(pci_read_config, pci_read_config_method), 119 DEVMETHOD(pci_write_config, pci_write_config_method), 120 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 121 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 122 DEVMETHOD(pci_enable_io, pci_enable_io_method), 123 DEVMETHOD(pci_disable_io, pci_disable_io_method), 124 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 125 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 126 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 127 128 { 0, 0 } 129}; 130 131DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 132 133devclass_t pci_devclass; 134DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 135MODULE_VERSION(pci, 1); 136 137static char *pci_vendordata; 138static size_t pci_vendordata_size; 139 140 141struct pci_quirk { 142 uint32_t devid; /* Vendor/device of the card */ 143 int type; 144#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 145 int arg1; 146 int arg2; 147}; 148 149struct pci_quirk pci_quirks[] = { 150 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 151 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 153 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 154 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 155 156 { 0 } 157}; 158 159/* map register information */ 160#define PCI_MAPMEM 0x01 /* memory map */ 161#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 162#define PCI_MAPPORT 0x04 /* port map */ 163 164struct devlist pci_devq; 165uint32_t pci_generation; 166uint32_t pci_numdevs = 0; 167 168/* sysctl vars */ 169SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 170 171static int pci_enable_io_modes = 1; 172TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 173SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 174 &pci_enable_io_modes, 1, 175 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 176enable these bits correctly. We'd like to do this all the time, but there\n\ 177are some peripherals that this causes problems with."); 178 179static int pci_do_powerstate = 0; 180TUNABLE_INT("hw.pci.do_powerstate", (int *)&pci_do_powerstate); 181SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 182 &pci_do_powerstate, 0, 183 "Enable setting the power states of the PCI devices. This means that we\n\ 184set devices into D0 before probe/attach, and D3 if they fail to attach. It\n\ 185also means we set devices into D3 state before shutdown."); 186 187/* Find a device_t by bus/slot/function */ 188 189device_t 190pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 191{ 192 struct pci_devinfo *dinfo; 193 194 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 195 if ((dinfo->cfg.bus == bus) && 196 (dinfo->cfg.slot == slot) && 197 (dinfo->cfg.func == func)) { 198 return (dinfo->cfg.dev); 199 } 200 } 201 202 return (NULL); 203} 204 205/* Find a device_t by vendor/device ID */ 206 207device_t 208pci_find_device(uint16_t vendor, uint16_t device) 209{ 210 struct pci_devinfo *dinfo; 211 212 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 213 if ((dinfo->cfg.vendor == vendor) && 214 (dinfo->cfg.device == device)) { 215 return (dinfo->cfg.dev); 216 } 217 } 218 219 return (NULL); 220} 221 222/* return base address of memory or port map */ 223 224static uint32_t 225pci_mapbase(unsigned mapreg) 226{ 227 int mask = 0x03; 228 if ((mapreg & 0x01) == 0) 229 mask = 0x0f; 230 return (mapreg & ~mask); 231} 232 233/* return map type of memory or port map */ 234 235static int 236pci_maptype(unsigned mapreg) 237{ 238 static uint8_t maptype[0x10] = { 239 PCI_MAPMEM, PCI_MAPPORT, 240 PCI_MAPMEM, 0, 241 PCI_MAPMEM, PCI_MAPPORT, 242 0, 0, 243 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 244 PCI_MAPMEM|PCI_MAPMEMP, 0, 245 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 246 0, 0, 247 }; 248 249 return maptype[mapreg & 0x0f]; 250} 251 252/* return log2 of map size decoded for memory or port map */ 253 254static int 255pci_mapsize(unsigned testval) 256{ 257 int ln2size; 258 259 testval = pci_mapbase(testval); 260 ln2size = 0; 261 if (testval != 0) { 262 while ((testval & 1) == 0) 263 { 264 ln2size++; 265 testval >>= 1; 266 } 267 } 268 return (ln2size); 269} 270 271/* return log2 of address range supported by map register */ 272 273static int 274pci_maprange(unsigned mapreg) 275{ 276 int ln2range = 0; 277 switch (mapreg & 0x07) { 278 case 0x00: 279 case 0x01: 280 case 0x05: 281 ln2range = 32; 282 break; 283 case 0x02: 284 ln2range = 20; 285 break; 286 case 0x04: 287 ln2range = 64; 288 break; 289 } 290 return (ln2range); 291} 292 293/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 294 295static void 296pci_fixancient(pcicfgregs *cfg) 297{ 298 if (cfg->hdrtype != 0) 299 return; 300 301 /* PCI to PCI bridges use header type 1 */ 302 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 303 cfg->hdrtype = 1; 304} 305 306/* extract header type specific config data */ 307 308static void 309pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 310{ 311#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 312 switch (cfg->hdrtype) { 313 case 0: 314 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 315 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 316 cfg->nummaps = PCI_MAXMAPS_0; 317 break; 318 case 1: 319 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 320 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 321 cfg->nummaps = PCI_MAXMAPS_1; 322 break; 323 case 2: 324 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 325 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 326 cfg->nummaps = PCI_MAXMAPS_2; 327 break; 328 } 329#undef REG 330} 331 332/* read configuration header into pcicfgregs structure */ 333 334struct pci_devinfo * 335pci_read_device(device_t pcib, int b, int s, int f, size_t size) 336{ 337#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 338 pcicfgregs *cfg = NULL; 339 struct pci_devinfo *devlist_entry; 340 struct devlist *devlist_head; 341 342 devlist_head = &pci_devq; 343 344 devlist_entry = NULL; 345 346 if (REG(PCIR_DEVVENDOR, 4) != -1) { 347 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 348 if (devlist_entry == NULL) 349 return (NULL); 350 351 cfg = &devlist_entry->cfg; 352 353 cfg->bus = b; 354 cfg->slot = s; 355 cfg->func = f; 356 cfg->vendor = REG(PCIR_VENDOR, 2); 357 cfg->device = REG(PCIR_DEVICE, 2); 358 cfg->cmdreg = REG(PCIR_COMMAND, 2); 359 cfg->statreg = REG(PCIR_STATUS, 2); 360 cfg->baseclass = REG(PCIR_CLASS, 1); 361 cfg->subclass = REG(PCIR_SUBCLASS, 1); 362 cfg->progif = REG(PCIR_PROGIF, 1); 363 cfg->revid = REG(PCIR_REVID, 1); 364 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 365 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 366 cfg->lattimer = REG(PCIR_LATTIMER, 1); 367 cfg->intpin = REG(PCIR_INTPIN, 1); 368 cfg->intline = REG(PCIR_INTLINE, 1); 369 370 cfg->mingnt = REG(PCIR_MINGNT, 1); 371 cfg->maxlat = REG(PCIR_MAXLAT, 1); 372 373 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 374 cfg->hdrtype &= ~PCIM_MFDEV; 375 376 pci_fixancient(cfg); 377 pci_hdrtypedata(pcib, b, s, f, cfg); 378 379 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 380 pci_read_extcap(pcib, cfg); 381 382 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 383 384 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 385 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 386 devlist_entry->conf.pc_sel.pc_func = cfg->func; 387 devlist_entry->conf.pc_hdr = cfg->hdrtype; 388 389 devlist_entry->conf.pc_subvendor = cfg->subvendor; 390 devlist_entry->conf.pc_subdevice = cfg->subdevice; 391 devlist_entry->conf.pc_vendor = cfg->vendor; 392 devlist_entry->conf.pc_device = cfg->device; 393 394 devlist_entry->conf.pc_class = cfg->baseclass; 395 devlist_entry->conf.pc_subclass = cfg->subclass; 396 devlist_entry->conf.pc_progif = cfg->progif; 397 devlist_entry->conf.pc_revid = cfg->revid; 398 399 pci_numdevs++; 400 pci_generation++; 401 } 402 return (devlist_entry); 403#undef REG 404} 405 406static void 407pci_read_extcap(device_t pcib, pcicfgregs *cfg) 408{ 409#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 410 int ptr, nextptr, ptrptr; 411 412 switch (cfg->hdrtype & PCIM_HDRTYPE) { 413 case 0: 414 ptrptr = PCIR_CAP_PTR; 415 break; 416 case 2: 417 ptrptr = 0x14; 418 break; 419 default: 420 return; /* no extended capabilities support */ 421 } 422 nextptr = REG(ptrptr, 1); /* sanity check? */ 423 424 /* 425 * Read capability entries. 426 */ 427 while (nextptr != 0) { 428 /* Sanity check */ 429 if (nextptr > 255) { 430 printf("illegal PCI extended capability offset %d\n", 431 nextptr); 432 return; 433 } 434 /* Find the next entry */ 435 ptr = nextptr; 436 nextptr = REG(ptr + 1, 1); 437 438 /* Process this entry */ 439 switch (REG(ptr, 1)) { 440 case PCIY_PMG: /* PCI power management */ 441 if (cfg->pp.pp_cap == 0) { 442 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 443 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 444 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 445 if ((nextptr - ptr) > PCIR_POWER_DATA) 446 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 447 } 448 break; 449 case PCIY_MSI: /* PCI MSI */ 450 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 451 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 452 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 453 else 454 cfg->msi.msi_data = PCIR_MSI_DATA; 455 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 456 PCIM_MSICTRL_MMC_MASK)>>1); 457 default: 458 break; 459 } 460 } 461#undef REG 462} 463 464/* free pcicfgregs structure and all depending data structures */ 465 466int 467pci_freecfg(struct pci_devinfo *dinfo) 468{ 469 struct devlist *devlist_head; 470 471 devlist_head = &pci_devq; 472 473 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 474 free(dinfo, M_DEVBUF); 475 476 /* increment the generation count */ 477 pci_generation++; 478 479 /* we're losing one device */ 480 pci_numdevs--; 481 return (0); 482} 483 484/* 485 * PCI power manangement 486 */ 487int 488pci_set_powerstate_method(device_t dev, device_t child, int state) 489{ 490 struct pci_devinfo *dinfo = device_get_ivars(child); 491 pcicfgregs *cfg = &dinfo->cfg; 492 uint16_t status; 493 int result; 494 495 /* 496 * Dx -> Dx is a nop always. 497 */ 498 if (pci_get_powerstate(child) == state) 499 return (0); 500 501 if (cfg->pp.pp_cap != 0) { 502 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 503 & ~PCIM_PSTAT_DMASK; 504 result = 0; 505 switch (state) { 506 case PCI_POWERSTATE_D0: 507 status |= PCIM_PSTAT_D0; 508 break; 509 case PCI_POWERSTATE_D1: 510 if (cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) { 511 status |= PCIM_PSTAT_D1; 512 } else { 513 result = EOPNOTSUPP; 514 } 515 break; 516 case PCI_POWERSTATE_D2: 517 if (cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) { 518 status |= PCIM_PSTAT_D2; 519 } else { 520 result = EOPNOTSUPP; 521 } 522 break; 523 case PCI_POWERSTATE_D3: 524 status |= PCIM_PSTAT_D3; 525 break; 526 default: 527 result = EINVAL; 528 } 529 if (result == 0) 530 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 531 2); 532 } else { 533 result = ENXIO; 534 } 535 return(result); 536} 537 538int 539pci_get_powerstate_method(device_t dev, device_t child) 540{ 541 struct pci_devinfo *dinfo = device_get_ivars(child); 542 pcicfgregs *cfg = &dinfo->cfg; 543 uint16_t status; 544 int result; 545 546 if (cfg->pp.pp_cap != 0) { 547 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 548 switch (status & PCIM_PSTAT_DMASK) { 549 case PCIM_PSTAT_D0: 550 result = PCI_POWERSTATE_D0; 551 break; 552 case PCIM_PSTAT_D1: 553 result = PCI_POWERSTATE_D1; 554 break; 555 case PCIM_PSTAT_D2: 556 result = PCI_POWERSTATE_D2; 557 break; 558 case PCIM_PSTAT_D3: 559 result = PCI_POWERSTATE_D3; 560 break; 561 default: 562 result = PCI_POWERSTATE_UNKNOWN; 563 break; 564 } 565 } else { 566 /* No support, device is always at D0 */ 567 result = PCI_POWERSTATE_D0; 568 } 569 return(result); 570} 571 572/* 573 * Some convenience functions for PCI device drivers. 574 */ 575 576static __inline void 577pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 578{ 579 uint16_t command; 580 581 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 582 command |= bit; 583 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 584} 585 586static __inline void 587pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 588{ 589 uint16_t command; 590 591 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 592 command &= ~bit; 593 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 594} 595 596int 597pci_enable_busmaster_method(device_t dev, device_t child) 598{ 599 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 600 return (0); 601} 602 603int 604pci_disable_busmaster_method(device_t dev, device_t child) 605{ 606 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 607 return (0); 608} 609 610int 611pci_enable_io_method(device_t dev, device_t child, int space) 612{ 613 uint16_t command; 614 uint16_t bit; 615 char *error; 616 617 bit = 0; 618 error = NULL; 619 620 switch(space) { 621 case SYS_RES_IOPORT: 622 bit = PCIM_CMD_PORTEN; 623 error = "port"; 624 break; 625 case SYS_RES_MEMORY: 626 bit = PCIM_CMD_MEMEN; 627 error = "memory"; 628 break; 629 default: 630 return (EINVAL); 631 } 632 pci_set_command_bit(dev, child, bit); 633 /* Some devices seem to need a brief stall here, what do to? */ 634 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 635 if (command & bit) 636 return (0); 637 device_printf(child, "failed to enable %s mapping!\n", error); 638 return (ENXIO); 639} 640 641int 642pci_disable_io_method(device_t dev, device_t child, int space) 643{ 644 uint16_t command; 645 uint16_t bit; 646 char *error; 647 648 bit = 0; 649 error = NULL; 650 651 switch(space) { 652 case SYS_RES_IOPORT: 653 bit = PCIM_CMD_PORTEN; 654 error = "port"; 655 break; 656 case SYS_RES_MEMORY: 657 bit = PCIM_CMD_MEMEN; 658 error = "memory"; 659 break; 660 default: 661 return (EINVAL); 662 } 663 pci_clear_command_bit(dev, child, bit); 664 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 665 if (command & bit) { 666 device_printf(child, "failed to disable %s mapping!\n", error); 667 return (ENXIO); 668 } 669 return (0); 670} 671 672/* 673 * New style pci driver. Parent device is either a pci-host-bridge or a 674 * pci-pci-bridge. Both kinds are represented by instances of pcib. 675 */ 676 677void 678pci_print_verbose(struct pci_devinfo *dinfo) 679{ 680 if (bootverbose) { 681 pcicfgregs *cfg = &dinfo->cfg; 682 683 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 684 cfg->vendor, cfg->device, cfg->revid); 685 printf("\tbus=%d, slot=%d, func=%d\n", 686 cfg->bus, cfg->slot, cfg->func); 687 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 688 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 689 cfg->mfdev); 690 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 691 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 692 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 693 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 694 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 695 if (cfg->intpin > 0) 696 printf("\tintpin=%c, irq=%d\n", 697 cfg->intpin +'a' -1, cfg->intline); 698 if (cfg->pp.pp_cap) { 699 uint16_t status; 700 701 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 702 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 703 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 704 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 705 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 706 status & PCIM_PSTAT_DMASK); 707 } 708 if (cfg->msi.msi_data) { 709 int ctrl; 710 711 ctrl = cfg->msi.msi_ctrl; 712 printf("\tMSI supports %d message%s%s%s\n", 713 cfg->msi.msi_msgnum, 714 (cfg->msi.msi_msgnum == 1) ? "" : "s", 715 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 716 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 717 } 718 } 719} 720 721static int 722pci_porten(device_t pcib, int b, int s, int f) 723{ 724 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 725 & PCIM_CMD_PORTEN) != 0; 726} 727 728static int 729pci_memen(device_t pcib, int b, int s, int f) 730{ 731 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 732 & PCIM_CMD_MEMEN) != 0; 733} 734 735/* 736 * Add a resource based on a pci map register. Return 1 if the map 737 * register is a 32bit map register or 2 if it is a 64bit register. 738 */ 739static int 740pci_add_map(device_t pcib, device_t bus, device_t dev, 741 int b, int s, int f, int reg, struct resource_list *rl) 742{ 743 uint32_t map; 744 uint64_t base; 745 uint64_t start, end, count; 746 uint8_t ln2size; 747 uint8_t ln2range; 748 uint32_t testval; 749 uint16_t cmd; 750 int type; 751 752 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 753 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 754 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 755 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 756 757 if (pci_maptype(map) & PCI_MAPMEM) 758 type = SYS_RES_MEMORY; 759 else 760 type = SYS_RES_IOPORT; 761 ln2size = pci_mapsize(testval); 762 ln2range = pci_maprange(testval); 763 base = pci_mapbase(map); 764 765 /* 766 * For I/O registers, if bottom bit is set, and the next bit up 767 * isn't clear, we know we have a BAR that doesn't conform to the 768 * spec, so ignore it. Also, sanity check the size of the data 769 * areas to the type of memory involved. Memory must be at least 770 * 32 bytes in size, while I/O ranges must be at least 4. 771 */ 772 if ((testval & 0x1) == 0x1 && 773 (testval & 0x2) != 0) 774 return (1); 775 if ((type == SYS_RES_MEMORY && ln2size < 5) || 776 (type == SYS_RES_IOPORT && ln2size < 2)) 777 return (1); 778 779 if (ln2range == 64) 780 /* Read the other half of a 64bit map register */ 781 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 782 783 if (bootverbose) { 784 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 785 reg, pci_maptype(map), ln2range, 786 (unsigned int) base, ln2size); 787 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 788 printf(", port disabled\n"); 789 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 790 printf(", memory disabled\n"); 791 else 792 printf(", enabled\n"); 793 } 794 795 /* 796 * This code theoretically does the right thing, but has 797 * undesirable side effects in some cases where peripherals 798 * respond oddly to having these bits enabled. Let the user 799 * be able to turn them off (since pci_enable_io_modes is 1 by 800 * default). 801 */ 802 if (pci_enable_io_modes) { 803 /* Turn on resources that have been left off by a lazy BIOS */ 804 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 805 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 806 cmd |= PCIM_CMD_PORTEN; 807 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 808 } 809 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 810 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 811 cmd |= PCIM_CMD_MEMEN; 812 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 813 } 814 } else { 815 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 816 return (1); 817 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 818 return (1); 819 } 820 /* 821 * If base is 0, then we have problems. It is best to ignore 822 * such entires for the moment. These will be allocated later if 823 * the driver specifically requests them. 824 */ 825 if (base == 0) 826 return 1; 827 828 start = base; 829 end = base + (1 << ln2size) - 1; 830 count = 1 << ln2size; 831 resource_list_add(rl, type, reg, start, end, count); 832 833 /* 834 * Not quite sure what to do on failure of allocating the resource 835 * since I can postulate several right answers. 836 */ 837 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 838 return ((ln2range == 64) ? 2 : 1); 839} 840 841static int 842pci_is_ata_legacy(device_t dev) 843{ 844 /* 845 * ATA PCI in compatibility mode are hard wired to certain 846 * compatibility addresses. Such entries does not contain 847 * valid resources as they are at fixed positions to be 848 * compatible with old ISA requirements. 849 */ 850 if ((pci_get_class(dev) == PCIC_STORAGE) && 851 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 852 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) && 853 !(pci_get_progif(dev) & 854 (PCIP_STORAGE_IDE_MODEPRIM | PCIP_STORAGE_IDE_MODESEC))) 855 return 1; 856 return 0; 857} 858 859/* 860 * The ATA PCI spec specifies that in legacy mode, the device shall 861 * decode the resources listed below. The ata driver allocates 862 * resources in this order, and many atapci devices actually have 863 * values similar to these in the actual underlying bars. Part of the 864 * problem is that the floppy controller and ata overlap for 1 byte, 865 * which makes it difficult to properly allocate things. 866 * 867 * My reading of the pci spec is such that this appears to be the only 868 * allowed exception to the rule that devices only decode the addresses 869 * presented in their BARs. We also ensure that the bits that take 870 * the device out of legacy mode are set to 0 before making this 871 * reservation. 872 */ 873static void 874pci_add_ata_legacy_maps(device_t pcib, device_t bus, device_t dev, int b, 875 int s, int f, struct resource_list *rl) 876{ 877 int rid; 878 int type; 879 880 type = SYS_RES_IOPORT; 881 if ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MODEPRIM) == 0) { 882 rid = PCIR_BAR(0); 883 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 884 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 885 0); 886 rid = PCIR_BAR(1); 887 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 888 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 889 0); 890 } 891 if ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MODESEC) == 0) { 892 rid = PCIR_BAR(2); 893 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 894 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 895 0); 896 rid = PCIR_BAR(3); 897 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 898 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 899 0); 900 } 901 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 902} 903 904static void 905pci_add_resources(device_t pcib, device_t bus, device_t dev) 906{ 907 struct pci_devinfo *dinfo = device_get_ivars(dev); 908 pcicfgregs *cfg = &dinfo->cfg; 909 struct resource_list *rl = &dinfo->resources; 910 struct pci_quirk *q; 911 int b, i, irq, f, s; 912 913 b = cfg->bus; 914 s = cfg->slot; 915 f = cfg->func; 916 917 if (pci_is_ata_legacy(dev)) 918 pci_add_ata_legacy_maps(pcib, bus, dev, b, s, f, rl); 919 else 920 for (i = 0; i < cfg->nummaps;) 921 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 922 rl); 923 924 for (q = &pci_quirks[0]; q->devid; q++) { 925 if (q->devid == ((cfg->device << 16) | cfg->vendor) 926 && q->type == PCI_QUIRK_MAP_REG) 927 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 928 } 929 930 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 931#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) 932 /* 933 * Try to re-route interrupts. Sometimes the BIOS or 934 * firmware may leave bogus values in these registers. 935 * If the re-route fails, then just stick with what we 936 * have. 937 */ 938 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 939 if (PCI_INTERRUPT_VALID(irq)) { 940 pci_write_config(dev, PCIR_INTLINE, irq, 1); 941 cfg->intline = irq; 942 } else 943#endif 944 irq = cfg->intline; 945 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 946 } 947} 948 949void 950pci_add_children(device_t dev, int busno, size_t dinfo_size) 951{ 952#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 953 device_t pcib = device_get_parent(dev); 954 struct pci_devinfo *dinfo; 955 int maxslots; 956 int s, f, pcifunchigh; 957 uint8_t hdrtype; 958 959 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 960 ("dinfo_size too small")); 961 maxslots = PCIB_MAXSLOTS(pcib); 962 for (s = 0; s <= maxslots; s++) { 963 pcifunchigh = 0; 964 f = 0; 965 hdrtype = REG(PCIR_HDRTYPE, 1); 966 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 967 continue; 968 if (hdrtype & PCIM_MFDEV) 969 pcifunchigh = PCI_FUNCMAX; 970 for (f = 0; f <= pcifunchigh; f++) { 971 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 972 if (dinfo != NULL) { 973 pci_add_child(dev, dinfo); 974 } 975 } 976 } 977#undef REG 978} 979 980void 981pci_add_child(device_t bus, struct pci_devinfo *dinfo) 982{ 983 device_t pcib; 984 985 pcib = device_get_parent(bus); 986 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 987 device_set_ivars(dinfo->cfg.dev, dinfo); 988 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 989 pci_cfg_restore(dinfo->cfg.dev, dinfo); 990 pci_add_resources(pcib, bus, dinfo->cfg.dev); 991 pci_print_verbose(dinfo); 992} 993 994static int 995pci_probe(device_t dev) 996{ 997 998 device_set_desc(dev, "PCI bus"); 999 1000 /* Allow other subclasses to override this driver. */ 1001 return (-1000); 1002} 1003 1004static int 1005pci_attach(device_t dev) 1006{ 1007 int busno; 1008 1009 /* 1010 * Since there can be multiple independantly numbered PCI 1011 * busses on some large alpha systems, we can't use the unit 1012 * number to decide what bus we are probing. We ask the parent 1013 * pcib what our bus number is. 1014 */ 1015 busno = pcib_get_bus(dev); 1016 if (bootverbose) 1017 device_printf(dev, "physical bus=%d\n", busno); 1018 1019 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1020 1021 return (bus_generic_attach(dev)); 1022} 1023 1024int 1025pci_suspend(device_t dev) 1026{ 1027 int numdevs; 1028 device_t *devlist; 1029 device_t child; 1030 struct pci_devinfo *dinfo; 1031 int i; 1032 1033 /* 1034 * Save the pci configuration space for each child. We don't need 1035 * to do this, unless the BIOS suspend code powers down the bus and 1036 * the devices on the bus. 1037 */ 1038 device_get_children(dev, &devlist, &numdevs); 1039 for (i = 0; i < numdevs; i++) { 1040 child = devlist[i]; 1041 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1042 pci_cfg_save(child, dinfo, 0); 1043 } 1044 free(devlist, M_TEMP); 1045 return (bus_generic_suspend(dev)); 1046} 1047 1048int 1049pci_resume(device_t dev) 1050{ 1051 int numdevs; 1052 device_t *devlist; 1053 device_t child; 1054 struct pci_devinfo *dinfo; 1055 int i; 1056 1057 /* 1058 * Restore the pci configuration space for each child. 1059 */ 1060 device_get_children(dev, &devlist, &numdevs); 1061 for (i = 0; i < numdevs; i++) { 1062 child = devlist[i]; 1063 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1064 pci_cfg_restore(child, dinfo); 1065 } 1066 free(devlist, M_TEMP); 1067 return (bus_generic_resume(dev)); 1068} 1069 1070static void 1071pci_load_vendor_data(void) 1072{ 1073 caddr_t vendordata, info; 1074 1075 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1076 info = preload_search_info(vendordata, MODINFO_ADDR); 1077 pci_vendordata = *(char **)info; 1078 info = preload_search_info(vendordata, MODINFO_SIZE); 1079 pci_vendordata_size = *(size_t *)info; 1080 /* terminate the database */ 1081 pci_vendordata[pci_vendordata_size] = '\n'; 1082 } 1083} 1084 1085void 1086pci_driver_added(device_t dev, driver_t *driver) 1087{ 1088 int numdevs; 1089 device_t *devlist; 1090 device_t child; 1091 struct pci_devinfo *dinfo; 1092 int i; 1093 1094 if (bootverbose) 1095 device_printf(dev, "driver added\n"); 1096 DEVICE_IDENTIFY(driver, dev); 1097 device_get_children(dev, &devlist, &numdevs); 1098 for (i = 0; i < numdevs; i++) { 1099 child = devlist[i]; 1100 if (device_get_state(child) != DS_NOTPRESENT) 1101 continue; 1102 dinfo = device_get_ivars(child); 1103 pci_print_verbose(dinfo); 1104/*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */ 1105 if (bootverbose) 1106 printf("pci%d:%d:%d: reprobing on driver added\n", 1107 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1108 pci_cfg_restore(child, dinfo); 1109 if (device_probe_and_attach(child) != 0) 1110 pci_cfg_save(child, dinfo, 1); 1111 } 1112 free(devlist, M_TEMP); 1113} 1114 1115int 1116pci_print_child(device_t dev, device_t child) 1117{ 1118 struct pci_devinfo *dinfo; 1119 struct resource_list *rl; 1120 int retval = 0; 1121 1122 dinfo = device_get_ivars(child); 1123 rl = &dinfo->resources; 1124 1125 retval += bus_print_child_header(dev, child); 1126 1127 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1128 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1129 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1130 if (device_get_flags(dev)) 1131 retval += printf(" flags %#x", device_get_flags(dev)); 1132 1133 retval += printf(" at device %d.%d", pci_get_slot(child), 1134 pci_get_function(child)); 1135 1136 retval += bus_print_child_footer(dev, child); 1137 1138 return (retval); 1139} 1140 1141static struct 1142{ 1143 int class; 1144 int subclass; 1145 char *desc; 1146} pci_nomatch_tab[] = { 1147 {PCIC_OLD, -1, "old"}, 1148 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1149 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1150 {PCIC_STORAGE, -1, "mass storage"}, 1151 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1152 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1153 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1154 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1155 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1156 {PCIC_NETWORK, -1, "network"}, 1157 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1158 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1159 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1160 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1161 {PCIC_DISPLAY, -1, "display"}, 1162 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1163 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1164 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1165 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1166 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1167 {PCIC_MEMORY, -1, "memory"}, 1168 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1169 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1170 {PCIC_BRIDGE, -1, "bridge"}, 1171 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1172 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1173 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1174 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1175 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1176 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1177 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1178 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1179 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1180 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1181 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1182 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1183 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1184 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1185 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1186 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1187 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1188 {PCIC_INPUTDEV, -1, "input device"}, 1189 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1190 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1191 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1192 {PCIC_DOCKING, -1, "docking station"}, 1193 {PCIC_PROCESSOR, -1, "processor"}, 1194 {PCIC_SERIALBUS, -1, "serial bus"}, 1195 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1196 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1197 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1198 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1199 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1200 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1201 {0, 0, NULL} 1202}; 1203 1204void 1205pci_probe_nomatch(device_t dev, device_t child) 1206{ 1207 int i; 1208 char *cp, *scp, *device; 1209 1210 /* 1211 * Look for a listing for this device in a loaded device database. 1212 */ 1213 if ((device = pci_describe_device(child)) != NULL) { 1214 device_printf(dev, "<%s>", device); 1215 free(device, M_DEVBUF); 1216 } else { 1217 /* 1218 * Scan the class/subclass descriptions for a general 1219 * description. 1220 */ 1221 cp = "unknown"; 1222 scp = NULL; 1223 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1224 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1225 if (pci_nomatch_tab[i].subclass == -1) { 1226 cp = pci_nomatch_tab[i].desc; 1227 } else if (pci_nomatch_tab[i].subclass == 1228 pci_get_subclass(child)) { 1229 scp = pci_nomatch_tab[i].desc; 1230 } 1231 } 1232 } 1233 device_printf(dev, "<%s%s%s>", 1234 cp ? cp : "", 1235 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1236 scp ? scp : ""); 1237 } 1238 printf(" at device %d.%d (no driver attached)\n", 1239 pci_get_slot(child), pci_get_function(child)); 1240 pci_cfg_save(child, (struct pci_devinfo *) device_get_ivars(child), 1); 1241 return; 1242} 1243 1244/* 1245 * Parse the PCI device database, if loaded, and return a pointer to a 1246 * description of the device. 1247 * 1248 * The database is flat text formatted as follows: 1249 * 1250 * Any line not in a valid format is ignored. 1251 * Lines are terminated with newline '\n' characters. 1252 * 1253 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1254 * the vendor name. 1255 * 1256 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1257 * - devices cannot be listed without a corresponding VENDOR line. 1258 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1259 * another TAB, then the device name. 1260 */ 1261 1262/* 1263 * Assuming (ptr) points to the beginning of a line in the database, 1264 * return the vendor or device and description of the next entry. 1265 * The value of (vendor) or (device) inappropriate for the entry type 1266 * is set to -1. Returns nonzero at the end of the database. 1267 * 1268 * Note that this is slightly unrobust in the face of corrupt data; 1269 * we attempt to safeguard against this by spamming the end of the 1270 * database with a newline when we initialise. 1271 */ 1272static int 1273pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1274{ 1275 char *cp = *ptr; 1276 int left; 1277 1278 *device = -1; 1279 *vendor = -1; 1280 **desc = '\0'; 1281 for (;;) { 1282 left = pci_vendordata_size - (cp - pci_vendordata); 1283 if (left <= 0) { 1284 *ptr = cp; 1285 return(1); 1286 } 1287 1288 /* vendor entry? */ 1289 if (*cp != '\t' && 1290 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1291 break; 1292 /* device entry? */ 1293 if (*cp == '\t' && 1294 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1295 break; 1296 1297 /* skip to next line */ 1298 while (*cp != '\n' && left > 0) { 1299 cp++; 1300 left--; 1301 } 1302 if (*cp == '\n') { 1303 cp++; 1304 left--; 1305 } 1306 } 1307 /* skip to next line */ 1308 while (*cp != '\n' && left > 0) { 1309 cp++; 1310 left--; 1311 } 1312 if (*cp == '\n' && left > 0) 1313 cp++; 1314 *ptr = cp; 1315 return(0); 1316} 1317 1318static char * 1319pci_describe_device(device_t dev) 1320{ 1321 int vendor, device; 1322 char *desc, *vp, *dp, *line; 1323 1324 desc = vp = dp = NULL; 1325 1326 /* 1327 * If we have no vendor data, we can't do anything. 1328 */ 1329 if (pci_vendordata == NULL) 1330 goto out; 1331 1332 /* 1333 * Scan the vendor data looking for this device 1334 */ 1335 line = pci_vendordata; 1336 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1337 goto out; 1338 for (;;) { 1339 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1340 goto out; 1341 if (vendor == pci_get_vendor(dev)) 1342 break; 1343 } 1344 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1345 goto out; 1346 for (;;) { 1347 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1348 *dp = 0; 1349 break; 1350 } 1351 if (vendor != -1) { 1352 *dp = 0; 1353 break; 1354 } 1355 if (device == pci_get_device(dev)) 1356 break; 1357 } 1358 if (dp[0] == '\0') 1359 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1360 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1361 NULL) 1362 sprintf(desc, "%s, %s", vp, dp); 1363 out: 1364 if (vp != NULL) 1365 free(vp, M_DEVBUF); 1366 if (dp != NULL) 1367 free(dp, M_DEVBUF); 1368 return(desc); 1369} 1370 1371int 1372pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1373{ 1374 struct pci_devinfo *dinfo; 1375 pcicfgregs *cfg; 1376 1377 dinfo = device_get_ivars(child); 1378 cfg = &dinfo->cfg; 1379 1380 switch (which) { 1381 case PCI_IVAR_ETHADDR: 1382 /* 1383 * The generic accessor doesn't deal with failure, so 1384 * we set the return value, then return an error. 1385 */ 1386 *((uint8_t **) result) = NULL; 1387 return (EINVAL); 1388 case PCI_IVAR_SUBVENDOR: 1389 *result = cfg->subvendor; 1390 break; 1391 case PCI_IVAR_SUBDEVICE: 1392 *result = cfg->subdevice; 1393 break; 1394 case PCI_IVAR_VENDOR: 1395 *result = cfg->vendor; 1396 break; 1397 case PCI_IVAR_DEVICE: 1398 *result = cfg->device; 1399 break; 1400 case PCI_IVAR_DEVID: 1401 *result = (cfg->device << 16) | cfg->vendor; 1402 break; 1403 case PCI_IVAR_CLASS: 1404 *result = cfg->baseclass; 1405 break; 1406 case PCI_IVAR_SUBCLASS: 1407 *result = cfg->subclass; 1408 break; 1409 case PCI_IVAR_PROGIF: 1410 *result = cfg->progif; 1411 break; 1412 case PCI_IVAR_REVID: 1413 *result = cfg->revid; 1414 break; 1415 case PCI_IVAR_INTPIN: 1416 *result = cfg->intpin; 1417 break; 1418 case PCI_IVAR_IRQ: 1419 *result = cfg->intline; 1420 break; 1421 case PCI_IVAR_BUS: 1422 *result = cfg->bus; 1423 break; 1424 case PCI_IVAR_SLOT: 1425 *result = cfg->slot; 1426 break; 1427 case PCI_IVAR_FUNCTION: 1428 *result = cfg->func; 1429 break; 1430 default: 1431 return (ENOENT); 1432 } 1433 return (0); 1434} 1435 1436int 1437pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1438{ 1439 struct pci_devinfo *dinfo; 1440 1441 dinfo = device_get_ivars(child); 1442 1443 switch (which) { 1444 case PCI_IVAR_INTPIN: 1445 dinfo->cfg.intpin = value; 1446 return (0); 1447 case PCI_IVAR_ETHADDR: 1448 case PCI_IVAR_SUBVENDOR: 1449 case PCI_IVAR_SUBDEVICE: 1450 case PCI_IVAR_VENDOR: 1451 case PCI_IVAR_DEVICE: 1452 case PCI_IVAR_DEVID: 1453 case PCI_IVAR_CLASS: 1454 case PCI_IVAR_SUBCLASS: 1455 case PCI_IVAR_PROGIF: 1456 case PCI_IVAR_REVID: 1457 case PCI_IVAR_IRQ: 1458 case PCI_IVAR_BUS: 1459 case PCI_IVAR_SLOT: 1460 case PCI_IVAR_FUNCTION: 1461 return (EINVAL); /* disallow for now */ 1462 1463 default: 1464 return (ENOENT); 1465 } 1466} 1467 1468 1469#include "opt_ddb.h" 1470#ifdef DDB 1471#include <ddb/ddb.h> 1472#include <sys/cons.h> 1473 1474/* 1475 * List resources based on pci map registers, used for within ddb 1476 */ 1477 1478DB_SHOW_COMMAND(pciregs, db_pci_dump) 1479{ 1480 struct pci_devinfo *dinfo; 1481 struct devlist *devlist_head; 1482 struct pci_conf *p; 1483 const char *name; 1484 int i, error, none_count, quit; 1485 1486 none_count = 0; 1487 /* get the head of the device queue */ 1488 devlist_head = &pci_devq; 1489 1490 /* 1491 * Go through the list of devices and print out devices 1492 */ 1493 db_setup_paging(db_simple_pager, &quit, DB_LINES_PER_PAGE); 1494 for (error = 0, i = 0, quit = 0, 1495 dinfo = STAILQ_FIRST(devlist_head); 1496 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1497 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1498 1499 /* Populate pd_name and pd_unit */ 1500 name = NULL; 1501 if (dinfo->cfg.dev) 1502 name = device_get_name(dinfo->cfg.dev); 1503 1504 p = &dinfo->conf; 1505 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1506 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1507 (name && *name) ? name : "none", 1508 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1509 none_count++, 1510 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1511 p->pc_sel.pc_func, (p->pc_class << 16) | 1512 (p->pc_subclass << 8) | p->pc_progif, 1513 (p->pc_subdevice << 16) | p->pc_subvendor, 1514 (p->pc_device << 16) | p->pc_vendor, 1515 p->pc_revid, p->pc_hdr); 1516 } 1517} 1518#endif /* DDB */ 1519 1520static struct resource * 1521pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1522 u_long start, u_long end, u_long count, u_int flags) 1523{ 1524 struct pci_devinfo *dinfo = device_get_ivars(child); 1525 struct resource_list *rl = &dinfo->resources; 1526 struct resource_list_entry *rle; 1527 struct resource *res; 1528 uint32_t map, testval; 1529 int mapsize; 1530 1531 /* 1532 * Weed out the bogons, and figure out how large the BAR/map 1533 * is. Bars that read back 0 here are bogus and unimplemented. 1534 * Note: atapci in legacy mode are special and handled elsewhere 1535 * in the code. If you have a atapci device in legacy mode and 1536 * it fails here, that other code is broken. 1537 */ 1538 res = NULL; 1539 map = pci_read_config(child, *rid, 4); 1540 pci_write_config(child, *rid, 0xffffffff, 4); 1541 testval = pci_read_config(child, *rid, 4); 1542 if (testval == 0) 1543 return (NULL); 1544 if (pci_maptype(testval) & PCI_MAPMEM) { 1545 if (type != SYS_RES_MEMORY) { 1546 device_printf(child, 1547 "failed: rid %#x is memory, requested %d\n", 1548 *rid, type); 1549 goto out; 1550 } 1551 } else { 1552 if (type != SYS_RES_IOPORT) { 1553 device_printf(child, 1554 "failed: rid %#x is ioport, requested %d\n", 1555 *rid, type); 1556 goto out; 1557 } 1558 } 1559 /* 1560 * For real BARs, we need to override the size that 1561 * the driver requests, because that's what the BAR 1562 * actually uses and we would otherwise have a 1563 * situation where we might allocate the excess to 1564 * another driver, which won't work. 1565 */ 1566 mapsize = pci_mapsize(testval); 1567 count = 1 << mapsize; 1568 if (RF_ALIGNMENT(flags) < mapsize) 1569 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1570 1571 /* 1572 * Allocate enough resource, and then write back the 1573 * appropriate bar for that resource. 1574 */ 1575 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1576 start, end, count, flags); 1577 if (res == NULL) { 1578 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1579 count, *rid, type); 1580 goto out; 1581 } 1582 resource_list_add(rl, type, *rid, start, end, count); 1583 rle = resource_list_find(rl, type, *rid); 1584 if (rle == NULL) 1585 panic("pci_alloc_map: unexpedly can't find resource."); 1586 rle->res = res; 1587 if (bootverbose) 1588 device_printf(child, 1589 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1590 count, *rid, type, rman_get_start(res)); 1591 map = rman_get_start(res); 1592out:; 1593 pci_write_config(child, *rid, map, 4); 1594 return (res); 1595} 1596 1597 1598struct resource * 1599pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1600 u_long start, u_long end, u_long count, u_int flags) 1601{ 1602 struct pci_devinfo *dinfo = device_get_ivars(child); 1603 struct resource_list *rl = &dinfo->resources; 1604 struct resource_list_entry *rle; 1605 pcicfgregs *cfg = &dinfo->cfg; 1606 1607 /* 1608 * Perform lazy resource allocation 1609 */ 1610 if (device_get_parent(child) == dev) { 1611 switch (type) { 1612 case SYS_RES_IRQ: 1613 /* 1614 * If the child device doesn't have an 1615 * interrupt routed and is deserving of an 1616 * interrupt, try to assign it one. 1617 */ 1618 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1619 (cfg->intpin != 0)) { 1620 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1621 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1622 pci_write_config(child, PCIR_INTLINE, 1623 cfg->intline, 1); 1624 resource_list_add(rl, SYS_RES_IRQ, 0, 1625 cfg->intline, cfg->intline, 1); 1626 } 1627 } 1628 break; 1629 case SYS_RES_IOPORT: 1630 case SYS_RES_MEMORY: 1631 if (*rid < PCIR_BAR(cfg->nummaps)) { 1632 /* 1633 * Enable the I/O mode. We should 1634 * also be assigning resources too 1635 * when none are present. The 1636 * resource_list_alloc kind of sorta does 1637 * this... 1638 */ 1639 if (PCI_ENABLE_IO(dev, child, type)) 1640 return (NULL); 1641 } 1642 rle = resource_list_find(rl, type, *rid); 1643 if (rle == NULL) 1644 return (pci_alloc_map(dev, child, type, rid, 1645 start, end, count, flags)); 1646 break; 1647 } 1648 /* 1649 * If we've already allocated the resource, then 1650 * return it now. But first we may need to activate 1651 * it, since we don't allocate the resource as active 1652 * above. Normally this would be done down in the 1653 * nexus, but since we short-circuit that path we have 1654 * to do its job here. Not sure if we should free the 1655 * resource if it fails to activate. 1656 */ 1657 rle = resource_list_find(rl, type, *rid); 1658 if (rle != NULL && rle->res != NULL) { 1659 if (bootverbose) 1660 device_printf(child, 1661 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1662 rman_get_size(rle->res), *rid, type, 1663 rman_get_start(rle->res)); 1664 if ((flags & RF_ACTIVE) && 1665 bus_generic_activate_resource(dev, child, type, 1666 *rid, rle->res) != 0) 1667 return NULL; 1668 return (rle->res); 1669 } 1670 } 1671 return (resource_list_alloc(rl, dev, child, type, rid, 1672 start, end, count, flags)); 1673} 1674 1675void 1676pci_delete_resource(device_t dev, device_t child, int type, int rid) 1677{ 1678 struct pci_devinfo *dinfo; 1679 struct resource_list *rl; 1680 struct resource_list_entry *rle; 1681 1682 if (device_get_parent(child) != dev) 1683 return; 1684 1685 dinfo = device_get_ivars(child); 1686 rl = &dinfo->resources; 1687 rle = resource_list_find(rl, type, rid); 1688 if (rle) { 1689 if (rle->res) { 1690 if (rman_get_device(rle->res) != dev || 1691 rman_get_flags(rle->res) & RF_ACTIVE) { 1692 device_printf(dev, "delete_resource: " 1693 "Resource still owned by child, oops. " 1694 "(type=%d, rid=%d, addr=%lx)\n", 1695 rle->type, rle->rid, 1696 rman_get_start(rle->res)); 1697 return; 1698 } 1699 bus_release_resource(dev, type, rid, rle->res); 1700 } 1701 resource_list_delete(rl, type, rid); 1702 } 1703 /* 1704 * Why do we turn off the PCI configuration BAR when we delete a 1705 * resource? -- imp 1706 */ 1707 pci_write_config(child, rid, 0, 4); 1708 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1709} 1710 1711struct resource_list * 1712pci_get_resource_list (device_t dev, device_t child) 1713{ 1714 struct pci_devinfo *dinfo = device_get_ivars(child); 1715 1716 return (&dinfo->resources); 1717} 1718 1719uint32_t 1720pci_read_config_method(device_t dev, device_t child, int reg, int width) 1721{ 1722 struct pci_devinfo *dinfo = device_get_ivars(child); 1723 pcicfgregs *cfg = &dinfo->cfg; 1724 1725 return (PCIB_READ_CONFIG(device_get_parent(dev), 1726 cfg->bus, cfg->slot, cfg->func, reg, width)); 1727} 1728 1729void 1730pci_write_config_method(device_t dev, device_t child, int reg, 1731 uint32_t val, int width) 1732{ 1733 struct pci_devinfo *dinfo = device_get_ivars(child); 1734 pcicfgregs *cfg = &dinfo->cfg; 1735 1736 PCIB_WRITE_CONFIG(device_get_parent(dev), 1737 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1738} 1739 1740int 1741pci_child_location_str_method(device_t dev, device_t child, char *buf, 1742 size_t buflen) 1743{ 1744 struct pci_devinfo *dinfo; 1745 1746 dinfo = device_get_ivars(child); 1747 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1748 pci_get_function(child)); 1749 return (0); 1750} 1751 1752int 1753pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1754 size_t buflen) 1755{ 1756 struct pci_devinfo *dinfo; 1757 pcicfgregs *cfg; 1758 1759 dinfo = device_get_ivars(child); 1760 cfg = &dinfo->cfg; 1761 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1762 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1763 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1764 cfg->progif); 1765 return (0); 1766} 1767 1768int 1769pci_assign_interrupt_method(device_t dev, device_t child) 1770{ 1771 struct pci_devinfo *dinfo = device_get_ivars(child); 1772 pcicfgregs *cfg = &dinfo->cfg; 1773 1774 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1775 cfg->intpin)); 1776} 1777 1778static int 1779pci_modevent(module_t mod, int what, void *arg) 1780{ 1781 static dev_t pci_cdev; 1782 1783 switch (what) { 1784 case MOD_LOAD: 1785 STAILQ_INIT(&pci_devq); 1786 pci_generation = 0; 1787 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1788 "pci"); 1789 pci_load_vendor_data(); 1790 break; 1791 1792 case MOD_UNLOAD: 1793 destroy_dev(pci_cdev); 1794 break; 1795 } 1796 1797 return (0); 1798} 1799 1800static void 1801pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1802{ 1803 int i; 1804 1805 /* 1806 * Only do header type 0 devices. Type 1 devices are bridges, 1807 * which we know need special treatment. Type 2 devices are 1808 * cardbus bridges which also require special treatment. 1809 * Other types are unknown, and we err on the side of safety 1810 * by ignoring them. 1811 */ 1812 if (dinfo->cfg.hdrtype != 0) 1813 return; 1814 /* 1815 * Restore the device to full power mode. We must do this 1816 * before we restore the registers because moving from D3 to 1817 * D0 will cause the chip's BARs and some other registers to 1818 * be reset to some unknown power on reset values. Cut down 1819 * the noise on boot by doing nothing if we are already in 1820 * state D0. 1821 */ 1822 if (pci_do_powerstate && (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)) { 1823 if (bootverbose) 1824 printf( 1825 "pci%d:%d:%d: Transition from D%d to D0\n", 1826 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1827 pci_get_powerstate(dev)); 1828 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1829 } 1830 for (i = 0; i < dinfo->cfg.nummaps; i++) 1831 pci_write_config(dev, PCIR_MAPS + i * 4, dinfo->cfg.bar[i], 4); 1832 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1833 pci_write_config(dev, PCIR_SUBVEND_0, dinfo->cfg.subdevice, 2); 1834 pci_write_config(dev, PCIR_SUBDEV_0, dinfo->cfg.subdevice, 2); 1835 pci_write_config(dev, PCIR_VENDOR, dinfo->cfg.vendor, 2); 1836 pci_write_config(dev, PCIR_DEVICE, dinfo->cfg.device, 2); 1837 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1838 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1839 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1840 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1841 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1842 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1843 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1844 pci_write_config(dev, PCIR_CLASS, dinfo->cfg.baseclass, 1); 1845 pci_write_config(dev, PCIR_SUBCLASS, dinfo->cfg.subclass, 1); 1846 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1847 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1848} 1849 1850static void 1851pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1852{ 1853 int i; 1854 uint32_t cls; 1855 int ps; 1856 1857 /* 1858 * Only do header type 0 devices. Type 1 devices are bridges, which 1859 * we know need special treatment. Type 2 devices are cardbus bridges 1860 * which also require special treatment. Other types are unknown, and 1861 * we err on the side of safety by ignoring them. Powering down 1862 * bridges should not be undertaken lightly. 1863 */ 1864 if (dinfo->cfg.hdrtype != 0) 1865 return; 1866 for (i = 0; i < dinfo->cfg.nummaps; i++) 1867 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1868 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1869 1870 /* 1871 * Some drivers apparently write to these registers w/o 1872 * updating our cahced copy. No harm happens if we update the 1873 * copy, so do so here so we can restore them. The COMMAND 1874 * register is modified by the bus w/o updating the cache. This 1875 * should represent the normally writable portion of the 'defined' 1876 * part of type 0 headers. In theory we also need to save/restore 1877 * the PCI capability structures we know about, but apart from power 1878 * we don't know any that are writable. 1879 */ 1880 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1881 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1882 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1883 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1884 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1885 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1886 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1887 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1888 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1889 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1890 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1891 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1892 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1893 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1894 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1895 1896 /* 1897 * don't set the state for display devices and for memory devices 1898 * since bad things happen. we should (a) have drivers that can easily 1899 * detach and (b) use generic drivers for these devices so that some 1900 * device actually attaches. We need to make sure that when we 1901 * implement (a) we don't power the device down on a reattach. 1902 */ 1903 cls = pci_get_class(dev); 1904 if (pci_do_powerstate && setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY) { 1905 /* 1906 * PCI spec is clear that we can only go into D3 state from 1907 * D0 state. Transition from D[12] into D0 before going 1908 * to D3 state. 1909 */ 1910 ps = pci_get_powerstate(dev); 1911 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1912 if (bootverbose) 1913 printf( 1914 "pci%d:%d:%d: Transition from D%d to D0\n", 1915 dinfo->cfg.bus, dinfo->cfg.slot, 1916 dinfo->cfg.func, ps); 1917 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1918 } 1919 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1920 if (bootverbose) 1921 printf( 1922 "pci%d:%d:%d: Transition from D0 to D3\n", 1923 dinfo->cfg.bus, dinfo->cfg.slot, 1924 dinfo->cfg.func); 1925 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1926 } 1927 } 1928} 1929