pci.c revision 128107
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 128107 2004-04-11 07:02:49Z imp $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static uint32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68 69static int pci_porten(device_t pcib, int b, int s, int f); 70static int pci_memen(device_t pcib, int b, int s, int f); 71static int pci_add_map(device_t pcib, device_t bus, device_t dev, 72 int b, int s, int f, int reg, 73 struct resource_list *rl); 74static void pci_add_resources(device_t pcib, device_t bus, 75 device_t dev); 76static int pci_probe(device_t dev); 77static int pci_attach(device_t dev); 78static void pci_load_vendor_data(void); 79static int pci_describe_parse_line(char **ptr, int *vendor, 80 int *device, char **desc); 81static char *pci_describe_device(device_t dev); 82static int pci_modevent(module_t mod, int what, void *arg); 83static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 84 pcicfgregs *cfg); 85static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 86static void pci_cfg_restore(device_t, struct pci_devinfo *); 87static void pci_cfg_save(device_t, struct pci_devinfo *, int); 88 89static device_method_t pci_methods[] = { 90 /* Device interface */ 91 DEVMETHOD(device_probe, pci_probe), 92 DEVMETHOD(device_attach, pci_attach), 93 DEVMETHOD(device_shutdown, bus_generic_shutdown), 94 DEVMETHOD(device_suspend, pci_suspend), 95 DEVMETHOD(device_resume, pci_resume), 96 97 /* Bus interface */ 98 DEVMETHOD(bus_print_child, pci_print_child), 99 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 100 DEVMETHOD(bus_read_ivar, pci_read_ivar), 101 DEVMETHOD(bus_write_ivar, pci_write_ivar), 102 DEVMETHOD(bus_driver_added, pci_driver_added), 103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 105 106 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 107 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 108 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 109 DEVMETHOD(bus_delete_resource, pci_delete_resource), 110 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 111 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 112 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 113 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 114 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 115 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 116 117 /* PCI interface */ 118 DEVMETHOD(pci_read_config, pci_read_config_method), 119 DEVMETHOD(pci_write_config, pci_write_config_method), 120 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 121 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 122 DEVMETHOD(pci_enable_io, pci_enable_io_method), 123 DEVMETHOD(pci_disable_io, pci_disable_io_method), 124 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 125 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 126 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 127 128 { 0, 0 } 129}; 130 131DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 132 133devclass_t pci_devclass; 134DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 135MODULE_VERSION(pci, 1); 136 137static char *pci_vendordata; 138static size_t pci_vendordata_size; 139 140 141struct pci_quirk { 142 uint32_t devid; /* Vendor/device of the card */ 143 int type; 144#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 145 int arg1; 146 int arg2; 147}; 148 149struct pci_quirk pci_quirks[] = { 150 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 151 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 153 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 154 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 155 156 { 0 } 157}; 158 159/* map register information */ 160#define PCI_MAPMEM 0x01 /* memory map */ 161#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 162#define PCI_MAPPORT 0x04 /* port map */ 163 164struct devlist pci_devq; 165uint32_t pci_generation; 166uint32_t pci_numdevs = 0; 167 168/* sysctl vars */ 169SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 170 171static int pci_enable_io_modes = 1; 172TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 173SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 174 &pci_enable_io_modes, 1, 175 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 176enable these bits correctly. We'd like to do this all the time, but there\n\ 177are some peripherals that this causes problems with."); 178 179static int pci_do_powerstate = 0; 180TUNABLE_INT("hw.pci.do_powerstate", (int *)&pci_do_powerstate); 181SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 182 &pci_do_powerstate, 0, 183 "Enable setting the power states of the PCI devices. This means that we\n\ 184set devices into D0 before probe/attach, and D3 if they fail to attach. It\n\ 185also means we set devices into D3 state before shutdown."); 186 187/* Find a device_t by bus/slot/function */ 188 189device_t 190pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 191{ 192 struct pci_devinfo *dinfo; 193 194 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 195 if ((dinfo->cfg.bus == bus) && 196 (dinfo->cfg.slot == slot) && 197 (dinfo->cfg.func == func)) { 198 return (dinfo->cfg.dev); 199 } 200 } 201 202 return (NULL); 203} 204 205/* Find a device_t by vendor/device ID */ 206 207device_t 208pci_find_device(uint16_t vendor, uint16_t device) 209{ 210 struct pci_devinfo *dinfo; 211 212 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 213 if ((dinfo->cfg.vendor == vendor) && 214 (dinfo->cfg.device == device)) { 215 return (dinfo->cfg.dev); 216 } 217 } 218 219 return (NULL); 220} 221 222/* return base address of memory or port map */ 223 224static uint32_t 225pci_mapbase(unsigned mapreg) 226{ 227 int mask = 0x03; 228 if ((mapreg & 0x01) == 0) 229 mask = 0x0f; 230 return (mapreg & ~mask); 231} 232 233/* return map type of memory or port map */ 234 235static int 236pci_maptype(unsigned mapreg) 237{ 238 static uint8_t maptype[0x10] = { 239 PCI_MAPMEM, PCI_MAPPORT, 240 PCI_MAPMEM, 0, 241 PCI_MAPMEM, PCI_MAPPORT, 242 0, 0, 243 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 244 PCI_MAPMEM|PCI_MAPMEMP, 0, 245 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 246 0, 0, 247 }; 248 249 return maptype[mapreg & 0x0f]; 250} 251 252/* return log2 of map size decoded for memory or port map */ 253 254static int 255pci_mapsize(unsigned testval) 256{ 257 int ln2size; 258 259 testval = pci_mapbase(testval); 260 ln2size = 0; 261 if (testval != 0) { 262 while ((testval & 1) == 0) 263 { 264 ln2size++; 265 testval >>= 1; 266 } 267 } 268 return (ln2size); 269} 270 271/* return log2 of address range supported by map register */ 272 273static int 274pci_maprange(unsigned mapreg) 275{ 276 int ln2range = 0; 277 switch (mapreg & 0x07) { 278 case 0x00: 279 case 0x01: 280 case 0x05: 281 ln2range = 32; 282 break; 283 case 0x02: 284 ln2range = 20; 285 break; 286 case 0x04: 287 ln2range = 64; 288 break; 289 } 290 return (ln2range); 291} 292 293/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 294 295static void 296pci_fixancient(pcicfgregs *cfg) 297{ 298 if (cfg->hdrtype != 0) 299 return; 300 301 /* PCI to PCI bridges use header type 1 */ 302 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 303 cfg->hdrtype = 1; 304} 305 306/* extract header type specific config data */ 307 308static void 309pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 310{ 311#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 312 switch (cfg->hdrtype) { 313 case 0: 314 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 315 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 316 cfg->nummaps = PCI_MAXMAPS_0; 317 break; 318 case 1: 319 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 320 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 321 cfg->nummaps = PCI_MAXMAPS_1; 322 break; 323 case 2: 324 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 325 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 326 cfg->nummaps = PCI_MAXMAPS_2; 327 break; 328 } 329#undef REG 330} 331 332/* read configuration header into pcicfgregs structure */ 333 334struct pci_devinfo * 335pci_read_device(device_t pcib, int b, int s, int f, size_t size) 336{ 337#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 338 pcicfgregs *cfg = NULL; 339 struct pci_devinfo *devlist_entry; 340 struct devlist *devlist_head; 341 342 devlist_head = &pci_devq; 343 344 devlist_entry = NULL; 345 346 if (REG(PCIR_DEVVENDOR, 4) != -1) { 347 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 348 if (devlist_entry == NULL) 349 return (NULL); 350 351 cfg = &devlist_entry->cfg; 352 353 cfg->bus = b; 354 cfg->slot = s; 355 cfg->func = f; 356 cfg->vendor = REG(PCIR_VENDOR, 2); 357 cfg->device = REG(PCIR_DEVICE, 2); 358 cfg->cmdreg = REG(PCIR_COMMAND, 2); 359 cfg->statreg = REG(PCIR_STATUS, 2); 360 cfg->baseclass = REG(PCIR_CLASS, 1); 361 cfg->subclass = REG(PCIR_SUBCLASS, 1); 362 cfg->progif = REG(PCIR_PROGIF, 1); 363 cfg->revid = REG(PCIR_REVID, 1); 364 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 365 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 366 cfg->lattimer = REG(PCIR_LATTIMER, 1); 367 cfg->intpin = REG(PCIR_INTPIN, 1); 368 cfg->intline = REG(PCIR_INTLINE, 1); 369 370 cfg->mingnt = REG(PCIR_MINGNT, 1); 371 cfg->maxlat = REG(PCIR_MAXLAT, 1); 372 373 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 374 cfg->hdrtype &= ~PCIM_MFDEV; 375 376 pci_fixancient(cfg); 377 pci_hdrtypedata(pcib, b, s, f, cfg); 378 379 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 380 pci_read_extcap(pcib, cfg); 381 382 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 383 384 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 385 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 386 devlist_entry->conf.pc_sel.pc_func = cfg->func; 387 devlist_entry->conf.pc_hdr = cfg->hdrtype; 388 389 devlist_entry->conf.pc_subvendor = cfg->subvendor; 390 devlist_entry->conf.pc_subdevice = cfg->subdevice; 391 devlist_entry->conf.pc_vendor = cfg->vendor; 392 devlist_entry->conf.pc_device = cfg->device; 393 394 devlist_entry->conf.pc_class = cfg->baseclass; 395 devlist_entry->conf.pc_subclass = cfg->subclass; 396 devlist_entry->conf.pc_progif = cfg->progif; 397 devlist_entry->conf.pc_revid = cfg->revid; 398 399 pci_numdevs++; 400 pci_generation++; 401 } 402 return (devlist_entry); 403#undef REG 404} 405 406static void 407pci_read_extcap(device_t pcib, pcicfgregs *cfg) 408{ 409#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 410 int ptr, nextptr, ptrptr; 411 412 switch (cfg->hdrtype & PCIM_HDRTYPE) { 413 case 0: 414 ptrptr = PCIR_CAP_PTR; 415 break; 416 case 2: 417 ptrptr = 0x14; 418 break; 419 default: 420 return; /* no extended capabilities support */ 421 } 422 nextptr = REG(ptrptr, 1); /* sanity check? */ 423 424 /* 425 * Read capability entries. 426 */ 427 while (nextptr != 0) { 428 /* Sanity check */ 429 if (nextptr > 255) { 430 printf("illegal PCI extended capability offset %d\n", 431 nextptr); 432 return; 433 } 434 /* Find the next entry */ 435 ptr = nextptr; 436 nextptr = REG(ptr + 1, 1); 437 438 /* Process this entry */ 439 switch (REG(ptr, 1)) { 440 case PCIY_PMG: /* PCI power management */ 441 if (cfg->pp.pp_cap == 0) { 442 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 443 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 444 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 445 if ((nextptr - ptr) > PCIR_POWER_DATA) 446 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 447 } 448 break; 449 case PCIY_MSI: /* PCI MSI */ 450 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 451 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 452 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 453 else 454 cfg->msi.msi_data = PCIR_MSI_DATA; 455 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 456 PCIM_MSICTRL_MMC_MASK)>>1); 457 default: 458 break; 459 } 460 } 461#undef REG 462} 463 464/* free pcicfgregs structure and all depending data structures */ 465 466int 467pci_freecfg(struct pci_devinfo *dinfo) 468{ 469 struct devlist *devlist_head; 470 471 devlist_head = &pci_devq; 472 473 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 474 free(dinfo, M_DEVBUF); 475 476 /* increment the generation count */ 477 pci_generation++; 478 479 /* we're losing one device */ 480 pci_numdevs--; 481 return (0); 482} 483 484/* 485 * PCI power manangement 486 */ 487int 488pci_set_powerstate_method(device_t dev, device_t child, int state) 489{ 490 struct pci_devinfo *dinfo = device_get_ivars(child); 491 pcicfgregs *cfg = &dinfo->cfg; 492 uint16_t status; 493 int result; 494 495 /* 496 * Dx -> Dx is a nop always. 497 */ 498 if (pci_get_powerstate(dev) == state) 499 return (0); 500 501 if (cfg->pp.pp_cap != 0) { 502 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 503 & ~PCIM_PSTAT_DMASK; 504 result = 0; 505 switch (state) { 506 case PCI_POWERSTATE_D0: 507 status |= PCIM_PSTAT_D0; 508 break; 509 case PCI_POWERSTATE_D1: 510 if (cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) { 511 status |= PCIM_PSTAT_D1; 512 } else { 513 result = EOPNOTSUPP; 514 } 515 break; 516 case PCI_POWERSTATE_D2: 517 if (cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) { 518 status |= PCIM_PSTAT_D2; 519 } else { 520 result = EOPNOTSUPP; 521 } 522 break; 523 case PCI_POWERSTATE_D3: 524 status |= PCIM_PSTAT_D3; 525 break; 526 default: 527 result = EINVAL; 528 } 529 if (result == 0) 530 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 531 2); 532 } else { 533 result = ENXIO; 534 } 535 return(result); 536} 537 538int 539pci_get_powerstate_method(device_t dev, device_t child) 540{ 541 struct pci_devinfo *dinfo = device_get_ivars(child); 542 pcicfgregs *cfg = &dinfo->cfg; 543 uint16_t status; 544 int result; 545 546 if (cfg->pp.pp_cap != 0) { 547 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 548 switch (status & PCIM_PSTAT_DMASK) { 549 case PCIM_PSTAT_D0: 550 result = PCI_POWERSTATE_D0; 551 break; 552 case PCIM_PSTAT_D1: 553 result = PCI_POWERSTATE_D1; 554 break; 555 case PCIM_PSTAT_D2: 556 result = PCI_POWERSTATE_D2; 557 break; 558 case PCIM_PSTAT_D3: 559 result = PCI_POWERSTATE_D3; 560 break; 561 default: 562 result = PCI_POWERSTATE_UNKNOWN; 563 break; 564 } 565 } else { 566 /* No support, device is always at D0 */ 567 result = PCI_POWERSTATE_D0; 568 } 569 return(result); 570} 571 572/* 573 * Some convenience functions for PCI device drivers. 574 */ 575 576static __inline void 577pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 578{ 579 uint16_t command; 580 581 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 582 command |= bit; 583 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 584} 585 586static __inline void 587pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 588{ 589 uint16_t command; 590 591 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 592 command &= ~bit; 593 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 594} 595 596int 597pci_enable_busmaster_method(device_t dev, device_t child) 598{ 599 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 600 return (0); 601} 602 603int 604pci_disable_busmaster_method(device_t dev, device_t child) 605{ 606 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 607 return (0); 608} 609 610int 611pci_enable_io_method(device_t dev, device_t child, int space) 612{ 613 uint16_t command; 614 uint16_t bit; 615 char *error; 616 617 bit = 0; 618 error = NULL; 619 620 switch(space) { 621 case SYS_RES_IOPORT: 622 bit = PCIM_CMD_PORTEN; 623 error = "port"; 624 break; 625 case SYS_RES_MEMORY: 626 bit = PCIM_CMD_MEMEN; 627 error = "memory"; 628 break; 629 default: 630 return (EINVAL); 631 } 632 pci_set_command_bit(dev, child, bit); 633 /* Some devices seem to need a brief stall here, what do to? */ 634 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 635 if (command & bit) 636 return (0); 637 device_printf(child, "failed to enable %s mapping!\n", error); 638 return (ENXIO); 639} 640 641int 642pci_disable_io_method(device_t dev, device_t child, int space) 643{ 644 uint16_t command; 645 uint16_t bit; 646 char *error; 647 648 bit = 0; 649 error = NULL; 650 651 switch(space) { 652 case SYS_RES_IOPORT: 653 bit = PCIM_CMD_PORTEN; 654 error = "port"; 655 break; 656 case SYS_RES_MEMORY: 657 bit = PCIM_CMD_MEMEN; 658 error = "memory"; 659 break; 660 default: 661 return (EINVAL); 662 } 663 pci_clear_command_bit(dev, child, bit); 664 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 665 if (command & bit) { 666 device_printf(child, "failed to disable %s mapping!\n", error); 667 return (ENXIO); 668 } 669 return (0); 670} 671 672/* 673 * New style pci driver. Parent device is either a pci-host-bridge or a 674 * pci-pci-bridge. Both kinds are represented by instances of pcib. 675 */ 676 677void 678pci_print_verbose(struct pci_devinfo *dinfo) 679{ 680 if (bootverbose) { 681 pcicfgregs *cfg = &dinfo->cfg; 682 683 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 684 cfg->vendor, cfg->device, cfg->revid); 685 printf("\tbus=%d, slot=%d, func=%d\n", 686 cfg->bus, cfg->slot, cfg->func); 687 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 688 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 689 cfg->mfdev); 690 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 691 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 692 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 693 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 694 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 695 if (cfg->intpin > 0) 696 printf("\tintpin=%c, irq=%d\n", 697 cfg->intpin +'a' -1, cfg->intline); 698 if (cfg->pp.pp_cap) { 699 uint16_t status; 700 701 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 702 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 703 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 704 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 705 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 706 status & PCIM_PSTAT_DMASK); 707 } 708 if (cfg->msi.msi_data) { 709 int ctrl; 710 711 ctrl = cfg->msi.msi_ctrl; 712 printf("\tMSI supports %d message%s%s%s\n", 713 cfg->msi.msi_msgnum, 714 (cfg->msi.msi_msgnum == 1) ? "" : "s", 715 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 716 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 717 } 718 } 719} 720 721static int 722pci_porten(device_t pcib, int b, int s, int f) 723{ 724 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 725 & PCIM_CMD_PORTEN) != 0; 726} 727 728static int 729pci_memen(device_t pcib, int b, int s, int f) 730{ 731 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 732 & PCIM_CMD_MEMEN) != 0; 733} 734 735/* 736 * Add a resource based on a pci map register. Return 1 if the map 737 * register is a 32bit map register or 2 if it is a 64bit register. 738 */ 739static int 740pci_add_map(device_t pcib, device_t bus, device_t dev, 741 int b, int s, int f, int reg, struct resource_list *rl) 742{ 743 uint32_t map; 744 uint64_t base; 745 uint64_t start, end, count; 746 uint8_t ln2size; 747 uint8_t ln2range; 748 uint32_t testval; 749 uint16_t cmd; 750 int type; 751 752 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 753 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 754 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 755 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 756 757 if (pci_maptype(map) & PCI_MAPMEM) 758 type = SYS_RES_MEMORY; 759 else 760 type = SYS_RES_IOPORT; 761 ln2size = pci_mapsize(testval); 762 ln2range = pci_maprange(testval); 763 base = pci_mapbase(map); 764 765 /* 766 * For I/O registers, if bottom bit is set, and the next bit up 767 * isn't clear, we know we have a BAR that doesn't conform to the 768 * spec, so ignore it. Also, sanity check the size of the data 769 * areas to the type of memory involved. Memory must be at least 770 * 32 bytes in size, while I/O ranges must be at least 4. 771 */ 772 if ((testval & 0x1) == 0x1 && 773 (testval & 0x2) != 0) 774 return (1); 775 if ((type == SYS_RES_MEMORY && ln2size < 5) || 776 (type == SYS_RES_IOPORT && ln2size < 2)) 777 return (1); 778 779 if (ln2range == 64) 780 /* Read the other half of a 64bit map register */ 781 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 782 783 if (bootverbose) { 784 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 785 reg, pci_maptype(map), ln2range, 786 (unsigned int) base, ln2size); 787 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 788 printf(", port disabled\n"); 789 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 790 printf(", memory disabled\n"); 791 else 792 printf(", enabled\n"); 793 } 794 795 /* 796 * This code theoretically does the right thing, but has 797 * undesirable side effects in some cases where peripherals 798 * respond oddly to having these bits enabled. Let the user 799 * be able to turn them off (since pci_enable_io_modes is 1 by 800 * default). 801 */ 802 if (pci_enable_io_modes) { 803 /* Turn on resources that have been left off by a lazy BIOS */ 804 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 805 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 806 cmd |= PCIM_CMD_PORTEN; 807 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 808 } 809 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 810 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 811 cmd |= PCIM_CMD_MEMEN; 812 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 813 } 814 } else { 815 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 816 return (1); 817 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 818 return (1); 819 } 820 /* 821 * If base is 0, then we have problems. It is best to ignore 822 * such entires for the moment. These will be allocated later if 823 * the driver specifically requests them. 824 */ 825 if (base == 0) 826 return 1; 827 start = base; 828 end = base + (1 << ln2size) - 1; 829 count = 1 << ln2size; 830 resource_list_add(rl, type, reg, start, end, count); 831 832 /* 833 * Not quite sure what to do on failure of allocating the resource 834 * since I can postulate several right answers. 835 */ 836 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 837 return ((ln2range == 64) ? 2 : 1); 838} 839 840static void 841pci_add_resources(device_t pcib, device_t bus, device_t dev) 842{ 843 struct pci_devinfo *dinfo = device_get_ivars(dev); 844 pcicfgregs *cfg = &dinfo->cfg; 845 struct resource_list *rl = &dinfo->resources; 846 struct pci_quirk *q; 847 int b, i, irq, f, s; 848 849 b = cfg->bus; 850 s = cfg->slot; 851 f = cfg->func; 852 for (i = 0; i < cfg->nummaps;) 853 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), rl); 854 855 for (q = &pci_quirks[0]; q->devid; q++) { 856 if (q->devid == ((cfg->device << 16) | cfg->vendor) 857 && q->type == PCI_QUIRK_MAP_REG) 858 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 859 } 860 861 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 862#if defined(__ia64__) || defined(__i386__) || defined(__amd64__) 863 /* 864 * Try to re-route interrupts. Sometimes the BIOS or 865 * firmware may leave bogus values in these registers. 866 * If the re-route fails, then just stick with what we 867 * have. 868 */ 869 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 870 if (PCI_INTERRUPT_VALID(irq)) { 871 pci_write_config(dev, PCIR_INTLINE, irq, 1); 872 cfg->intline = irq; 873 } else 874#endif 875 irq = cfg->intline; 876 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 877 } 878} 879 880void 881pci_add_children(device_t dev, int busno, size_t dinfo_size) 882{ 883#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 884 device_t pcib = device_get_parent(dev); 885 struct pci_devinfo *dinfo; 886 int maxslots; 887 int s, f, pcifunchigh; 888 uint8_t hdrtype; 889 890 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 891 ("dinfo_size too small")); 892 maxslots = PCIB_MAXSLOTS(pcib); 893 for (s = 0; s <= maxslots; s++) { 894 pcifunchigh = 0; 895 f = 0; 896 hdrtype = REG(PCIR_HDRTYPE, 1); 897 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 898 continue; 899 if (hdrtype & PCIM_MFDEV) 900 pcifunchigh = PCI_FUNCMAX; 901 for (f = 0; f <= pcifunchigh; f++) { 902 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 903 if (dinfo != NULL) { 904 pci_add_child(dev, dinfo); 905 } 906 } 907 } 908#undef REG 909} 910 911void 912pci_add_child(device_t bus, struct pci_devinfo *dinfo) 913{ 914 device_t pcib; 915 916 pcib = device_get_parent(bus); 917 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 918 device_set_ivars(dinfo->cfg.dev, dinfo); 919 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 920 pci_cfg_restore(dinfo->cfg.dev, dinfo); 921 pci_add_resources(pcib, bus, dinfo->cfg.dev); 922 pci_print_verbose(dinfo); 923} 924 925static int 926pci_probe(device_t dev) 927{ 928 929 device_set_desc(dev, "PCI bus"); 930 931 /* Allow other subclasses to override this driver. */ 932 return (-1000); 933} 934 935static int 936pci_attach(device_t dev) 937{ 938 int busno; 939 940 /* 941 * Since there can be multiple independantly numbered PCI 942 * busses on some large alpha systems, we can't use the unit 943 * number to decide what bus we are probing. We ask the parent 944 * pcib what our bus number is. 945 */ 946 busno = pcib_get_bus(dev); 947 if (bootverbose) 948 device_printf(dev, "physical bus=%d\n", busno); 949 950 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 951 952 return (bus_generic_attach(dev)); 953} 954 955int 956pci_suspend(device_t dev) 957{ 958 int numdevs; 959 device_t *devlist; 960 device_t child; 961 struct pci_devinfo *dinfo; 962 int i; 963 964 /* 965 * Save the pci configuration space for each child. We don't need 966 * to do this, unless the BIOS suspend code powers down the bus and 967 * the devices on the bus. 968 */ 969 device_get_children(dev, &devlist, &numdevs); 970 for (i = 0; i < numdevs; i++) { 971 child = devlist[i]; 972 dinfo = (struct pci_devinfo *) device_get_ivars(child); 973 pci_cfg_save(child, dinfo, 0); 974 } 975 free(devlist, M_TEMP); 976 return (bus_generic_suspend(dev)); 977} 978 979int 980pci_resume(device_t dev) 981{ 982 int numdevs; 983 device_t *devlist; 984 device_t child; 985 struct pci_devinfo *dinfo; 986 int i; 987 988 /* 989 * Restore the pci configuration space for each child. 990 */ 991 device_get_children(dev, &devlist, &numdevs); 992 for (i = 0; i < numdevs; i++) { 993 child = devlist[i]; 994 dinfo = (struct pci_devinfo *) device_get_ivars(child); 995 pci_cfg_restore(child, dinfo); 996 } 997 free(devlist, M_TEMP); 998 return (bus_generic_resume(dev)); 999} 1000 1001static void 1002pci_load_vendor_data(void) 1003{ 1004 caddr_t vendordata, info; 1005 1006 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1007 info = preload_search_info(vendordata, MODINFO_ADDR); 1008 pci_vendordata = *(char **)info; 1009 info = preload_search_info(vendordata, MODINFO_SIZE); 1010 pci_vendordata_size = *(size_t *)info; 1011 /* terminate the database */ 1012 pci_vendordata[pci_vendordata_size] = '\n'; 1013 } 1014} 1015 1016void 1017pci_driver_added(device_t dev, driver_t *driver) 1018{ 1019 int numdevs; 1020 device_t *devlist; 1021 device_t child; 1022 struct pci_devinfo *dinfo; 1023 int i; 1024 1025 device_printf(dev, "driver added\n"); 1026 DEVICE_IDENTIFY(driver, dev); 1027 device_get_children(dev, &devlist, &numdevs); 1028 for (i = 0; i < numdevs; i++) { 1029 child = devlist[i]; 1030 if (device_get_state(child) != DS_NOTPRESENT) 1031 continue; 1032 dinfo = device_get_ivars(child); 1033 pci_print_verbose(dinfo); 1034/*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */ 1035 printf("pci%d:%d:%d: reprobing on driver added\n", 1036 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1037 pci_cfg_restore(child, dinfo); 1038 if (device_probe_and_attach(child) != 0) 1039 pci_cfg_save(child, dinfo, 1); 1040 } 1041 free(devlist, M_TEMP); 1042} 1043 1044int 1045pci_print_child(device_t dev, device_t child) 1046{ 1047 struct pci_devinfo *dinfo; 1048 struct resource_list *rl; 1049 int retval = 0; 1050 1051 dinfo = device_get_ivars(child); 1052 rl = &dinfo->resources; 1053 1054 retval += bus_print_child_header(dev, child); 1055 1056 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1057 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1058 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1059 if (device_get_flags(dev)) 1060 retval += printf(" flags %#x", device_get_flags(dev)); 1061 1062 retval += printf(" at device %d.%d", pci_get_slot(child), 1063 pci_get_function(child)); 1064 1065 retval += bus_print_child_footer(dev, child); 1066 1067 return (retval); 1068} 1069 1070static struct 1071{ 1072 int class; 1073 int subclass; 1074 char *desc; 1075} pci_nomatch_tab[] = { 1076 {PCIC_OLD, -1, "old"}, 1077 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1078 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1079 {PCIC_STORAGE, -1, "mass storage"}, 1080 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1081 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1082 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1083 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1084 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1085 {PCIC_NETWORK, -1, "network"}, 1086 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1087 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1088 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1089 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1090 {PCIC_DISPLAY, -1, "display"}, 1091 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1092 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1093 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1094 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1095 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1096 {PCIC_MEMORY, -1, "memory"}, 1097 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1098 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1099 {PCIC_BRIDGE, -1, "bridge"}, 1100 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1101 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1102 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1103 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1104 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1105 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1106 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1107 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1108 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1109 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1110 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1111 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1112 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1113 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1114 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1115 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1116 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1117 {PCIC_INPUTDEV, -1, "input device"}, 1118 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1119 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1120 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1121 {PCIC_DOCKING, -1, "docking station"}, 1122 {PCIC_PROCESSOR, -1, "processor"}, 1123 {PCIC_SERIALBUS, -1, "serial bus"}, 1124 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1125 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1126 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1127 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1128 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1129 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1130 {0, 0, NULL} 1131}; 1132 1133void 1134pci_probe_nomatch(device_t dev, device_t child) 1135{ 1136 int i; 1137 char *cp, *scp, *device; 1138 1139 /* 1140 * Look for a listing for this device in a loaded device database. 1141 */ 1142 if ((device = pci_describe_device(child)) != NULL) { 1143 device_printf(dev, "<%s>", device); 1144 free(device, M_DEVBUF); 1145 } else { 1146 /* 1147 * Scan the class/subclass descriptions for a general 1148 * description. 1149 */ 1150 cp = "unknown"; 1151 scp = NULL; 1152 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1153 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1154 if (pci_nomatch_tab[i].subclass == -1) { 1155 cp = pci_nomatch_tab[i].desc; 1156 } else if (pci_nomatch_tab[i].subclass == 1157 pci_get_subclass(child)) { 1158 scp = pci_nomatch_tab[i].desc; 1159 } 1160 } 1161 } 1162 device_printf(dev, "<%s%s%s>", 1163 cp ? cp : "", 1164 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1165 scp ? scp : ""); 1166 } 1167 printf(" at device %d.%d (no driver attached)\n", 1168 pci_get_slot(child), pci_get_function(child)); 1169 pci_cfg_save(child, (struct pci_devinfo *) device_get_ivars(child), 1); 1170 return; 1171} 1172 1173/* 1174 * Parse the PCI device database, if loaded, and return a pointer to a 1175 * description of the device. 1176 * 1177 * The database is flat text formatted as follows: 1178 * 1179 * Any line not in a valid format is ignored. 1180 * Lines are terminated with newline '\n' characters. 1181 * 1182 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1183 * the vendor name. 1184 * 1185 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1186 * - devices cannot be listed without a corresponding VENDOR line. 1187 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1188 * another TAB, then the device name. 1189 */ 1190 1191/* 1192 * Assuming (ptr) points to the beginning of a line in the database, 1193 * return the vendor or device and description of the next entry. 1194 * The value of (vendor) or (device) inappropriate for the entry type 1195 * is set to -1. Returns nonzero at the end of the database. 1196 * 1197 * Note that this is slightly unrobust in the face of corrupt data; 1198 * we attempt to safeguard against this by spamming the end of the 1199 * database with a newline when we initialise. 1200 */ 1201static int 1202pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1203{ 1204 char *cp = *ptr; 1205 int left; 1206 1207 *device = -1; 1208 *vendor = -1; 1209 **desc = '\0'; 1210 for (;;) { 1211 left = pci_vendordata_size - (cp - pci_vendordata); 1212 if (left <= 0) { 1213 *ptr = cp; 1214 return(1); 1215 } 1216 1217 /* vendor entry? */ 1218 if (*cp != '\t' && 1219 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1220 break; 1221 /* device entry? */ 1222 if (*cp == '\t' && 1223 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1224 break; 1225 1226 /* skip to next line */ 1227 while (*cp != '\n' && left > 0) { 1228 cp++; 1229 left--; 1230 } 1231 if (*cp == '\n') { 1232 cp++; 1233 left--; 1234 } 1235 } 1236 /* skip to next line */ 1237 while (*cp != '\n' && left > 0) { 1238 cp++; 1239 left--; 1240 } 1241 if (*cp == '\n' && left > 0) 1242 cp++; 1243 *ptr = cp; 1244 return(0); 1245} 1246 1247static char * 1248pci_describe_device(device_t dev) 1249{ 1250 int vendor, device; 1251 char *desc, *vp, *dp, *line; 1252 1253 desc = vp = dp = NULL; 1254 1255 /* 1256 * If we have no vendor data, we can't do anything. 1257 */ 1258 if (pci_vendordata == NULL) 1259 goto out; 1260 1261 /* 1262 * Scan the vendor data looking for this device 1263 */ 1264 line = pci_vendordata; 1265 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1266 goto out; 1267 for (;;) { 1268 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1269 goto out; 1270 if (vendor == pci_get_vendor(dev)) 1271 break; 1272 } 1273 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1274 goto out; 1275 for (;;) { 1276 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1277 *dp = 0; 1278 break; 1279 } 1280 if (vendor != -1) { 1281 *dp = 0; 1282 break; 1283 } 1284 if (device == pci_get_device(dev)) 1285 break; 1286 } 1287 if (dp[0] == '\0') 1288 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1289 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1290 NULL) 1291 sprintf(desc, "%s, %s", vp, dp); 1292 out: 1293 if (vp != NULL) 1294 free(vp, M_DEVBUF); 1295 if (dp != NULL) 1296 free(dp, M_DEVBUF); 1297 return(desc); 1298} 1299 1300int 1301pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1302{ 1303 struct pci_devinfo *dinfo; 1304 pcicfgregs *cfg; 1305 1306 dinfo = device_get_ivars(child); 1307 cfg = &dinfo->cfg; 1308 1309 switch (which) { 1310 case PCI_IVAR_ETHADDR: 1311 /* 1312 * The generic accessor doesn't deal with failure, so 1313 * we set the return value, then return an error. 1314 */ 1315 *((uint8_t **) result) = NULL; 1316 return (EINVAL); 1317 case PCI_IVAR_SUBVENDOR: 1318 *result = cfg->subvendor; 1319 break; 1320 case PCI_IVAR_SUBDEVICE: 1321 *result = cfg->subdevice; 1322 break; 1323 case PCI_IVAR_VENDOR: 1324 *result = cfg->vendor; 1325 break; 1326 case PCI_IVAR_DEVICE: 1327 *result = cfg->device; 1328 break; 1329 case PCI_IVAR_DEVID: 1330 *result = (cfg->device << 16) | cfg->vendor; 1331 break; 1332 case PCI_IVAR_CLASS: 1333 *result = cfg->baseclass; 1334 break; 1335 case PCI_IVAR_SUBCLASS: 1336 *result = cfg->subclass; 1337 break; 1338 case PCI_IVAR_PROGIF: 1339 *result = cfg->progif; 1340 break; 1341 case PCI_IVAR_REVID: 1342 *result = cfg->revid; 1343 break; 1344 case PCI_IVAR_INTPIN: 1345 *result = cfg->intpin; 1346 break; 1347 case PCI_IVAR_IRQ: 1348 *result = cfg->intline; 1349 break; 1350 case PCI_IVAR_BUS: 1351 *result = cfg->bus; 1352 break; 1353 case PCI_IVAR_SLOT: 1354 *result = cfg->slot; 1355 break; 1356 case PCI_IVAR_FUNCTION: 1357 *result = cfg->func; 1358 break; 1359 default: 1360 return (ENOENT); 1361 } 1362 return (0); 1363} 1364 1365int 1366pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1367{ 1368 struct pci_devinfo *dinfo; 1369 1370 dinfo = device_get_ivars(child); 1371 1372 switch (which) { 1373 case PCI_IVAR_INTPIN: 1374 dinfo->cfg.intpin = value; 1375 return (0); 1376 case PCI_IVAR_ETHADDR: 1377 case PCI_IVAR_SUBVENDOR: 1378 case PCI_IVAR_SUBDEVICE: 1379 case PCI_IVAR_VENDOR: 1380 case PCI_IVAR_DEVICE: 1381 case PCI_IVAR_DEVID: 1382 case PCI_IVAR_CLASS: 1383 case PCI_IVAR_SUBCLASS: 1384 case PCI_IVAR_PROGIF: 1385 case PCI_IVAR_REVID: 1386 case PCI_IVAR_IRQ: 1387 case PCI_IVAR_BUS: 1388 case PCI_IVAR_SLOT: 1389 case PCI_IVAR_FUNCTION: 1390 return (EINVAL); /* disallow for now */ 1391 1392 default: 1393 return (ENOENT); 1394 } 1395} 1396 1397 1398#include "opt_ddb.h" 1399#ifdef DDB 1400#include <ddb/ddb.h> 1401#include <sys/cons.h> 1402 1403/* 1404 * List resources based on pci map registers, used for within ddb 1405 */ 1406 1407DB_SHOW_COMMAND(pciregs, db_pci_dump) 1408{ 1409 struct pci_devinfo *dinfo; 1410 struct devlist *devlist_head; 1411 struct pci_conf *p; 1412 const char *name; 1413 int i, error, none_count, quit; 1414 1415 none_count = 0; 1416 /* get the head of the device queue */ 1417 devlist_head = &pci_devq; 1418 1419 /* 1420 * Go through the list of devices and print out devices 1421 */ 1422 db_setup_paging(db_simple_pager, &quit, DB_LINES_PER_PAGE); 1423 for (error = 0, i = 0, quit = 0, 1424 dinfo = STAILQ_FIRST(devlist_head); 1425 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1426 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1427 1428 /* Populate pd_name and pd_unit */ 1429 name = NULL; 1430 if (dinfo->cfg.dev) 1431 name = device_get_name(dinfo->cfg.dev); 1432 1433 p = &dinfo->conf; 1434 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1435 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1436 (name && *name) ? name : "none", 1437 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1438 none_count++, 1439 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1440 p->pc_sel.pc_func, (p->pc_class << 16) | 1441 (p->pc_subclass << 8) | p->pc_progif, 1442 (p->pc_subdevice << 16) | p->pc_subvendor, 1443 (p->pc_device << 16) | p->pc_vendor, 1444 p->pc_revid, p->pc_hdr); 1445 } 1446} 1447#endif /* DDB */ 1448 1449/* 1450 * XXX I'm not sure the following is good for 64-bit bars. 1451 */ 1452static struct resource * 1453pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1454 u_long start, u_long end, u_long count, u_int flags) 1455{ 1456 struct pci_devinfo *dinfo = device_get_ivars(child); 1457 struct resource_list *rl = &dinfo->resources; 1458 struct resource_list_entry *rle; 1459 struct resource *res; 1460 uint32_t map, testval; 1461 int mapsize; 1462 1463 /* 1464 * Weed out the bogons, and figure out how large the BAR/map is. 1465 */ 1466 map = pci_read_config(child, *rid, 4); 1467 if (pci_maptype(map) & PCI_MAPMEM) { 1468 if (type != SYS_RES_MEMORY) { 1469 device_printf(child, "rid %#x says memory, driver wants %d failed.\n", *rid, type); 1470 return (NULL); 1471 } 1472 } else { 1473 if (type != SYS_RES_IOPORT) { 1474 device_printf(child, "rid %#x says ioport, driver wants %d failed.\n", *rid, type); 1475 return (NULL); 1476 } 1477 } 1478 pci_write_config(child, *rid, 0xffffffff, 4); 1479 testval = pci_read_config(child, *rid, 4); 1480 1481 /* 1482 * Allocate enough resource, and then write back the 1483 * appropriate bar for that resource (this is the part 1484 * I'm not sure is good for 64-bit bars). 1485 */ 1486 mapsize = pci_mapsize(testval); 1487 count = 1 << mapsize; 1488 if (RF_ALIGNMENT(flags) < mapsize) 1489 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1490 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1491 start, end, count, flags); 1492 if (res == NULL) { 1493 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1494 count, *rid, type); 1495 pci_write_config(child, *rid, map, 4); 1496 return (NULL); 1497 } 1498 resource_list_add(rl, type, *rid, start, end, count); 1499 rle = resource_list_find(rl, type, *rid); 1500 if (rle == NULL) 1501 panic("pci_alloc_map: unexpedly can't find resource."); 1502 rle->res = res; 1503 device_printf(child, "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1504 count, *rid, type, rman_get_start(res)); 1505 pci_write_config(child, *rid, rman_get_start(res), 4); 1506 return (res); 1507} 1508 1509 1510struct resource * 1511pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1512 u_long start, u_long end, u_long count, u_int flags) 1513{ 1514 struct pci_devinfo *dinfo = device_get_ivars(child); 1515 struct resource_list *rl = &dinfo->resources; 1516 struct resource_list_entry *rle; 1517 pcicfgregs *cfg = &dinfo->cfg; 1518 1519 /* 1520 * Perform lazy resource allocation 1521 */ 1522 if (device_get_parent(child) == dev) { 1523 switch (type) { 1524 case SYS_RES_IRQ: 1525 /* 1526 * If the child device doesn't have an 1527 * interrupt routed and is deserving of an 1528 * interrupt, try to assign it one. 1529 */ 1530 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1531 (cfg->intpin != 0)) { 1532 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1533 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1534 pci_write_config(child, PCIR_INTLINE, 1535 cfg->intline, 1); 1536 resource_list_add(rl, SYS_RES_IRQ, 0, 1537 cfg->intline, cfg->intline, 1); 1538 } 1539 } 1540 break; 1541 case SYS_RES_IOPORT: 1542 case SYS_RES_MEMORY: 1543 if (*rid < PCIR_BAR(cfg->nummaps)) { 1544 /* 1545 * Enable the I/O mode. We should 1546 * also be assigning resources too 1547 * when none are present. The 1548 * resource_list_alloc kind of sorta does 1549 * this... 1550 */ 1551 if (PCI_ENABLE_IO(dev, child, type)) 1552 return (NULL); 1553 } 1554 rle = resource_list_find(rl, type, *rid); 1555 if (rle == NULL) 1556 return (pci_alloc_map(dev, child, type, rid, 1557 start, end, count, flags)); 1558 break; 1559 } 1560 /* 1561 * If we've already allocated the resource, then 1562 * return it now. But first we may need to activate 1563 * it, since we don't allocate the resource as active 1564 * above. Normally this would be done down in the 1565 * nexus, but since we short-circuit that path we have 1566 * to do its job here. Not sure if we should free the 1567 * resource if it fails to activate. 1568 */ 1569 rle = resource_list_find(rl, type, *rid); 1570 if (rle != NULL && rle->res != NULL) { 1571 device_printf(child, "Bus reserved %#lx bytes for rid %#x type %d at %#lx\n", rman_get_size(rle->res), *rid, type, rman_get_start(rle->res)); 1572 if ((flags & RF_ACTIVE) && 1573 bus_generic_activate_resource(dev, child, type, 1574 *rid, rle->res) != 0) 1575 return NULL; 1576 return (rle->res); 1577 } 1578 } 1579 return (resource_list_alloc(rl, dev, child, type, rid, 1580 start, end, count, flags)); 1581} 1582 1583void 1584pci_delete_resource(device_t dev, device_t child, int type, int rid) 1585{ 1586 struct pci_devinfo *dinfo; 1587 struct resource_list *rl; 1588 struct resource_list_entry *rle; 1589 1590 if (device_get_parent(child) != dev) 1591 return; 1592 1593 dinfo = device_get_ivars(child); 1594 rl = &dinfo->resources; 1595 rle = resource_list_find(rl, type, rid); 1596 if (rle) { 1597 if (rle->res) { 1598 if (rman_get_device(rle->res) != dev || 1599 rman_get_flags(rle->res) & RF_ACTIVE) { 1600 device_printf(dev, "delete_resource: " 1601 "Resource still owned by child, oops. " 1602 "(type=%d, rid=%d, addr=%lx)\n", 1603 rle->type, rle->rid, 1604 rman_get_start(rle->res)); 1605 return; 1606 } 1607 bus_release_resource(dev, type, rid, rle->res); 1608 } 1609 resource_list_delete(rl, type, rid); 1610 } 1611 /* 1612 * Why do we turn off the PCI configuration BAR when we delete a 1613 * resource? -- imp 1614 */ 1615 pci_write_config(child, rid, 0, 4); 1616 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1617} 1618 1619struct resource_list * 1620pci_get_resource_list (device_t dev, device_t child) 1621{ 1622 struct pci_devinfo *dinfo = device_get_ivars(child); 1623 1624 return (&dinfo->resources); 1625} 1626 1627uint32_t 1628pci_read_config_method(device_t dev, device_t child, int reg, int width) 1629{ 1630 struct pci_devinfo *dinfo = device_get_ivars(child); 1631 pcicfgregs *cfg = &dinfo->cfg; 1632 1633 return (PCIB_READ_CONFIG(device_get_parent(dev), 1634 cfg->bus, cfg->slot, cfg->func, reg, width)); 1635} 1636 1637void 1638pci_write_config_method(device_t dev, device_t child, int reg, 1639 uint32_t val, int width) 1640{ 1641 struct pci_devinfo *dinfo = device_get_ivars(child); 1642 pcicfgregs *cfg = &dinfo->cfg; 1643 1644 PCIB_WRITE_CONFIG(device_get_parent(dev), 1645 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1646} 1647 1648int 1649pci_child_location_str_method(device_t dev, device_t child, char *buf, 1650 size_t buflen) 1651{ 1652 struct pci_devinfo *dinfo; 1653 1654 dinfo = device_get_ivars(child); 1655 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1656 pci_get_function(child)); 1657 return (0); 1658} 1659 1660int 1661pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1662 size_t buflen) 1663{ 1664 struct pci_devinfo *dinfo; 1665 pcicfgregs *cfg; 1666 1667 dinfo = device_get_ivars(child); 1668 cfg = &dinfo->cfg; 1669 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1670 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1671 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1672 cfg->progif); 1673 return (0); 1674} 1675 1676int 1677pci_assign_interrupt_method(device_t dev, device_t child) 1678{ 1679 struct pci_devinfo *dinfo = device_get_ivars(child); 1680 pcicfgregs *cfg = &dinfo->cfg; 1681 1682 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1683 cfg->intpin)); 1684} 1685 1686static int 1687pci_modevent(module_t mod, int what, void *arg) 1688{ 1689 static dev_t pci_cdev; 1690 1691 switch (what) { 1692 case MOD_LOAD: 1693 STAILQ_INIT(&pci_devq); 1694 pci_generation = 0; 1695 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1696 "pci"); 1697 pci_load_vendor_data(); 1698 break; 1699 1700 case MOD_UNLOAD: 1701 destroy_dev(pci_cdev); 1702 break; 1703 } 1704 1705 return (0); 1706} 1707 1708static void 1709pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1710{ 1711 int i; 1712 1713 /* 1714 * Only do header type 0 devices. Type 1 devices are bridges, 1715 * which we know need special treatment. Type 2 devices are 1716 * cardbus bridges which also require special treatment. 1717 * Other types are unknown, and we err on the side of safety 1718 * by ignoring them. 1719 */ 1720 if (dinfo->cfg.hdrtype != 0) 1721 return; 1722 /* 1723 * Restore the device to full power mode. We must do this 1724 * before we restore the registers because moving from D3 to 1725 * D0 will cause the chip's BARs and some other registers to 1726 * be reset to some unknown power on reset values. Cut down 1727 * the noise on boot by doing nothing if we are already in 1728 * state D0. 1729 */ 1730 if (pci_do_powerstate && (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)) { 1731 printf("pci%d:%d:%d: Transition from D%d to D0\n", dinfo->cfg.bus, 1732 dinfo->cfg.slot, dinfo->cfg.func, 1733 pci_get_powerstate(dev)); 1734 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1735 } 1736 for (i = 0; i < dinfo->cfg.nummaps; i++) 1737 pci_write_config(dev, PCIR_MAPS + i * 4, dinfo->cfg.bar[i], 4); 1738 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1739 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1740 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1741 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1742 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1743 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1744 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1745 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1746} 1747 1748static void 1749pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1750{ 1751 int i; 1752 uint32_t cls; 1753 int ps; 1754 1755 /* 1756 * Only do header type 0 devices. Type 1 devices are bridges, which 1757 * we know need special treatment. Type 2 devices are cardbus bridges 1758 * which also require special treatment. Other types are unknown, and 1759 * we err on the side of safety by ignoring them. Powering down 1760 * bridges should not be undertaken lightly. 1761 */ 1762 if (dinfo->cfg.hdrtype != 0) 1763 return; 1764 for (i = 0; i < dinfo->cfg.nummaps; i++) 1765 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1766 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1767 1768 /* 1769 * Some drivers apparently write to these registers w/o 1770 * updating our cahced copy. No harm happens if we update the 1771 * copy, so do so here so we can restore them. The COMMAND 1772 * register is modified by the bus w/o updating the cache. This 1773 * should represent the normally writable portion of the 'defined' 1774 * part of type 0 headers. In theory we also need to save/restore 1775 * the PCI capability structures we know about, but apart from power 1776 * we don't know any that are writable. 1777 */ 1778 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1779 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1780 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1781 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1782 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1783 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1784 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1785 1786 /* 1787 * don't set the state for display devices and for memory devices 1788 * since bad things happen. we should (a) have drivers that can easily 1789 * detach and (b) use generic drivers for these devices so that some 1790 * device actually attaches. We need to make sure that when we 1791 * implement (a) we don't power the device down on a reattach. 1792 */ 1793 cls = pci_get_class(dev); 1794 if (pci_do_powerstate && setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY) { 1795 /* 1796 * PCI spec is clear that we can only go into D3 state from 1797 * D0 state. Transition from D[12] into D0 before going 1798 * to D3 state. 1799 */ 1800 ps = pci_get_powerstate(dev); 1801 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1802 printf("pci%d:%d:%d: Transition from D%d to D0\n", dinfo->cfg.bus, 1803 dinfo->cfg.slot, dinfo->cfg.func, ps); 1804 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1805 } 1806 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1807 printf("pci%d:%d:%d: Transition from D0 to D3\n", dinfo->cfg.bus, 1808 dinfo->cfg.slot, dinfo->cfg.func); 1809 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1810 } 1811 } 1812} 1813