pci.c revision 12651
1/************************************************************************** 2** 3** $Id: pci.c,v 1.34 1995/11/21 13:59:56 bde Exp $ 4** 5** General subroutines for the PCI bus. 6** pci_configure () 7** 8** FreeBSD 9** 10**------------------------------------------------------------------------- 11** 12** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 13** 14** Redistribution and use in source and binary forms, with or without 15** modification, are permitted provided that the following conditions 16** are met: 17** 1. Redistributions of source code must retain the above copyright 18** notice, this list of conditions and the following disclaimer. 19** 2. Redistributions in binary form must reproduce the above copyright 20** notice, this list of conditions and the following disclaimer in the 21** documentation and/or other materials provided with the distribution. 22** 3. The name of the author may not be used to endorse or promote products 23** derived from this software without specific prior written permission. 24** 25** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35** 36*************************************************************************** 37*/ 38 39#include <pci.h> 40#if NPCI > 0 41 42/*======================================================== 43** 44** #includes and declarations 45** 46**======================================================== 47*/ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/malloc.h> 52#include <sys/errno.h> 53#include <sys/kernel.h> 54#include <sys/sysctl.h> 55#include <sys/proc.h> /* declaration of wakeup(), used by vm.h */ 56#include <sys/devconf.h> 57 58#include <machine/cpu.h> /* bootverbose */ 59 60#include <vm/vm.h> 61#include <vm/vm_param.h> 62 63#include <machine/pmap.h> 64#include <sys/devconf.h> 65 66#include <i386/isa/isa_device.h> /* XXX inthand2_t */ 67 68#include <pci/pcivar.h> 69#include <pci/pcireg.h> 70#include <pci/pcibus.h> 71 72#define PCI_MAX_IRQ (16) 73 74 75/*======================================================== 76** 77** Structs and Functions 78** 79**======================================================== 80*/ 81 82struct pci_devconf { 83 struct kern_devconf pdc_kdc; 84 struct pci_info pdc_pi; 85}; 86 87struct pcicb { 88 struct pcicb *pcicb_next; 89 struct pcicb *pcicb_up; 90 struct pcicb *pcicb_down; 91 pcici_t pcicb_bridge; 92 93 u_long pcicb_seen; 94 u_char pcicb_bus; 95 u_char pcicb_subordinate; 96 u_char pcicb_flags; 97#define PCICB_ISAMEM 0x01 98 u_int pcicb_mfrom; 99 u_int pcicb_mupto; 100 u_int pcicb_mamount; 101 u_short pcicb_pfrom; 102 u_short pcicb_pupto; 103 u_short pcicb_pamount; 104 u_char pcicb_bfrom; 105 u_char pcicb_bupto; 106 107 u_long pcicb_iobase; 108 u_long pcicb_iolimit; 109 u_long pcicb_membase; 110 u_long pcicb_memlimit; 111 u_long pcicb_p_membase; 112 u_long pcicb_p_memlimit; 113}; 114 115static int pci_externalize (struct kern_devconf *, struct sysctl_req *); 116 117static int pci_internalize (struct kern_devconf *, struct sysctl_req *); 118 119static void 120not_supported (pcici_t tag, u_long type); 121 122static void 123pci_bus_config (void); 124 125static void 126pci_bridge_config (void); 127 128/*======================================================== 129** 130** Variables 131** 132**======================================================== 133*/ 134 135/* 136** log2 of safe burst len (in words) 137*/ 138 139unsigned pci_max_burst_len = 3; /* 2=16Byte, 3=32Byte, 4=64Byte, ... */ 140unsigned pci_mechanism = 0; 141unsigned pci_maxdevice = 0; 142struct pcibus* pcibus; 143 144/*-------------------------------------------------------- 145** 146** Local variables. 147** 148**-------------------------------------------------------- 149*/ 150 151static int pci_conf_count; 152static int pci_info_done; 153static struct pcicb pcibus0 = { 154 NULL, NULL, NULL, 155 { 0 }, 156 0, 0, 0, 0, 157 0, 0, 0, 0, 0, 0, 0, 0, /* real allocation */ 158 0, 0xFFFF, /* iobase/limit */ 159 0x4000000, 0xFFFFFFFFu, /* nonprefetch membase/limit */ 160 0x4000000, 0xFFFFFFFFu /* prefetch membase/limit */ 161}; 162static struct pcicb *pcicb; 163 164/*======================================================== 165** 166** pci_configure () 167** 168** Autoconfiguration of pci devices. 169** 170** May be called more than once. 171** Any device is attached only once. 172** 173** Has to take care of mirrored devices, which are 174** entailed by incomplete decoding of pci address lines. 175** 176**======================================================== 177*/ 178 179void pci_configure() 180{ 181 struct pcibus **pbp = (struct pcibus**) pcibus_set.ls_items; 182 183 /* 184 ** check pci bus present 185 */ 186 187 while (!pci_maxdevice && (pcibus = *pbp++)) { 188 (*pcibus->pb_setup)(); 189 } 190 191 if (!pci_maxdevice) return; 192 193 /* 194 ** hello world .. 195 */ 196 197 for (pcicb = &pcibus0; pcicb != NULL;) { 198 pci_bus_config (); 199 200 if (pcicb->pcicb_down) { 201 pcicb = pcicb->pcicb_down; 202 continue; 203 }; 204 205 while (pcicb && !pcicb->pcicb_next) 206 pcicb = pcicb->pcicb_up; 207 208 if (pcicb) 209 pcicb = pcicb->pcicb_next; 210 } 211 pci_conf_count++; 212} 213 214/*======================================================== 215** 216** Subroutines for configuration. 217** 218**======================================================== 219*/ 220 221static void 222pci_register_io (struct pcicb * cb, u_int base, u_int limit) 223{ 224#ifdef PCI_BRIDGE_DEBUG 225 if (bootverbose) 226 printf ("register_io: bus=%d base=%x limit=%x\n", 227 cb->pcicb_bus, base, limit); 228#endif 229 230 if (!cb->pcicb_pfrom || base < cb->pcicb_pfrom) 231 cb->pcicb_pfrom = base; 232 if (limit > cb->pcicb_pupto) 233 cb->pcicb_pupto = limit; 234 235 /* 236 ** XXX should set bridge io mapping here 237 ** but it can be mapped in 4k blocks only, 238 ** leading to conflicts with isa/eisa .. 239 */ 240} 241 242static void 243pci_register_memory (struct pcicb * cb, u_int base, u_int limit) 244{ 245#ifdef PCI_BRIDGE_DEBUG 246 if (bootverbose) 247 printf ("register_mem: bus=%d base=%x limit=%x\n", 248 cb->pcicb_bus, base, limit); 249#endif 250 251 if (!cb->pcicb_mfrom || base < cb->pcicb_mfrom) 252 cb->pcicb_mfrom = base; 253 if (limit > cb->pcicb_mupto) 254 cb->pcicb_mupto = limit; 255 /* 256 ** set the bridges mapping 257 ** 258 ** XXX should handle the 1Mb granularity. 259 */ 260 if (cb->pcicb_bridge.tag) { 261 pci_conf_write(cb->pcicb_bridge, 262 PCI_PCI_BRIDGE_MEM_REG, 263 (cb->pcicb_memlimit & 0xffff0000) | 264 (cb->pcicb_membase >> 16)); 265 if (bootverbose) 266 printf ("\t[pci%d uses memory from %x to %x]\n", 267 cb->pcicb_bus, 268 (unsigned) cb->pcicb_membase, 269 (unsigned) cb->pcicb_memlimit); 270 } 271} 272 273/* 274** XXX This function is neither complete nor tested. 275** It's only used if the bios hasn't done it's job 276** of mapping the pci devices in the physical memory. 277*/ 278 279static u_int 280pci_memalloc (struct pcicb * cb, u_int addr, u_int size) 281{ 282 u_int result = 0, limit=0, newbase=0; 283#ifdef PCI_BRIDGE_DEBUG 284 if (bootverbose) 285 printf ("memalloc: bus=%d addr=%x size=%x ..\n", 286 cb->pcicb_bus, addr, size); 287#endif 288 289 if (!cb) goto done; 290 291 if (!cb->pcicb_membase) { 292 printf ("memalloc: bus%d: membase not set.\n", 293 cb->pcicb_bus); 294 goto done; 295 } 296 297 /* 298 ** get upper allocation limit 299 */ 300 limit = cb->pcicb_memlimit; 301 if (cb->pcicb_mfrom && cb->pcicb_mfrom <= limit) 302 limit = cb->pcicb_mfrom-1; 303 304 /* 305 ** address fixed, and impossible to allocate ? 306 */ 307 if (addr && addr+size-1 > limit) 308 goto done; 309 310 /* 311 ** get possible address 312 */ 313 314 result = addr; 315 if (!result) result = ((limit + 1) / size - 1) * size; 316 317 /* 318 ** if not local available, request from parent. 319 */ 320 321 if (result < cb->pcicb_membase) { 322 newbase = pci_memalloc (cb->pcicb_up, result, size); 323 if (newbase) cb->pcicb_membase = result; 324 else result=0; 325 } 326done: 327 if (result) 328 pci_register_memory (cb, result, result+size-1); 329 330#ifdef PCI_BRIDGE_DEBUG 331 printf ("memalloc: bus=%d addr=%x size=%x --> %x (limit=%x).\n", 332 cb->pcicb_bus, addr, size, result, limit); 333#endif 334 335 return (result); 336} 337 338/*======================================================== 339** 340** pci_bus_config() 341** 342** Autoconfiguration of one pci bus. 343** 344**======================================================== 345*/ 346 347static void 348pci_bus_config (void) 349{ 350 u_char device; 351 u_char reg; 352 pcici_t tag, mtag; 353 pcidi_t type; 354 u_long data; 355 int unit; 356 int pciint; 357 int irq; 358 359 struct pci_device *dvp; 360 361 struct pci_devconf *pdcp; 362 363 /* 364 ** first initialize the bridge (bus controller chip) 365 */ 366 pci_bridge_config (); 367 368 printf ("Probing for devices on the PCI bus:\n"); 369#ifndef PCI_QUIET 370 if (bootverbose && !pci_info_done) { 371 pci_info_done=1; 372 printf ("\tconfiguration mode %d allows %d devices.\n", 373 pci_mechanism, pci_maxdevice); 374 }; 375#endif 376 for (device=0; device<pci_maxdevice; device ++) { 377 char *name = NULL; 378 struct pci_device **dvpp; 379 380 if ((pcicb->pcicb_seen >> device) & 1) 381 continue; 382 383 tag = pcibus->pb_tag (pcicb->pcicb_bus, device, 0); 384 type = pcibus->pb_read (tag, PCI_ID_REG); 385 386 if ((!type) || (type==0xfffffffful)) continue; 387 388 /* 389 ** lookup device in ioconfiguration: 390 */ 391 392 dvpp = (struct pci_device **)pcidevice_set.ls_items; 393 394 while (dvp = *dvpp++) { 395 if (dvp->pd_probe) { 396 if (name=(*dvp->pd_probe)(tag, type)) 397 break; 398 } 399 }; 400 /* 401 ** check for mirrored devices. 402 */ 403 if (device & 0x10) { 404 mtag=pcibus->pb_tag (pcicb->pcicb_bus, 405 (u_char)(device & ~0x10), 0); 406 } else if (device & 0x08) { 407 mtag=pcibus->pb_tag (pcicb->pcicb_bus, 408 (u_char)(device & ~0x08), 0); 409 } else goto real_device; 410 411 if (type!=pcibus->pb_read (mtag, PCI_ID_REG)) 412 goto real_device; 413 414 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) 415 if (pcibus->pb_read(tag,reg)!=pcibus->pb_read(mtag,reg)) 416 goto real_device; 417 418#ifndef PCI_QUIET 419 if (dvp==NULL) continue; 420 if (bootverbose) 421 printf ("%s? <%s> mirrored on pci%d:%d\n", 422 dvp->pd_name, name, pcicb->pcicb_bus, device); 423#endif 424 continue; 425 426 real_device: 427 428 if (dvp==NULL) { 429#ifndef PCI_QUIET 430 if (pci_conf_count) 431 continue; 432 printf("%s%d:%d: ", pcibus->pb_name, 433 pcicb->pcicb_bus, device); 434 not_supported (tag, type); 435#endif 436 continue; 437 }; 438 439 pcicb->pcicb_seen |= (1ul << device); 440 441 /* 442 ** Get and increment the unit. 443 */ 444 445 unit = (*dvp->pd_count)++; 446 447 /* 448 ** ignore device ? 449 */ 450 451 if (!*name) continue; 452 453 /* 454 ** Announce this device 455 */ 456 457 printf ("%s%d <%s> rev %d", dvp->pd_name, unit, name, 458 (unsigned) pci_conf_read (tag, PCI_CLASS_REG) & 0xff); 459 460 /* 461 ** Get the int pin number (pci interrupt number a-d) 462 ** from the pci configuration space. 463 */ 464 465 data = pcibus->pb_read (tag, PCI_INTERRUPT_REG); 466 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 467 468 if (pciint) { 469 470 printf (" int %c irq ", 0x60+pciint); 471 472 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 473 474 /* 475 ** If it's zero, the isa irq number is unknown, 476 ** and we cannot bind the pci interrupt. 477 */ 478 479 if (irq) 480 printf ("%d", irq); 481 else 482 printf ("??"); 483 }; 484 485 printf (" on pci%d:%d\n", pcicb->pcicb_bus, device); 486 487 /* 488 ** Read the current mapping, 489 ** and update the pcicb fields. 490 */ 491 492 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) { 493 u_int map, addr, size; 494 495 data = pci_conf_read(tag, PCI_CLASS_REG); 496 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 497 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 498 continue; 499 }; 500 501 map = pcibus->pb_read (tag, reg); 502 if (!(map & PCI_MAP_MEMORY_ADDRESS_MASK)) 503 continue; 504 505 pcibus->pb_write (tag, reg, 0xffffffff); 506 data = pcibus->pb_read (tag, reg); 507 pcibus->pb_write (tag, reg, map); 508 509 switch (data & 7) { 510 511 default: 512 continue; 513 case 1: 514 case 5: 515 size = -(data & PCI_MAP_IO_ADDRESS_MASK); 516 addr = map & PCI_MAP_IO_ADDRESS_MASK; 517 518 pci_register_io (pcicb, addr, addr+size-1); 519 pcicb->pcicb_pamount += size; 520 break; 521 522 case 0: 523 case 2: 524 case 4: 525 size = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 526 addr = map & PCI_MAP_MEMORY_ADDRESS_MASK; 527 if (addr >= 0x100000) { 528 pci_register_memory 529 (pcicb, addr, addr+size-1); 530 pcicb->pcicb_mamount += size; 531 } else { 532 pcicb->pcicb_flags |= PCICB_ISAMEM; 533 }; 534 break; 535 }; 536 if (bootverbose) 537 printf ("\tmapreg[%02x] type=%d addr=%08x size=%04x.\n", 538 reg, map&7, addr, size); 539 }; 540 541 /* 542 ** Allocate a devconf structure 543 ** We should, and eventually will, set the 544 ** parent pointer to a pci bus devconf structure, 545 ** and arrange to set the state field dynamically. 546 */ 547 548 pdcp = (struct pci_devconf *) 549 malloc (sizeof (struct pci_devconf),M_DEVBUF,M_WAITOK); 550 bzero(pdcp, sizeof(struct pci_devconf)); 551 552 pdcp -> pdc_pi.pi_bus = pcicb->pcicb_bus; 553 pdcp -> pdc_pi.pi_device = device; 554 555 pdcp -> pdc_kdc.kdc_name = dvp->pd_name; 556 pdcp -> pdc_kdc.kdc_unit = unit; 557 558 pdcp -> pdc_kdc.kdc_md.mddc_devtype = MDDT_PCI; 559 560 pdcp -> pdc_kdc.kdc_externalize = pci_externalize; 561 pdcp -> pdc_kdc.kdc_internalize = pci_internalize; 562 563 pdcp -> pdc_kdc.kdc_datalen = PCI_EXTERNAL_LEN; 564 pdcp -> pdc_kdc.kdc_parentdata = &pdcp->pdc_pi; 565 pdcp -> pdc_kdc.kdc_state = DC_UNKNOWN; 566 pdcp -> pdc_kdc.kdc_description = name; 567 pdcp -> pdc_kdc.kdc_shutdown = dvp->pd_shutdown; 568 569 /* 570 ** And register this device 571 */ 572 573 dev_attach (&pdcp->pdc_kdc); 574 575 /* 576 ** attach device 577 ** may produce additional log messages, 578 ** i.e. when installing subdevices. 579 */ 580 581 (*dvp->pd_attach) (tag, unit); 582 583 /* 584 ** Special processing of certain classes 585 */ 586 587 data = pci_conf_read(tag, PCI_CLASS_REG); 588 589 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 590 struct pcicb *this, **link; 591 unsigned char primary, secondary, subordinate; 592 u_int command; 593 594 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 595 596 /* 597 ** get current configuration of the bridge. 598 */ 599 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 600 primary = PCI_PRIMARY_BUS_EXTRACT (data); 601 secondary = PCI_SECONDARY_BUS_EXTRACT(data); 602 subordinate = PCI_SUBORDINATE_BUS_EXTRACT(data); 603#ifndef PCI_QUIET 604 if (bootverbose) { 605 printf ("\tbridge from pci%d to pci%d through %d.\n", 606 primary, secondary, subordinate); 607 printf ("\tmapping regs: io:%08lx mem:%08lx pmem:%08lx", 608 pci_conf_read (tag, PCI_PCI_BRIDGE_IO_REG), 609 pci_conf_read (tag, PCI_PCI_BRIDGE_MEM_REG), 610 pci_conf_read (tag, PCI_PCI_BRIDGE_PMEM_REG)); 611 } 612#endif 613 /* 614 ** check for uninitialized bridge. 615 */ 616 if (secondary == 0 || secondary < primary || 617 pcicb->pcicb_bus != primary) 618 { 619 printf ("\tINCORRECTLY or NEVER CONFIGURED.\n"); 620 /* 621 ** disable this bridge 622 */ 623 pcibus->pb_write (tag, PCI_COMMAND_STATUS_REG, 624 0xffff0000); 625 secondary = 0; 626 subordinate = 0; 627 }; 628 629 /* 630 ** allocate bus descriptor for bus behind the bridge 631 */ 632 link = &pcicb->pcicb_down; 633 while (*link) link = &(*link)->pcicb_next; 634 635 this = malloc (sizeof (*this), M_DEVBUF, M_WAITOK); 636 637 /* 638 ** Initialize this descriptor so far. 639 ** (the initialization is completed just before 640 ** scanning the bus behind the bridge. 641 */ 642 bzero (this, sizeof(*this)); 643 this->pcicb_up = pcicb; 644 this->pcicb_bridge = tag; 645 this->pcicb_bus = secondary; 646 this->pcicb_subordinate = subordinate; 647 648 command = pci_conf_read(tag,PCI_COMMAND_STATUS_REG); 649 650 if (command & PCI_COMMAND_IO_ENABLE){ 651 /* 652 ** Bridge was configured by the bios. 653 ** Read out the mapped io region. 654 */ 655 u_int reg, data, mask; 656 657 reg = pci_conf_read (tag, 658 PCI_PCI_BRIDGE_IO_REG); 659 pci_conf_write(tag, 660 PCI_PCI_BRIDGE_IO_REG, 0xFFFF); 661 data = pci_conf_read (tag, 662 PCI_PCI_BRIDGE_IO_REG); 663 pci_conf_write(tag, 664 PCI_PCI_BRIDGE_IO_REG, reg & 0xffff); 665 666 mask = (0xFF00 ^ (data & 0xFF00)) | 0xFF; 667 668 this->pcicb_iobase = 669 PCI_PPB_IOBASE_EXTRACT (reg); 670 this->pcicb_iolimit = 671 PCI_PPB_IOLIMIT_EXTRACT(reg) | mask; 672 673 /* 674 ** Note the used io space. 675 */ 676 pci_register_io (pcicb, this->pcicb_iobase, 677 this->pcicb_iolimit); 678 679 }; 680 681 if (command & PCI_COMMAND_MEM_ENABLE) { 682 /* 683 ** Bridge was configured by the bios. 684 ** Read out the mapped memory regions. 685 */ 686 u_int reg, data, mask; 687 688 /* 689 ** non prefetchable memory 690 */ 691 reg = pci_conf_read (tag, 692 PCI_PCI_BRIDGE_MEM_REG); 693 pci_conf_write(tag, 694 PCI_PCI_BRIDGE_MEM_REG, 0xFFFFFFFF); 695 data = pci_conf_read (tag, 696 PCI_PCI_BRIDGE_MEM_REG); 697 pci_conf_write(tag, 698 PCI_PCI_BRIDGE_MEM_REG, reg); 699 700 mask = 0xFFFFFFFF ^ (data & 0xFFFF0000); 701 this->pcicb_membase = 702 PCI_PPB_MEMBASE_EXTRACT (reg); 703 this->pcicb_memlimit = 704 PCI_PPB_MEMLIMIT_EXTRACT(reg) | mask; 705 706 /* 707 ** Register used memory space. 708 */ 709 pci_register_memory (pcicb, 710 this->pcicb_membase, 711 this->pcicb_memlimit); 712 713 /* 714 ** prefetchable memory 715 */ 716 reg = pci_conf_read (tag, 717 PCI_PCI_BRIDGE_PMEM_REG); 718 pci_conf_write(tag, 719 PCI_PCI_BRIDGE_PMEM_REG, 0xFFFFFFFF); 720 data = pci_conf_read (tag, 721 PCI_PCI_BRIDGE_PMEM_REG); 722 pci_conf_write(tag, 723 PCI_PCI_BRIDGE_PMEM_REG, reg); 724 725 mask = 0xFFFFFFFF ^ (data & 0xFFFF0000); 726 this->pcicb_p_membase= 727 PCI_PPB_MEMBASE_EXTRACT (reg); 728 this->pcicb_p_memlimit= 729 PCI_PPB_MEMLIMIT_EXTRACT(reg) | mask; 730 731 /* 732 ** Register used memory space. 733 */ 734 pci_register_memory (pcicb, 735 this->pcicb_p_membase, 736 this->pcicb_p_memlimit); 737 } 738 739 /* 740 ** Link it in chain. 741 */ 742 *link=this; 743 744 /* 745 ** Update mapping info of parent bus. 746 */ 747 if (!pcicb->pcicb_bfrom||secondary< pcicb->pcicb_bfrom) 748 pcicb->pcicb_bfrom = secondary; 749 if (subordinate > pcicb->pcicb_bupto) 750 pcicb->pcicb_bupto = subordinate; 751 752 break; 753 } 754 } 755 756#ifndef PCI_QUIET 757 if (bootverbose) { 758 if (pcicb->pcicb_mamount) 759 printf ("%s%d: uses %d bytes of memory from %x upto %x.\n", 760 pcibus->pb_name, pcicb->pcicb_bus, 761 pcicb->pcicb_mamount, 762 pcicb->pcicb_mfrom, pcicb->pcicb_mupto); 763 if (pcicb->pcicb_pamount) 764 printf ("%s%d: uses %d bytes of I/O space from %x upto %x.\n", 765 pcibus->pb_name, pcicb->pcicb_bus, 766 pcicb->pcicb_pamount, 767 pcicb->pcicb_pfrom, pcicb->pcicb_pupto); 768 if (pcicb->pcicb_bfrom) 769 printf ("%s%d: subordinate busses from %x upto %x.\n", 770 pcibus->pb_name, pcicb->pcicb_bus, 771 pcicb->pcicb_bfrom, pcicb->pcicb_bupto); 772 } 773#endif 774} 775 776/*======================================================== 777** 778** pci_bridge_config() 779** 780** Configuration of a pci bridge. 781** 782**======================================================== 783*/ 784 785static void 786pci_bridge_config (void) 787{ 788 pcici_t tag; 789 struct pcicb* parent; 790 791 tag = pcicb->pcicb_bridge; 792 if (!tag.tag) return; 793 794 if (!pcicb->pcicb_bus) { 795 u_int data; 796 /* 797 ** Get the lowest available bus number. 798 */ 799 pcicb->pcicb_bus = ++pcibus0.pcicb_subordinate; 800 801 /* 802 ** and configure the bridge 803 */ 804 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 805 data = PCI_PRIMARY_BUS_INSERT(data, pcicb->pcicb_up->pcicb_bus); 806 data = PCI_SECONDARY_BUS_INSERT(data, pcicb->pcicb_bus); 807 data = PCI_SUBORDINATE_BUS_INSERT(data, pcicb->pcicb_bus); 808 pci_conf_write (tag, PCI_PCI_BRIDGE_BUS_REG, data); 809 810 /* 811 ** Propagate the new upper bus number limit. 812 */ 813 for (parent = pcicb->pcicb_up; parent != NULL; 814 parent = parent->pcicb_up) 815 { 816 if (parent->pcicb_subordinate >= pcicb->pcicb_bus) 817 continue; 818 parent->pcicb_subordinate = pcicb->pcicb_bus; 819 if (!parent->pcicb_bridge.tag) 820 continue; 821 data = pci_conf_read 822 (parent->pcicb_bridge, PCI_PCI_BRIDGE_BUS_REG); 823 data = PCI_SUBORDINATE_BUS_INSERT 824 (data, pcicb->pcicb_bus); 825 pci_conf_write (parent->pcicb_bridge, 826 PCI_PCI_BRIDGE_BUS_REG, data); 827 } 828 } 829 830 if (!pcicb->pcicb_membase) { 831 u_int size = 0x100000; 832 pcicb->pcicb_membase = pci_memalloc (pcicb->pcicb_up, 0, size); 833 if (pcicb->pcicb_membase) 834 pcicb->pcicb_memlimit = pcicb->pcicb_membase+size-1; 835 } 836} 837 838/*----------------------------------------------------------------- 839** 840** The following functions are provided for the device driver 841** to read/write the configuration space. 842** 843** pci_conf_read(): 844** Read a long word from the pci configuration space. 845** Requires a tag (from pcitag) and the register 846** number (should be a long word alligned one). 847** 848** pci_conf_write(): 849** Writes a long word to the pci configuration space. 850** Requires a tag (from pcitag), the register number 851** (should be a long word alligned one), and a value. 852** 853**----------------------------------------------------------------- 854*/ 855 856u_long 857pci_conf_read (pcici_t tag, u_long reg) 858{ 859 return (pcibus->pb_read (tag, reg)); 860} 861 862void 863pci_conf_write (pcici_t tag, u_long reg, u_long data) 864{ 865 pcibus->pb_write (tag, reg, data); 866} 867 868/*----------------------------------------------------------------------- 869** 870** Map device into port space. 871** 872** Actually the device should have been mapped by the bios. 873** This function only reads and verifies the value. 874** 875** PCI-Specification: 6.2.5.1: address maps 876** 877**----------------------------------------------------------------------- 878*/ 879 880int pci_map_port (pcici_t tag, u_long reg, u_short* pa) 881{ 882 unsigned data, ioaddr, iosize; 883 struct pcicb *link = pcicb; 884 885 /* 886 ** sanity check 887 */ 888 889 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 890 printf ("pci_map_port failed: bad register=0x%x\n", 891 (unsigned)reg); 892 return (0); 893 }; 894 895 /*if (pcicb->pcicb_flags & PCICB_NOIOSET) { 896 printf ("pci_map_port failed: pci%d has not been configured for I/O access\n", 897 pcicb->pcicb_bus); 898 return (0); 899 }*/ 900 901 /* 902 ** get size and type of port 903 ** 904 ** type is in the lowest two bits. 905 ** If device requires 2^n bytes, the next 906 ** n-2 bits are hardwired as 0. 907 */ 908 909 ioaddr = pcibus->pb_read (tag, reg) & PCI_MAP_IO_ADDRESS_MASK; 910 if (!ioaddr || ioaddr > 0xfffful) { 911 printf ("pci_map_port failed: not configured by bios.\n"); 912 return (0); 913 }; 914 915 pcibus->pb_write (tag, reg, 0xfffffffful); 916 data = pcibus->pb_read (tag, reg); 917 pcibus->pb_write (tag, reg, ioaddr); 918 919 if ((data & 0x03) != PCI_MAP_IO) { 920 printf ("pci_map_port failed: bad port type=0x%x\n", 921 (unsigned) data); 922 return (0); 923 }; 924 iosize = -(data & PCI_MAP_IO_ADDRESS_MASK); 925 if (ioaddr < pcicb->pcicb_iobase 926 || ioaddr + iosize > pcicb->pcicb_iolimit) { 927 printf ("pci_map_port failed: device's iorange 0x%x-0x%x " 928 "is incompatible with its bridge's range 0x%x-0x%x\n", 929 (unsigned) ioaddr, (unsigned) ioaddr + iosize - 1, 930 (unsigned) pcicb->pcicb_iobase, 931 (unsigned) pcicb->pcicb_iolimit); 932 return (0); 933 } 934 935#ifndef PCI_QUIET 936 if (bootverbose) 937 printf ("\treg%d: ioaddr=0x%x size=0x%x\n", 938 (unsigned) reg, (unsigned) ioaddr, (unsigned) iosize); 939#endif 940 /* 941 ** set the configuration register of and 942 ** return the address to the driver. 943 ** Make sure to enable each upstream bridge 944 ** so I/O and DMA can go all the way. 945 */ 946 947 for (;;) { 948 data = pcibus->pb_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 949 data |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 950 (void) pcibus->pb_write(tag, PCI_COMMAND_STATUS_REG, data); 951 if ((link = link->pcicb_up) == NULL) 952 break; 953 tag = link->pcicb_bridge; 954 } 955 956 *pa = ioaddr; 957 958 return (1); 959} 960 961/*----------------------------------------------------------------------- 962** 963** Map device into virtual and physical space 964** 965** Actually the device should have been mapped by the bios. 966** This function only reads and verifies the value. 967** 968** PCI-Specification: 6.2.5.1: address maps 969** 970**----------------------------------------------------------------------- 971*/ 972 973int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa) 974{ 975 struct pcicb *link = pcicb; 976 unsigned data ,paddr; 977 vm_size_t psize, poffs; 978 vm_offset_t vaddr; 979 980 /* 981 ** sanity check 982 */ 983 984 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 985 printf ("pci_map_mem failed: bad register=0x%x\n", 986 (unsigned)reg); 987 return (0); 988 }; 989 990 /* 991 ** save old mapping, get size and type of memory 992 ** 993 ** type is in the lowest four bits. 994 ** If device requires 2^n bytes, the next 995 ** n-4 bits are read as 0. 996 */ 997 998 paddr = pcibus->pb_read (tag, reg) & PCI_MAP_MEMORY_ADDRESS_MASK; 999 pcibus->pb_write (tag, reg, 0xfffffffful); 1000 data = pcibus->pb_read (tag, reg); 1001 pcibus->pb_write (tag, reg, paddr); 1002 1003 /* 1004 ** check the type 1005 */ 1006 1007 if ((data & PCI_MAP_MEMORY_TYPE_MASK) != PCI_MAP_MEMORY_TYPE_32BIT) { 1008 printf ("pci_map_mem failed: bad memory type=0x%x\n", 1009 (unsigned) data); 1010 return (0); 1011 }; 1012 1013 /* 1014 ** get the size. 1015 */ 1016 1017 psize = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 1018 1019 if (!paddr || paddr == PCI_MAP_MEMORY_ADDRESS_MASK) { 1020 paddr = pci_memalloc (pcicb, 0, psize); 1021 if (!paddr) { 1022 printf ("pci_map_mem: not configured by bios.\n"); 1023 return (0); 1024 }; 1025 pci_register_memory (pcicb, paddr, paddr+psize-1); 1026 }; 1027 1028 if (paddr < pcicb->pcicb_membase || 1029 paddr + psize - 1 > pcicb->pcicb_memlimit) { 1030 printf ("pci_map_mem failed: device's memrange 0x%x-0x%x is " 1031 "incompatible with its bridge's memrange 0x%x-0x%x\n", 1032 (unsigned) paddr, 1033 (unsigned) (paddr + psize - 1), 1034 (unsigned) pcicb->pcicb_membase, 1035 (unsigned) pcicb->pcicb_memlimit); 1036/* return (0);*/ 1037/* ACHTUNG: Ist der Code richtig, wenn eine PCI-PCI-Bridge fuer 1038 * die PCI-Slots verwendet wird, aber die Onboard-Devices direkt 1039 * an der CPU-PCI-Bridge haengen (Siehe Compaq Prolinea Problem) ??? 1040 */ 1041 } 1042 pcibus->pb_write (tag, reg, paddr); 1043 1044 /* 1045 ** Truncate paddr to page boundary. 1046 ** (Or does pmap_mapdev the job?) 1047 */ 1048 1049 poffs = paddr - trunc_page (paddr); 1050 vaddr = (vm_offset_t) pmap_mapdev (paddr-poffs, psize+poffs); 1051 1052 if (!vaddr) return (0); 1053 1054 vaddr += poffs; 1055 1056#ifndef PCI_QUIET 1057 /* 1058 ** display values. 1059 */ 1060 1061 if (bootverbose) 1062 printf ("\treg%d: virtual=0x%lx physical=0x%lx size=0x%lx\n", 1063 (unsigned) reg, (u_long)vaddr, (u_long)paddr, (u_long)psize); 1064#endif 1065 /* 1066 ** set the configuration register and 1067 ** return the address to the driver 1068 ** Make sure to enable each upstream bridge 1069 ** so memory and DMA can go all the way. 1070 */ 1071 1072 for (;;) { 1073 data = pcibus->pb_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 1074 data |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1075 (void) pcibus->pb_write(tag, PCI_COMMAND_STATUS_REG, data); 1076 if ((link = link->pcicb_up) == NULL) 1077 break; 1078 tag = link->pcicb_bridge; 1079 } 1080 1081 *va = vaddr; 1082 *pa = paddr; 1083 1084 return (1); 1085} 1086 1087/*------------------------------------------------------------ 1088** 1089** Interface functions for the devconf module. 1090** 1091**------------------------------------------------------------ 1092*/ 1093 1094static int 1095pci_externalize (struct kern_devconf *kdcp, struct sysctl_req *req) 1096{ 1097 struct pci_externalize_buffer buffer; 1098 struct pci_info * pip = kdcp->kdc_parentdata; 1099 pcici_t tag; 1100 int i; 1101 1102 tag = pcibus->pb_tag (pip->pi_bus, pip->pi_device, 0); 1103 1104 buffer.peb_pci_info = *pip; 1105 1106 for (i=0; i<PCI_EXT_CONF_LEN; i++) { 1107 buffer.peb_config[i] = pcibus->pb_read (tag, i*4); 1108 }; 1109 1110 return SYSCTL_OUT(req, &buffer, sizeof buffer); 1111} 1112 1113 1114static int 1115pci_internalize (struct kern_devconf *kdcp, struct sysctl_req *re) 1116{ 1117 return EOPNOTSUPP; 1118} 1119 1120/*----------------------------------------------------------------------- 1121** 1122** Pci meta interrupt handler 1123** 1124** This handler assumes level triggered interrupts. 1125** It's possible to build a kernel which handles shared 1126** edge triggered interrupts by the options "PCI_EDGE_INT". 1127** But there is a performance penalty. 1128** 1129** (Of course you can delete the #ifdef PCI_EDGE_INT bracketed 1130** code at all :-) :-) :-) 1131** 1132**----------------------------------------------------------------------- 1133*/ 1134 1135struct pci_int_desc* 1136 pci_int_desc [PCI_MAX_IRQ]; 1137 1138#ifndef NO_SHARED_IRQ 1139 1140static inline unsigned 1141splq (unsigned mask) 1142{ 1143 unsigned temp=cpl; 1144 cpl |= mask; 1145 return temp; 1146} 1147 1148static void 1149pci_int (int irq) 1150{ 1151 struct pci_int_desc * p; 1152 int c, s; 1153#ifdef PCI_EDGE_INT 1154 int i, n; 1155#endif 1156 if (irq<0 || irq >= PCI_MAX_IRQ) { 1157 printf ("pci_int: irq %d out of range, ignored\n", irq); 1158 return; 1159 }; 1160 1161#ifdef PCI_EDGE_INT 1162 for (i=0; i<1000; i++) { 1163 n = 0; 1164#endif 1165 for (p = pci_int_desc[irq]; p!=NULL; p=p->pcid_next) { 1166 s = splq (*p->pcid_maskptr); 1167 c= (*p->pcid_handler) (p->pcid_argument); 1168 p-> pcid_tally += c; 1169 splx (s); 1170#ifdef PCI_EDGE_INT 1171 n += c; 1172#endif 1173#if 0 1174 if (c && p->pcid_tally<20) 1175 printf ("PCI_INT: irq=%d h=%p cpl o=%x n=%x val=%d\n", 1176 irq, p->pcid_handler, s, cpl, c); 1177#endif 1178 }; 1179#ifdef PCI_EDGE_INT 1180 if (!n) return; 1181 }; 1182 printf ("pci_int(%d): permanent interrupt request.\n", irq); 1183#endif 1184} 1185#endif 1186 1187/*----------------------------------------------------------------------- 1188** 1189** Auxiliary function for interrupt (un)mapping. 1190** 1191**----------------------------------------------------------------------- 1192*/ 1193 1194static u_int 1195getirq (pcici_t tag) 1196{ 1197 u_int irq; 1198 1199 irq = PCI_INTERRUPT_LINE_EXTRACT( 1200 pcibus->pb_read (tag, PCI_INTERRUPT_REG)); 1201 1202 if (irq <= 0) { 1203 printf ("\tint line register not set by bios\n"); 1204 return (0); 1205 } 1206 1207 if (irq >= pcibus->pb_maxirq || irq >= PCI_MAX_IRQ) { 1208 printf ("\tirq %d invalid.\n", irq); 1209 return (0); 1210 } 1211 1212 return (irq); 1213} 1214 1215static struct pci_int_desc ** 1216getintdescbytag (u_int irq, pcici_t tag) 1217{ 1218 struct pci_int_desc *p, **pp; 1219 1220 pp=&pci_int_desc[irq]; 1221 while (((p=*pp)) && !sametag(p->pcid_tag,tag)) 1222 pp=&p->pcid_next; 1223 1224 if (!p) return (NULL); 1225 1226 return (pp); 1227} 1228 1229static struct pci_int_desc * 1230getintdescbymptr (u_int irq, unsigned * mptr) 1231{ 1232 struct pci_int_desc *p; 1233 1234 for (p=pci_int_desc[irq];p;p=p->pcid_next) 1235 if (p->pcid_maskptr == mptr) break; 1236 return (p); 1237} 1238 1239/*----------------------------------------------------------------------- 1240** 1241** Map pci interrupt. 1242** 1243**----------------------------------------------------------------------- 1244*/ 1245 1246static unsigned pci_mask0 = 0; 1247 1248int pci_map_int (pcici_t tag, int(*func)(), void* arg, unsigned* maskptr) 1249{ 1250 u_int irq; 1251 int result, oldspl; 1252 unsigned mask; 1253 struct pci_int_desc *tail, *mdp=NULL, *new=NULL; 1254 1255 /* 1256 ** Get irq line from configuration space, 1257 ** and check for consistency. 1258 */ 1259 1260 irq = getirq (tag); 1261 if (irq >= PCI_MAX_IRQ) { 1262 printf ("\tillegal irq %d.\n", irq); 1263 return (0); 1264 }; 1265 mask= 1ul << irq; 1266 1267 /* 1268 ** disable this interrupt. 1269 */ 1270 1271 oldspl = splq (mask); 1272 1273 /* 1274 ** If handler for this tag already installed, 1275 ** remove it first. 1276 */ 1277 1278 if (getintdescbytag (irq, tag) != NULL) 1279 pci_unmap_int (tag); 1280 1281 /* 1282 ** If this irq not yet included in the mask, include it. 1283 */ 1284 1285 mdp = getintdescbymptr (irq, maskptr); 1286 if (!mdp) { 1287 result = pcibus->pb_imaskinc (irq, maskptr); 1288 if (result) 1289 goto conflict; 1290 }; 1291 1292 /* 1293 ** Allocate descriptor and initialize it. 1294 */ 1295 1296 tail = pci_int_desc[irq]; 1297 1298 new = malloc (sizeof (*new), M_DEVBUF, M_WAITOK); 1299 bzero (new, sizeof (*new)); 1300 1301 new->pcid_next = tail; 1302 new->pcid_tag = tag; 1303 new->pcid_handler = func; 1304 new->pcid_argument = arg; 1305 new->pcid_maskptr = maskptr; 1306 new->pcid_tally = 0; 1307 new->pcid_mask = mask; 1308 1309 /* 1310 ** If first handler: install it. 1311 ** If second handler: install shared-int-handler. 1312 */ 1313 1314 if (!tail) { 1315 /* 1316 ** first handler for this irq. 1317 */ 1318 1319 result = pcibus->pb_iattach 1320 (irq, (void(*)()) func, (int) arg, maskptr); 1321 if (result) goto conflict; 1322 1323#ifdef NO_SHARED_IRQ 1324 } else goto conflict; 1325#else 1326 } else if (!tail->pcid_next) { 1327 /* 1328 ** Second handler for this irq. 1329 */ 1330 1331 if (bootverbose) 1332 printf ("\tusing shared irq %d.\n", irq); 1333 1334 /* 1335 ** replace old handler by shared-int-handler. 1336 */ 1337 1338 result = pcibus->pb_idetach (irq,(void(*)())tail->pcid_handler); 1339 if (result) 1340 printf ("\tCANNOT DETACH INT HANDLER.\n"); 1341 1342 result = pcibus->pb_iattach (irq, pci_int, irq, &pci_mask0); 1343 if (result) { 1344 printf ("\tCANNOT ATTACH SHARED INT HANDLER.\n"); 1345 goto fail; 1346 }; 1347 } 1348#endif 1349 /* 1350 ** Link new descriptor, reenable ints and done. 1351 */ 1352 1353 pci_int_desc[irq] = new; 1354 splx (oldspl); 1355 return (1); 1356 1357 /* 1358 ** Handle some problems. 1359 */ 1360 1361conflict: 1362 printf ("\tirq %d already in use.\n", irq); 1363fail: 1364 /* 1365 ** If descriptor allocated, free it. 1366 ** If included in mask, remove it. 1367 */ 1368 1369 if (new) free(new, M_DEVBUF); 1370 if (!mdp) (void) pcibus->pb_imaskexc (irq, maskptr); 1371 splx (oldspl); 1372 return (0); 1373} 1374 1375/*----------------------------------------------------------------------- 1376** 1377** Unmap pci interrupt. 1378** 1379**----------------------------------------------------------------------- 1380*/ 1381 1382int pci_unmap_int (pcici_t tag) 1383{ 1384 int result, oldspl; 1385 struct pci_int_desc *this, **hook, *tail; 1386 unsigned irq; 1387 1388 /* 1389 ** Get irq line from configuration space, 1390 ** and check for consistency. 1391 */ 1392 1393 irq = getirq (tag); 1394 if (irq >= PCI_MAX_IRQ) { 1395 printf ("\tillegal irq %d.\n", irq); 1396 return (0); 1397 }; 1398 1399 /* 1400 ** Search and unlink interrupt descriptor. 1401 */ 1402 1403 hook = getintdescbytag (irq, tag); 1404 if (hook == NULL) { 1405 printf ("\tno irq %d handler for pci %x\n", 1406 irq, tag.tag); 1407 return (0); 1408 }; 1409 1410 this = *hook; 1411 *hook= this->pcid_next; 1412 1413 /* 1414 ** Message 1415 */ 1416 1417 printf ("\tirq %d handler %p(%p) unmapped for pci %x after %d ints.\n", 1418 irq, this->pcid_handler, this->pcid_argument, 1419 this->pcid_tag.tag, this->pcid_tally); 1420 1421 /* 1422 ** If this irq no longer included in the mask, remove it. 1423 */ 1424 1425 if (!getintdescbymptr (irq, this->pcid_maskptr)) 1426 (void) pcibus->pb_imaskexc (irq, this->pcid_maskptr); 1427 1428 tail = pci_int_desc[irq]; 1429 1430 if (tail == NULL) { 1431 1432 /* 1433 ** Remove the old handler. 1434 */ 1435 1436 result = pcibus->pb_idetach (irq,(void(*)())this->pcid_handler); 1437 if (result) 1438 printf ("\tirq %d: cannot remove handler.\n", irq); 1439 1440 } else if (tail->pcid_next == NULL) { 1441 1442 /* 1443 ** Remove the shared int handler. 1444 ** Install the last remaining handler. 1445 */ 1446 1447 oldspl = splq (1ul << irq); 1448 1449 result = pcibus->pb_idetach (irq, pci_int); 1450 if (result) 1451 printf ("\tirq %d: cannot remove handler.\n", irq); 1452 1453 result = pcibus->pb_iattach (irq, 1454 (void(*)()) tail->pcid_handler, 1455 (int) tail->pcid_argument, 1456 tail->pcid_maskptr); 1457 1458 if (result) 1459 printf ("\tirq %d: cannot install handler.\n", irq); 1460 1461 splx (oldspl); 1462 }; 1463 1464 free (this, M_DEVBUF); 1465 return (1); 1466} 1467 1468/*----------------------------------------------------------- 1469** 1470** Display of unknown devices. 1471** 1472**----------------------------------------------------------- 1473*/ 1474struct vt { 1475 u_short ident; 1476 char* name; 1477}; 1478 1479static struct vt VendorTable[] = { 1480 {0x0e11, "Compaq"}, 1481 {0x1000, "NCR/Symbios"}, 1482 {0x1002, "ATI Technologies Inc."}, 1483 {0x1004, "VLSI"}, 1484 {0x100B, "National Semiconductor"}, 1485 {0x100E, "Weitek"}, 1486 {0x1011, "Digital Equipment Corporation"}, 1487 {0x1013, "Cirrus Logic"}, 1488 {0x101A, "NCR"}, 1489 {0x1022, "AMD"}, 1490 {0x102B, "Matrox"}, 1491 {0x102C, "Chips & Technologies"}, 1492 {0x1039, "Silicon Integrated Systems"}, 1493 {0x1042, "SMC"}, 1494 {0x1044, "DPT"}, 1495 {0x1045, "OPTI"}, 1496 {0x104B, "Bus Logic"}, 1497 {0x1060, "UMC"}, 1498 {0x1080, "Contaq"}, 1499 {0x1095, "CMD"}, 1500 {0x10b9, "ACER Labs"}, 1501 {0x1106, "VIA Technologies"}, 1502 {0x5333, "S3 Inc."}, 1503 {0x8086, "Intel Corporation"}, 1504 {0x9004, "Adaptec"}, 1505 {0,0} 1506}; 1507 1508typedef struct { 1509 const char subclass; 1510 const char *name; 1511} subclass_name; 1512 1513/* 0x00 prehistoric subclasses */ 1514static const subclass_name old_subclasses[] = 1515{ 1516 { 0x00, "misc" }, 1517 { 0x01, "vga" }, 1518 { 0x00, NULL } 1519}; 1520 1521/* 0x01 mass storage subclasses */ 1522static const subclass_name storage_subclasses[] = 1523{ 1524 { 0x00, "scsi" }, 1525 { 0x01, "ide" }, 1526 { 0x02, "floppy"}, 1527 { 0x03, "ipi" }, 1528 { 0x80, "misc" }, 1529 { 0x00, NULL } 1530}; 1531 1532/* 0x02 network subclasses */ 1533static const subclass_name network_subclasses[] = 1534{ 1535 { 0x00, "ethernet" }, 1536 { 0x01, "tokenring" }, 1537 { 0x02, "fddi" }, 1538 { 0x80, "misc" }, 1539 { 0x00, NULL } 1540}; 1541 1542/* 0x03 display subclasses */ 1543static const subclass_name display_subclasses[] = 1544{ 1545 { 0x00, "vga" }, 1546 { 0x01, "xga" }, 1547 { 0x80, "misc" }, 1548 { 0x00, NULL } 1549}; 1550 1551/* 0x04 multimedia subclasses */ 1552static const subclass_name multimedia_subclasses[] = 1553{ 1554 { 0x00, "video" }, 1555 { 0x01, "audio" }, 1556 { 0x80, "misc" }, 1557 { 0x00, NULL } 1558}; 1559 1560/* 0x05 memory subclasses */ 1561static const subclass_name memory_subclasses[] = 1562{ 1563 { 0x00, "ram" }, 1564 { 0x01, "flash" }, 1565 { 0x80, "misc" }, 1566 { 0x00, NULL } 1567}; 1568 1569/* 0x06 bridge subclasses */ 1570static const subclass_name bridge_subclasses[] = 1571{ 1572 { 0x00, "host" }, 1573 { 0x01, "isa" }, 1574 { 0x02, "eisa" }, 1575 { 0x03, "mc" }, 1576 { 0x04, "pci" }, 1577 { 0x05, "pcmcia"}, 1578 { 0x80, "misc" }, 1579 { 0x00, NULL } 1580}; 1581 1582static const subclass_name *const subclasses[] = { 1583 old_subclasses, 1584 storage_subclasses, 1585 network_subclasses, 1586 display_subclasses, 1587 multimedia_subclasses, 1588 memory_subclasses, 1589 bridge_subclasses, 1590}; 1591 1592static const char *const majclasses[] = { 1593 "old", 1594 "storage", 1595 "network", 1596 "display", 1597 "multimedia", 1598 "memory", 1599 "bridge" 1600}; 1601 1602 1603void not_supported (pcici_t tag, u_long type) 1604{ 1605 u_char reg; 1606 u_long data; 1607 struct vt * vp; 1608 1609 /* 1610 ** lookup the names. 1611 */ 1612 1613 for (vp=VendorTable; vp->ident; vp++) 1614 if (vp->ident == (type & 0xffff)) 1615 break; 1616 1617 /* 1618 ** and display them. 1619 */ 1620 1621 if (vp->ident) printf (vp->name); 1622 else printf ("vendor=0x%04lx", type & 0xffff); 1623 1624 printf (", device=0x%04lx", type >> 16); 1625 1626 data = (pcibus->pb_read(tag, PCI_CLASS_REG) >> 24) & 0xff; 1627 if (data < sizeof(majclasses) / sizeof(majclasses[0])) 1628 printf(", class=%s", majclasses[data]); 1629 if (data < sizeof(subclasses) / sizeof(subclasses[0])) { 1630 const subclass_name *p = subclasses[data]; 1631 1632 data = (pcibus->pb_read(tag, PCI_CLASS_REG) >> 16) & 0xff; 1633 while (p->name && (p->subclass != data)) 1634 p++; 1635 if (p->name) { 1636 printf(" (%s)", p->name); 1637 } else { 1638 printf(" (unknown subclass 0x%02lx)", data); 1639 } 1640 } 1641 1642 printf (" [no driver assigned]\n"); 1643 1644 if (bootverbose) { 1645 for (reg=PCI_MAP_REG_START; reg<PCI_MAP_REG_END; reg+=4) { 1646 data = pcibus->pb_read (tag, reg); 1647 if ((data&~7)==0) continue; 1648 switch (data&7) { 1649 1650 case 1: 1651 case 5: 1652 printf (" map(%x): io(%lx)\n", 1653 reg, data & ~3); 1654 break; 1655 case 0: 1656 printf (" map(%x): mem32(%lx)\n", 1657 reg, data & ~7); 1658 break; 1659 case 2: 1660 printf (" map(%x): mem20(%lx)\n", 1661 reg, data & ~7); 1662 break; 1663 case 4: 1664 printf (" map(%x): mem64(%lx)\n", 1665 reg, data & ~7); 1666 break; 1667 } 1668 } 1669 } 1670} 1671#endif /* NPCI */ 1672