pci.c revision 120155
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 120155 2003-09-17 08:32:44Z iwasaki $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static uint32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68 69static int pci_porten(device_t pcib, int b, int s, int f); 70static int pci_memen(device_t pcib, int b, int s, int f); 71static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 72 struct resource_list *rl); 73static void pci_add_resources(device_t pcib, device_t bus, 74 device_t dev); 75static int pci_probe(device_t dev); 76static int pci_attach(device_t dev); 77static void pci_load_vendor_data(void); 78static int pci_describe_parse_line(char **ptr, int *vendor, 79 int *device, char **desc); 80static char *pci_describe_device(device_t dev); 81static int pci_modevent(module_t mod, int what, void *arg); 82static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 83 pcicfgregs *cfg); 84static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 85 86static device_method_t pci_methods[] = { 87 /* Device interface */ 88 DEVMETHOD(device_probe, pci_probe), 89 DEVMETHOD(device_attach, pci_attach), 90 DEVMETHOD(device_shutdown, bus_generic_shutdown), 91 DEVMETHOD(device_suspend, bus_generic_suspend), 92 DEVMETHOD(device_resume, pci_resume), 93 94 /* Bus interface */ 95 DEVMETHOD(bus_print_child, pci_print_child), 96 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 97 DEVMETHOD(bus_read_ivar, pci_read_ivar), 98 DEVMETHOD(bus_write_ivar, pci_write_ivar), 99 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 100 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 101 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 102 103 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 104 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 105 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 106 DEVMETHOD(bus_delete_resource, pci_delete_resource), 107 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 108 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 109 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 110 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 111 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 112 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 113 114 /* PCI interface */ 115 DEVMETHOD(pci_read_config, pci_read_config_method), 116 DEVMETHOD(pci_write_config, pci_write_config_method), 117 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 118 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 119 DEVMETHOD(pci_enable_io, pci_enable_io_method), 120 DEVMETHOD(pci_disable_io, pci_disable_io_method), 121 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 122 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 123 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 124 125 { 0, 0 } 126}; 127 128static driver_t pci_driver = { 129 "pci", 130 pci_methods, 131 0, /* no softc */ 132}; 133 134devclass_t pci_devclass; 135DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 136MODULE_VERSION(pci, 1); 137 138static char *pci_vendordata; 139static size_t pci_vendordata_size; 140 141 142struct pci_quirk { 143 uint32_t devid; /* Vendor/device of the card */ 144 int type; 145#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 146 int arg1; 147 int arg2; 148}; 149 150struct pci_quirk pci_quirks[] = { 151 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 152 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 153 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 154 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 155 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 156 157 { 0 } 158}; 159 160/* map register information */ 161#define PCI_MAPMEM 0x01 /* memory map */ 162#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 163#define PCI_MAPPORT 0x04 /* port map */ 164 165struct devlist pci_devq; 166uint32_t pci_generation; 167uint32_t pci_numdevs = 0; 168 169/* sysctl vars */ 170SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 171 172static int pci_enable_io_modes = 1; 173TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 174SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 175 &pci_enable_io_modes, 1, 176 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 177enable these bits correctly. We'd like to do this all the time, but there\n\ 178are some peripherals that this causes problems with."); 179 180/* Find a device_t by bus/slot/function */ 181 182device_t 183pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 184{ 185 struct pci_devinfo *dinfo; 186 187 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 188 if ((dinfo->cfg.bus == bus) && 189 (dinfo->cfg.slot == slot) && 190 (dinfo->cfg.func == func)) { 191 return (dinfo->cfg.dev); 192 } 193 } 194 195 return (NULL); 196} 197 198/* Find a device_t by vendor/device ID */ 199 200device_t 201pci_find_device(uint16_t vendor, uint16_t device) 202{ 203 struct pci_devinfo *dinfo; 204 205 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 206 if ((dinfo->cfg.vendor == vendor) && 207 (dinfo->cfg.device == device)) { 208 return (dinfo->cfg.dev); 209 } 210 } 211 212 return (NULL); 213} 214 215/* return base address of memory or port map */ 216 217static uint32_t 218pci_mapbase(unsigned mapreg) 219{ 220 int mask = 0x03; 221 if ((mapreg & 0x01) == 0) 222 mask = 0x0f; 223 return (mapreg & ~mask); 224} 225 226/* return map type of memory or port map */ 227 228static int 229pci_maptype(unsigned mapreg) 230{ 231 static uint8_t maptype[0x10] = { 232 PCI_MAPMEM, PCI_MAPPORT, 233 PCI_MAPMEM, 0, 234 PCI_MAPMEM, PCI_MAPPORT, 235 0, 0, 236 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 237 PCI_MAPMEM|PCI_MAPMEMP, 0, 238 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 239 0, 0, 240 }; 241 242 return maptype[mapreg & 0x0f]; 243} 244 245/* return log2 of map size decoded for memory or port map */ 246 247static int 248pci_mapsize(unsigned testval) 249{ 250 int ln2size; 251 252 testval = pci_mapbase(testval); 253 ln2size = 0; 254 if (testval != 0) { 255 while ((testval & 1) == 0) 256 { 257 ln2size++; 258 testval >>= 1; 259 } 260 } 261 return (ln2size); 262} 263 264/* return log2 of address range supported by map register */ 265 266static int 267pci_maprange(unsigned mapreg) 268{ 269 int ln2range = 0; 270 switch (mapreg & 0x07) { 271 case 0x00: 272 case 0x01: 273 case 0x05: 274 ln2range = 32; 275 break; 276 case 0x02: 277 ln2range = 20; 278 break; 279 case 0x04: 280 ln2range = 64; 281 break; 282 } 283 return (ln2range); 284} 285 286/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 287 288static void 289pci_fixancient(pcicfgregs *cfg) 290{ 291 if (cfg->hdrtype != 0) 292 return; 293 294 /* PCI to PCI bridges use header type 1 */ 295 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 296 cfg->hdrtype = 1; 297} 298 299/* extract header type specific config data */ 300 301static void 302pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 303{ 304#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 305 switch (cfg->hdrtype) { 306 case 0: 307 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 308 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 309 cfg->nummaps = PCI_MAXMAPS_0; 310 break; 311 case 1: 312 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 313 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 314 cfg->nummaps = PCI_MAXMAPS_1; 315 break; 316 case 2: 317 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 318 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 319 cfg->nummaps = PCI_MAXMAPS_2; 320 break; 321 } 322#undef REG 323} 324 325/* read configuration header into pcicfgregs structure */ 326 327struct pci_devinfo * 328pci_read_device(device_t pcib, int b, int s, int f, size_t size) 329{ 330#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 331 pcicfgregs *cfg = NULL; 332 struct pci_devinfo *devlist_entry; 333 struct devlist *devlist_head; 334 335 devlist_head = &pci_devq; 336 337 devlist_entry = NULL; 338 339 if (REG(PCIR_DEVVENDOR, 4) != -1) { 340 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 341 if (devlist_entry == NULL) 342 return (NULL); 343 344 cfg = &devlist_entry->cfg; 345 346 cfg->bus = b; 347 cfg->slot = s; 348 cfg->func = f; 349 cfg->vendor = REG(PCIR_VENDOR, 2); 350 cfg->device = REG(PCIR_DEVICE, 2); 351 cfg->cmdreg = REG(PCIR_COMMAND, 2); 352 cfg->statreg = REG(PCIR_STATUS, 2); 353 cfg->baseclass = REG(PCIR_CLASS, 1); 354 cfg->subclass = REG(PCIR_SUBCLASS, 1); 355 cfg->progif = REG(PCIR_PROGIF, 1); 356 cfg->revid = REG(PCIR_REVID, 1); 357 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 358 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 359 cfg->lattimer = REG(PCIR_LATTIMER, 1); 360 cfg->intpin = REG(PCIR_INTPIN, 1); 361 cfg->intline = REG(PCIR_INTLINE, 1); 362 363 cfg->mingnt = REG(PCIR_MINGNT, 1); 364 cfg->maxlat = REG(PCIR_MAXLAT, 1); 365 366 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 367 cfg->hdrtype &= ~PCIM_MFDEV; 368 369 pci_fixancient(cfg); 370 pci_hdrtypedata(pcib, b, s, f, cfg); 371 372 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 373 pci_read_extcap(pcib, cfg); 374 375 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 376 377 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 378 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 379 devlist_entry->conf.pc_sel.pc_func = cfg->func; 380 devlist_entry->conf.pc_hdr = cfg->hdrtype; 381 382 devlist_entry->conf.pc_subvendor = cfg->subvendor; 383 devlist_entry->conf.pc_subdevice = cfg->subdevice; 384 devlist_entry->conf.pc_vendor = cfg->vendor; 385 devlist_entry->conf.pc_device = cfg->device; 386 387 devlist_entry->conf.pc_class = cfg->baseclass; 388 devlist_entry->conf.pc_subclass = cfg->subclass; 389 devlist_entry->conf.pc_progif = cfg->progif; 390 devlist_entry->conf.pc_revid = cfg->revid; 391 392 pci_numdevs++; 393 pci_generation++; 394 } 395 return (devlist_entry); 396#undef REG 397} 398 399static void 400pci_read_extcap(device_t pcib, pcicfgregs *cfg) 401{ 402#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 403 int ptr, nextptr, ptrptr; 404 405 switch (cfg->hdrtype & PCIM_HDRTYPE) { 406 case 0: 407 ptrptr = PCIR_CAP_PTR; 408 break; 409 case 2: 410 ptrptr = 0x14; 411 break; 412 default: 413 return; /* no extended capabilities support */ 414 } 415 nextptr = REG(ptrptr, 1); /* sanity check? */ 416 417 /* 418 * Read capability entries. 419 */ 420 while (nextptr != 0) { 421 /* Sanity check */ 422 if (nextptr > 255) { 423 printf("illegal PCI extended capability offset %d\n", 424 nextptr); 425 return; 426 } 427 /* Find the next entry */ 428 ptr = nextptr; 429 nextptr = REG(ptr + 1, 1); 430 431 /* Process this entry */ 432 switch (REG(ptr, 1)) { 433 case PCIY_PMG: /* PCI power management */ 434 if (cfg->pp.pp_cap == 0) { 435 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 436 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 437 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 438 if ((nextptr - ptr) > PCIR_POWER_DATA) 439 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 440 } 441 break; 442 case PCIY_MSI: /* PCI MSI */ 443 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 444 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 445 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 446 else 447 cfg->msi.msi_data = PCIR_MSI_DATA; 448 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 449 PCIM_MSICTRL_MMC_MASK)>>1); 450 default: 451 break; 452 } 453 } 454#undef REG 455} 456 457/* free pcicfgregs structure and all depending data structures */ 458 459int 460pci_freecfg(struct pci_devinfo *dinfo) 461{ 462 struct devlist *devlist_head; 463 464 devlist_head = &pci_devq; 465 466 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 467 free(dinfo, M_DEVBUF); 468 469 /* increment the generation count */ 470 pci_generation++; 471 472 /* we're losing one device */ 473 pci_numdevs--; 474 return (0); 475} 476 477/* 478 * PCI power manangement 479 */ 480int 481pci_set_powerstate_method(device_t dev, device_t child, int state) 482{ 483 struct pci_devinfo *dinfo = device_get_ivars(child); 484 pcicfgregs *cfg = &dinfo->cfg; 485 uint16_t status; 486 int result; 487 488 if (cfg->pp.pp_cap != 0) { 489 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 490 & ~PCIM_PSTAT_DMASK; 491 result = 0; 492 switch (state) { 493 case PCI_POWERSTATE_D0: 494 status |= PCIM_PSTAT_D0; 495 break; 496 case PCI_POWERSTATE_D1: 497 if (cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) { 498 status |= PCIM_PSTAT_D1; 499 } else { 500 result = EOPNOTSUPP; 501 } 502 break; 503 case PCI_POWERSTATE_D2: 504 if (cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) { 505 status |= PCIM_PSTAT_D2; 506 } else { 507 result = EOPNOTSUPP; 508 } 509 break; 510 case PCI_POWERSTATE_D3: 511 status |= PCIM_PSTAT_D3; 512 break; 513 default: 514 result = EINVAL; 515 } 516 if (result == 0) 517 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 518 2); 519 } else { 520 result = ENXIO; 521 } 522 return(result); 523} 524 525int 526pci_get_powerstate_method(device_t dev, device_t child) 527{ 528 struct pci_devinfo *dinfo = device_get_ivars(child); 529 pcicfgregs *cfg = &dinfo->cfg; 530 uint16_t status; 531 int result; 532 533 if (cfg->pp.pp_cap != 0) { 534 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 535 switch (status & PCIM_PSTAT_DMASK) { 536 case PCIM_PSTAT_D0: 537 result = PCI_POWERSTATE_D0; 538 break; 539 case PCIM_PSTAT_D1: 540 result = PCI_POWERSTATE_D1; 541 break; 542 case PCIM_PSTAT_D2: 543 result = PCI_POWERSTATE_D2; 544 break; 545 case PCIM_PSTAT_D3: 546 result = PCI_POWERSTATE_D3; 547 break; 548 default: 549 result = PCI_POWERSTATE_UNKNOWN; 550 break; 551 } 552 } else { 553 /* No support, device is always at D0 */ 554 result = PCI_POWERSTATE_D0; 555 } 556 return(result); 557} 558 559/* 560 * Some convenience functions for PCI device drivers. 561 */ 562 563static __inline void 564pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 565{ 566 uint16_t command; 567 568 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 569 command |= bit; 570 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 571} 572 573static __inline void 574pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 575{ 576 uint16_t command; 577 578 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 579 command &= ~bit; 580 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 581} 582 583int 584pci_enable_busmaster_method(device_t dev, device_t child) 585{ 586 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 587 return (0); 588} 589 590int 591pci_disable_busmaster_method(device_t dev, device_t child) 592{ 593 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 594 return (0); 595} 596 597int 598pci_enable_io_method(device_t dev, device_t child, int space) 599{ 600 uint16_t command; 601 uint16_t bit; 602 char *error; 603 604 bit = 0; 605 error = NULL; 606 607 switch(space) { 608 case SYS_RES_IOPORT: 609 bit = PCIM_CMD_PORTEN; 610 error = "port"; 611 break; 612 case SYS_RES_MEMORY: 613 bit = PCIM_CMD_MEMEN; 614 error = "memory"; 615 break; 616 default: 617 return (EINVAL); 618 } 619 pci_set_command_bit(dev, child, bit); 620 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 621 if (command & bit) 622 return (0); 623 device_printf(child, "failed to enable %s mapping!\n", error); 624 return (ENXIO); 625} 626 627int 628pci_disable_io_method(device_t dev, device_t child, int space) 629{ 630 uint16_t command; 631 uint16_t bit; 632 char *error; 633 634 bit = 0; 635 error = NULL; 636 637 switch(space) { 638 case SYS_RES_IOPORT: 639 bit = PCIM_CMD_PORTEN; 640 error = "port"; 641 break; 642 case SYS_RES_MEMORY: 643 bit = PCIM_CMD_MEMEN; 644 error = "memory"; 645 break; 646 default: 647 return (EINVAL); 648 } 649 pci_clear_command_bit(dev, child, bit); 650 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 651 if (command & bit) { 652 device_printf(child, "failed to disable %s mapping!\n", error); 653 return (ENXIO); 654 } 655 return (0); 656} 657 658/* 659 * New style pci driver. Parent device is either a pci-host-bridge or a 660 * pci-pci-bridge. Both kinds are represented by instances of pcib. 661 */ 662 663void 664pci_print_verbose(struct pci_devinfo *dinfo) 665{ 666 if (bootverbose) { 667 pcicfgregs *cfg = &dinfo->cfg; 668 669 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 670 cfg->vendor, cfg->device, cfg->revid); 671 printf("\tbus=%d, slot=%d, func=%d\n", 672 cfg->bus, cfg->slot, cfg->func); 673 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 674 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 675 cfg->mfdev); 676 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 677 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 678 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 679 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 680 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 681 if (cfg->intpin > 0) 682 printf("\tintpin=%c, irq=%d\n", 683 cfg->intpin +'a' -1, cfg->intline); 684 if (cfg->pp.pp_cap) { 685 uint16_t status; 686 687 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 688 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 689 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 690 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 691 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 692 status & PCIM_PSTAT_DMASK); 693 } 694 if (cfg->msi.msi_data) { 695 int ctrl; 696 697 ctrl = cfg->msi.msi_ctrl; 698 printf("\tMSI supports %d message%s%s%s\n", 699 cfg->msi.msi_msgnum, 700 (cfg->msi.msi_msgnum == 1) ? "" : "s", 701 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 702 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 703 } 704 } 705} 706 707static int 708pci_porten(device_t pcib, int b, int s, int f) 709{ 710 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 711 & PCIM_CMD_PORTEN) != 0; 712} 713 714static int 715pci_memen(device_t pcib, int b, int s, int f) 716{ 717 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 718 & PCIM_CMD_MEMEN) != 0; 719} 720 721/* 722 * Add a resource based on a pci map register. Return 1 if the map 723 * register is a 32bit map register or 2 if it is a 64bit register. 724 */ 725static int 726pci_add_map(device_t pcib, int b, int s, int f, int reg, 727 struct resource_list *rl) 728{ 729 uint32_t map; 730 uint64_t base; 731 uint8_t ln2size; 732 uint8_t ln2range; 733 uint32_t testval; 734 uint16_t cmd; 735 int type; 736 737 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 738 739 if (map == 0 || map == 0xffffffff) 740 return (1); /* skip invalid entry */ 741 742 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 743 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 744 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 745 746 base = pci_mapbase(map); 747 if (pci_maptype(map) & PCI_MAPMEM) 748 type = SYS_RES_MEMORY; 749 else 750 type = SYS_RES_IOPORT; 751 ln2size = pci_mapsize(testval); 752 ln2range = pci_maprange(testval); 753 if (ln2range == 64) { 754 /* Read the other half of a 64bit map register */ 755 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 756 } 757 758 if (bootverbose) { 759 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 760 reg, pci_maptype(map), ln2range, 761 (unsigned int) base, ln2size); 762 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 763 printf(", port disabled\n"); 764 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 765 printf(", memory disabled\n"); 766 else 767 printf(", enabled\n"); 768 } 769 770 /* 771 * This code theoretically does the right thing, but has 772 * undesirable side effects in some cases where 773 * peripherals respond oddly to having these bits 774 * enabled. Leave them alone by default. 775 */ 776 if (pci_enable_io_modes) { 777 /* Turn on resources that have been left off by a lazy BIOS */ 778 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 779 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 780 cmd |= PCIM_CMD_PORTEN; 781 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 782 } 783 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 784 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 785 cmd |= PCIM_CMD_MEMEN; 786 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 787 } 788 } else { 789 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 790 return (1); 791 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 792 return (1); 793 } 794 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1, 795 (1 << ln2size)); 796 797 return ((ln2range == 64) ? 2 : 1); 798} 799 800static void 801pci_add_resources(device_t pcib, device_t bus, device_t dev) 802{ 803 struct pci_devinfo *dinfo = device_get_ivars(dev); 804 pcicfgregs *cfg = &dinfo->cfg; 805 struct resource_list *rl = &dinfo->resources; 806 struct pci_quirk *q; 807 int b, i, irq, f, s; 808 809 b = cfg->bus; 810 s = cfg->slot; 811 f = cfg->func; 812 for (i = 0; i < cfg->nummaps;) { 813 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i), rl); 814 } 815 816 for (q = &pci_quirks[0]; q->devid; q++) { 817 if (q->devid == ((cfg->device << 16) | cfg->vendor) 818 && q->type == PCI_QUIRK_MAP_REG) 819 pci_add_map(pcib, b, s, f, q->arg1, rl); 820 } 821 822 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 823#if defined(__ia64__) || (defined(__i386__) && !defined(SMP)) 824 /* 825 * Try to re-route interrupts. Sometimes the BIOS or 826 * firmware may leave bogus values in these registers. 827 * If the re-route fails, then just stick with what we 828 * have. 829 */ 830 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 831 if (PCI_INTERRUPT_VALID(irq)) { 832 pci_write_config(dev, PCIR_INTLINE, irq, 1); 833 cfg->intline = irq; 834 } else 835#endif 836 irq = cfg->intline; 837 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 838 } 839} 840 841void 842pci_add_children(device_t dev, int busno, size_t dinfo_size) 843{ 844#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 845 device_t pcib = device_get_parent(dev); 846 struct pci_devinfo *dinfo; 847 int maxslots; 848 int s, f, pcifunchigh; 849 uint8_t hdrtype; 850 851 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 852 ("dinfo_size too small")); 853 maxslots = PCIB_MAXSLOTS(pcib); 854 for (s = 0; s <= maxslots; s++) { 855 pcifunchigh = 0; 856 f = 0; 857 hdrtype = REG(PCIR_HDRTYPE, 1); 858 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 859 continue; 860 if (hdrtype & PCIM_MFDEV) 861 pcifunchigh = PCI_FUNCMAX; 862 for (f = 0; f <= pcifunchigh; f++) { 863 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 864 if (dinfo != NULL) { 865 pci_add_child(dev, dinfo); 866 } 867 } 868 } 869#undef REG 870} 871 872void 873pci_add_child(device_t bus, struct pci_devinfo *dinfo) 874{ 875 device_t pcib; 876 877 pcib = device_get_parent(bus); 878 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 879 device_set_ivars(dinfo->cfg.dev, dinfo); 880 pci_add_resources(pcib, bus, dinfo->cfg.dev); 881 pci_print_verbose(dinfo); 882} 883 884static int 885pci_probe(device_t dev) 886{ 887 888 device_set_desc(dev, "PCI bus"); 889 890 /* Allow other subclasses to override this driver. */ 891 return (-1000); 892} 893 894static int 895pci_attach(device_t dev) 896{ 897 int busno; 898 899 /* 900 * Since there can be multiple independantly numbered PCI 901 * busses on some large alpha systems, we can't use the unit 902 * number to decide what bus we are probing. We ask the parent 903 * pcib what our bus number is. 904 */ 905 busno = pcib_get_bus(dev); 906 if (bootverbose) 907 device_printf(dev, "physical bus=%d\n", busno); 908 909 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 910 911 return (bus_generic_attach(dev)); 912} 913 914static void 915pci_load_vendor_data(void) 916{ 917 caddr_t vendordata, info; 918 919 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 920 info = preload_search_info(vendordata, MODINFO_ADDR); 921 pci_vendordata = *(char **)info; 922 info = preload_search_info(vendordata, MODINFO_SIZE); 923 pci_vendordata_size = *(size_t *)info; 924 /* terminate the database */ 925 pci_vendordata[pci_vendordata_size] = '\n'; 926 } 927} 928 929int 930pci_print_child(device_t dev, device_t child) 931{ 932 struct pci_devinfo *dinfo; 933 struct resource_list *rl; 934 int retval = 0; 935 936 dinfo = device_get_ivars(child); 937 rl = &dinfo->resources; 938 939 retval += bus_print_child_header(dev, child); 940 941 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 942 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 943 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 944 if (device_get_flags(dev)) 945 retval += printf(" flags %#x", device_get_flags(dev)); 946 947 retval += printf(" at device %d.%d", pci_get_slot(child), 948 pci_get_function(child)); 949 950 retval += bus_print_child_footer(dev, child); 951 952 return (retval); 953} 954 955static struct 956{ 957 int class; 958 int subclass; 959 char *desc; 960} pci_nomatch_tab[] = { 961 {PCIC_OLD, -1, "old"}, 962 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 963 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 964 {PCIC_STORAGE, -1, "mass storage"}, 965 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 966 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 967 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 968 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 969 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 970 {PCIC_NETWORK, -1, "network"}, 971 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 972 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 973 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 974 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 975 {PCIC_DISPLAY, -1, "display"}, 976 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 977 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 978 {PCIC_MULTIMEDIA, -1, "multimedia"}, 979 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 980 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 981 {PCIC_MEMORY, -1, "memory"}, 982 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 983 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 984 {PCIC_BRIDGE, -1, "bridge"}, 985 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 986 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 987 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 988 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 989 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 990 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 991 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 992 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 993 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 994 {PCIC_SIMPLECOMM, -1, "simple comms"}, 995 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 996 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 997 {PCIC_BASEPERIPH, -1, "base peripheral"}, 998 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 999 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1000 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1001 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1002 {PCIC_INPUTDEV, -1, "input device"}, 1003 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1004 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1005 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1006 {PCIC_DOCKING, -1, "docking station"}, 1007 {PCIC_PROCESSOR, -1, "processor"}, 1008 {PCIC_SERIALBUS, -1, "serial bus"}, 1009 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1010 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1011 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1012 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1013 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1014 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1015 {0, 0, NULL} 1016}; 1017 1018void 1019pci_probe_nomatch(device_t dev, device_t child) 1020{ 1021 int i; 1022 char *cp, *scp, *device; 1023 1024 /* 1025 * Look for a listing for this device in a loaded device database. 1026 */ 1027 if ((device = pci_describe_device(child)) != NULL) { 1028 device_printf(dev, "<%s>", device); 1029 free(device, M_DEVBUF); 1030 } else { 1031 /* 1032 * Scan the class/subclass descriptions for a general 1033 * description. 1034 */ 1035 cp = "unknown"; 1036 scp = NULL; 1037 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1038 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1039 if (pci_nomatch_tab[i].subclass == -1) { 1040 cp = pci_nomatch_tab[i].desc; 1041 } else if (pci_nomatch_tab[i].subclass == 1042 pci_get_subclass(child)) { 1043 scp = pci_nomatch_tab[i].desc; 1044 } 1045 } 1046 } 1047 device_printf(dev, "<%s%s%s>", 1048 cp ? cp : "", 1049 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1050 scp ? scp : ""); 1051 } 1052 printf(" at device %d.%d (no driver attached)\n", 1053 pci_get_slot(child), pci_get_function(child)); 1054 return; 1055} 1056 1057/* 1058 * Parse the PCI device database, if loaded, and return a pointer to a 1059 * description of the device. 1060 * 1061 * The database is flat text formatted as follows: 1062 * 1063 * Any line not in a valid format is ignored. 1064 * Lines are terminated with newline '\n' characters. 1065 * 1066 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1067 * the vendor name. 1068 * 1069 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1070 * - devices cannot be listed without a corresponding VENDOR line. 1071 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1072 * another TAB, then the device name. 1073 */ 1074 1075/* 1076 * Assuming (ptr) points to the beginning of a line in the database, 1077 * return the vendor or device and description of the next entry. 1078 * The value of (vendor) or (device) inappropriate for the entry type 1079 * is set to -1. Returns nonzero at the end of the database. 1080 * 1081 * Note that this is slightly unrobust in the face of corrupt data; 1082 * we attempt to safeguard against this by spamming the end of the 1083 * database with a newline when we initialise. 1084 */ 1085static int 1086pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1087{ 1088 char *cp = *ptr; 1089 int left; 1090 1091 *device = -1; 1092 *vendor = -1; 1093 **desc = '\0'; 1094 for (;;) { 1095 left = pci_vendordata_size - (cp - pci_vendordata); 1096 if (left <= 0) { 1097 *ptr = cp; 1098 return(1); 1099 } 1100 1101 /* vendor entry? */ 1102 if (*cp != '\t' && 1103 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1104 break; 1105 /* device entry? */ 1106 if (*cp == '\t' && 1107 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1108 break; 1109 1110 /* skip to next line */ 1111 while (*cp != '\n' && left > 0) { 1112 cp++; 1113 left--; 1114 } 1115 if (*cp == '\n') { 1116 cp++; 1117 left--; 1118 } 1119 } 1120 /* skip to next line */ 1121 while (*cp != '\n' && left > 0) { 1122 cp++; 1123 left--; 1124 } 1125 if (*cp == '\n' && left > 0) 1126 cp++; 1127 *ptr = cp; 1128 return(0); 1129} 1130 1131static char * 1132pci_describe_device(device_t dev) 1133{ 1134 int vendor, device; 1135 char *desc, *vp, *dp, *line; 1136 1137 desc = vp = dp = NULL; 1138 1139 /* 1140 * If we have no vendor data, we can't do anything. 1141 */ 1142 if (pci_vendordata == NULL) 1143 goto out; 1144 1145 /* 1146 * Scan the vendor data looking for this device 1147 */ 1148 line = pci_vendordata; 1149 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1150 goto out; 1151 for (;;) { 1152 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1153 goto out; 1154 if (vendor == pci_get_vendor(dev)) 1155 break; 1156 } 1157 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1158 goto out; 1159 for (;;) { 1160 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1161 *dp = 0; 1162 break; 1163 } 1164 if (vendor != -1) { 1165 *dp = 0; 1166 break; 1167 } 1168 if (device == pci_get_device(dev)) 1169 break; 1170 } 1171 if (dp[0] == '\0') 1172 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1173 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1174 NULL) 1175 sprintf(desc, "%s, %s", vp, dp); 1176 out: 1177 if (vp != NULL) 1178 free(vp, M_DEVBUF); 1179 if (dp != NULL) 1180 free(dp, M_DEVBUF); 1181 return(desc); 1182} 1183 1184int 1185pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1186{ 1187 struct pci_devinfo *dinfo; 1188 pcicfgregs *cfg; 1189 1190 dinfo = device_get_ivars(child); 1191 cfg = &dinfo->cfg; 1192 1193 switch (which) { 1194 case PCI_IVAR_ETHADDR: 1195 /* 1196 * The generic accessor doesn't deal with failure, so 1197 * we set the return value, then return an error. 1198 */ 1199 *((uint8_t **) result) = NULL; 1200 return (EINVAL); 1201 case PCI_IVAR_SUBVENDOR: 1202 *result = cfg->subvendor; 1203 break; 1204 case PCI_IVAR_SUBDEVICE: 1205 *result = cfg->subdevice; 1206 break; 1207 case PCI_IVAR_VENDOR: 1208 *result = cfg->vendor; 1209 break; 1210 case PCI_IVAR_DEVICE: 1211 *result = cfg->device; 1212 break; 1213 case PCI_IVAR_DEVID: 1214 *result = (cfg->device << 16) | cfg->vendor; 1215 break; 1216 case PCI_IVAR_CLASS: 1217 *result = cfg->baseclass; 1218 break; 1219 case PCI_IVAR_SUBCLASS: 1220 *result = cfg->subclass; 1221 break; 1222 case PCI_IVAR_PROGIF: 1223 *result = cfg->progif; 1224 break; 1225 case PCI_IVAR_REVID: 1226 *result = cfg->revid; 1227 break; 1228 case PCI_IVAR_INTPIN: 1229 *result = cfg->intpin; 1230 break; 1231 case PCI_IVAR_IRQ: 1232 *result = cfg->intline; 1233 break; 1234 case PCI_IVAR_BUS: 1235 *result = cfg->bus; 1236 break; 1237 case PCI_IVAR_SLOT: 1238 *result = cfg->slot; 1239 break; 1240 case PCI_IVAR_FUNCTION: 1241 *result = cfg->func; 1242 break; 1243 default: 1244 return (ENOENT); 1245 } 1246 return (0); 1247} 1248 1249int 1250pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1251{ 1252 struct pci_devinfo *dinfo; 1253 1254 dinfo = device_get_ivars(child); 1255 1256 switch (which) { 1257 case PCI_IVAR_INTPIN: 1258 dinfo->cfg.intpin = value; 1259 return (0); 1260 case PCI_IVAR_ETHADDR: 1261 case PCI_IVAR_SUBVENDOR: 1262 case PCI_IVAR_SUBDEVICE: 1263 case PCI_IVAR_VENDOR: 1264 case PCI_IVAR_DEVICE: 1265 case PCI_IVAR_DEVID: 1266 case PCI_IVAR_CLASS: 1267 case PCI_IVAR_SUBCLASS: 1268 case PCI_IVAR_PROGIF: 1269 case PCI_IVAR_REVID: 1270 case PCI_IVAR_IRQ: 1271 case PCI_IVAR_BUS: 1272 case PCI_IVAR_SLOT: 1273 case PCI_IVAR_FUNCTION: 1274 return (EINVAL); /* disallow for now */ 1275 1276 default: 1277 return (ENOENT); 1278 } 1279} 1280 1281 1282#include "opt_ddb.h" 1283#ifdef DDB 1284#include <ddb/ddb.h> 1285#include <sys/cons.h> 1286 1287/* 1288 * List resources based on pci map registers, used for within ddb 1289 */ 1290 1291DB_SHOW_COMMAND(pciregs, db_pci_dump) 1292{ 1293 struct pci_devinfo *dinfo; 1294 struct devlist *devlist_head; 1295 struct pci_conf *p; 1296 const char *name; 1297 int i, error, none_count, quit; 1298 1299 none_count = 0; 1300 /* get the head of the device queue */ 1301 devlist_head = &pci_devq; 1302 1303 /* 1304 * Go through the list of devices and print out devices 1305 */ 1306 db_setup_paging(db_simple_pager, &quit, DB_LINES_PER_PAGE); 1307 for (error = 0, i = 0, quit = 0, 1308 dinfo = STAILQ_FIRST(devlist_head); 1309 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1310 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1311 1312 /* Populate pd_name and pd_unit */ 1313 name = NULL; 1314 if (dinfo->cfg.dev) 1315 name = device_get_name(dinfo->cfg.dev); 1316 1317 p = &dinfo->conf; 1318 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1319 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1320 (name && *name) ? name : "none", 1321 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1322 none_count++, 1323 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1324 p->pc_sel.pc_func, (p->pc_class << 16) | 1325 (p->pc_subclass << 8) | p->pc_progif, 1326 (p->pc_subdevice << 16) | p->pc_subvendor, 1327 (p->pc_device << 16) | p->pc_vendor, 1328 p->pc_revid, p->pc_hdr); 1329 } 1330} 1331#endif /* DDB */ 1332 1333struct resource * 1334pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1335 u_long start, u_long end, u_long count, u_int flags) 1336{ 1337 struct pci_devinfo *dinfo = device_get_ivars(child); 1338 struct resource_list *rl = &dinfo->resources; 1339 pcicfgregs *cfg = &dinfo->cfg; 1340 1341 /* 1342 * Perform lazy resource allocation 1343 * 1344 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1345 */ 1346 if (device_get_parent(child) == dev) { 1347 switch (type) { 1348 case SYS_RES_IRQ: 1349 /* 1350 * If the child device doesn't have an 1351 * interrupt routed and is deserving of an 1352 * interrupt, try to assign it one. 1353 */ 1354 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1355 (cfg->intpin != 0)) { 1356 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1357 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1358 pci_write_config(child, PCIR_INTLINE, 1359 cfg->intline, 1); 1360 resource_list_add(rl, SYS_RES_IRQ, 0, 1361 cfg->intline, cfg->intline, 1); 1362 } 1363 } 1364 break; 1365 case SYS_RES_IOPORT: 1366 case SYS_RES_MEMORY: 1367 if (*rid < PCIR_BAR(cfg->nummaps)) { 1368 /* 1369 * Enable the I/O mode. We should 1370 * also be allocating resources 1371 * too. XXX 1372 */ 1373 if (PCI_ENABLE_IO(dev, child, type)) 1374 return (NULL); 1375 } 1376 break; 1377 } 1378 } 1379 1380 return (resource_list_alloc(rl, dev, child, type, rid, 1381 start, end, count, flags)); 1382} 1383 1384void 1385pci_delete_resource(device_t dev, device_t child, int type, int rid) 1386{ 1387 struct pci_devinfo *dinfo; 1388 struct resource_list *rl; 1389 struct resource_list_entry *rle; 1390 1391 if (device_get_parent(child) != dev) 1392 return; 1393 1394 dinfo = device_get_ivars(child); 1395 rl = &dinfo->resources; 1396 rle = resource_list_find(rl, type, rid); 1397 if (rle) { 1398 if (rle->res) { 1399 if (rman_get_device(rle->res) != dev || 1400 rman_get_flags(rle->res) & RF_ACTIVE) { 1401 device_printf(dev, "delete_resource: " 1402 "Resource still owned by child, oops. " 1403 "(type=%d, rid=%d, addr=%lx)\n", 1404 rle->type, rle->rid, 1405 rman_get_start(rle->res)); 1406 return; 1407 } 1408 bus_release_resource(dev, type, rid, rle->res); 1409 } 1410 resource_list_delete(rl, type, rid); 1411 } 1412 /* 1413 * Why do we turn off the PCI configuration BAR when we delete a 1414 * resource? -- imp 1415 */ 1416 pci_write_config(child, rid, 0, 4); 1417 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1418} 1419 1420struct resource_list * 1421pci_get_resource_list (device_t dev, device_t child) 1422{ 1423 struct pci_devinfo * dinfo = device_get_ivars(child); 1424 struct resource_list * rl = &dinfo->resources; 1425 1426 if (!rl) 1427 return (NULL); 1428 1429 return (rl); 1430} 1431 1432uint32_t 1433pci_read_config_method(device_t dev, device_t child, int reg, int width) 1434{ 1435 struct pci_devinfo *dinfo = device_get_ivars(child); 1436 pcicfgregs *cfg = &dinfo->cfg; 1437 1438 return (PCIB_READ_CONFIG(device_get_parent(dev), 1439 cfg->bus, cfg->slot, cfg->func, reg, width)); 1440} 1441 1442void 1443pci_write_config_method(device_t dev, device_t child, int reg, 1444 uint32_t val, int width) 1445{ 1446 struct pci_devinfo *dinfo = device_get_ivars(child); 1447 pcicfgregs *cfg = &dinfo->cfg; 1448 1449 PCIB_WRITE_CONFIG(device_get_parent(dev), 1450 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1451} 1452 1453int 1454pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1455 size_t buflen) 1456{ 1457 struct pci_devinfo *dinfo; 1458 1459 dinfo = device_get_ivars(child); 1460 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1461 pci_get_function(child)); 1462 return (0); 1463} 1464 1465int 1466pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1467 size_t buflen) 1468{ 1469 struct pci_devinfo *dinfo; 1470 pcicfgregs *cfg; 1471 1472 dinfo = device_get_ivars(child); 1473 cfg = &dinfo->cfg; 1474 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1475 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1476 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1477 cfg->progif); 1478 return (0); 1479} 1480 1481int 1482pci_assign_interrupt_method(device_t dev, device_t child) 1483{ 1484 struct pci_devinfo *dinfo = device_get_ivars(child); 1485 pcicfgregs *cfg = &dinfo->cfg; 1486 1487 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1488 cfg->intpin)); 1489} 1490 1491static int 1492pci_modevent(module_t mod, int what, void *arg) 1493{ 1494 static dev_t pci_cdev; 1495 1496 switch (what) { 1497 case MOD_LOAD: 1498 STAILQ_INIT(&pci_devq); 1499 pci_generation = 0; 1500 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1501 "pci"); 1502 pci_load_vendor_data(); 1503 break; 1504 1505 case MOD_UNLOAD: 1506 destroy_dev(pci_cdev); 1507 break; 1508 } 1509 1510 return (0); 1511} 1512 1513int 1514pci_resume(device_t dev) 1515{ 1516 int numdevs; 1517 int i; 1518 device_t *children; 1519 device_t child; 1520 struct pci_devinfo *dinfo; 1521 pcicfgregs *cfg; 1522 1523 device_get_children(dev, &children, &numdevs); 1524 1525 for (i = 0; i < numdevs; i++) { 1526 child = children[i]; 1527 1528 dinfo = device_get_ivars(child); 1529 cfg = &dinfo->cfg; 1530 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1531 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1532 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1533 pci_write_config(child, PCIR_INTLINE, 1534 cfg->intline, 1); 1535 } 1536 } 1537 } 1538 1539 free(children, M_TEMP); 1540 1541 return (bus_generic_resume(dev)); 1542} 1543 1544