pci.c revision 116104
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 116104 2003-06-09 18:08:46Z jhb $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static u_int32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68 69static int pci_porten(device_t pcib, int b, int s, int f); 70static int pci_memen(device_t pcib, int b, int s, int f); 71static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 72 struct resource_list *rl); 73static void pci_add_resources(device_t pcib, device_t dev); 74static int pci_probe(device_t dev); 75static int pci_attach(device_t dev); 76static void pci_load_vendor_data(void); 77static int pci_describe_parse_line(char **ptr, int *vendor, 78 int *device, char **desc); 79static char *pci_describe_device(device_t dev); 80static int pci_modevent(module_t mod, int what, void *arg); 81static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 82 pcicfgregs *cfg); 83static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 84 85static device_method_t pci_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, pci_probe), 88 DEVMETHOD(device_attach, pci_attach), 89 DEVMETHOD(device_shutdown, bus_generic_shutdown), 90 DEVMETHOD(device_suspend, bus_generic_suspend), 91 DEVMETHOD(device_resume, bus_generic_resume), 92 93 /* Bus interface */ 94 DEVMETHOD(bus_print_child, pci_print_child), 95 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 96 DEVMETHOD(bus_read_ivar, pci_read_ivar), 97 DEVMETHOD(bus_write_ivar, pci_write_ivar), 98 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 99 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 100 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 101 102 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 103 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 104 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 105 DEVMETHOD(bus_delete_resource, pci_delete_resource), 106 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 107 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 108 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 109 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 110 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 111 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 112 113 /* PCI interface */ 114 DEVMETHOD(pci_read_config, pci_read_config_method), 115 DEVMETHOD(pci_write_config, pci_write_config_method), 116 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 117 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 118 DEVMETHOD(pci_enable_io, pci_enable_io_method), 119 DEVMETHOD(pci_disable_io, pci_disable_io_method), 120 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 121 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 122 123 { 0, 0 } 124}; 125 126static driver_t pci_driver = { 127 "pci", 128 pci_methods, 129 0, /* no softc */ 130}; 131 132devclass_t pci_devclass; 133DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 134MODULE_VERSION(pci, 1); 135 136static char *pci_vendordata; 137static size_t pci_vendordata_size; 138 139 140struct pci_quirk { 141 u_int32_t devid; /* Vendor/device of the card */ 142 int type; 143#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 144 int arg1; 145 int arg2; 146}; 147 148struct pci_quirk pci_quirks[] = { 149 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 150 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 151 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 153 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 154 155 { 0 } 156}; 157 158/* map register information */ 159#define PCI_MAPMEM 0x01 /* memory map */ 160#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 161#define PCI_MAPPORT 0x04 /* port map */ 162 163struct devlist pci_devq; 164u_int32_t pci_generation; 165u_int32_t pci_numdevs = 0; 166 167/* sysctl vars */ 168SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 169 170static int pci_enable_io_modes = 1; 171TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 172SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 173 &pci_enable_io_modes, 1, 174 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 175enable these bits correctly. We'd like to do this all the time, but there\n\ 176are some peripherals that this causes problems with."); 177 178/* Find a device_t by bus/slot/function */ 179 180device_t 181pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func) 182{ 183 struct pci_devinfo *dinfo; 184 185 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 186 if ((dinfo->cfg.bus == bus) && 187 (dinfo->cfg.slot == slot) && 188 (dinfo->cfg.func == func)) { 189 return (dinfo->cfg.dev); 190 } 191 } 192 193 return (NULL); 194} 195 196/* Find a device_t by vendor/device ID */ 197 198device_t 199pci_find_device(u_int16_t vendor, u_int16_t device) 200{ 201 struct pci_devinfo *dinfo; 202 203 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 204 if ((dinfo->cfg.vendor == vendor) && 205 (dinfo->cfg.device == device)) { 206 return (dinfo->cfg.dev); 207 } 208 } 209 210 return (NULL); 211} 212 213/* return base address of memory or port map */ 214 215static u_int32_t 216pci_mapbase(unsigned mapreg) 217{ 218 int mask = 0x03; 219 if ((mapreg & 0x01) == 0) 220 mask = 0x0f; 221 return (mapreg & ~mask); 222} 223 224/* return map type of memory or port map */ 225 226static int 227pci_maptype(unsigned mapreg) 228{ 229 static u_int8_t maptype[0x10] = { 230 PCI_MAPMEM, PCI_MAPPORT, 231 PCI_MAPMEM, 0, 232 PCI_MAPMEM, PCI_MAPPORT, 233 0, 0, 234 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 235 PCI_MAPMEM|PCI_MAPMEMP, 0, 236 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 237 0, 0, 238 }; 239 240 return maptype[mapreg & 0x0f]; 241} 242 243/* return log2 of map size decoded for memory or port map */ 244 245static int 246pci_mapsize(unsigned testval) 247{ 248 int ln2size; 249 250 testval = pci_mapbase(testval); 251 ln2size = 0; 252 if (testval != 0) { 253 while ((testval & 1) == 0) 254 { 255 ln2size++; 256 testval >>= 1; 257 } 258 } 259 return (ln2size); 260} 261 262/* return log2 of address range supported by map register */ 263 264static int 265pci_maprange(unsigned mapreg) 266{ 267 int ln2range = 0; 268 switch (mapreg & 0x07) { 269 case 0x00: 270 case 0x01: 271 case 0x05: 272 ln2range = 32; 273 break; 274 case 0x02: 275 ln2range = 20; 276 break; 277 case 0x04: 278 ln2range = 64; 279 break; 280 } 281 return (ln2range); 282} 283 284/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 285 286static void 287pci_fixancient(pcicfgregs *cfg) 288{ 289 if (cfg->hdrtype != 0) 290 return; 291 292 /* PCI to PCI bridges use header type 1 */ 293 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 294 cfg->hdrtype = 1; 295} 296 297/* extract header type specific config data */ 298 299static void 300pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 301{ 302#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 303 switch (cfg->hdrtype) { 304 case 0: 305 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 306 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 307 cfg->nummaps = PCI_MAXMAPS_0; 308 break; 309 case 1: 310 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 311 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 312 cfg->nummaps = PCI_MAXMAPS_1; 313 break; 314 case 2: 315 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 316 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 317 cfg->nummaps = PCI_MAXMAPS_2; 318 break; 319 } 320#undef REG 321} 322 323/* read configuration header into pcicfgregs structure */ 324 325struct pci_devinfo * 326pci_read_device(device_t pcib, int b, int s, int f, size_t size) 327{ 328#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 329 pcicfgregs *cfg = NULL; 330 struct pci_devinfo *devlist_entry; 331 struct devlist *devlist_head; 332 333 devlist_head = &pci_devq; 334 335 devlist_entry = NULL; 336 337 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 338 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 339 if (devlist_entry == NULL) 340 return (NULL); 341 342 cfg = &devlist_entry->cfg; 343 344 cfg->bus = b; 345 cfg->slot = s; 346 cfg->func = f; 347 cfg->vendor = REG(PCIR_VENDOR, 2); 348 cfg->device = REG(PCIR_DEVICE, 2); 349 cfg->cmdreg = REG(PCIR_COMMAND, 2); 350 cfg->statreg = REG(PCIR_STATUS, 2); 351 cfg->baseclass = REG(PCIR_CLASS, 1); 352 cfg->subclass = REG(PCIR_SUBCLASS, 1); 353 cfg->progif = REG(PCIR_PROGIF, 1); 354 cfg->revid = REG(PCIR_REVID, 1); 355 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 356 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 357 cfg->lattimer = REG(PCIR_LATTIMER, 1); 358 cfg->intpin = REG(PCIR_INTPIN, 1); 359 cfg->intline = REG(PCIR_INTLINE, 1); 360 361 cfg->mingnt = REG(PCIR_MINGNT, 1); 362 cfg->maxlat = REG(PCIR_MAXLAT, 1); 363 364 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 365 cfg->hdrtype &= ~PCIM_MFDEV; 366 367 pci_fixancient(cfg); 368 pci_hdrtypedata(pcib, b, s, f, cfg); 369 370 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 371 pci_read_extcap(pcib, cfg); 372 373 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 374 375 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 376 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 377 devlist_entry->conf.pc_sel.pc_func = cfg->func; 378 devlist_entry->conf.pc_hdr = cfg->hdrtype; 379 380 devlist_entry->conf.pc_subvendor = cfg->subvendor; 381 devlist_entry->conf.pc_subdevice = cfg->subdevice; 382 devlist_entry->conf.pc_vendor = cfg->vendor; 383 devlist_entry->conf.pc_device = cfg->device; 384 385 devlist_entry->conf.pc_class = cfg->baseclass; 386 devlist_entry->conf.pc_subclass = cfg->subclass; 387 devlist_entry->conf.pc_progif = cfg->progif; 388 devlist_entry->conf.pc_revid = cfg->revid; 389 390 pci_numdevs++; 391 pci_generation++; 392 } 393 return (devlist_entry); 394#undef REG 395} 396 397static void 398pci_read_extcap(device_t pcib, pcicfgregs *cfg) 399{ 400#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 401 int ptr, nextptr, ptrptr; 402 403 switch (cfg->hdrtype) { 404 case 0: 405 ptrptr = 0x34; 406 break; 407 case 2: 408 ptrptr = 0x14; 409 break; 410 default: 411 return; /* no extended capabilities support */ 412 } 413 nextptr = REG(ptrptr, 1); /* sanity check? */ 414 415 /* 416 * Read capability entries. 417 */ 418 while (nextptr != 0) { 419 /* Sanity check */ 420 if (nextptr > 255) { 421 printf("illegal PCI extended capability offset %d\n", 422 nextptr); 423 return; 424 } 425 /* Find the next entry */ 426 ptr = nextptr; 427 nextptr = REG(ptr + 1, 1); 428 429 /* Process this entry */ 430 switch (REG(ptr, 1)) { 431 case 0x01: /* PCI power management */ 432 if (cfg->pp_cap == 0) { 433 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 434 cfg->pp_status = ptr + PCIR_POWER_STATUS; 435 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 436 if ((nextptr - ptr) > PCIR_POWER_DATA) 437 cfg->pp_data = ptr + PCIR_POWER_DATA; 438 } 439 break; 440 default: 441 break; 442 } 443 } 444#undef REG 445} 446 447/* free pcicfgregs structure and all depending data structures */ 448 449int 450pci_freecfg(struct pci_devinfo *dinfo) 451{ 452 struct devlist *devlist_head; 453 454 devlist_head = &pci_devq; 455 456 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 457 free(dinfo, M_DEVBUF); 458 459 /* increment the generation count */ 460 pci_generation++; 461 462 /* we're losing one device */ 463 pci_numdevs--; 464 return (0); 465} 466 467/* 468 * PCI power manangement 469 */ 470int 471pci_set_powerstate_method(device_t dev, device_t child, int state) 472{ 473 struct pci_devinfo *dinfo = device_get_ivars(child); 474 pcicfgregs *cfg = &dinfo->cfg; 475 u_int16_t status; 476 int result; 477 478 if (cfg->pp_cap != 0) { 479 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 480 result = 0; 481 switch (state) { 482 case PCI_POWERSTATE_D0: 483 status |= PCIM_PSTAT_D0; 484 break; 485 case PCI_POWERSTATE_D1: 486 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 487 status |= PCIM_PSTAT_D1; 488 } else { 489 result = EOPNOTSUPP; 490 } 491 break; 492 case PCI_POWERSTATE_D2: 493 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 494 status |= PCIM_PSTAT_D2; 495 } else { 496 result = EOPNOTSUPP; 497 } 498 break; 499 case PCI_POWERSTATE_D3: 500 status |= PCIM_PSTAT_D3; 501 break; 502 default: 503 result = EINVAL; 504 } 505 if (result == 0) 506 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 507 } else { 508 result = ENXIO; 509 } 510 return(result); 511} 512 513int 514pci_get_powerstate_method(device_t dev, device_t child) 515{ 516 struct pci_devinfo *dinfo = device_get_ivars(child); 517 pcicfgregs *cfg = &dinfo->cfg; 518 u_int16_t status; 519 int result; 520 521 if (cfg->pp_cap != 0) { 522 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 523 switch (status & PCIM_PSTAT_DMASK) { 524 case PCIM_PSTAT_D0: 525 result = PCI_POWERSTATE_D0; 526 break; 527 case PCIM_PSTAT_D1: 528 result = PCI_POWERSTATE_D1; 529 break; 530 case PCIM_PSTAT_D2: 531 result = PCI_POWERSTATE_D2; 532 break; 533 case PCIM_PSTAT_D3: 534 result = PCI_POWERSTATE_D3; 535 break; 536 default: 537 result = PCI_POWERSTATE_UNKNOWN; 538 break; 539 } 540 } else { 541 /* No support, device is always at D0 */ 542 result = PCI_POWERSTATE_D0; 543 } 544 return(result); 545} 546 547/* 548 * Some convenience functions for PCI device drivers. 549 */ 550 551static __inline void 552pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 553{ 554 u_int16_t command; 555 556 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 557 command |= bit; 558 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 559} 560 561static __inline void 562pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 563{ 564 u_int16_t command; 565 566 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 567 command &= ~bit; 568 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 569} 570 571int 572pci_enable_busmaster_method(device_t dev, device_t child) 573{ 574 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 575 return (0); 576} 577 578int 579pci_disable_busmaster_method(device_t dev, device_t child) 580{ 581 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 582 return (0); 583} 584 585int 586pci_enable_io_method(device_t dev, device_t child, int space) 587{ 588 u_int16_t command; 589 u_int16_t bit; 590 char *error; 591 592 bit = 0; 593 error = NULL; 594 595 switch(space) { 596 case SYS_RES_IOPORT: 597 bit = PCIM_CMD_PORTEN; 598 error = "port"; 599 break; 600 case SYS_RES_MEMORY: 601 bit = PCIM_CMD_MEMEN; 602 error = "memory"; 603 break; 604 default: 605 return (EINVAL); 606 } 607 pci_set_command_bit(dev, child, bit); 608 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 609 if (command & bit) 610 return (0); 611 device_printf(child, "failed to enable %s mapping!\n", error); 612 return (ENXIO); 613} 614 615int 616pci_disable_io_method(device_t dev, device_t child, int space) 617{ 618 u_int16_t command; 619 u_int16_t bit; 620 char *error; 621 622 bit = 0; 623 error = NULL; 624 625 switch(space) { 626 case SYS_RES_IOPORT: 627 bit = PCIM_CMD_PORTEN; 628 error = "port"; 629 break; 630 case SYS_RES_MEMORY: 631 bit = PCIM_CMD_MEMEN; 632 error = "memory"; 633 break; 634 default: 635 return (EINVAL); 636 } 637 pci_clear_command_bit(dev, child, bit); 638 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 639 if (command & bit) { 640 device_printf(child, "failed to disable %s mapping!\n", error); 641 return (ENXIO); 642 } 643 return (0); 644} 645 646/* 647 * New style pci driver. Parent device is either a pci-host-bridge or a 648 * pci-pci-bridge. Both kinds are represented by instances of pcib. 649 */ 650 651void 652pci_print_verbose(struct pci_devinfo *dinfo) 653{ 654 if (bootverbose) { 655 pcicfgregs *cfg = &dinfo->cfg; 656 657 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 658 cfg->vendor, cfg->device, cfg->revid); 659 printf("\tbus=%d, slot=%d, func=%d\n", 660 cfg->bus, cfg->slot, cfg->func); 661 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 662 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 663 cfg->mfdev); 664 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 665 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 666 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 667 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 668 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 669 if (cfg->intpin > 0) 670 printf("\tintpin=%c, irq=%d\n", 671 cfg->intpin +'a' -1, cfg->intline); 672 if (cfg->pp_cap) { 673 u_int16_t status; 674 675 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 676 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 677 cfg->pp_cap & PCIM_PCAP_SPEC, 678 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 679 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 680 status & PCIM_PSTAT_DMASK); 681 } 682 } 683} 684 685static int 686pci_porten(device_t pcib, int b, int s, int f) 687{ 688 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 689 & PCIM_CMD_PORTEN) != 0; 690} 691 692static int 693pci_memen(device_t pcib, int b, int s, int f) 694{ 695 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 696 & PCIM_CMD_MEMEN) != 0; 697} 698 699/* 700 * Add a resource based on a pci map register. Return 1 if the map 701 * register is a 32bit map register or 2 if it is a 64bit register. 702 */ 703static int 704pci_add_map(device_t pcib, int b, int s, int f, int reg, 705 struct resource_list *rl) 706{ 707 u_int32_t map; 708 u_int64_t base; 709 u_int8_t ln2size; 710 u_int8_t ln2range; 711 u_int32_t testval; 712 u_int16_t cmd; 713 int type; 714 715 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 716 717 if (map == 0 || map == 0xffffffff) 718 return (1); /* skip invalid entry */ 719 720 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 721 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 722 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 723 724 base = pci_mapbase(map); 725 if (pci_maptype(map) & PCI_MAPMEM) 726 type = SYS_RES_MEMORY; 727 else 728 type = SYS_RES_IOPORT; 729 ln2size = pci_mapsize(testval); 730 ln2range = pci_maprange(testval); 731 if (ln2range == 64) { 732 /* Read the other half of a 64bit map register */ 733 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 734 } 735 736 if (bootverbose) { 737 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 738 reg, pci_maptype(map), ln2range, 739 (unsigned int) base, ln2size); 740 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 741 printf(", port disabled\n"); 742 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 743 printf(", memory disabled\n"); 744 else 745 printf(", enabled\n"); 746 } 747 748 /* 749 * This code theoretically does the right thing, but has 750 * undesirable side effects in some cases where 751 * peripherals respond oddly to having these bits 752 * enabled. Leave them alone by default. 753 */ 754 if (pci_enable_io_modes) { 755 /* Turn on resources that have been left off by a lazy BIOS */ 756 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 757 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 758 cmd |= PCIM_CMD_PORTEN; 759 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 760 } 761 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 762 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 763 cmd |= PCIM_CMD_MEMEN; 764 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 765 } 766 } else { 767 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 768 return (1); 769 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 770 return (1); 771 } 772 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1, 773 (1 << ln2size)); 774 775 return ((ln2range == 64) ? 2 : 1); 776} 777 778static void 779pci_add_resources(device_t pcib, device_t dev) 780{ 781 struct pci_devinfo *dinfo = device_get_ivars(dev); 782 pcicfgregs *cfg = &dinfo->cfg; 783 struct resource_list *rl = &dinfo->resources; 784 struct pci_quirk *q; 785 int b, i, irq, f, s; 786 787 b = cfg->bus; 788 s = cfg->slot; 789 f = cfg->func; 790 for (i = 0; i < cfg->nummaps;) { 791 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 792 } 793 794 for (q = &pci_quirks[0]; q->devid; q++) { 795 if (q->devid == ((cfg->device << 16) | cfg->vendor) 796 && q->type == PCI_QUIRK_MAP_REG) 797 pci_add_map(pcib, b, s, f, q->arg1, rl); 798 } 799 800 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 801#if defined(__ia64__) || (defined(__i386__) && !defined(SMP) && !defined(PC98)) 802 /* 803 * Try to re-route interrupts. Sometimes the BIOS or 804 * firmware may leave bogus values in these registers. 805 * If the re-route fails, then just stick with what we 806 * have. 807 */ 808 irq = PCIB_ROUTE_INTERRUPT(pcib, dev, cfg->intpin); 809 if (PCI_INTERRUPT_VALID(irq)) { 810 pci_write_config(dev, PCIR_INTLINE, irq, 1); 811 cfg->intline = irq; 812 } else 813#endif 814 irq = cfg->intline; 815 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 816 } 817} 818 819void 820pci_add_children(device_t dev, int busno, size_t dinfo_size) 821{ 822 device_t pcib = device_get_parent(dev); 823 struct pci_devinfo *dinfo; 824 int maxslots; 825 int s, f, pcifunchigh; 826 827 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 828 ("dinfo_size too small")); 829 maxslots = PCIB_MAXSLOTS(pcib); 830 for (s = 0; s <= maxslots; s++) { 831 pcifunchigh = 0; 832 for (f = 0; f <= pcifunchigh; f++) { 833 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 834 if (dinfo != NULL) { 835 if (dinfo->cfg.mfdev) 836 pcifunchigh = PCI_FUNCMAX; 837 pci_add_child(dev, dinfo); 838 } 839 } 840 } 841} 842 843void 844pci_add_child(device_t bus, struct pci_devinfo *dinfo) 845{ 846 device_t pcib; 847 848 pcib = device_get_parent(bus); 849 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 850 device_set_ivars(dinfo->cfg.dev, dinfo); 851 pci_add_resources(pcib, dinfo->cfg.dev); 852 pci_print_verbose(dinfo); 853} 854 855static int 856pci_probe(device_t dev) 857{ 858 859 device_set_desc(dev, "PCI bus"); 860 861 /* Allow other subclasses to override this driver. */ 862 return (-1000); 863} 864 865static int 866pci_attach(device_t dev) 867{ 868 int busno; 869 870 /* 871 * Since there can be multiple independantly numbered PCI 872 * busses on some large alpha systems, we can't use the unit 873 * number to decide what bus we are probing. We ask the parent 874 * pcib what our bus number is. 875 */ 876 busno = pcib_get_bus(dev); 877 if (bootverbose) 878 device_printf(dev, "physical bus=%d\n", busno); 879 880 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 881 882 return (bus_generic_attach(dev)); 883} 884 885static void 886pci_load_vendor_data(void) 887{ 888 caddr_t vendordata, info; 889 890 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 891 info = preload_search_info(vendordata, MODINFO_ADDR); 892 pci_vendordata = *(char **)info; 893 info = preload_search_info(vendordata, MODINFO_SIZE); 894 pci_vendordata_size = *(size_t *)info; 895 /* terminate the database */ 896 pci_vendordata[pci_vendordata_size] = '\n'; 897 } 898} 899 900int 901pci_print_child(device_t dev, device_t child) 902{ 903 struct pci_devinfo *dinfo; 904 struct resource_list *rl; 905 int retval = 0; 906 907 dinfo = device_get_ivars(child); 908 rl = &dinfo->resources; 909 910 retval += bus_print_child_header(dev, child); 911 912 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 913 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 914 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 915 if (device_get_flags(dev)) 916 retval += printf(" flags %#x", device_get_flags(dev)); 917 918 retval += printf(" at device %d.%d", pci_get_slot(child), 919 pci_get_function(child)); 920 921 retval += bus_print_child_footer(dev, child); 922 923 return (retval); 924} 925 926static struct 927{ 928 int class; 929 int subclass; 930 char *desc; 931} pci_nomatch_tab[] = { 932 {PCIC_OLD, -1, "old"}, 933 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 934 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 935 {PCIC_STORAGE, -1, "mass storage"}, 936 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 937 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 938 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 939 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 940 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 941 {PCIC_NETWORK, -1, "network"}, 942 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 943 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 944 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 945 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 946 {PCIC_DISPLAY, -1, "display"}, 947 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 948 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 949 {PCIC_MULTIMEDIA, -1, "multimedia"}, 950 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 951 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 952 {PCIC_MEMORY, -1, "memory"}, 953 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 954 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 955 {PCIC_BRIDGE, -1, "bridge"}, 956 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 957 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 958 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 959 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 960 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 961 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 962 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 963 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 964 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 965 {PCIC_SIMPLECOMM, -1, "simple comms"}, 966 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 967 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 968 {PCIC_BASEPERIPH, -1, "base peripheral"}, 969 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 970 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 971 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 972 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 973 {PCIC_INPUTDEV, -1, "input device"}, 974 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 975 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 976 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 977 {PCIC_DOCKING, -1, "docking station"}, 978 {PCIC_PROCESSOR, -1, "processor"}, 979 {PCIC_SERIALBUS, -1, "serial bus"}, 980 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 981 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 982 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 983 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 984 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 985 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 986 {0, 0, NULL} 987}; 988 989void 990pci_probe_nomatch(device_t dev, device_t child) 991{ 992 int i; 993 char *cp, *scp, *device; 994 995 /* 996 * Look for a listing for this device in a loaded device database. 997 */ 998 if ((device = pci_describe_device(child)) != NULL) { 999 device_printf(dev, "<%s>", device); 1000 free(device, M_DEVBUF); 1001 } else { 1002 /* 1003 * Scan the class/subclass descriptions for a general 1004 * description. 1005 */ 1006 cp = "unknown"; 1007 scp = NULL; 1008 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1009 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1010 if (pci_nomatch_tab[i].subclass == -1) { 1011 cp = pci_nomatch_tab[i].desc; 1012 } else if (pci_nomatch_tab[i].subclass == 1013 pci_get_subclass(child)) { 1014 scp = pci_nomatch_tab[i].desc; 1015 } 1016 } 1017 } 1018 device_printf(dev, "<%s%s%s>", 1019 cp ? cp : "", 1020 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1021 scp ? scp : ""); 1022 } 1023 printf(" at device %d.%d (no driver attached)\n", 1024 pci_get_slot(child), pci_get_function(child)); 1025 return; 1026} 1027 1028/* 1029 * Parse the PCI device database, if loaded, and return a pointer to a 1030 * description of the device. 1031 * 1032 * The database is flat text formatted as follows: 1033 * 1034 * Any line not in a valid format is ignored. 1035 * Lines are terminated with newline '\n' characters. 1036 * 1037 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1038 * the vendor name. 1039 * 1040 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1041 * - devices cannot be listed without a corresponding VENDOR line. 1042 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1043 * another TAB, then the device name. 1044 */ 1045 1046/* 1047 * Assuming (ptr) points to the beginning of a line in the database, 1048 * return the vendor or device and description of the next entry. 1049 * The value of (vendor) or (device) inappropriate for the entry type 1050 * is set to -1. Returns nonzero at the end of the database. 1051 * 1052 * Note that this is slightly unrobust in the face of corrupt data; 1053 * we attempt to safeguard against this by spamming the end of the 1054 * database with a newline when we initialise. 1055 */ 1056static int 1057pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1058{ 1059 char *cp = *ptr; 1060 int left; 1061 1062 *device = -1; 1063 *vendor = -1; 1064 **desc = '\0'; 1065 for (;;) { 1066 left = pci_vendordata_size - (cp - pci_vendordata); 1067 if (left <= 0) { 1068 *ptr = cp; 1069 return(1); 1070 } 1071 1072 /* vendor entry? */ 1073 if (*cp != '\t' && 1074 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1075 break; 1076 /* device entry? */ 1077 if (*cp == '\t' && 1078 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1079 break; 1080 1081 /* skip to next line */ 1082 while (*cp != '\n' && left > 0) { 1083 cp++; 1084 left--; 1085 } 1086 if (*cp == '\n') { 1087 cp++; 1088 left--; 1089 } 1090 } 1091 /* skip to next line */ 1092 while (*cp != '\n' && left > 0) { 1093 cp++; 1094 left--; 1095 } 1096 if (*cp == '\n' && left > 0) 1097 cp++; 1098 *ptr = cp; 1099 return(0); 1100} 1101 1102static char * 1103pci_describe_device(device_t dev) 1104{ 1105 int vendor, device; 1106 char *desc, *vp, *dp, *line; 1107 1108 desc = vp = dp = NULL; 1109 1110 /* 1111 * If we have no vendor data, we can't do anything. 1112 */ 1113 if (pci_vendordata == NULL) 1114 goto out; 1115 1116 /* 1117 * Scan the vendor data looking for this device 1118 */ 1119 line = pci_vendordata; 1120 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1121 goto out; 1122 for (;;) { 1123 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1124 goto out; 1125 if (vendor == pci_get_vendor(dev)) 1126 break; 1127 } 1128 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1129 goto out; 1130 for (;;) { 1131 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1132 *dp = 0; 1133 break; 1134 } 1135 if (vendor != -1) { 1136 *dp = 0; 1137 break; 1138 } 1139 if (device == pci_get_device(dev)) 1140 break; 1141 } 1142 if (dp[0] == '\0') 1143 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1144 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1145 NULL) 1146 sprintf(desc, "%s, %s", vp, dp); 1147 out: 1148 if (vp != NULL) 1149 free(vp, M_DEVBUF); 1150 if (dp != NULL) 1151 free(dp, M_DEVBUF); 1152 return(desc); 1153} 1154 1155int 1156pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1157{ 1158 struct pci_devinfo *dinfo; 1159 pcicfgregs *cfg; 1160 1161 dinfo = device_get_ivars(child); 1162 cfg = &dinfo->cfg; 1163 1164 switch (which) { 1165 case PCI_IVAR_ETHADDR: 1166 /* 1167 * The generic accessor doesn't deal with failure, so 1168 * we set the return value, then return an error. 1169 */ 1170 *((u_int8_t **) result) = NULL; 1171 return (EINVAL); 1172 case PCI_IVAR_SUBVENDOR: 1173 *result = cfg->subvendor; 1174 break; 1175 case PCI_IVAR_SUBDEVICE: 1176 *result = cfg->subdevice; 1177 break; 1178 case PCI_IVAR_VENDOR: 1179 *result = cfg->vendor; 1180 break; 1181 case PCI_IVAR_DEVICE: 1182 *result = cfg->device; 1183 break; 1184 case PCI_IVAR_DEVID: 1185 *result = (cfg->device << 16) | cfg->vendor; 1186 break; 1187 case PCI_IVAR_CLASS: 1188 *result = cfg->baseclass; 1189 break; 1190 case PCI_IVAR_SUBCLASS: 1191 *result = cfg->subclass; 1192 break; 1193 case PCI_IVAR_PROGIF: 1194 *result = cfg->progif; 1195 break; 1196 case PCI_IVAR_REVID: 1197 *result = cfg->revid; 1198 break; 1199 case PCI_IVAR_INTPIN: 1200 *result = cfg->intpin; 1201 break; 1202 case PCI_IVAR_IRQ: 1203 *result = cfg->intline; 1204 break; 1205 case PCI_IVAR_BUS: 1206 *result = cfg->bus; 1207 break; 1208 case PCI_IVAR_SLOT: 1209 *result = cfg->slot; 1210 break; 1211 case PCI_IVAR_FUNCTION: 1212 *result = cfg->func; 1213 break; 1214 default: 1215 return (ENOENT); 1216 } 1217 return (0); 1218} 1219 1220int 1221pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1222{ 1223 struct pci_devinfo *dinfo; 1224 1225 dinfo = device_get_ivars(child); 1226 1227 switch (which) { 1228 case PCI_IVAR_ETHADDR: 1229 case PCI_IVAR_SUBVENDOR: 1230 case PCI_IVAR_SUBDEVICE: 1231 case PCI_IVAR_VENDOR: 1232 case PCI_IVAR_DEVICE: 1233 case PCI_IVAR_DEVID: 1234 case PCI_IVAR_CLASS: 1235 case PCI_IVAR_SUBCLASS: 1236 case PCI_IVAR_PROGIF: 1237 case PCI_IVAR_REVID: 1238 case PCI_IVAR_INTPIN: 1239 case PCI_IVAR_IRQ: 1240 case PCI_IVAR_BUS: 1241 case PCI_IVAR_SLOT: 1242 case PCI_IVAR_FUNCTION: 1243 return (EINVAL); /* disallow for now */ 1244 1245 default: 1246 return (ENOENT); 1247 } 1248} 1249 1250 1251#include "opt_ddb.h" 1252#ifdef DDB 1253#include <ddb/ddb.h> 1254#include <sys/cons.h> 1255 1256/* 1257 * List resources based on pci map registers, used for within ddb 1258 */ 1259 1260DB_SHOW_COMMAND(pciregs, db_pci_dump) 1261{ 1262 struct pci_devinfo *dinfo; 1263 struct devlist *devlist_head; 1264 struct pci_conf *p; 1265 const char *name; 1266 int i, error, none_count, nl; 1267 1268 none_count = 0; 1269 nl = 0; 1270 /* get the head of the device queue */ 1271 devlist_head = &pci_devq; 1272 1273 /* 1274 * Go through the list of devices and print out devices 1275 */ 1276 for (error = 0, i = 0, 1277 dinfo = STAILQ_FIRST(devlist_head); 1278 (dinfo != NULL) && (error == 0) && (i < pci_numdevs); 1279 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1280 1281 /* Populate pd_name and pd_unit */ 1282 name = NULL; 1283 if (dinfo->cfg.dev) 1284 name = device_get_name(dinfo->cfg.dev); 1285 1286 p = &dinfo->conf; 1287 /* 1288 * XXX just take 20 for now... 1289 */ 1290 if (nl++ == 20) { 1291 int c; 1292 1293 db_printf("--More--"); 1294 c = cngetc(); 1295 db_printf("\r"); 1296 /* 1297 * A whole screenfull or just one line? 1298 */ 1299 switch (c) { 1300 case '\n': /* just one line */ 1301 nl = 20; 1302 break; 1303 case ' ': 1304 nl = 0; /* another screenfull */ 1305 break; 1306 default: /* exit */ 1307 db_printf("\n"); 1308 return; 1309 } 1310 } 1311 1312 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1313 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1314 (name && *name) ? name : "none", 1315 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1316 none_count++, 1317 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1318 p->pc_sel.pc_func, (p->pc_class << 16) | 1319 (p->pc_subclass << 8) | p->pc_progif, 1320 (p->pc_subdevice << 16) | p->pc_subvendor, 1321 (p->pc_device << 16) | p->pc_vendor, 1322 p->pc_revid, p->pc_hdr); 1323 } 1324} 1325#endif /* DDB */ 1326 1327struct resource * 1328pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1329 u_long start, u_long end, u_long count, u_int flags) 1330{ 1331 struct pci_devinfo *dinfo = device_get_ivars(child); 1332 struct resource_list *rl = &dinfo->resources; 1333 pcicfgregs *cfg = &dinfo->cfg; 1334 1335 /* 1336 * Perform lazy resource allocation 1337 * 1338 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1339 */ 1340 if (device_get_parent(child) == dev) { 1341 switch (type) { 1342 case SYS_RES_IRQ: 1343 /* 1344 * If the child device doesn't have an 1345 * interrupt routed and is deserving of an 1346 * interrupt, try to assign it one. 1347 */ 1348 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1349 (cfg->intpin != 0)) { 1350 cfg->intline = PCIB_ROUTE_INTERRUPT( 1351 device_get_parent(dev), child, cfg->intpin); 1352 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1353 pci_write_config(child, PCIR_INTLINE, 1354 cfg->intline, 1); 1355 resource_list_add(rl, SYS_RES_IRQ, 0, 1356 cfg->intline, cfg->intline, 1); 1357 } 1358 } 1359 break; 1360 case SYS_RES_IOPORT: 1361 case SYS_RES_MEMORY: 1362 /* 1363 * Enable the I/O mode. We should also be allocating 1364 * resources too. XXX 1365 */ 1366 if (PCI_ENABLE_IO(dev, child, type)) 1367 return (NULL); 1368 break; 1369 } 1370 } 1371 1372 return (resource_list_alloc(rl, dev, child, type, rid, 1373 start, end, count, flags)); 1374} 1375 1376void 1377pci_delete_resource(device_t dev, device_t child, int type, int rid) 1378{ 1379 struct pci_devinfo *dinfo; 1380 struct resource_list *rl; 1381 struct resource_list_entry *rle; 1382 1383 if (device_get_parent(child) != dev) 1384 return; 1385 1386 dinfo = device_get_ivars(child); 1387 rl = &dinfo->resources; 1388 rle = resource_list_find(rl, type, rid); 1389 if (rle) { 1390 if (rle->res) { 1391 if (rman_get_device(rle->res) != dev || 1392 rman_get_flags(rle->res) & RF_ACTIVE) { 1393 device_printf(dev, "delete_resource: " 1394 "Resource still owned by child, oops. " 1395 "(type=%d, rid=%d, addr=%lx)\n", 1396 rle->type, rle->rid, 1397 rman_get_start(rle->res)); 1398 return; 1399 } 1400 bus_release_resource(dev, type, rid, rle->res); 1401 } 1402 resource_list_delete(rl, type, rid); 1403 } 1404 /* 1405 * Why do we turn off the PCI configuration BAR when we delete a 1406 * resource? -- imp 1407 */ 1408 pci_write_config(child, rid, 0, 4); 1409 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1410} 1411 1412struct resource_list * 1413pci_get_resource_list (device_t dev, device_t child) 1414{ 1415 struct pci_devinfo * dinfo = device_get_ivars(child); 1416 struct resource_list * rl = &dinfo->resources; 1417 1418 if (!rl) 1419 return (NULL); 1420 1421 return (rl); 1422} 1423 1424u_int32_t 1425pci_read_config_method(device_t dev, device_t child, int reg, int width) 1426{ 1427 struct pci_devinfo *dinfo = device_get_ivars(child); 1428 pcicfgregs *cfg = &dinfo->cfg; 1429 1430 return (PCIB_READ_CONFIG(device_get_parent(dev), 1431 cfg->bus, cfg->slot, cfg->func, reg, width)); 1432} 1433 1434void 1435pci_write_config_method(device_t dev, device_t child, int reg, 1436 u_int32_t val, int width) 1437{ 1438 struct pci_devinfo *dinfo = device_get_ivars(child); 1439 pcicfgregs *cfg = &dinfo->cfg; 1440 1441 PCIB_WRITE_CONFIG(device_get_parent(dev), 1442 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1443} 1444 1445int 1446pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1447 size_t buflen) 1448{ 1449 struct pci_devinfo *dinfo; 1450 1451 dinfo = device_get_ivars(child); 1452 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1453 pci_get_function(child)); 1454 return (0); 1455} 1456 1457int 1458pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1459 size_t buflen) 1460{ 1461 struct pci_devinfo *dinfo; 1462 pcicfgregs *cfg; 1463 1464 dinfo = device_get_ivars(child); 1465 cfg = &dinfo->cfg; 1466 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1467 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1468 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1469 cfg->progif); 1470 return (0); 1471} 1472 1473static int 1474pci_modevent(module_t mod, int what, void *arg) 1475{ 1476 static dev_t pci_cdev; 1477 1478 switch (what) { 1479 case MOD_LOAD: 1480 STAILQ_INIT(&pci_devq); 1481 pci_generation = 0; 1482 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1483 "pci"); 1484 pci_load_vendor_data(); 1485 break; 1486 1487 case MOD_UNLOAD: 1488 destroy_dev(pci_cdev); 1489 break; 1490 } 1491 1492 return (0); 1493} 1494