pci.c revision 116031
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 116031 2003-06-08 11:18:35Z nyan $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static u_int32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68 69static int pci_porten(device_t pcib, int b, int s, int f); 70static int pci_memen(device_t pcib, int b, int s, int f); 71static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 72 struct resource_list *rl); 73static void pci_add_resources(device_t pcib, device_t dev); 74static int pci_probe(device_t dev); 75static int pci_attach(device_t dev); 76static void pci_load_vendor_data(void); 77static int pci_describe_parse_line(char **ptr, int *vendor, 78 int *device, char **desc); 79static char *pci_describe_device(device_t dev); 80static int pci_modevent(module_t mod, int what, void *arg); 81static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 82 pcicfgregs *cfg); 83static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 84 85static device_method_t pci_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, pci_probe), 88 DEVMETHOD(device_attach, pci_attach), 89 DEVMETHOD(device_shutdown, bus_generic_shutdown), 90 DEVMETHOD(device_suspend, bus_generic_suspend), 91 DEVMETHOD(device_resume, bus_generic_resume), 92 93 /* Bus interface */ 94 DEVMETHOD(bus_print_child, pci_print_child), 95 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 96 DEVMETHOD(bus_read_ivar, pci_read_ivar), 97 DEVMETHOD(bus_write_ivar, pci_write_ivar), 98 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 99 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 100 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 101 102 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 103 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 104 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 105 DEVMETHOD(bus_delete_resource, pci_delete_resource), 106 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 107 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 108 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 109 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 110 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 111 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 112 113 /* PCI interface */ 114 DEVMETHOD(pci_read_config, pci_read_config_method), 115 DEVMETHOD(pci_write_config, pci_write_config_method), 116 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 117 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 118 DEVMETHOD(pci_enable_io, pci_enable_io_method), 119 DEVMETHOD(pci_disable_io, pci_disable_io_method), 120 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 121 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 122 123 { 0, 0 } 124}; 125 126static driver_t pci_driver = { 127 "pci", 128 pci_methods, 129 0, /* no softc */ 130}; 131 132devclass_t pci_devclass; 133DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 134MODULE_VERSION(pci, 1); 135 136static char *pci_vendordata; 137static size_t pci_vendordata_size; 138 139 140struct pci_quirk { 141 u_int32_t devid; /* Vendor/device of the card */ 142 int type; 143#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 144 int arg1; 145 int arg2; 146}; 147 148struct pci_quirk pci_quirks[] = { 149 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 150 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 151 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 153 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 154 155 { 0 } 156}; 157 158/* map register information */ 159#define PCI_MAPMEM 0x01 /* memory map */ 160#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 161#define PCI_MAPPORT 0x04 /* port map */ 162 163struct devlist pci_devq; 164u_int32_t pci_generation; 165u_int32_t pci_numdevs = 0; 166 167/* sysctl vars */ 168SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 169 170static int pci_enable_io_modes = 1; 171TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 172SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 173 &pci_enable_io_modes, 1, 174 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 175enable these bits correctly. We'd like to do this all the time, but there\n\ 176are some peripherals that this causes problems with."); 177 178/* Find a device_t by bus/slot/function */ 179 180device_t 181pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func) 182{ 183 struct pci_devinfo *dinfo; 184 185 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 186 if ((dinfo->cfg.bus == bus) && 187 (dinfo->cfg.slot == slot) && 188 (dinfo->cfg.func == func)) { 189 return (dinfo->cfg.dev); 190 } 191 } 192 193 return (NULL); 194} 195 196/* Find a device_t by vendor/device ID */ 197 198device_t 199pci_find_device(u_int16_t vendor, u_int16_t device) 200{ 201 struct pci_devinfo *dinfo; 202 203 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 204 if ((dinfo->cfg.vendor == vendor) && 205 (dinfo->cfg.device == device)) { 206 return (dinfo->cfg.dev); 207 } 208 } 209 210 return (NULL); 211} 212 213/* return base address of memory or port map */ 214 215static u_int32_t 216pci_mapbase(unsigned mapreg) 217{ 218 int mask = 0x03; 219 if ((mapreg & 0x01) == 0) 220 mask = 0x0f; 221 return (mapreg & ~mask); 222} 223 224/* return map type of memory or port map */ 225 226static int 227pci_maptype(unsigned mapreg) 228{ 229 static u_int8_t maptype[0x10] = { 230 PCI_MAPMEM, PCI_MAPPORT, 231 PCI_MAPMEM, 0, 232 PCI_MAPMEM, PCI_MAPPORT, 233 0, 0, 234 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 235 PCI_MAPMEM|PCI_MAPMEMP, 0, 236 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 237 0, 0, 238 }; 239 240 return maptype[mapreg & 0x0f]; 241} 242 243/* return log2 of map size decoded for memory or port map */ 244 245static int 246pci_mapsize(unsigned testval) 247{ 248 int ln2size; 249 250 testval = pci_mapbase(testval); 251 ln2size = 0; 252 if (testval != 0) { 253 while ((testval & 1) == 0) 254 { 255 ln2size++; 256 testval >>= 1; 257 } 258 } 259 return (ln2size); 260} 261 262/* return log2 of address range supported by map register */ 263 264static int 265pci_maprange(unsigned mapreg) 266{ 267 int ln2range = 0; 268 switch (mapreg & 0x07) { 269 case 0x00: 270 case 0x01: 271 case 0x05: 272 ln2range = 32; 273 break; 274 case 0x02: 275 ln2range = 20; 276 break; 277 case 0x04: 278 ln2range = 64; 279 break; 280 } 281 return (ln2range); 282} 283 284/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 285 286static void 287pci_fixancient(pcicfgregs *cfg) 288{ 289 if (cfg->hdrtype != 0) 290 return; 291 292 /* PCI to PCI bridges use header type 1 */ 293 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 294 cfg->hdrtype = 1; 295} 296 297/* extract header type specific config data */ 298 299static void 300pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 301{ 302#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 303 switch (cfg->hdrtype) { 304 case 0: 305 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 306 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 307 cfg->nummaps = PCI_MAXMAPS_0; 308 break; 309 case 1: 310 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 311 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 312 cfg->nummaps = PCI_MAXMAPS_1; 313 break; 314 case 2: 315 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 316 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 317 cfg->nummaps = PCI_MAXMAPS_2; 318 break; 319 } 320#undef REG 321} 322 323/* read configuration header into pcicfgregs structure */ 324 325struct pci_devinfo * 326pci_read_device(device_t pcib, int b, int s, int f, size_t size) 327{ 328#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 329 pcicfgregs *cfg = NULL; 330 struct pci_devinfo *devlist_entry; 331 struct devlist *devlist_head; 332 333 devlist_head = &pci_devq; 334 335 devlist_entry = NULL; 336 337 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 338 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 339 if (devlist_entry == NULL) 340 return (NULL); 341 342 cfg = &devlist_entry->cfg; 343 344 cfg->bus = b; 345 cfg->slot = s; 346 cfg->func = f; 347 cfg->vendor = REG(PCIR_VENDOR, 2); 348 cfg->device = REG(PCIR_DEVICE, 2); 349 cfg->cmdreg = REG(PCIR_COMMAND, 2); 350 cfg->statreg = REG(PCIR_STATUS, 2); 351 cfg->baseclass = REG(PCIR_CLASS, 1); 352 cfg->subclass = REG(PCIR_SUBCLASS, 1); 353 cfg->progif = REG(PCIR_PROGIF, 1); 354 cfg->revid = REG(PCIR_REVID, 1); 355 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 356 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 357 cfg->lattimer = REG(PCIR_LATTIMER, 1); 358 cfg->intpin = REG(PCIR_INTPIN, 1); 359 cfg->intline = REG(PCIR_INTLINE, 1); 360 361 cfg->mingnt = REG(PCIR_MINGNT, 1); 362 cfg->maxlat = REG(PCIR_MAXLAT, 1); 363 364 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 365 cfg->hdrtype &= ~PCIM_MFDEV; 366 367 pci_fixancient(cfg); 368 pci_hdrtypedata(pcib, b, s, f, cfg); 369 370 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 371 pci_read_extcap(pcib, cfg); 372 373 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 374 375 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 376 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 377 devlist_entry->conf.pc_sel.pc_func = cfg->func; 378 devlist_entry->conf.pc_hdr = cfg->hdrtype; 379 380 devlist_entry->conf.pc_subvendor = cfg->subvendor; 381 devlist_entry->conf.pc_subdevice = cfg->subdevice; 382 devlist_entry->conf.pc_vendor = cfg->vendor; 383 devlist_entry->conf.pc_device = cfg->device; 384 385 devlist_entry->conf.pc_class = cfg->baseclass; 386 devlist_entry->conf.pc_subclass = cfg->subclass; 387 devlist_entry->conf.pc_progif = cfg->progif; 388 devlist_entry->conf.pc_revid = cfg->revid; 389 390 pci_numdevs++; 391 pci_generation++; 392 } 393 return (devlist_entry); 394#undef REG 395} 396 397static void 398pci_read_extcap(device_t pcib, pcicfgregs *cfg) 399{ 400#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 401 int ptr, nextptr, ptrptr; 402 403 switch (cfg->hdrtype) { 404 case 0: 405 ptrptr = 0x34; 406 break; 407 case 2: 408 ptrptr = 0x14; 409 break; 410 default: 411 return; /* no extended capabilities support */ 412 } 413 nextptr = REG(ptrptr, 1); /* sanity check? */ 414 415 /* 416 * Read capability entries. 417 */ 418 while (nextptr != 0) { 419 /* Sanity check */ 420 if (nextptr > 255) { 421 printf("illegal PCI extended capability offset %d\n", 422 nextptr); 423 return; 424 } 425 /* Find the next entry */ 426 ptr = nextptr; 427 nextptr = REG(ptr + 1, 1); 428 429 /* Process this entry */ 430 switch (REG(ptr, 1)) { 431 case 0x01: /* PCI power management */ 432 if (cfg->pp_cap == 0) { 433 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 434 cfg->pp_status = ptr + PCIR_POWER_STATUS; 435 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 436 if ((nextptr - ptr) > PCIR_POWER_DATA) 437 cfg->pp_data = ptr + PCIR_POWER_DATA; 438 } 439 break; 440 default: 441 break; 442 } 443 } 444#undef REG 445} 446 447/* free pcicfgregs structure and all depending data structures */ 448 449int 450pci_freecfg(struct pci_devinfo *dinfo) 451{ 452 struct devlist *devlist_head; 453 454 devlist_head = &pci_devq; 455 456 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 457 free(dinfo, M_DEVBUF); 458 459 /* increment the generation count */ 460 pci_generation++; 461 462 /* we're losing one device */ 463 pci_numdevs--; 464 return (0); 465} 466 467/* 468 * PCI power manangement 469 */ 470int 471pci_set_powerstate_method(device_t dev, device_t child, int state) 472{ 473 struct pci_devinfo *dinfo = device_get_ivars(child); 474 pcicfgregs *cfg = &dinfo->cfg; 475 u_int16_t status; 476 int result; 477 478 if (cfg->pp_cap != 0) { 479 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 480 result = 0; 481 switch (state) { 482 case PCI_POWERSTATE_D0: 483 status |= PCIM_PSTAT_D0; 484 break; 485 case PCI_POWERSTATE_D1: 486 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 487 status |= PCIM_PSTAT_D1; 488 } else { 489 result = EOPNOTSUPP; 490 } 491 break; 492 case PCI_POWERSTATE_D2: 493 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 494 status |= PCIM_PSTAT_D2; 495 } else { 496 result = EOPNOTSUPP; 497 } 498 break; 499 case PCI_POWERSTATE_D3: 500 status |= PCIM_PSTAT_D3; 501 break; 502 default: 503 result = EINVAL; 504 } 505 if (result == 0) 506 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 507 } else { 508 result = ENXIO; 509 } 510 return(result); 511} 512 513int 514pci_get_powerstate_method(device_t dev, device_t child) 515{ 516 struct pci_devinfo *dinfo = device_get_ivars(child); 517 pcicfgregs *cfg = &dinfo->cfg; 518 u_int16_t status; 519 int result; 520 521 if (cfg->pp_cap != 0) { 522 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 523 switch (status & PCIM_PSTAT_DMASK) { 524 case PCIM_PSTAT_D0: 525 result = PCI_POWERSTATE_D0; 526 break; 527 case PCIM_PSTAT_D1: 528 result = PCI_POWERSTATE_D1; 529 break; 530 case PCIM_PSTAT_D2: 531 result = PCI_POWERSTATE_D2; 532 break; 533 case PCIM_PSTAT_D3: 534 result = PCI_POWERSTATE_D3; 535 break; 536 default: 537 result = PCI_POWERSTATE_UNKNOWN; 538 break; 539 } 540 } else { 541 /* No support, device is always at D0 */ 542 result = PCI_POWERSTATE_D0; 543 } 544 return(result); 545} 546 547/* 548 * Some convenience functions for PCI device drivers. 549 */ 550 551static __inline void 552pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 553{ 554 u_int16_t command; 555 556 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 557 command |= bit; 558 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 559} 560 561static __inline void 562pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 563{ 564 u_int16_t command; 565 566 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 567 command &= ~bit; 568 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 569} 570 571int 572pci_enable_busmaster_method(device_t dev, device_t child) 573{ 574 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 575 return (0); 576} 577 578int 579pci_disable_busmaster_method(device_t dev, device_t child) 580{ 581 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 582 return (0); 583} 584 585int 586pci_enable_io_method(device_t dev, device_t child, int space) 587{ 588 u_int16_t command; 589 u_int16_t bit; 590 char *error; 591 592 bit = 0; 593 error = NULL; 594 595 switch(space) { 596 case SYS_RES_IOPORT: 597 bit = PCIM_CMD_PORTEN; 598 error = "port"; 599 break; 600 case SYS_RES_MEMORY: 601 bit = PCIM_CMD_MEMEN; 602 error = "memory"; 603 break; 604 default: 605 return (EINVAL); 606 } 607 pci_set_command_bit(dev, child, bit); 608 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 609 if (command & bit) 610 return (0); 611 device_printf(child, "failed to enable %s mapping!\n", error); 612 return (ENXIO); 613} 614 615int 616pci_disable_io_method(device_t dev, device_t child, int space) 617{ 618 u_int16_t command; 619 u_int16_t bit; 620 char *error; 621 622 bit = 0; 623 error = NULL; 624 625 switch(space) { 626 case SYS_RES_IOPORT: 627 bit = PCIM_CMD_PORTEN; 628 error = "port"; 629 break; 630 case SYS_RES_MEMORY: 631 bit = PCIM_CMD_MEMEN; 632 error = "memory"; 633 break; 634 default: 635 return (EINVAL); 636 } 637 pci_clear_command_bit(dev, child, bit); 638 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 639 if (command & bit) { 640 device_printf(child, "failed to disable %s mapping!\n", error); 641 return (ENXIO); 642 } 643 return (0); 644} 645 646/* 647 * New style pci driver. Parent device is either a pci-host-bridge or a 648 * pci-pci-bridge. Both kinds are represented by instances of pcib. 649 */ 650 651void 652pci_print_verbose(struct pci_devinfo *dinfo) 653{ 654 if (bootverbose) { 655 pcicfgregs *cfg = &dinfo->cfg; 656 657 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 658 cfg->vendor, cfg->device, cfg->revid); 659 printf("\tbus=%d, slot=%d, func=%d\n", 660 cfg->bus, cfg->slot, cfg->func); 661 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 662 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 663 cfg->mfdev); 664 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 665 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 666 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 667 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 668 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 669 if (cfg->intpin > 0) 670 printf("\tintpin=%c, irq=%d\n", 671 cfg->intpin +'a' -1, cfg->intline); 672 if (cfg->pp_cap) { 673 u_int16_t status; 674 675 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 676 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 677 cfg->pp_cap & PCIM_PCAP_SPEC, 678 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 679 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 680 status & PCIM_PSTAT_DMASK); 681 } 682 } 683} 684 685static int 686pci_porten(device_t pcib, int b, int s, int f) 687{ 688 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 689 & PCIM_CMD_PORTEN) != 0; 690} 691 692static int 693pci_memen(device_t pcib, int b, int s, int f) 694{ 695 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 696 & PCIM_CMD_MEMEN) != 0; 697} 698 699/* 700 * Add a resource based on a pci map register. Return 1 if the map 701 * register is a 32bit map register or 2 if it is a 64bit register. 702 */ 703static int 704pci_add_map(device_t pcib, int b, int s, int f, int reg, 705 struct resource_list *rl) 706{ 707 u_int32_t map; 708 u_int64_t base; 709 u_int8_t ln2size; 710 u_int8_t ln2range; 711 u_int32_t testval; 712 u_int16_t cmd; 713 int type; 714 715 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 716 717 if (map == 0 || map == 0xffffffff) 718 return (1); /* skip invalid entry */ 719 720 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 721 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 722 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 723 724 base = pci_mapbase(map); 725 if (pci_maptype(map) & PCI_MAPMEM) 726 type = SYS_RES_MEMORY; 727 else 728 type = SYS_RES_IOPORT; 729 ln2size = pci_mapsize(testval); 730 ln2range = pci_maprange(testval); 731 if (ln2range == 64) { 732 /* Read the other half of a 64bit map register */ 733 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 734 } 735 736 if (bootverbose) { 737 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 738 reg, pci_maptype(map), ln2range, 739 (unsigned int) base, ln2size); 740 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 741 printf(", port disabled\n"); 742 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 743 printf(", memory disabled\n"); 744 else 745 printf(", enabled\n"); 746 } 747 748 /* 749 * This code theoretically does the right thing, but has 750 * undesirable side effects in some cases where 751 * peripherals respond oddly to having these bits 752 * enabled. Leave them alone by default. 753 */ 754 if (pci_enable_io_modes) { 755 /* Turn on resources that have been left off by a lazy BIOS */ 756 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 757 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 758 cmd |= PCIM_CMD_PORTEN; 759 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 760 } 761 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 762 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 763 cmd |= PCIM_CMD_MEMEN; 764 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 765 } 766 } else { 767 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 768 return (1); 769 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 770 return (1); 771 } 772 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1, 773 (1 << ln2size)); 774 775 return ((ln2range == 64) ? 2 : 1); 776} 777 778static void 779pci_add_resources(device_t pcib, device_t dev) 780{ 781 struct pci_devinfo *dinfo = device_get_ivars(dev); 782 pcicfgregs *cfg = &dinfo->cfg; 783 struct resource_list *rl = &dinfo->resources; 784 struct pci_quirk *q; 785 int b, i, irq, f, s; 786 787 b = cfg->bus; 788 s = cfg->slot; 789 f = cfg->func; 790 for (i = 0; i < cfg->nummaps;) { 791 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 792 } 793 794 for (q = &pci_quirks[0]; q->devid; q++) { 795 if (q->devid == ((cfg->device << 16) | cfg->vendor) 796 && q->type == PCI_QUIRK_MAP_REG) 797 pci_add_map(pcib, b, s, f, q->arg1, rl); 798 } 799 800 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 801#if defined(__ia64__) || (defined(__i386__) && !defined(SMP) && !defined(PC98)) 802 /* 803 * Try to re-route interrupts. Sometimes the BIOS or 804 * firmware may leave bogus values in these registers. 805 * If the re-route fails, then just stick with what we 806 * have. 807 */ 808 irq = PCIB_ROUTE_INTERRUPT(pcib, dev, cfg->intpin); 809 if (PCI_INTERRUPT_VALID(irq)) 810 cfg->intline = irq; 811 else 812#endif 813 irq = cfg->intline; 814 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 815 } 816} 817 818void 819pci_add_children(device_t dev, int busno, size_t dinfo_size) 820{ 821 device_t pcib = device_get_parent(dev); 822 struct pci_devinfo *dinfo; 823 int maxslots; 824 int s, f, pcifunchigh; 825 826 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 827 ("dinfo_size too small")); 828 maxslots = PCIB_MAXSLOTS(pcib); 829 for (s = 0; s <= maxslots; s++) { 830 pcifunchigh = 0; 831 for (f = 0; f <= pcifunchigh; f++) { 832 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 833 if (dinfo != NULL) { 834 if (dinfo->cfg.mfdev) 835 pcifunchigh = PCI_FUNCMAX; 836 pci_add_child(dev, dinfo); 837 } 838 } 839 } 840} 841 842void 843pci_add_child(device_t bus, struct pci_devinfo *dinfo) 844{ 845 device_t pcib; 846 847 pcib = device_get_parent(bus); 848 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 849 device_set_ivars(dinfo->cfg.dev, dinfo); 850 pci_add_resources(pcib, dinfo->cfg.dev); 851 pci_print_verbose(dinfo); 852} 853 854static int 855pci_probe(device_t dev) 856{ 857 858 device_set_desc(dev, "PCI bus"); 859 860 /* Allow other subclasses to override this driver. */ 861 return (-1000); 862} 863 864static int 865pci_attach(device_t dev) 866{ 867 int busno; 868 869 /* 870 * Since there can be multiple independantly numbered PCI 871 * busses on some large alpha systems, we can't use the unit 872 * number to decide what bus we are probing. We ask the parent 873 * pcib what our bus number is. 874 */ 875 busno = pcib_get_bus(dev); 876 if (bootverbose) 877 device_printf(dev, "physical bus=%d\n", busno); 878 879 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 880 881 return (bus_generic_attach(dev)); 882} 883 884static void 885pci_load_vendor_data(void) 886{ 887 caddr_t vendordata, info; 888 889 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 890 info = preload_search_info(vendordata, MODINFO_ADDR); 891 pci_vendordata = *(char **)info; 892 info = preload_search_info(vendordata, MODINFO_SIZE); 893 pci_vendordata_size = *(size_t *)info; 894 /* terminate the database */ 895 pci_vendordata[pci_vendordata_size] = '\n'; 896 } 897} 898 899int 900pci_print_child(device_t dev, device_t child) 901{ 902 struct pci_devinfo *dinfo; 903 struct resource_list *rl; 904 int retval = 0; 905 906 dinfo = device_get_ivars(child); 907 rl = &dinfo->resources; 908 909 retval += bus_print_child_header(dev, child); 910 911 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 912 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 913 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 914 if (device_get_flags(dev)) 915 retval += printf(" flags %#x", device_get_flags(dev)); 916 917 retval += printf(" at device %d.%d", pci_get_slot(child), 918 pci_get_function(child)); 919 920 retval += bus_print_child_footer(dev, child); 921 922 return (retval); 923} 924 925static struct 926{ 927 int class; 928 int subclass; 929 char *desc; 930} pci_nomatch_tab[] = { 931 {PCIC_OLD, -1, "old"}, 932 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 933 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 934 {PCIC_STORAGE, -1, "mass storage"}, 935 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 936 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 937 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 938 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 939 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 940 {PCIC_NETWORK, -1, "network"}, 941 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 942 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 943 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 944 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 945 {PCIC_DISPLAY, -1, "display"}, 946 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 947 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 948 {PCIC_MULTIMEDIA, -1, "multimedia"}, 949 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 950 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 951 {PCIC_MEMORY, -1, "memory"}, 952 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 953 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 954 {PCIC_BRIDGE, -1, "bridge"}, 955 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 956 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 957 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 958 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 959 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 960 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 961 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 962 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 963 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 964 {PCIC_SIMPLECOMM, -1, "simple comms"}, 965 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 966 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 967 {PCIC_BASEPERIPH, -1, "base peripheral"}, 968 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 969 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 970 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 971 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 972 {PCIC_INPUTDEV, -1, "input device"}, 973 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 974 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 975 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 976 {PCIC_DOCKING, -1, "docking station"}, 977 {PCIC_PROCESSOR, -1, "processor"}, 978 {PCIC_SERIALBUS, -1, "serial bus"}, 979 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 980 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 981 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 982 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 983 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 984 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 985 {0, 0, NULL} 986}; 987 988void 989pci_probe_nomatch(device_t dev, device_t child) 990{ 991 int i; 992 char *cp, *scp, *device; 993 994 /* 995 * Look for a listing for this device in a loaded device database. 996 */ 997 if ((device = pci_describe_device(child)) != NULL) { 998 device_printf(dev, "<%s>", device); 999 free(device, M_DEVBUF); 1000 } else { 1001 /* 1002 * Scan the class/subclass descriptions for a general 1003 * description. 1004 */ 1005 cp = "unknown"; 1006 scp = NULL; 1007 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1008 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1009 if (pci_nomatch_tab[i].subclass == -1) { 1010 cp = pci_nomatch_tab[i].desc; 1011 } else if (pci_nomatch_tab[i].subclass == 1012 pci_get_subclass(child)) { 1013 scp = pci_nomatch_tab[i].desc; 1014 } 1015 } 1016 } 1017 device_printf(dev, "<%s%s%s>", 1018 cp ? cp : "", 1019 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1020 scp ? scp : ""); 1021 } 1022 printf(" at device %d.%d (no driver attached)\n", 1023 pci_get_slot(child), pci_get_function(child)); 1024 return; 1025} 1026 1027/* 1028 * Parse the PCI device database, if loaded, and return a pointer to a 1029 * description of the device. 1030 * 1031 * The database is flat text formatted as follows: 1032 * 1033 * Any line not in a valid format is ignored. 1034 * Lines are terminated with newline '\n' characters. 1035 * 1036 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1037 * the vendor name. 1038 * 1039 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1040 * - devices cannot be listed without a corresponding VENDOR line. 1041 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1042 * another TAB, then the device name. 1043 */ 1044 1045/* 1046 * Assuming (ptr) points to the beginning of a line in the database, 1047 * return the vendor or device and description of the next entry. 1048 * The value of (vendor) or (device) inappropriate for the entry type 1049 * is set to -1. Returns nonzero at the end of the database. 1050 * 1051 * Note that this is slightly unrobust in the face of corrupt data; 1052 * we attempt to safeguard against this by spamming the end of the 1053 * database with a newline when we initialise. 1054 */ 1055static int 1056pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1057{ 1058 char *cp = *ptr; 1059 int left; 1060 1061 *device = -1; 1062 *vendor = -1; 1063 **desc = '\0'; 1064 for (;;) { 1065 left = pci_vendordata_size - (cp - pci_vendordata); 1066 if (left <= 0) { 1067 *ptr = cp; 1068 return(1); 1069 } 1070 1071 /* vendor entry? */ 1072 if (*cp != '\t' && 1073 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1074 break; 1075 /* device entry? */ 1076 if (*cp == '\t' && 1077 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1078 break; 1079 1080 /* skip to next line */ 1081 while (*cp != '\n' && left > 0) { 1082 cp++; 1083 left--; 1084 } 1085 if (*cp == '\n') { 1086 cp++; 1087 left--; 1088 } 1089 } 1090 /* skip to next line */ 1091 while (*cp != '\n' && left > 0) { 1092 cp++; 1093 left--; 1094 } 1095 if (*cp == '\n' && left > 0) 1096 cp++; 1097 *ptr = cp; 1098 return(0); 1099} 1100 1101static char * 1102pci_describe_device(device_t dev) 1103{ 1104 int vendor, device; 1105 char *desc, *vp, *dp, *line; 1106 1107 desc = vp = dp = NULL; 1108 1109 /* 1110 * If we have no vendor data, we can't do anything. 1111 */ 1112 if (pci_vendordata == NULL) 1113 goto out; 1114 1115 /* 1116 * Scan the vendor data looking for this device 1117 */ 1118 line = pci_vendordata; 1119 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1120 goto out; 1121 for (;;) { 1122 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1123 goto out; 1124 if (vendor == pci_get_vendor(dev)) 1125 break; 1126 } 1127 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1128 goto out; 1129 for (;;) { 1130 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1131 *dp = 0; 1132 break; 1133 } 1134 if (vendor != -1) { 1135 *dp = 0; 1136 break; 1137 } 1138 if (device == pci_get_device(dev)) 1139 break; 1140 } 1141 if (dp[0] == '\0') 1142 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1143 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1144 NULL) 1145 sprintf(desc, "%s, %s", vp, dp); 1146 out: 1147 if (vp != NULL) 1148 free(vp, M_DEVBUF); 1149 if (dp != NULL) 1150 free(dp, M_DEVBUF); 1151 return(desc); 1152} 1153 1154int 1155pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1156{ 1157 struct pci_devinfo *dinfo; 1158 pcicfgregs *cfg; 1159 1160 dinfo = device_get_ivars(child); 1161 cfg = &dinfo->cfg; 1162 1163 switch (which) { 1164 case PCI_IVAR_ETHADDR: 1165 /* 1166 * The generic accessor doesn't deal with failure, so 1167 * we set the return value, then return an error. 1168 */ 1169 *((u_int8_t **) result) = NULL; 1170 return (EINVAL); 1171 case PCI_IVAR_SUBVENDOR: 1172 *result = cfg->subvendor; 1173 break; 1174 case PCI_IVAR_SUBDEVICE: 1175 *result = cfg->subdevice; 1176 break; 1177 case PCI_IVAR_VENDOR: 1178 *result = cfg->vendor; 1179 break; 1180 case PCI_IVAR_DEVICE: 1181 *result = cfg->device; 1182 break; 1183 case PCI_IVAR_DEVID: 1184 *result = (cfg->device << 16) | cfg->vendor; 1185 break; 1186 case PCI_IVAR_CLASS: 1187 *result = cfg->baseclass; 1188 break; 1189 case PCI_IVAR_SUBCLASS: 1190 *result = cfg->subclass; 1191 break; 1192 case PCI_IVAR_PROGIF: 1193 *result = cfg->progif; 1194 break; 1195 case PCI_IVAR_REVID: 1196 *result = cfg->revid; 1197 break; 1198 case PCI_IVAR_INTPIN: 1199 *result = cfg->intpin; 1200 break; 1201 case PCI_IVAR_IRQ: 1202 *result = cfg->intline; 1203 break; 1204 case PCI_IVAR_BUS: 1205 *result = cfg->bus; 1206 break; 1207 case PCI_IVAR_SLOT: 1208 *result = cfg->slot; 1209 break; 1210 case PCI_IVAR_FUNCTION: 1211 *result = cfg->func; 1212 break; 1213 default: 1214 return (ENOENT); 1215 } 1216 return (0); 1217} 1218 1219int 1220pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1221{ 1222 struct pci_devinfo *dinfo; 1223 1224 dinfo = device_get_ivars(child); 1225 1226 switch (which) { 1227 case PCI_IVAR_ETHADDR: 1228 case PCI_IVAR_SUBVENDOR: 1229 case PCI_IVAR_SUBDEVICE: 1230 case PCI_IVAR_VENDOR: 1231 case PCI_IVAR_DEVICE: 1232 case PCI_IVAR_DEVID: 1233 case PCI_IVAR_CLASS: 1234 case PCI_IVAR_SUBCLASS: 1235 case PCI_IVAR_PROGIF: 1236 case PCI_IVAR_REVID: 1237 case PCI_IVAR_INTPIN: 1238 case PCI_IVAR_IRQ: 1239 case PCI_IVAR_BUS: 1240 case PCI_IVAR_SLOT: 1241 case PCI_IVAR_FUNCTION: 1242 return (EINVAL); /* disallow for now */ 1243 1244 default: 1245 return (ENOENT); 1246 } 1247} 1248 1249 1250#include "opt_ddb.h" 1251#ifdef DDB 1252#include <ddb/ddb.h> 1253#include <sys/cons.h> 1254 1255/* 1256 * List resources based on pci map registers, used for within ddb 1257 */ 1258 1259DB_SHOW_COMMAND(pciregs, db_pci_dump) 1260{ 1261 struct pci_devinfo *dinfo; 1262 struct devlist *devlist_head; 1263 struct pci_conf *p; 1264 const char *name; 1265 int i, error, none_count, nl; 1266 1267 none_count = 0; 1268 nl = 0; 1269 /* get the head of the device queue */ 1270 devlist_head = &pci_devq; 1271 1272 /* 1273 * Go through the list of devices and print out devices 1274 */ 1275 for (error = 0, i = 0, 1276 dinfo = STAILQ_FIRST(devlist_head); 1277 (dinfo != NULL) && (error == 0) && (i < pci_numdevs); 1278 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1279 1280 /* Populate pd_name and pd_unit */ 1281 name = NULL; 1282 if (dinfo->cfg.dev) 1283 name = device_get_name(dinfo->cfg.dev); 1284 1285 p = &dinfo->conf; 1286 /* 1287 * XXX just take 20 for now... 1288 */ 1289 if (nl++ == 20) { 1290 int c; 1291 1292 db_printf("--More--"); 1293 c = cngetc(); 1294 db_printf("\r"); 1295 /* 1296 * A whole screenfull or just one line? 1297 */ 1298 switch (c) { 1299 case '\n': /* just one line */ 1300 nl = 20; 1301 break; 1302 case ' ': 1303 nl = 0; /* another screenfull */ 1304 break; 1305 default: /* exit */ 1306 db_printf("\n"); 1307 return; 1308 } 1309 } 1310 1311 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1312 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1313 (name && *name) ? name : "none", 1314 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1315 none_count++, 1316 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1317 p->pc_sel.pc_func, (p->pc_class << 16) | 1318 (p->pc_subclass << 8) | p->pc_progif, 1319 (p->pc_subdevice << 16) | p->pc_subvendor, 1320 (p->pc_device << 16) | p->pc_vendor, 1321 p->pc_revid, p->pc_hdr); 1322 } 1323} 1324#endif /* DDB */ 1325 1326struct resource * 1327pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1328 u_long start, u_long end, u_long count, u_int flags) 1329{ 1330 struct pci_devinfo *dinfo = device_get_ivars(child); 1331 struct resource_list *rl = &dinfo->resources; 1332 pcicfgregs *cfg = &dinfo->cfg; 1333 1334 /* 1335 * Perform lazy resource allocation 1336 * 1337 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1338 */ 1339 if (device_get_parent(child) == dev) { 1340 switch (type) { 1341 case SYS_RES_IRQ: 1342 /* 1343 * If the child device doesn't have an 1344 * interrupt routed and is deserving of an 1345 * interrupt, try to assign it one. 1346 */ 1347 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1348 (cfg->intpin != 0)) { 1349 cfg->intline = PCIB_ROUTE_INTERRUPT( 1350 device_get_parent(dev), child, cfg->intpin); 1351 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1352 pci_write_config(child, PCIR_INTLINE, 1353 cfg->intline, 1); 1354 resource_list_add(rl, SYS_RES_IRQ, 0, 1355 cfg->intline, cfg->intline, 1); 1356 } 1357 } 1358 break; 1359 case SYS_RES_IOPORT: 1360 case SYS_RES_MEMORY: 1361 /* 1362 * Enable the I/O mode. We should also be allocating 1363 * resources too. XXX 1364 */ 1365 if (PCI_ENABLE_IO(dev, child, type)) 1366 return (NULL); 1367 break; 1368 } 1369 } 1370 1371 return (resource_list_alloc(rl, dev, child, type, rid, 1372 start, end, count, flags)); 1373} 1374 1375void 1376pci_delete_resource(device_t dev, device_t child, int type, int rid) 1377{ 1378 struct pci_devinfo *dinfo; 1379 struct resource_list *rl; 1380 struct resource_list_entry *rle; 1381 1382 if (device_get_parent(child) != dev) 1383 return; 1384 1385 dinfo = device_get_ivars(child); 1386 rl = &dinfo->resources; 1387 rle = resource_list_find(rl, type, rid); 1388 if (rle) { 1389 if (rle->res) { 1390 if (rman_get_device(rle->res) != dev || 1391 rman_get_flags(rle->res) & RF_ACTIVE) { 1392 device_printf(dev, "delete_resource: " 1393 "Resource still owned by child, oops. " 1394 "(type=%d, rid=%d, addr=%lx)\n", 1395 rle->type, rle->rid, 1396 rman_get_start(rle->res)); 1397 return; 1398 } 1399 bus_release_resource(dev, type, rid, rle->res); 1400 } 1401 resource_list_delete(rl, type, rid); 1402 } 1403 /* 1404 * Why do we turn off the PCI configuration BAR when we delete a 1405 * resource? -- imp 1406 */ 1407 pci_write_config(child, rid, 0, 4); 1408 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1409} 1410 1411struct resource_list * 1412pci_get_resource_list (device_t dev, device_t child) 1413{ 1414 struct pci_devinfo * dinfo = device_get_ivars(child); 1415 struct resource_list * rl = &dinfo->resources; 1416 1417 if (!rl) 1418 return (NULL); 1419 1420 return (rl); 1421} 1422 1423u_int32_t 1424pci_read_config_method(device_t dev, device_t child, int reg, int width) 1425{ 1426 struct pci_devinfo *dinfo = device_get_ivars(child); 1427 pcicfgregs *cfg = &dinfo->cfg; 1428 1429 return (PCIB_READ_CONFIG(device_get_parent(dev), 1430 cfg->bus, cfg->slot, cfg->func, reg, width)); 1431} 1432 1433void 1434pci_write_config_method(device_t dev, device_t child, int reg, 1435 u_int32_t val, int width) 1436{ 1437 struct pci_devinfo *dinfo = device_get_ivars(child); 1438 pcicfgregs *cfg = &dinfo->cfg; 1439 1440 PCIB_WRITE_CONFIG(device_get_parent(dev), 1441 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1442} 1443 1444int 1445pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1446 size_t buflen) 1447{ 1448 struct pci_devinfo *dinfo; 1449 1450 dinfo = device_get_ivars(child); 1451 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1452 pci_get_function(child)); 1453 return (0); 1454} 1455 1456int 1457pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1458 size_t buflen) 1459{ 1460 struct pci_devinfo *dinfo; 1461 pcicfgregs *cfg; 1462 1463 dinfo = device_get_ivars(child); 1464 cfg = &dinfo->cfg; 1465 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1466 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1467 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1468 cfg->progif); 1469 return (0); 1470} 1471 1472static int 1473pci_modevent(module_t mod, int what, void *arg) 1474{ 1475 static dev_t pci_cdev; 1476 1477 switch (what) { 1478 case MOD_LOAD: 1479 STAILQ_INIT(&pci_devq); 1480 pci_generation = 0; 1481 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1482 "pci"); 1483 pci_load_vendor_data(); 1484 break; 1485 1486 case MOD_UNLOAD: 1487 destroy_dev(pci_cdev); 1488 break; 1489 } 1490 1491 return (0); 1492} 1493