pci.c revision 10748
1/************************************************************************** 2** 3** $Id: pci.c,v 1.30 1995/09/14 13:09:40 se Exp $ 4** 5** General subroutines for the PCI bus. 6** pci_configure () 7** 8** FreeBSD 9** 10**------------------------------------------------------------------------- 11** 12** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 13** 14** Redistribution and use in source and binary forms, with or without 15** modification, are permitted provided that the following conditions 16** are met: 17** 1. Redistributions of source code must retain the above copyright 18** notice, this list of conditions and the following disclaimer. 19** 2. Redistributions in binary form must reproduce the above copyright 20** notice, this list of conditions and the following disclaimer in the 21** documentation and/or other materials provided with the distribution. 22** 3. The name of the author may not be used to endorse or promote products 23** derived from this software without specific prior written permission. 24** 25** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35** 36*************************************************************************** 37*/ 38 39#include <pci.h> 40#if NPCI > 0 41 42/*======================================================== 43** 44** #includes and declarations 45** 46**======================================================== 47*/ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/malloc.h> 52#include <sys/errno.h> 53#include <sys/kernel.h> 54#include <sys/proc.h> /* declaration of wakeup(), used by vm.h */ 55#include <sys/devconf.h> 56 57#include <machine/cpu.h> /* bootverbose */ 58 59#include <vm/vm.h> 60#include <vm/vm_param.h> 61 62#include <machine/pmap.h> 63#include <sys/devconf.h> 64 65#include <pci/pcivar.h> 66#include <pci/pcireg.h> 67#include <pci/pcibus.h> 68 69#define PCI_MAX_IRQ (16) 70 71 72/*======================================================== 73** 74** Structs and Functions 75** 76**======================================================== 77*/ 78 79struct pci_devconf { 80 struct kern_devconf pdc_kdc; 81 struct pci_info pdc_pi; 82}; 83 84struct pcicb { 85 struct pcicb *pcicb_next; 86 struct pcicb *pcicb_up; 87 struct pcicb *pcicb_down; 88 pcici_t pcicb_bridge; 89 90 u_long pcicb_seen; 91 u_char pcicb_bus; 92 u_char pcicb_subordinate; 93 u_char pcicb_flags; 94#define PCICB_ISAMEM 0x01 95 u_int pcicb_mfrom; 96 u_int pcicb_mupto; 97 u_int pcicb_mamount; 98 u_short pcicb_pfrom; 99 u_short pcicb_pupto; 100 u_short pcicb_pamount; 101 u_char pcicb_bfrom; 102 u_char pcicb_bupto; 103 104 u_long pcicb_iobase; 105 u_long pcicb_iolimit; 106 u_long pcicb_membase; 107 u_long pcicb_memlimit; 108 u_long pcicb_p_membase; 109 u_long pcicb_p_memlimit; 110}; 111 112static int 113pci_externalize (struct proc *, struct kern_devconf *, void *, size_t); 114 115static int 116pci_internalize (struct proc *, struct kern_devconf *, void *, size_t); 117 118static void 119not_supported (pcici_t tag, u_long type); 120 121static void 122pci_bus_config (void); 123 124static void 125pci_bridge_config (void); 126 127/*======================================================== 128** 129** Variables 130** 131**======================================================== 132*/ 133 134/* 135** log2 of safe burst len (in words) 136*/ 137 138unsigned pci_max_burst_len = 2; /* 2=16Byte, 3=32Byte, 4=64Byte, ... */ 139unsigned pci_mechanism = 0; 140unsigned pci_maxdevice = 0; 141struct pcibus* pcibus; 142 143/*-------------------------------------------------------- 144** 145** Local variables. 146** 147**-------------------------------------------------------- 148*/ 149 150static int pci_conf_count; 151static int pci_info_done; 152static struct pcicb pcibus0 = { 153 NULL, NULL, NULL, 154 { 0 }, 155 0, 0, 0, 0, 156 0, 0, 0, 0, 0, 0, 0, 0, /* real allocation */ 157 0, 0xFFFF, /* iobase/limit */ 158 0x4000000, 0xFFFFFFFFu, /* nonprefetch membase/limit */ 159 0x4000000, 0xFFFFFFFFu /* prefetch membase/limit */ 160}; 161static struct pcicb *pcicb; 162 163/*======================================================== 164** 165** pci_configure () 166** 167** Autoconfiguration of pci devices. 168** 169** May be called more than once. 170** Any device is attached only once. 171** 172** Has to take care of mirrored devices, which are 173** entailed by incomplete decoding of pci address lines. 174** 175**======================================================== 176*/ 177 178void pci_configure() 179{ 180 struct pcibus **pbp = (struct pcibus**) pcibus_set.ls_items; 181 182 /* 183 ** check pci bus present 184 */ 185 186 while (!pci_maxdevice && (pcibus = *pbp++)) { 187 (*pcibus->pb_setup)(); 188 } 189 190 if (!pci_maxdevice) return; 191 192 /* 193 ** hello world .. 194 */ 195 196 for (pcicb = &pcibus0; pcicb != NULL;) { 197 pci_bus_config (); 198 199 if (pcicb->pcicb_down) { 200 pcicb = pcicb->pcicb_down; 201 continue; 202 }; 203 204 while (pcicb && !pcicb->pcicb_next) 205 pcicb = pcicb->pcicb_up; 206 207 if (pcicb) 208 pcicb = pcicb->pcicb_next; 209 } 210 pci_conf_count++; 211} 212 213/*======================================================== 214** 215** Subroutines for configuration. 216** 217**======================================================== 218*/ 219 220static void 221pci_register_io (struct pcicb * cb, u_int base, u_int limit) 222{ 223#ifdef PCI_BRIDGE_DEBUG 224 if (bootverbose) 225 printf ("register_io: bus=%d base=%x limit=%x\n", 226 cb->pcicb_bus, base, limit); 227#endif 228 229 if (!cb->pcicb_pfrom || base < cb->pcicb_pfrom) 230 cb->pcicb_pfrom = base; 231 if (limit > cb->pcicb_pupto) 232 cb->pcicb_pupto = limit; 233 234 /* 235 ** XXX should set bridge io mapping here 236 ** but it can be mapped in 4k blocks only, 237 ** leading to conflicts with isa/eisa .. 238 */ 239} 240 241static void 242pci_register_memory (struct pcicb * cb, u_int base, u_int limit) 243{ 244#ifdef PCI_BRIDGE_DEBUG 245 if (bootverbose) 246 printf ("register_mem: bus=%d base=%x limit=%x\n", 247 cb->pcicb_bus, base, limit); 248#endif 249 250 if (!cb->pcicb_mfrom || base < cb->pcicb_mfrom) 251 cb->pcicb_mfrom = base; 252 if (limit > cb->pcicb_mupto) 253 cb->pcicb_mupto = limit; 254 /* 255 ** set the bridges mapping 256 ** 257 ** XXX should handle the 1Mb granularity. 258 */ 259 if (cb->pcicb_bridge.tag) { 260 pci_conf_write(cb->pcicb_bridge, 261 PCI_PCI_BRIDGE_MEM_REG, 262 (cb->pcicb_memlimit & 0xffff0000) | 263 (cb->pcicb_membase >> 16)); 264 if (bootverbose) 265 printf ("\t[pci%d uses memory from %x to %x]\n", 266 cb->pcicb_bus, 267 (unsigned) cb->pcicb_membase, 268 (unsigned) cb->pcicb_memlimit); 269 } 270} 271 272/* 273** XXX This function is neither complete nor tested. 274** It's only used if the bios hasn't done it's job 275** of mapping the pci devices in the physical memory. 276*/ 277 278static u_int 279pci_memalloc (struct pcicb * cb, u_int addr, u_int size) 280{ 281 u_int result = 0, limit=0, newbase=0; 282#ifdef PCI_BRIDGE_DEBUG 283 if (bootverbose) 284 printf ("memalloc: bus=%d addr=%x size=%x ..\n", 285 cb->pcicb_bus, addr, size); 286#endif 287 288 if (!cb) goto done; 289 290 if (!cb->pcicb_membase) { 291 printf ("memalloc: bus%d: membase not set.\n", 292 cb->pcicb_bus); 293 goto done; 294 } 295 296 /* 297 ** get upper allocation limit 298 */ 299 limit = cb->pcicb_memlimit; 300 if (cb->pcicb_mfrom && cb->pcicb_mfrom <= limit) 301 limit = cb->pcicb_mfrom-1; 302 303 /* 304 ** address fixed, and impossible to allocate ? 305 */ 306 if (addr && addr+size-1 > limit) 307 goto done; 308 309 /* 310 ** get possible address 311 */ 312 313 result = addr; 314 if (!result) result = ((limit + 1) / size - 1) * size; 315 316 /* 317 ** if not local available, request from parent. 318 */ 319 320 if (result < cb->pcicb_membase) { 321 newbase = pci_memalloc (cb->pcicb_up, result, size); 322 if (newbase) cb->pcicb_membase = result; 323 else result=0; 324 } 325done: 326 if (result) 327 pci_register_memory (cb, result, result+size-1); 328 329#ifdef PCI_BRIDGE_DEBUG 330 printf ("memalloc: bus=%d addr=%x size=%x --> %x (limit=%x).\n", 331 cb->pcicb_bus, addr, size, result, limit); 332#endif 333 334 return (result); 335} 336 337/*======================================================== 338** 339** pci_bus_config() 340** 341** Autoconfiguration of one pci bus. 342** 343**======================================================== 344*/ 345 346static void 347pci_bus_config (void) 348{ 349 u_char device; 350 u_char reg; 351 pcici_t tag, mtag; 352 pcidi_t type; 353 u_long data; 354 int unit; 355 int pciint; 356 int irq; 357 358 struct pci_device *dvp; 359 360 struct pci_devconf *pdcp; 361 362 /* 363 ** first initialize the bridge (bus controller chip) 364 */ 365 pci_bridge_config (); 366 367 printf ("Probing for devices on the PCI bus:\n"); 368#ifndef PCI_QUIET 369 if (bootverbose && !pci_info_done) { 370 pci_info_done=1; 371 printf ("\tconfiguration mode %d allows %d devices.\n", 372 pci_mechanism, pci_maxdevice); 373 }; 374#endif 375 for (device=0; device<pci_maxdevice; device ++) { 376 char *name = NULL; 377 struct pci_device **dvpp; 378 379 if ((pcicb->pcicb_seen >> device) & 1) 380 continue; 381 382 tag = pcibus->pb_tag (pcicb->pcicb_bus, device, 0); 383 type = pcibus->pb_read (tag, PCI_ID_REG); 384 385 if ((!type) || (type==0xfffffffful)) continue; 386 387 /* 388 ** lookup device in ioconfiguration: 389 */ 390 391 dvpp = (struct pci_device **)pcidevice_set.ls_items; 392 393 while (dvp = *dvpp++) { 394 if (dvp->pd_probe) { 395 if (name=(*dvp->pd_probe)(tag, type)) 396 break; 397 } 398 }; 399 /* 400 ** check for mirrored devices. 401 */ 402 if (device & 0x10) { 403 mtag=pcibus->pb_tag (pcicb->pcicb_bus, 404 (u_char)(device & ~0x10), 0); 405 } else if (device & 0x08) { 406 mtag=pcibus->pb_tag (pcicb->pcicb_bus, 407 (u_char)(device & ~0x08), 0); 408 } else goto real_device; 409 410 if (type!=pcibus->pb_read (mtag, PCI_ID_REG)) 411 goto real_device; 412 413 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) 414 if (pcibus->pb_read(tag,reg)!=pcibus->pb_read(mtag,reg)) 415 goto real_device; 416 417#ifndef PCI_QUIET 418 if (dvp==NULL) continue; 419 if (bootverbose) 420 printf ("%s? <%s> mirrored on pci%d:%d\n", 421 dvp->pd_name, name, pcicb->pcicb_bus, device); 422#endif 423 continue; 424 425 real_device: 426 427 if (dvp==NULL) { 428#ifndef PCI_QUIET 429 if (pci_conf_count) 430 continue; 431 printf("%s%d:%d: ", pcibus->pb_name, 432 pcicb->pcicb_bus, device); 433 not_supported (tag, type); 434#endif 435 continue; 436 }; 437 438 pcicb->pcicb_seen |= (1ul << device); 439 440 /* 441 ** Get and increment the unit. 442 */ 443 444 unit = (*dvp->pd_count)++; 445 446 /* 447 ** ignore device ? 448 */ 449 450 if (!*name) continue; 451 452 /* 453 ** Announce this device 454 */ 455 456 printf ("%s%d <%s> rev %d", dvp->pd_name, unit, name, 457 (unsigned) pci_conf_read (tag, PCI_CLASS_REG) & 0xff); 458 459 /* 460 ** Get the int pin number (pci interrupt number a-d) 461 ** from the pci configuration space. 462 */ 463 464 data = pcibus->pb_read (tag, PCI_INTERRUPT_REG); 465 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 466 467 if (pciint) { 468 469 printf (" int %c irq ", 0x60+pciint); 470 471 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 472 473 /* 474 ** If it's zero, the isa irq number is unknown, 475 ** and we cannot bind the pci interrupt. 476 */ 477 478 if (irq) 479 printf ("%d", irq); 480 else 481 printf ("??"); 482 }; 483 484 printf (" on pci%d:%d\n", pcicb->pcicb_bus, device); 485 486 /* 487 ** Read the current mapping, 488 ** and update the pcicb fields. 489 */ 490 491 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) { 492 u_int map, addr, size; 493 494 data = pci_conf_read(tag, PCI_CLASS_REG); 495 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 496 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 497 continue; 498 }; 499 500 map = pcibus->pb_read (tag, reg); 501 if (!(map & PCI_MAP_MEMORY_ADDRESS_MASK)) 502 continue; 503 504 pcibus->pb_write (tag, reg, 0xffffffff); 505 data = pcibus->pb_read (tag, reg); 506 pcibus->pb_write (tag, reg, map); 507 508 switch (data & 7) { 509 510 default: 511 continue; 512 case 1: 513 case 5: 514 size = -(data & PCI_MAP_IO_ADDRESS_MASK); 515 addr = map & PCI_MAP_IO_ADDRESS_MASK; 516 517 pci_register_io (pcicb, addr, addr+size-1); 518 pcicb->pcicb_pamount += size; 519 break; 520 521 case 0: 522 case 2: 523 case 4: 524 size = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 525 addr = map & PCI_MAP_MEMORY_ADDRESS_MASK; 526 if (addr >= 0x100000) { 527 pci_register_memory 528 (pcicb, addr, addr+size-1); 529 pcicb->pcicb_mamount += size; 530 } else { 531 pcicb->pcicb_flags |= PCICB_ISAMEM; 532 }; 533 break; 534 }; 535 if (bootverbose) 536 printf ("\tmapreg[%02x] type=%d addr=%08x size=%04x.\n", 537 reg, map&7, addr, size); 538 }; 539 540 /* 541 ** Allocate a devconf structure 542 ** We should, and eventually will, set the 543 ** parent pointer to a pci bus devconf structure, 544 ** and arrange to set the state field dynamically. 545 */ 546 547 pdcp = (struct pci_devconf *) 548 malloc (sizeof (struct pci_devconf),M_DEVBUF,M_WAITOK); 549 bzero(pdcp, sizeof(struct pci_devconf)); 550 551 pdcp -> pdc_pi.pi_bus = pcicb->pcicb_bus; 552 pdcp -> pdc_pi.pi_device = device; 553 554 pdcp -> pdc_kdc.kdc_name = dvp->pd_name; 555 pdcp -> pdc_kdc.kdc_unit = unit; 556 557 pdcp -> pdc_kdc.kdc_md.mddc_devtype = MDDT_PCI; 558 559 pdcp -> pdc_kdc.kdc_externalize = pci_externalize; 560 pdcp -> pdc_kdc.kdc_internalize = pci_internalize; 561 562 pdcp -> pdc_kdc.kdc_datalen = PCI_EXTERNAL_LEN; 563 pdcp -> pdc_kdc.kdc_parentdata = &pdcp->pdc_pi; 564 pdcp -> pdc_kdc.kdc_state = DC_UNKNOWN; 565 pdcp -> pdc_kdc.kdc_description = name; 566 pdcp -> pdc_kdc.kdc_shutdown = dvp->pd_shutdown; 567 568 /* 569 ** And register this device 570 */ 571 572 dev_attach (&pdcp->pdc_kdc); 573 574 /* 575 ** attach device 576 ** may produce additional log messages, 577 ** i.e. when installing subdevices. 578 */ 579 580 (*dvp->pd_attach) (tag, unit); 581 582 /* 583 ** Special processing of certain classes 584 */ 585 586 data = pci_conf_read(tag, PCI_CLASS_REG); 587 588 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 589 struct pcicb *this, **link; 590 unsigned char primary, secondary, subordinate; 591 u_int command; 592 593 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 594 595 /* 596 ** get current configuration of the bridge. 597 */ 598 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 599 primary = PCI_PRIMARY_BUS_EXTRACT (data); 600 secondary = PCI_SECONDARY_BUS_EXTRACT(data); 601 subordinate = PCI_SUBORDINATE_BUS_EXTRACT(data); 602#ifndef PCI_QUIET 603 if (bootverbose) { 604 printf ("\tbridge from pci%d to pci%d through %d.\n", 605 primary, secondary, subordinate); 606 printf ("\tmapping regs: io:%08lx mem:%08lx pmem:%08lx", 607 pci_conf_read (tag, PCI_PCI_BRIDGE_IO_REG), 608 pci_conf_read (tag, PCI_PCI_BRIDGE_MEM_REG), 609 pci_conf_read (tag, PCI_PCI_BRIDGE_PMEM_REG)); 610 } 611#endif 612 /* 613 ** check for uninitialized bridge. 614 */ 615 if (secondary == 0 || secondary < primary || 616 pcicb->pcicb_bus != primary) 617 { 618 printf ("\tINCORRECTLY or NEVER CONFIGURED.\n"); 619 /* 620 ** disable this bridge 621 */ 622 pcibus->pb_write (tag, PCI_COMMAND_STATUS_REG, 623 0xffff0000); 624 secondary = 0; 625 subordinate = 0; 626 }; 627 628 /* 629 ** allocate bus descriptor for bus behind the bridge 630 */ 631 link = &pcicb->pcicb_down; 632 while (*link) link = &(*link)->pcicb_next; 633 634 this = malloc (sizeof (*this), M_DEVBUF, M_WAITOK); 635 636 /* 637 ** Initialize this descriptor so far. 638 ** (the initialization is completed just before 639 ** scanning the bus behind the bridge. 640 */ 641 bzero (this, sizeof(*this)); 642 this->pcicb_up = pcicb; 643 this->pcicb_bridge = tag; 644 this->pcicb_bus = secondary; 645 this->pcicb_subordinate = subordinate; 646 647 command = pci_conf_read(tag,PCI_COMMAND_STATUS_REG); 648 649 if (command & PCI_COMMAND_IO_ENABLE){ 650 /* 651 ** Bridge was configured by the bios. 652 ** Read out the mapped io region. 653 */ 654 u_int reg, data, mask; 655 656 reg = pci_conf_read (tag, 657 PCI_PCI_BRIDGE_IO_REG); 658 pci_conf_write(tag, 659 PCI_PCI_BRIDGE_IO_REG, 0xFFFF); 660 data = pci_conf_read (tag, 661 PCI_PCI_BRIDGE_IO_REG); 662 pci_conf_write(tag, 663 PCI_PCI_BRIDGE_IO_REG, reg & 0xffff); 664 665 mask = (0xFF00 ^ (data & 0xFF00)) | 0xFF; 666 667 this->pcicb_iobase = 668 PCI_PPB_IOBASE_EXTRACT (reg); 669 this->pcicb_iolimit = 670 PCI_PPB_IOLIMIT_EXTRACT(reg) | mask; 671 672 /* 673 ** Note the used io space. 674 */ 675 pci_register_io (pcicb, this->pcicb_iobase, 676 this->pcicb_iolimit); 677 678 }; 679 680 if (command & PCI_COMMAND_MEM_ENABLE) { 681 /* 682 ** Bridge was configured by the bios. 683 ** Read out the mapped memory regions. 684 */ 685 u_int reg, data, mask; 686 687 /* 688 ** non prefetchable memory 689 */ 690 reg = pci_conf_read (tag, 691 PCI_PCI_BRIDGE_MEM_REG); 692 pci_conf_write(tag, 693 PCI_PCI_BRIDGE_MEM_REG, 0xFFFFFFFF); 694 data = pci_conf_read (tag, 695 PCI_PCI_BRIDGE_MEM_REG); 696 pci_conf_write(tag, 697 PCI_PCI_BRIDGE_MEM_REG, reg); 698 699 mask = 0xFFFFFFFF ^ (data & 0xFFFF0000); 700 this->pcicb_membase = 701 PCI_PPB_MEMBASE_EXTRACT (reg); 702 this->pcicb_memlimit = 703 PCI_PPB_MEMLIMIT_EXTRACT(reg) | mask; 704 705 /* 706 ** Register used memory space. 707 */ 708 pci_register_memory (pcicb, 709 this->pcicb_membase, 710 this->pcicb_memlimit); 711 712 /* 713 ** prefetchable memory 714 */ 715 reg = pci_conf_read (tag, 716 PCI_PCI_BRIDGE_PMEM_REG); 717 pci_conf_write(tag, 718 PCI_PCI_BRIDGE_PMEM_REG, 0xFFFFFFFF); 719 data = pci_conf_read (tag, 720 PCI_PCI_BRIDGE_PMEM_REG); 721 pci_conf_write(tag, 722 PCI_PCI_BRIDGE_PMEM_REG, reg); 723 724 mask = 0xFFFFFFFF ^ (data & 0xFFFF0000); 725 this->pcicb_p_membase= 726 PCI_PPB_MEMBASE_EXTRACT (reg); 727 this->pcicb_p_memlimit= 728 PCI_PPB_MEMLIMIT_EXTRACT(reg) | mask; 729 730 /* 731 ** Register used memory space. 732 */ 733 pci_register_memory (pcicb, 734 this->pcicb_p_membase, 735 this->pcicb_p_memlimit); 736 } 737 738 /* 739 ** Link it in chain. 740 */ 741 *link=this; 742 743 /* 744 ** Update mapping info of parent bus. 745 */ 746 if (!pcicb->pcicb_bfrom||secondary< pcicb->pcicb_bfrom) 747 pcicb->pcicb_bfrom = secondary; 748 if (subordinate > pcicb->pcicb_bupto) 749 pcicb->pcicb_bupto = subordinate; 750 751 break; 752 } 753 } 754 755#ifndef PCI_QUIET 756 if (bootverbose) { 757 if (pcicb->pcicb_mamount) 758 printf ("%s%d: uses %d bytes of memory from %x upto %x.\n", 759 pcibus->pb_name, pcicb->pcicb_bus, 760 pcicb->pcicb_mamount, 761 pcicb->pcicb_mfrom, pcicb->pcicb_mupto); 762 if (pcicb->pcicb_pamount) 763 printf ("%s%d: uses %d bytes of I/O space from %x upto %x.\n", 764 pcibus->pb_name, pcicb->pcicb_bus, 765 pcicb->pcicb_pamount, 766 pcicb->pcicb_pfrom, pcicb->pcicb_pupto); 767 if (pcicb->pcicb_bfrom) 768 printf ("%s%d: subordinate busses from %x upto %x.\n", 769 pcibus->pb_name, pcicb->pcicb_bus, 770 pcicb->pcicb_bfrom, pcicb->pcicb_bupto); 771 } 772#endif 773} 774 775/*======================================================== 776** 777** pci_bridge_config() 778** 779** Configuration of a pci bridge. 780** 781**======================================================== 782*/ 783 784static void 785pci_bridge_config (void) 786{ 787 pcici_t tag; 788 struct pcicb* parent; 789 790 tag = pcicb->pcicb_bridge; 791 if (!tag.tag) return; 792 793 if (!pcicb->pcicb_bus) { 794 u_int data; 795 /* 796 ** Get the lowest available bus number. 797 */ 798 pcicb->pcicb_bus = ++pcibus0.pcicb_subordinate; 799 800 /* 801 ** and configure the bridge 802 */ 803 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 804 data = PCI_PRIMARY_BUS_INSERT(data, pcicb->pcicb_up->pcicb_bus); 805 data = PCI_SECONDARY_BUS_INSERT(data, pcicb->pcicb_bus); 806 data = PCI_SUBORDINATE_BUS_INSERT(data, pcicb->pcicb_bus); 807 pci_conf_write (tag, PCI_PCI_BRIDGE_BUS_REG, data); 808 809 /* 810 ** Propagate the new upper bus number limit. 811 */ 812 for (parent = pcicb->pcicb_up; parent != NULL; 813 parent = parent->pcicb_up) 814 { 815 if (parent->pcicb_subordinate >= pcicb->pcicb_bus) 816 continue; 817 parent->pcicb_subordinate = pcicb->pcicb_bus; 818 if (!parent->pcicb_bridge.tag) 819 continue; 820 data = pci_conf_read 821 (parent->pcicb_bridge, PCI_PCI_BRIDGE_BUS_REG); 822 data = PCI_SUBORDINATE_BUS_INSERT 823 (data, pcicb->pcicb_bus); 824 pci_conf_write (parent->pcicb_bridge, 825 PCI_PCI_BRIDGE_BUS_REG, data); 826 } 827 } 828 829 if (!pcicb->pcicb_membase) { 830 u_int size = 0x100000; 831 pcicb->pcicb_membase = pci_memalloc (pcicb->pcicb_up, 0, size); 832 if (pcicb->pcicb_membase) 833 pcicb->pcicb_memlimit = pcicb->pcicb_membase+size-1; 834 } 835} 836 837/*----------------------------------------------------------------- 838** 839** The following functions are provided for the device driver 840** to read/write the configuration space. 841** 842** pci_conf_read(): 843** Read a long word from the pci configuration space. 844** Requires a tag (from pcitag) and the register 845** number (should be a long word alligned one). 846** 847** pci_conf_write(): 848** Writes a long word to the pci configuration space. 849** Requires a tag (from pcitag), the register number 850** (should be a long word alligned one), and a value. 851** 852**----------------------------------------------------------------- 853*/ 854 855u_long 856pci_conf_read (pcici_t tag, u_long reg) 857{ 858 return (pcibus->pb_read (tag, reg)); 859} 860 861void 862pci_conf_write (pcici_t tag, u_long reg, u_long data) 863{ 864 pcibus->pb_write (tag, reg, data); 865} 866 867/*----------------------------------------------------------------------- 868** 869** Map device into port space. 870** 871** Actually the device should have been mapped by the bios. 872** This function only reads and verifies the value. 873** 874** PCI-Specification: 6.2.5.1: address maps 875** 876**----------------------------------------------------------------------- 877*/ 878 879int pci_map_port (pcici_t tag, u_long reg, u_short* pa) 880{ 881 unsigned data, ioaddr, iosize; 882 struct pcicb *link = pcicb; 883 884 /* 885 ** sanity check 886 */ 887 888 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 889 printf ("pci_map_port failed: bad register=0x%x\n", 890 (unsigned)reg); 891 return (0); 892 }; 893 894 /*if (pcicb->pcicb_flags & PCICB_NOIOSET) { 895 printf ("pci_map_port failed: pci%d has not been configured for I/O access\n", 896 pcicb->pcicb_bus); 897 return (0); 898 }*/ 899 900 /* 901 ** get size and type of port 902 ** 903 ** type is in the lowest two bits. 904 ** If device requires 2^n bytes, the next 905 ** n-2 bits are hardwired as 0. 906 */ 907 908 ioaddr = pcibus->pb_read (tag, reg) & PCI_MAP_IO_ADDRESS_MASK; 909 if (!ioaddr || ioaddr > 0xfffful) { 910 printf ("pci_map_port failed: not configured by bios.\n"); 911 return (0); 912 }; 913 914 pcibus->pb_write (tag, reg, 0xfffffffful); 915 data = pcibus->pb_read (tag, reg); 916 pcibus->pb_write (tag, reg, ioaddr); 917 918 if ((data & 0x03) != PCI_MAP_IO) { 919 printf ("pci_map_port failed: bad port type=0x%x\n", 920 (unsigned) data); 921 return (0); 922 }; 923 iosize = -(data & PCI_MAP_IO_ADDRESS_MASK); 924 if (ioaddr < pcicb->pcicb_iobase 925 || ioaddr + iosize > pcicb->pcicb_iolimit) { 926 printf ("pci_map_port failed: device's iorange 0x%x-0x%x " 927 "is incompatible with its bridge's range 0x%x-0x%x\n", 928 (unsigned) ioaddr, (unsigned) ioaddr + iosize - 1, 929 (unsigned) pcicb->pcicb_iobase, 930 (unsigned) pcicb->pcicb_iolimit); 931 return (0); 932 } 933 934#ifndef PCI_QUIET 935 if (bootverbose) 936 printf ("\treg%d: ioaddr=0x%x size=0x%x\n", 937 (unsigned) reg, (unsigned) ioaddr, (unsigned) iosize); 938#endif 939 /* 940 ** set the configuration register of and 941 ** return the address to the driver. 942 ** Make sure to enable each upstream bridge 943 ** so I/O and DMA can go all the way. 944 */ 945 946 for (;;) { 947 data = pcibus->pb_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 948 data |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 949 (void) pcibus->pb_write(tag, PCI_COMMAND_STATUS_REG, data); 950 if ((link = link->pcicb_up) == NULL) 951 break; 952 tag = link->pcicb_bridge; 953 } 954 955 *pa = ioaddr; 956 957 return (1); 958} 959 960/*----------------------------------------------------------------------- 961** 962** Map device into virtual and physical space 963** 964** Actually the device should have been mapped by the bios. 965** This function only reads and verifies the value. 966** 967** PCI-Specification: 6.2.5.1: address maps 968** 969**----------------------------------------------------------------------- 970*/ 971 972int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa) 973{ 974 struct pcicb *link = pcicb; 975 unsigned data ,paddr; 976 vm_size_t psize, poffs; 977 vm_offset_t vaddr; 978 979 /* 980 ** sanity check 981 */ 982 983 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 984 printf ("pci_map_mem failed: bad register=0x%x\n", 985 (unsigned)reg); 986 return (0); 987 }; 988 989 /* 990 ** save old mapping, get size and type of memory 991 ** 992 ** type is in the lowest four bits. 993 ** If device requires 2^n bytes, the next 994 ** n-4 bits are read as 0. 995 */ 996 997 paddr = pcibus->pb_read (tag, reg) & PCI_MAP_MEMORY_ADDRESS_MASK; 998 pcibus->pb_write (tag, reg, 0xfffffffful); 999 data = pcibus->pb_read (tag, reg); 1000 pcibus->pb_write (tag, reg, paddr); 1001 1002 /* 1003 ** check the type 1004 */ 1005 1006 if ((data & PCI_MAP_MEMORY_TYPE_MASK) != PCI_MAP_MEMORY_TYPE_32BIT) { 1007 printf ("pci_map_mem failed: bad memory type=0x%x\n", 1008 (unsigned) data); 1009 return (0); 1010 }; 1011 1012 /* 1013 ** get the size. 1014 */ 1015 1016 psize = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 1017 1018 if (!paddr || paddr == PCI_MAP_MEMORY_ADDRESS_MASK) { 1019 paddr = pci_memalloc (pcicb, 0, psize); 1020 if (!paddr) { 1021 printf ("pci_map_mem: not configured by bios.\n"); 1022 return (0); 1023 }; 1024 pci_register_memory (pcicb, paddr, paddr+psize-1); 1025 }; 1026 1027 if (paddr < pcicb->pcicb_membase || 1028 paddr + psize - 1 > pcicb->pcicb_memlimit) { 1029 printf ("pci_map_mem failed: device's memrange 0x%x-0x%x is " 1030 "incompatible with its bridge's memrange 0x%x-0x%x\n", 1031 (unsigned) paddr, 1032 (unsigned) (paddr + psize - 1), 1033 (unsigned) pcicb->pcicb_membase, 1034 (unsigned) pcicb->pcicb_memlimit); 1035/* return (0);*/ 1036/* ACHTUNG: Ist der Code richtig, wenn eine PCI-PCI-Bridge fuer 1037 * die PCI-Slots verwendet wird, aber die Onboard-Devices direkt 1038 * an der CPU-PCI-Bridge haengen (Siehe Compaq Prolinea Problem) ??? 1039 */ 1040 } 1041 pcibus->pb_write (tag, reg, paddr); 1042 1043 /* 1044 ** Truncate paddr to page boundary. 1045 ** (Or does pmap_mapdev the job?) 1046 */ 1047 1048 poffs = paddr - trunc_page (paddr); 1049 vaddr = (vm_offset_t) pmap_mapdev (paddr-poffs, psize+poffs); 1050 1051 if (!vaddr) return (0); 1052 1053 vaddr += poffs; 1054 1055#ifndef PCI_QUIET 1056 /* 1057 ** display values. 1058 */ 1059 1060 if (bootverbose) 1061 printf ("\treg%d: virtual=0x%lx physical=0x%lx size=0x%lx\n", 1062 (unsigned) reg, (u_long)vaddr, (u_long)paddr, (u_long)psize); 1063#endif 1064 /* 1065 ** set the configuration register and 1066 ** return the address to the driver 1067 ** Make sure to enable each upstream bridge 1068 ** so memory and DMA can go all the way. 1069 */ 1070 1071 for (;;) { 1072 data = pcibus->pb_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 1073 data |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1074 (void) pcibus->pb_write(tag, PCI_COMMAND_STATUS_REG, data); 1075 if ((link = link->pcicb_up) == NULL) 1076 break; 1077 tag = link->pcicb_bridge; 1078 } 1079 1080 *va = vaddr; 1081 *pa = paddr; 1082 1083 return (1); 1084} 1085 1086/*------------------------------------------------------------ 1087** 1088** Interface functions for the devconf module. 1089** 1090**------------------------------------------------------------ 1091*/ 1092 1093static int 1094pci_externalize (struct proc *p, struct kern_devconf *kdcp, void *u, size_t l) 1095{ 1096 struct pci_externalize_buffer buffer; 1097 struct pci_info * pip = kdcp->kdc_parentdata; 1098 pcici_t tag; 1099 int i; 1100 1101 if (l < sizeof buffer) { 1102 return ENOMEM; 1103 }; 1104 1105 tag = pcibus->pb_tag (pip->pi_bus, pip->pi_device, 0); 1106 1107 buffer.peb_pci_info = *pip; 1108 1109 for (i=0; i<PCI_EXT_CONF_LEN; i++) { 1110 buffer.peb_config[i] = pcibus->pb_read (tag, i*4); 1111 }; 1112 1113 return copyout(&buffer, u, sizeof buffer); 1114} 1115 1116 1117static int 1118pci_internalize (struct proc *p, struct kern_devconf *kdcp, void *u, size_t s) 1119{ 1120 return EOPNOTSUPP; 1121} 1122 1123/*----------------------------------------------------------------------- 1124** 1125** Pci meta interrupt handler 1126** 1127** This handler assumes level triggered interrupts. 1128** It's possible to build a kernel which handles shared 1129** edge triggered interrupts by the options "PCI_EDGE_INT". 1130** But there is a performance penalty. 1131** 1132** (Of course you can delete the #ifdef PCI_EDGE_INT bracketed 1133** code at all :-) :-) :-) 1134** 1135**----------------------------------------------------------------------- 1136*/ 1137 1138struct pci_int_desc* 1139 pci_int_desc [PCI_MAX_IRQ]; 1140 1141#ifndef NO_SHARED_IRQ 1142 1143static inline unsigned 1144splq (unsigned mask) 1145{ 1146 unsigned temp=cpl; 1147 cpl |= mask; 1148 return temp; 1149} 1150 1151static void 1152pci_int (int irq) 1153{ 1154 struct pci_int_desc * p; 1155 int c, s; 1156#ifdef PCI_EDGE_INT 1157 int i, n; 1158#endif 1159 if (irq<0 || irq >= PCI_MAX_IRQ) { 1160 printf ("pci_int: irq %d out of range, ignored\n", irq); 1161 return; 1162 }; 1163 1164#ifdef PCI_EDGE_INT 1165 for (i=0; i<1000; i++) { 1166 n = 0; 1167#endif 1168 for (p = pci_int_desc[irq]; p!=NULL; p=p->pcid_next) { 1169 s = splq (*p->pcid_maskptr); 1170 c= (*p->pcid_handler) (p->pcid_argument); 1171 p-> pcid_tally += c; 1172 splx (s); 1173#ifdef PCI_EDGE_INT 1174 n += c; 1175#endif 1176#if 0 1177 if (c && p->pcid_tally<20) 1178 printf ("PCI_INT: irq=%d h=%p cpl o=%x n=%x val=%d\n", 1179 irq, p->pcid_handler, s, cpl, c); 1180#endif 1181 }; 1182#ifdef PCI_EDGE_INT 1183 if (!n) return; 1184 }; 1185 printf ("pci_int(%d): permanent interrupt request.\n", irq); 1186#endif 1187} 1188#endif 1189 1190/*----------------------------------------------------------------------- 1191** 1192** Auxiliary function for interrupt (un)mapping. 1193** 1194**----------------------------------------------------------------------- 1195*/ 1196 1197static u_int 1198getirq (pcici_t tag) 1199{ 1200 u_int irq; 1201 1202 irq = PCI_INTERRUPT_LINE_EXTRACT( 1203 pcibus->pb_read (tag, PCI_INTERRUPT_REG)); 1204 1205 if (irq <= 0) { 1206 printf ("\tint line register not set by bios\n"); 1207 return (0); 1208 } 1209 1210 if (irq >= pcibus->pb_maxirq || irq >= PCI_MAX_IRQ) { 1211 printf ("\tirq %d invalid.\n", irq); 1212 return (0); 1213 } 1214 1215 return (irq); 1216} 1217 1218static struct pci_int_desc ** 1219getintdescbytag (u_int irq, pcici_t tag) 1220{ 1221 struct pci_int_desc *p, **pp; 1222 1223 pp=&pci_int_desc[irq]; 1224 while (((p=*pp)) && !sametag(p->pcid_tag,tag)) 1225 pp=&p->pcid_next; 1226 1227 if (!p) return (NULL); 1228 1229 return (pp); 1230} 1231 1232static struct pci_int_desc * 1233getintdescbymptr (u_int irq, unsigned * mptr) 1234{ 1235 struct pci_int_desc *p; 1236 1237 for (p=pci_int_desc[irq];p;p=p->pcid_next) 1238 if (p->pcid_maskptr == mptr) break; 1239 return (p); 1240} 1241 1242/*----------------------------------------------------------------------- 1243** 1244** Map pci interrupt. 1245** 1246**----------------------------------------------------------------------- 1247*/ 1248 1249static unsigned pci_mask0 = 0; 1250 1251int pci_map_int (pcici_t tag, int(*func)(), void* arg, unsigned* maskptr) 1252{ 1253 u_int irq; 1254 int result, oldspl; 1255 unsigned mask; 1256 struct pci_int_desc *tail, *mdp=NULL, *new=NULL; 1257 1258 /* 1259 ** Get irq line from configuration space, 1260 ** and check for consistency. 1261 */ 1262 1263 irq = getirq (tag); 1264 if (irq >= PCI_MAX_IRQ) { 1265 printf ("\tillegal irq %d.\n", irq); 1266 return (0); 1267 }; 1268 mask= 1ul << irq; 1269 1270 /* 1271 ** disable this interrupt. 1272 */ 1273 1274 oldspl = splq (mask); 1275 1276 /* 1277 ** If handler for this tag already installed, 1278 ** remove it first. 1279 */ 1280 1281 if (getintdescbytag (irq, tag) != NULL) 1282 pci_unmap_int (tag); 1283 1284 /* 1285 ** If this irq not yet included in the mask, include it. 1286 */ 1287 1288 mdp = getintdescbymptr (irq, maskptr); 1289 if (!mdp) { 1290 result = pcibus->pb_imaskinc (irq, maskptr); 1291 if (result) 1292 goto conflict; 1293 }; 1294 1295 /* 1296 ** Allocate descriptor and initialize it. 1297 */ 1298 1299 tail = pci_int_desc[irq]; 1300 1301 new = malloc (sizeof (*new), M_DEVBUF, M_WAITOK); 1302 bzero (new, sizeof (*new)); 1303 1304 new->pcid_next = tail; 1305 new->pcid_tag = tag; 1306 new->pcid_handler = func; 1307 new->pcid_argument = arg; 1308 new->pcid_maskptr = maskptr; 1309 new->pcid_tally = 0; 1310 new->pcid_mask = mask; 1311 1312 /* 1313 ** If first handler: install it. 1314 ** If second handler: install shared-int-handler. 1315 */ 1316 1317 if (!tail) { 1318 /* 1319 ** first handler for this irq. 1320 */ 1321 1322 result = pcibus->pb_iattach 1323 (irq, (void(*)()) func, (int) arg, maskptr); 1324 if (result) goto conflict; 1325 1326#ifdef NO_SHARED_IRQ 1327 } else goto conflict; 1328#else 1329 } else if (!tail->pcid_next) { 1330 /* 1331 ** Second handler for this irq. 1332 */ 1333 1334 if (bootverbose) 1335 printf ("\tusing shared irq %d.\n", irq); 1336 1337 /* 1338 ** replace old handler by shared-int-handler. 1339 */ 1340 1341 result = pcibus->pb_idetach (irq,(void(*)())tail->pcid_handler); 1342 if (result) 1343 printf ("\tCANNOT DETACH INT HANDLER.\n"); 1344 1345 result = pcibus->pb_iattach (irq, pci_int, irq, &pci_mask0); 1346 if (result) { 1347 printf ("\tCANNOT ATTACH SHARED INT HANDLER.\n"); 1348 goto fail; 1349 }; 1350 } 1351#endif 1352 /* 1353 ** Link new descriptor, reenable ints and done. 1354 */ 1355 1356 pci_int_desc[irq] = new; 1357 splx (oldspl); 1358 return (1); 1359 1360 /* 1361 ** Handle some problems. 1362 */ 1363 1364conflict: 1365 printf ("\tirq %d already in use.\n", irq); 1366fail: 1367 /* 1368 ** If descriptor allocated, free it. 1369 ** If included in mask, remove it. 1370 */ 1371 1372 if (free) free (new, M_DEVBUF); 1373 if (!mdp) (void) pcibus->pb_imaskexc (irq, maskptr); 1374 splx (oldspl); 1375 return (0); 1376} 1377 1378/*----------------------------------------------------------------------- 1379** 1380** Unmap pci interrupt. 1381** 1382**----------------------------------------------------------------------- 1383*/ 1384 1385int pci_unmap_int (pcici_t tag) 1386{ 1387 int result, oldspl; 1388 struct pci_int_desc *this, **hook, *tail; 1389 unsigned irq; 1390 1391 /* 1392 ** Get irq line from configuration space, 1393 ** and check for consistency. 1394 */ 1395 1396 irq = getirq (tag); 1397 if (irq >= PCI_MAX_IRQ) { 1398 printf ("\tillegal irq %d.\n", irq); 1399 return (0); 1400 }; 1401 1402 /* 1403 ** Search and unlink interrupt descriptor. 1404 */ 1405 1406 hook = getintdescbytag (irq, tag); 1407 if (hook == NULL) { 1408 printf ("\tno irq %d handler for pci %x\n", 1409 irq, tag.tag); 1410 return (0); 1411 }; 1412 1413 this = *hook; 1414 *hook= this->pcid_next; 1415 1416 /* 1417 ** Message 1418 */ 1419 1420 printf ("\tirq %d handler %p(%p) unmapped for pci %x after %d ints.\n", 1421 irq, this->pcid_handler, this->pcid_argument, 1422 this->pcid_tag.tag, this->pcid_tally); 1423 1424 /* 1425 ** If this irq no longer included in the mask, remove it. 1426 */ 1427 1428 if (!getintdescbymptr (irq, this->pcid_maskptr)) 1429 (void) pcibus->pb_imaskexc (irq, this->pcid_maskptr); 1430 1431 tail = pci_int_desc[irq]; 1432 1433 if (tail == NULL) { 1434 1435 /* 1436 ** Remove the old handler. 1437 */ 1438 1439 result = pcibus->pb_idetach (irq,(void(*)())this->pcid_handler); 1440 if (result) 1441 printf ("\tirq %d: cannot remove handler.\n", irq); 1442 1443 } else if (tail->pcid_next == NULL) { 1444 1445 /* 1446 ** Remove the shared int handler. 1447 ** Install the last remaining handler. 1448 */ 1449 1450 oldspl = splq (1ul << irq); 1451 1452 result = pcibus->pb_idetach (irq, pci_int); 1453 if (result) 1454 printf ("\tirq %d: cannot remove handler.\n", irq); 1455 1456 result = pcibus->pb_iattach (irq, 1457 (void(*)()) tail->pcid_handler, 1458 (int) tail->pcid_argument, 1459 tail->pcid_maskptr); 1460 1461 if (result) 1462 printf ("\tirq %d: cannot install handler.\n", irq); 1463 1464 splx (oldspl); 1465 }; 1466 1467 free (this, M_DEVBUF); 1468 return (1); 1469} 1470 1471/*----------------------------------------------------------- 1472** 1473** Display of unknown devices. 1474** 1475**----------------------------------------------------------- 1476*/ 1477struct vt { 1478 u_short ident; 1479 char* name; 1480}; 1481 1482static struct vt VendorTable[] = { 1483 {0x0e11, "Compaq"}, 1484 {0x1000, "NCR/Symbios"}, 1485 {0x1002, "ATI Technologies Inc."}, 1486 {0x1004, "VLSI"}, 1487 {0x100B, "National Semiconductor"}, 1488 {0x100E, "Weitek"}, 1489 {0x1011, "Digital Equipment Corporation"}, 1490 {0x1013, "Cirrus Logic"}, 1491 {0x101A, "NCR"}, 1492 {0x1022, "AMD"}, 1493 {0x102B, "Matrox"}, 1494 {0x102C, "Chips & Technologies"}, 1495 {0x1039, "Silicon Integrated Systems"}, 1496 {0x1042, "SMC"}, 1497 {0x1044, "DPT"}, 1498 {0x1045, "OPTI"}, 1499 {0x104B, "Bus Logic"}, 1500 {0x1060, "UMC"}, 1501 {0x1080, "Contaq"}, 1502 {0x1095, "CMD"}, 1503 {0x1106, "VIA Technologies"}, 1504 {0x5333, "S3 Inc."}, 1505 {0x8086, "Intel Corporation"}, 1506 {0x9004, "Adaptec"}, 1507 {0,0} 1508}; 1509 1510typedef struct { 1511 const char subclass; 1512 const char *name; 1513} subclass_name; 1514 1515/* 0x00 prehistoric subclasses */ 1516static const subclass_name old_subclasses[] = 1517{ 1518 { 0x00, "misc" }, 1519 { 0x01, "vga" }, 1520 { 0x00, NULL } 1521}; 1522 1523/* 0x01 mass storage subclasses */ 1524static const subclass_name storage_subclasses[] = 1525{ 1526 { 0x00, "scsi" }, 1527 { 0x01, "ide" }, 1528 { 0x02, "floppy"}, 1529 { 0x03, "ipi" }, 1530 { 0x80, "misc" }, 1531 { 0x00, NULL } 1532}; 1533 1534/* 0x02 network subclasses */ 1535static const subclass_name network_subclasses[] = 1536{ 1537 { 0x00, "ethernet" }, 1538 { 0x01, "tokenring" }, 1539 { 0x02, "fddi" }, 1540 { 0x80, "misc" }, 1541 { 0x00, NULL } 1542}; 1543 1544/* 0x03 display subclasses */ 1545static const subclass_name display_subclasses[] = 1546{ 1547 { 0x00, "vga" }, 1548 { 0x01, "xga" }, 1549 { 0x80, "misc" }, 1550 { 0x00, NULL } 1551}; 1552 1553/* 0x04 multimedia subclasses */ 1554static const subclass_name multimedia_subclasses[] = 1555{ 1556 { 0x00, "video" }, 1557 { 0x01, "audio" }, 1558 { 0x80, "misc" }, 1559 { 0x00, NULL } 1560}; 1561 1562/* 0x05 memory subclasses */ 1563static const subclass_name memory_subclasses[] = 1564{ 1565 { 0x00, "ram" }, 1566 { 0x01, "flash" }, 1567 { 0x80, "misc" }, 1568 { 0x00, NULL } 1569}; 1570 1571/* 0x06 bridge subclasses */ 1572static const subclass_name bridge_subclasses[] = 1573{ 1574 { 0x00, "host" }, 1575 { 0x01, "isa" }, 1576 { 0x02, "eisa" }, 1577 { 0x03, "mc" }, 1578 { 0x04, "pci" }, 1579 { 0x05, "pcmcia"}, 1580 { 0x80, "misc" }, 1581 { 0x00, NULL } 1582}; 1583 1584static const subclass_name *const subclasses[] = { 1585 old_subclasses, 1586 storage_subclasses, 1587 network_subclasses, 1588 display_subclasses, 1589 multimedia_subclasses, 1590 memory_subclasses, 1591 bridge_subclasses, 1592}; 1593 1594static const char *const majclasses[] = { 1595 "old", 1596 "storage", 1597 "network", 1598 "display", 1599 "multimedia", 1600 "memory", 1601 "bridge" 1602}; 1603 1604 1605void not_supported (pcici_t tag, u_long type) 1606{ 1607 u_char reg; 1608 u_long data; 1609 struct vt * vp; 1610 1611 /* 1612 ** lookup the names. 1613 */ 1614 1615 for (vp=VendorTable; vp->ident; vp++) 1616 if (vp->ident == (type & 0xffff)) 1617 break; 1618 1619 /* 1620 ** and display them. 1621 */ 1622 1623 if (vp->ident) printf (vp->name); 1624 else printf ("vendor=0x%04lx", type & 0xffff); 1625 1626 printf (", device=0x%04lx", type >> 16); 1627 1628 data = (pcibus->pb_read(tag, PCI_CLASS_REG) >> 24) & 0xff; 1629 if (data < sizeof(majclasses) / sizeof(majclasses[0])) 1630 printf(", class=%s", majclasses[data]); 1631 if (data < sizeof(subclasses) / sizeof(subclasses[0])) { 1632 const subclass_name *p = subclasses[data]; 1633 1634 data = (pcibus->pb_read(tag, PCI_CLASS_REG) >> 16) & 0xff; 1635 while (p->name && (p->subclass != data)) 1636 p++; 1637 if (p->name) { 1638 printf(" (%s)", p->name); 1639 } else { 1640 printf(" (unknown subclass 0x%02lx)", data); 1641 } 1642 } 1643 1644 printf (" [no driver assigned]\n"); 1645 1646 if (bootverbose) { 1647 for (reg=PCI_MAP_REG_START; reg<PCI_MAP_REG_END; reg+=4) { 1648 data = pcibus->pb_read (tag, reg); 1649 if ((data&~7)==0) continue; 1650 switch (data&7) { 1651 1652 case 1: 1653 case 5: 1654 printf (" map(%x): io(%lx)\n", 1655 reg, data & ~3); 1656 break; 1657 case 0: 1658 printf (" map(%x): mem32(%lx)\n", 1659 reg, data & ~7); 1660 break; 1661 case 2: 1662 printf (" map(%x): mem20(%lx)\n", 1663 reg, data & ~7); 1664 break; 1665 case 4: 1666 printf (" map(%x): mem64(%lx)\n", 1667 reg, data & ~7); 1668 break; 1669 } 1670 } 1671 } 1672} 1673#endif /* NPCI */ 1674