pci.c revision 102919
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 102919 2002-09-04 03:13:16Z jhb $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static u_int32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 69 pcicfgregs *cfg); 70static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 71 72static int pci_porten(device_t pcib, int b, int s, int f); 73static int pci_memen(device_t pcib, int b, int s, int f); 74static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 75 struct resource_list *rl); 76static void pci_add_resources(device_t pcib, device_t dev); 77static int pci_probe(device_t dev); 78static int pci_attach(device_t dev); 79static void pci_load_vendor_data(void); 80static int pci_describe_parse_line(char **ptr, int *vendor, 81 int *device, char **desc); 82static char *pci_describe_device(device_t dev); 83static int pci_modevent(module_t mod, int what, void *arg); 84 85static device_method_t pci_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, pci_probe), 88 DEVMETHOD(device_attach, pci_attach), 89 DEVMETHOD(device_shutdown, bus_generic_shutdown), 90 DEVMETHOD(device_suspend, bus_generic_suspend), 91 DEVMETHOD(device_resume, bus_generic_resume), 92 93 /* Bus interface */ 94 DEVMETHOD(bus_print_child, pci_print_child), 95 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 96 DEVMETHOD(bus_read_ivar, pci_read_ivar), 97 DEVMETHOD(bus_write_ivar, pci_write_ivar), 98 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 99 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 100 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 101 102 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 103 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 104 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 105 DEVMETHOD(bus_delete_resource, pci_delete_resource), 106 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 107 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 108 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 109 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 110 111 /* PCI interface */ 112 DEVMETHOD(pci_read_config, pci_read_config_method), 113 DEVMETHOD(pci_write_config, pci_write_config_method), 114 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 115 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 116 DEVMETHOD(pci_enable_io, pci_enable_io_method), 117 DEVMETHOD(pci_disable_io, pci_disable_io_method), 118 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 119 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 120 121 { 0, 0 } 122}; 123 124static driver_t pci_driver = { 125 "pci", 126 pci_methods, 127 0, /* no softc */ 128}; 129 130devclass_t pci_devclass; 131DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 132MODULE_VERSION(pci, 1); 133 134static char *pci_vendordata; 135static size_t pci_vendordata_size; 136 137 138struct pci_quirk { 139 u_int32_t devid; /* Vendor/device of the card */ 140 int type; 141#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 142 int arg1; 143 int arg2; 144}; 145 146struct pci_quirk pci_quirks[] = { 147 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 148 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 149 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 150 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 151 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 153 { 0 } 154}; 155 156/* map register information */ 157#define PCI_MAPMEM 0x01 /* memory map */ 158#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 159#define PCI_MAPPORT 0x04 /* port map */ 160 161struct devlist pci_devq; 162u_int32_t pci_generation; 163u_int32_t pci_numdevs = 0; 164 165/* sysctl vars */ 166SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 167 168int pci_enable_io_modes = 1; 169TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 170SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 171 &pci_enable_io_modes, 1, 172 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 173enable these bits correctly. We'd like to do this all the time, but there\n\ 174are some peripherals that this causes problems with."); 175 176/* Find a device_t by bus/slot/function */ 177 178device_t 179pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 180{ 181 struct pci_devinfo *dinfo; 182 183 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 184 if ((dinfo->cfg.bus == bus) && 185 (dinfo->cfg.slot == slot) && 186 (dinfo->cfg.func == func)) { 187 return (dinfo->cfg.dev); 188 } 189 } 190 191 return (NULL); 192} 193 194/* Find a device_t by vendor/device ID */ 195 196device_t 197pci_find_device (u_int16_t vendor, u_int16_t device) 198{ 199 struct pci_devinfo *dinfo; 200 201 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 202 if ((dinfo->cfg.vendor == vendor) && 203 (dinfo->cfg.device == device)) { 204 return (dinfo->cfg.dev); 205 } 206 } 207 208 return (NULL); 209} 210 211/* return base address of memory or port map */ 212 213static u_int32_t 214pci_mapbase(unsigned mapreg) 215{ 216 int mask = 0x03; 217 if ((mapreg & 0x01) == 0) 218 mask = 0x0f; 219 return (mapreg & ~mask); 220} 221 222/* return map type of memory or port map */ 223 224static int 225pci_maptype(unsigned mapreg) 226{ 227 static u_int8_t maptype[0x10] = { 228 PCI_MAPMEM, PCI_MAPPORT, 229 PCI_MAPMEM, 0, 230 PCI_MAPMEM, PCI_MAPPORT, 231 0, 0, 232 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 233 PCI_MAPMEM|PCI_MAPMEMP, 0, 234 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 235 0, 0, 236 }; 237 238 return maptype[mapreg & 0x0f]; 239} 240 241/* return log2 of map size decoded for memory or port map */ 242 243static int 244pci_mapsize(unsigned testval) 245{ 246 int ln2size; 247 248 testval = pci_mapbase(testval); 249 ln2size = 0; 250 if (testval != 0) { 251 while ((testval & 1) == 0) 252 { 253 ln2size++; 254 testval >>= 1; 255 } 256 } 257 return (ln2size); 258} 259 260/* return log2 of address range supported by map register */ 261 262static int 263pci_maprange(unsigned mapreg) 264{ 265 int ln2range = 0; 266 switch (mapreg & 0x07) { 267 case 0x00: 268 case 0x01: 269 case 0x05: 270 ln2range = 32; 271 break; 272 case 0x02: 273 ln2range = 20; 274 break; 275 case 0x04: 276 ln2range = 64; 277 break; 278 } 279 return (ln2range); 280} 281 282/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 283 284static void 285pci_fixancient(pcicfgregs *cfg) 286{ 287 if (cfg->hdrtype != 0) 288 return; 289 290 /* PCI to PCI bridges use header type 1 */ 291 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 292 cfg->hdrtype = 1; 293} 294 295/* extract header type specific config data */ 296 297static void 298pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 299{ 300#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 301 switch (cfg->hdrtype) { 302 case 0: 303 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 304 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 305 cfg->nummaps = PCI_MAXMAPS_0; 306 break; 307 case 1: 308 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 309 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 310 cfg->nummaps = PCI_MAXMAPS_1; 311 break; 312 case 2: 313 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 314 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 315 cfg->nummaps = PCI_MAXMAPS_2; 316 break; 317 } 318#undef REG 319} 320 321/* read configuration header into pcicfgregs structure */ 322 323struct pci_devinfo * 324pci_read_device(device_t pcib, int b, int s, int f, size_t size) 325{ 326#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 327 pcicfgregs *cfg = NULL; 328 struct pci_devinfo *devlist_entry; 329 struct devlist *devlist_head; 330 331 devlist_head = &pci_devq; 332 333 devlist_entry = NULL; 334 335 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 336 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 337 if (devlist_entry == NULL) 338 return (NULL); 339 340 cfg = &devlist_entry->cfg; 341 342 cfg->bus = b; 343 cfg->slot = s; 344 cfg->func = f; 345 cfg->vendor = REG(PCIR_VENDOR, 2); 346 cfg->device = REG(PCIR_DEVICE, 2); 347 cfg->cmdreg = REG(PCIR_COMMAND, 2); 348 cfg->statreg = REG(PCIR_STATUS, 2); 349 cfg->baseclass = REG(PCIR_CLASS, 1); 350 cfg->subclass = REG(PCIR_SUBCLASS, 1); 351 cfg->progif = REG(PCIR_PROGIF, 1); 352 cfg->revid = REG(PCIR_REVID, 1); 353 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 354 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 355 cfg->lattimer = REG(PCIR_LATTIMER, 1); 356 cfg->intpin = REG(PCIR_INTPIN, 1); 357 cfg->intline = REG(PCIR_INTLINE, 1); 358 359 cfg->mingnt = REG(PCIR_MINGNT, 1); 360 cfg->maxlat = REG(PCIR_MAXLAT, 1); 361 362 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 363 cfg->hdrtype &= ~PCIM_MFDEV; 364 365 pci_fixancient(cfg); 366 pci_hdrtypedata(pcib, b, s, f, cfg); 367 368 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 369 pci_read_extcap(pcib, cfg); 370 371 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 372 373 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 374 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 375 devlist_entry->conf.pc_sel.pc_func = cfg->func; 376 devlist_entry->conf.pc_hdr = cfg->hdrtype; 377 378 devlist_entry->conf.pc_subvendor = cfg->subvendor; 379 devlist_entry->conf.pc_subdevice = cfg->subdevice; 380 devlist_entry->conf.pc_vendor = cfg->vendor; 381 devlist_entry->conf.pc_device = cfg->device; 382 383 devlist_entry->conf.pc_class = cfg->baseclass; 384 devlist_entry->conf.pc_subclass = cfg->subclass; 385 devlist_entry->conf.pc_progif = cfg->progif; 386 devlist_entry->conf.pc_revid = cfg->revid; 387 388 pci_numdevs++; 389 pci_generation++; 390 } 391 return (devlist_entry); 392#undef REG 393} 394 395static void 396pci_read_extcap(device_t pcib, pcicfgregs *cfg) 397{ 398#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 399 int ptr, nextptr, ptrptr; 400 401 switch (cfg->hdrtype) { 402 case 0: 403 ptrptr = 0x34; 404 break; 405 case 2: 406 ptrptr = 0x14; 407 break; 408 default: 409 return; /* no extended capabilities support */ 410 } 411 nextptr = REG(ptrptr, 1); /* sanity check? */ 412 413 /* 414 * Read capability entries. 415 */ 416 while (nextptr != 0) { 417 /* Sanity check */ 418 if (nextptr > 255) { 419 printf("illegal PCI extended capability offset %d\n", 420 nextptr); 421 return; 422 } 423 /* Find the next entry */ 424 ptr = nextptr; 425 nextptr = REG(ptr + 1, 1); 426 427 /* Process this entry */ 428 switch (REG(ptr, 1)) { 429 case 0x01: /* PCI power management */ 430 if (cfg->pp_cap == 0) { 431 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 432 cfg->pp_status = ptr + PCIR_POWER_STATUS; 433 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 434 if ((nextptr - ptr) > PCIR_POWER_DATA) 435 cfg->pp_data = ptr + PCIR_POWER_DATA; 436 } 437 break; 438 default: 439 break; 440 } 441 } 442#undef REG 443} 444 445/* free pcicfgregs structure and all depending data structures */ 446 447int 448pci_freecfg(struct pci_devinfo *dinfo) 449{ 450 struct devlist *devlist_head; 451 452 devlist_head = &pci_devq; 453 454 /* XXX this hasn't been tested */ 455 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 456 free(dinfo, M_DEVBUF); 457 458 /* increment the generation count */ 459 pci_generation++; 460 461 /* we're losing one device */ 462 pci_numdevs--; 463 return (0); 464} 465 466/* 467 * PCI power manangement 468 */ 469int 470pci_set_powerstate_method(device_t dev, device_t child, int state) 471{ 472 struct pci_devinfo *dinfo = device_get_ivars(child); 473 pcicfgregs *cfg = &dinfo->cfg; 474 u_int16_t status; 475 int result; 476 477 if (cfg->pp_cap != 0) { 478 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 479 result = 0; 480 switch (state) { 481 case PCI_POWERSTATE_D0: 482 status |= PCIM_PSTAT_D0; 483 break; 484 case PCI_POWERSTATE_D1: 485 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 486 status |= PCIM_PSTAT_D1; 487 } else { 488 result = EOPNOTSUPP; 489 } 490 break; 491 case PCI_POWERSTATE_D2: 492 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 493 status |= PCIM_PSTAT_D2; 494 } else { 495 result = EOPNOTSUPP; 496 } 497 break; 498 case PCI_POWERSTATE_D3: 499 status |= PCIM_PSTAT_D3; 500 break; 501 default: 502 result = EINVAL; 503 } 504 if (result == 0) 505 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 506 } else { 507 result = ENXIO; 508 } 509 return(result); 510} 511 512int 513pci_get_powerstate_method(device_t dev, device_t child) 514{ 515 struct pci_devinfo *dinfo = device_get_ivars(child); 516 pcicfgregs *cfg = &dinfo->cfg; 517 u_int16_t status; 518 int result; 519 520 if (cfg->pp_cap != 0) { 521 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 522 switch (status & PCIM_PSTAT_DMASK) { 523 case PCIM_PSTAT_D0: 524 result = PCI_POWERSTATE_D0; 525 break; 526 case PCIM_PSTAT_D1: 527 result = PCI_POWERSTATE_D1; 528 break; 529 case PCIM_PSTAT_D2: 530 result = PCI_POWERSTATE_D2; 531 break; 532 case PCIM_PSTAT_D3: 533 result = PCI_POWERSTATE_D3; 534 break; 535 default: 536 result = PCI_POWERSTATE_UNKNOWN; 537 break; 538 } 539 } else { 540 /* No support, device is always at D0 */ 541 result = PCI_POWERSTATE_D0; 542 } 543 return(result); 544} 545 546/* 547 * Some convenience functions for PCI device drivers. 548 */ 549 550static __inline void 551pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 552{ 553 u_int16_t command; 554 555 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 556 command |= bit; 557 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 558} 559 560static __inline void 561pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 562{ 563 u_int16_t command; 564 565 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 566 command &= ~bit; 567 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 568} 569 570void 571pci_enable_busmaster_method(device_t dev, device_t child) 572{ 573 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 574} 575 576void 577pci_disable_busmaster_method(device_t dev, device_t child) 578{ 579 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 580} 581 582void 583pci_enable_io_method(device_t dev, device_t child, int space) 584{ 585 switch(space) { 586 case SYS_RES_IOPORT: 587 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN); 588 break; 589 case SYS_RES_MEMORY: 590 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN); 591 break; 592 } 593} 594 595void 596pci_disable_io_method(device_t dev, device_t child, int space) 597{ 598 switch(space) { 599 case SYS_RES_IOPORT: 600 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN); 601 break; 602 case SYS_RES_MEMORY: 603 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN); 604 break; 605 } 606} 607 608/* 609 * New style pci driver. Parent device is either a pci-host-bridge or a 610 * pci-pci-bridge. Both kinds are represented by instances of pcib. 611 */ 612 613void 614pci_print_verbose(struct pci_devinfo *dinfo) 615{ 616 if (bootverbose) { 617 pcicfgregs *cfg = &dinfo->cfg; 618 619 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 620 cfg->vendor, cfg->device, cfg->revid); 621 printf("\tbus=%d, slot=%d, func=%d\n", 622 cfg->bus, cfg->slot, cfg->func); 623 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 624 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 625 cfg->mfdev); 626#ifdef PCI_DEBUG 627 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 628 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 629 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 630 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 631 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 632#endif /* PCI_DEBUG */ 633 if (cfg->intpin > 0) 634 printf("\tintpin=%c, irq=%d\n", 635 cfg->intpin +'a' -1, cfg->intline); 636 if (cfg->pp_cap) { 637 u_int16_t status; 638 639 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 640 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 641 cfg->pp_cap & PCIM_PCAP_SPEC, 642 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 643 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 644 status & PCIM_PSTAT_DMASK); 645 } 646 } 647} 648 649static int 650pci_porten(device_t pcib, int b, int s, int f) 651{ 652 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 653 & PCIM_CMD_PORTEN) != 0; 654} 655 656static int 657pci_memen(device_t pcib, int b, int s, int f) 658{ 659 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 660 & PCIM_CMD_MEMEN) != 0; 661} 662 663/* 664 * Add a resource based on a pci map register. Return 1 if the map 665 * register is a 32bit map register or 2 if it is a 64bit register. 666 */ 667static int 668pci_add_map(device_t pcib, int b, int s, int f, int reg, 669 struct resource_list *rl) 670{ 671 u_int32_t map; 672 u_int64_t base; 673 u_int8_t ln2size; 674 u_int8_t ln2range; 675 u_int32_t testval; 676 u_int16_t cmd; 677 int type; 678 679 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 680 681 if (map == 0 || map == 0xffffffff) 682 return (1); /* skip invalid entry */ 683 684 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 685 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 686 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 687 688 base = pci_mapbase(map); 689 if (pci_maptype(map) & PCI_MAPMEM) 690 type = SYS_RES_MEMORY; 691 else 692 type = SYS_RES_IOPORT; 693 ln2size = pci_mapsize(testval); 694 ln2range = pci_maprange(testval); 695 if (ln2range == 64) { 696 /* Read the other half of a 64bit map register */ 697 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 698 } 699 700 if (bootverbose) { 701 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 702 reg, pci_maptype(map), ln2range, 703 (unsigned int) base, ln2size); 704 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 705 printf(", port disabled\n"); 706 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 707 printf(", memory disabled\n"); 708 else 709 printf(", enabled\n"); 710 } 711 712 /* 713 * This code theoretically does the right thing, but has 714 * undesirable side effects in some cases where 715 * peripherals respond oddly to having these bits 716 * enabled. Leave them alone by default. 717 */ 718 if (pci_enable_io_modes) { 719 /* Turn on resources that have been left off by a lazy BIOS */ 720 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 721 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 722 cmd |= PCIM_CMD_PORTEN; 723 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 724 } 725 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 726 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 727 cmd |= PCIM_CMD_MEMEN; 728 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 729 } 730 } else { 731 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 732 return (1); 733 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 734 return (1); 735 } 736 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1, 737 (1 << ln2size)); 738 739 return ((ln2range == 64) ? 2 : 1); 740} 741 742static void 743pci_add_resources(device_t pcib, device_t dev) 744{ 745 struct pci_devinfo *dinfo = device_get_ivars(dev); 746 pcicfgregs *cfg = &dinfo->cfg; 747 struct resource_list *rl = &dinfo->resources; 748 struct pci_quirk *q; 749 int b, i, f, s; 750 751 b = cfg->bus; 752 s = cfg->slot; 753 f = cfg->func; 754 for (i = 0; i < cfg->nummaps;) { 755 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 756 } 757 758 for (q = &pci_quirks[0]; q->devid; q++) { 759 if (q->devid == ((cfg->device << 16) | cfg->vendor) 760 && q->type == PCI_QUIRK_MAP_REG) 761 pci_add_map(pcib, b, s, f, q->arg1, rl); 762 } 763 764 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 765#ifdef __ia64__ 766 /* 767 * Re-route interrupts on ia64 so that we can get the 768 * I/O SAPIC interrupt numbers (the BIOS leaves legacy 769 * PIC interrupt numbers in the intline registers). 770 */ 771 cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, dev, cfg->intpin); 772#endif 773 resource_list_add(rl, SYS_RES_IRQ, 0, cfg->intline, 774 cfg->intline, 1); 775 } 776} 777 778void 779pci_add_children(device_t dev, int busno, size_t dinfo_size) 780{ 781 device_t pcib = device_get_parent(dev); 782 struct pci_devinfo *dinfo; 783 int maxslots; 784 int s, f, pcifunchigh; 785 786 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 787 ("dinfo_size too small")); 788 maxslots = PCIB_MAXSLOTS(pcib); 789 for (s = 0; s <= maxslots; s++) { 790 pcifunchigh = 0; 791 for (f = 0; f <= pcifunchigh; f++) { 792 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 793 if (dinfo != NULL) { 794 if (dinfo->cfg.mfdev) 795 pcifunchigh = PCI_FUNCMAX; 796 pci_add_child(dev, dinfo); 797 } 798 } 799 } 800} 801 802void 803pci_add_child(device_t bus, struct pci_devinfo *dinfo) 804{ 805 device_t pcib; 806 807 pcib = device_get_parent(bus); 808 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 809 device_set_ivars(dinfo->cfg.dev, dinfo); 810 pci_add_resources(pcib, dinfo->cfg.dev); 811 pci_print_verbose(dinfo); 812} 813 814static int 815pci_probe(device_t dev) 816{ 817 818 if (pcib_get_bus(dev) < 0) 819 return (ENXIO); 820 821 device_set_desc(dev, "PCI bus"); 822 823 /* Allow other subclasses to override this driver. */ 824 return (-1000); 825} 826 827static int 828pci_attach(device_t dev) 829{ 830 int busno; 831 832 /* 833 * Since there can be multiple independantly numbered PCI 834 * busses on some large alpha systems, we can't use the unit 835 * number to decide what bus we are probing. We ask the parent 836 * pcib what our bus number is. 837 */ 838 busno = pcib_get_bus(dev); 839 if (bootverbose) 840 device_printf(dev, "physical bus=%d\n", busno); 841 842 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 843 844 return (bus_generic_attach(dev)); 845} 846 847static void 848pci_load_vendor_data(void) 849{ 850 caddr_t vendordata, info; 851 852 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 853 info = preload_search_info(vendordata, MODINFO_ADDR); 854 pci_vendordata = *(char **)info; 855 info = preload_search_info(vendordata, MODINFO_SIZE); 856 pci_vendordata_size = *(size_t *)info; 857 /* terminate the database */ 858 pci_vendordata[pci_vendordata_size] = '\n'; 859 } 860} 861 862int 863pci_print_child(device_t dev, device_t child) 864{ 865 struct pci_devinfo *dinfo; 866 struct resource_list *rl; 867 pcicfgregs *cfg; 868 int retval = 0; 869 870 dinfo = device_get_ivars(child); 871 cfg = &dinfo->cfg; 872 rl = &dinfo->resources; 873 874 retval += bus_print_child_header(dev, child); 875 876 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 877 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 878 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 879 if (device_get_flags(dev)) 880 retval += printf(" flags %#x", device_get_flags(dev)); 881 882 retval += printf(" at device %d.%d", pci_get_slot(child), 883 pci_get_function(child)); 884 885 retval += bus_print_child_footer(dev, child); 886 887 return (retval); 888} 889 890static struct 891{ 892 int class; 893 int subclass; 894 char *desc; 895} pci_nomatch_tab[] = { 896 {PCIC_OLD, -1, "old"}, 897 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 898 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 899 {PCIC_STORAGE, -1, "mass storage"}, 900 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 901 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 902 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 903 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 904 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 905 {PCIC_NETWORK, -1, "network"}, 906 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 907 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 908 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 909 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 910 {PCIC_DISPLAY, -1, "display"}, 911 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 912 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 913 {PCIC_MULTIMEDIA, -1, "multimedia"}, 914 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 915 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 916 {PCIC_MEMORY, -1, "memory"}, 917 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 918 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 919 {PCIC_BRIDGE, -1, "bridge"}, 920 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 921 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 922 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 923 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 924 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 925 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 926 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 927 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 928 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 929 {PCIC_SIMPLECOMM, -1, "simple comms"}, 930 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 931 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 932 {PCIC_BASEPERIPH, -1, "base peripheral"}, 933 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 934 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 935 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 936 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 937 {PCIC_INPUTDEV, -1, "input device"}, 938 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 939 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 940 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 941 {PCIC_DOCKING, -1, "docking station"}, 942 {PCIC_PROCESSOR, -1, "processor"}, 943 {PCIC_SERIALBUS, -1, "serial bus"}, 944 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 945 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 946 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 947 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 948 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 949 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 950 {0, 0, NULL} 951}; 952 953void 954pci_probe_nomatch(device_t dev, device_t child) 955{ 956 int i; 957 char *cp, *scp, *device; 958 959 /* 960 * Look for a listing for this device in a loaded device database. 961 */ 962 if ((device = pci_describe_device(child)) != NULL) { 963 device_printf(dev, "<%s>", device); 964 free(device, M_DEVBUF); 965 } else { 966 /* 967 * Scan the class/subclass descriptions for a general 968 * description. 969 */ 970 cp = "unknown"; 971 scp = NULL; 972 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 973 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 974 if (pci_nomatch_tab[i].subclass == -1) { 975 cp = pci_nomatch_tab[i].desc; 976 } else if (pci_nomatch_tab[i].subclass == 977 pci_get_subclass(child)) { 978 scp = pci_nomatch_tab[i].desc; 979 } 980 } 981 } 982 device_printf(dev, "<%s%s%s>", 983 cp ? : "", ((cp != NULL) && (scp != NULL)) ? ", " : "", 984 scp ? : ""); 985 } 986 printf(" at device %d.%d (no driver attached)\n", 987 pci_get_slot(child), pci_get_function(child)); 988 return; 989} 990 991/* 992 * Parse the PCI device database, if loaded, and return a pointer to a 993 * description of the device. 994 * 995 * The database is flat text formatted as follows: 996 * 997 * Any line not in a valid format is ignored. 998 * Lines are terminated with newline '\n' characters. 999 * 1000 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1001 * the vendor name. 1002 * 1003 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1004 * - devices cannot be listed without a corresponding VENDOR line. 1005 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1006 * another TAB, then the device name. 1007 */ 1008 1009/* 1010 * Assuming (ptr) points to the beginning of a line in the database, 1011 * return the vendor or device and description of the next entry. 1012 * The value of (vendor) or (device) inappropriate for the entry type 1013 * is set to -1. Returns nonzero at the end of the database. 1014 * 1015 * Note that this is slightly unrobust in the face of corrupt data; 1016 * we attempt to safeguard against this by spamming the end of the 1017 * database with a newline when we initialise. 1018 */ 1019static int 1020pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1021{ 1022 char *cp = *ptr; 1023 int left; 1024 1025 *device = -1; 1026 *vendor = -1; 1027 **desc = '\0'; 1028 for (;;) { 1029 left = pci_vendordata_size - (cp - pci_vendordata); 1030 if (left <= 0) { 1031 *ptr = cp; 1032 return(1); 1033 } 1034 1035 /* vendor entry? */ 1036 if (*cp != '\t' && 1037 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1038 break; 1039 /* device entry? */ 1040 if (*cp == '\t' && 1041 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1042 break; 1043 1044 /* skip to next line */ 1045 while (*cp != '\n' && left > 0) { 1046 cp++; 1047 left--; 1048 } 1049 if (*cp == '\n') { 1050 cp++; 1051 left--; 1052 } 1053 } 1054 /* skip to next line */ 1055 while (*cp != '\n' && left > 0) { 1056 cp++; 1057 left--; 1058 } 1059 if (*cp == '\n' && left > 0) 1060 cp++; 1061 *ptr = cp; 1062 return(0); 1063} 1064 1065static char * 1066pci_describe_device(device_t dev) 1067{ 1068 int vendor, device; 1069 char *desc, *vp, *dp, *line; 1070 1071 desc = vp = dp = NULL; 1072 1073 /* 1074 * If we have no vendor data, we can't do anything. 1075 */ 1076 if (pci_vendordata == NULL) 1077 goto out; 1078 1079 /* 1080 * Scan the vendor data looking for this device 1081 */ 1082 line = pci_vendordata; 1083 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1084 goto out; 1085 for (;;) { 1086 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1087 goto out; 1088 if (vendor == pci_get_vendor(dev)) 1089 break; 1090 } 1091 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1092 goto out; 1093 for (;;) { 1094 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1095 *dp = 0; 1096 break; 1097 } 1098 if (vendor != -1) { 1099 *dp = 0; 1100 break; 1101 } 1102 if (device == pci_get_device(dev)) 1103 break; 1104 } 1105 if (dp[0] == '\0') 1106 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1107 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1108 NULL) 1109 sprintf(desc, "%s, %s", vp, dp); 1110 out: 1111 if (vp != NULL) 1112 free(vp, M_DEVBUF); 1113 if (dp != NULL) 1114 free(dp, M_DEVBUF); 1115 return(desc); 1116} 1117 1118int 1119pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1120{ 1121 struct pci_devinfo *dinfo; 1122 pcicfgregs *cfg; 1123 1124 dinfo = device_get_ivars(child); 1125 cfg = &dinfo->cfg; 1126 1127 switch (which) { 1128 case PCI_IVAR_SUBVENDOR: 1129 *result = cfg->subvendor; 1130 break; 1131 case PCI_IVAR_SUBDEVICE: 1132 *result = cfg->subdevice; 1133 break; 1134 case PCI_IVAR_VENDOR: 1135 *result = cfg->vendor; 1136 break; 1137 case PCI_IVAR_DEVICE: 1138 *result = cfg->device; 1139 break; 1140 case PCI_IVAR_DEVID: 1141 *result = (cfg->device << 16) | cfg->vendor; 1142 break; 1143 case PCI_IVAR_CLASS: 1144 *result = cfg->baseclass; 1145 break; 1146 case PCI_IVAR_SUBCLASS: 1147 *result = cfg->subclass; 1148 break; 1149 case PCI_IVAR_PROGIF: 1150 *result = cfg->progif; 1151 break; 1152 case PCI_IVAR_REVID: 1153 *result = cfg->revid; 1154 break; 1155 case PCI_IVAR_INTPIN: 1156 *result = cfg->intpin; 1157 break; 1158 case PCI_IVAR_IRQ: 1159 *result = cfg->intline; 1160 break; 1161 case PCI_IVAR_BUS: 1162 *result = cfg->bus; 1163 break; 1164 case PCI_IVAR_SLOT: 1165 *result = cfg->slot; 1166 break; 1167 case PCI_IVAR_FUNCTION: 1168 *result = cfg->func; 1169 break; 1170 default: 1171 return (ENOENT); 1172 } 1173 return (0); 1174} 1175 1176int 1177pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1178{ 1179 struct pci_devinfo *dinfo; 1180 pcicfgregs *cfg; 1181 1182 dinfo = device_get_ivars(child); 1183 cfg = &dinfo->cfg; 1184 1185 switch (which) { 1186 case PCI_IVAR_SUBVENDOR: 1187 case PCI_IVAR_SUBDEVICE: 1188 case PCI_IVAR_VENDOR: 1189 case PCI_IVAR_DEVICE: 1190 case PCI_IVAR_DEVID: 1191 case PCI_IVAR_CLASS: 1192 case PCI_IVAR_SUBCLASS: 1193 case PCI_IVAR_PROGIF: 1194 case PCI_IVAR_REVID: 1195 case PCI_IVAR_INTPIN: 1196 case PCI_IVAR_IRQ: 1197 case PCI_IVAR_BUS: 1198 case PCI_IVAR_SLOT: 1199 case PCI_IVAR_FUNCTION: 1200 return (EINVAL); /* disallow for now */ 1201 1202 default: 1203 return (ENOENT); 1204 } 1205 return (0); 1206} 1207 1208 1209#include "opt_ddb.h" 1210#ifdef DDB 1211#include <ddb/ddb.h> 1212#include <sys/cons.h> 1213 1214/* 1215 * List resources based on pci map registers, used for within ddb 1216 */ 1217 1218DB_SHOW_COMMAND(pciregs, db_pci_dump) 1219{ 1220 struct pci_devinfo *dinfo; 1221 struct devlist *devlist_head; 1222 struct pci_conf *p; 1223 const char *name; 1224 int i, error, none_count, nl; 1225 1226 none_count = 0; 1227 nl = 0; 1228 /* get the head of the device queue */ 1229 devlist_head = &pci_devq; 1230 1231 /* 1232 * Go through the list of devices and print out devices 1233 */ 1234 for (error = 0, i = 0, 1235 dinfo = STAILQ_FIRST(devlist_head); 1236 (dinfo != NULL) && (error == 0) && (i < pci_numdevs); 1237 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1238 1239 /* Populate pd_name and pd_unit */ 1240 name = NULL; 1241 if (dinfo->cfg.dev) 1242 name = device_get_name(dinfo->cfg.dev); 1243 1244 p = &dinfo->conf; 1245 /* 1246 * XXX just take 20 for now... 1247 */ 1248 if (nl++ == 20) { 1249 int c; 1250 1251 db_printf("--More--"); 1252 c = cngetc(); 1253 db_printf("\r"); 1254 /* 1255 * A whole screenfull or just one line? 1256 */ 1257 switch (c) { 1258 case '\n': /* just one line */ 1259 nl = 20; 1260 break; 1261 case ' ': 1262 nl = 0; /* another screenfull */ 1263 break; 1264 default: /* exit */ 1265 db_printf("\n"); 1266 return; 1267 } 1268 } 1269 1270 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1271 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1272 (name && *name) ? name : "none", 1273 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1274 none_count++, 1275 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1276 p->pc_sel.pc_func, (p->pc_class << 16) | 1277 (p->pc_subclass << 8) | p->pc_progif, 1278 (p->pc_subdevice << 16) | p->pc_subvendor, 1279 (p->pc_device << 16) | p->pc_vendor, 1280 p->pc_revid, p->pc_hdr); 1281 } 1282} 1283#endif /* DDB */ 1284 1285struct resource * 1286pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1287 u_long start, u_long end, u_long count, u_int flags) 1288{ 1289 struct pci_devinfo *dinfo = device_get_ivars(child); 1290 struct resource_list *rl = &dinfo->resources; 1291 pcicfgregs *cfg = &dinfo->cfg; 1292 1293 /* 1294 * Perform lazy resource allocation 1295 * 1296 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1297 */ 1298 if (device_get_parent(child) == dev) { 1299 /* 1300 * If device doesn't have an interrupt routed, and is 1301 * deserving of an interrupt, try to assign it one. 1302 */ 1303 if ((type == SYS_RES_IRQ) && 1304 !PCI_INTERRUPT_VALID(cfg->intline) && 1305 (cfg->intpin != 0)) { 1306 cfg->intline = PCIB_ROUTE_INTERRUPT( 1307 device_get_parent(dev), child, cfg->intpin); 1308 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1309 pci_write_config(child, PCIR_INTLINE, 1310 cfg->intline, 1); 1311 resource_list_add(rl, SYS_RES_IRQ, 0, 1312 cfg->intline, cfg->intline, 1); 1313 } 1314 } 1315 } 1316 1317 return (resource_list_alloc(rl, dev, child, type, rid, 1318 start, end, count, flags)); 1319} 1320 1321void 1322pci_delete_resource(device_t dev, device_t child, int type, int rid) 1323{ 1324 struct pci_devinfo *dinfo; 1325 struct resource_list *rl; 1326 struct resource_list_entry *rle; 1327 1328 if (device_get_parent(child) != dev) 1329 return; 1330 1331 dinfo = device_get_ivars(child); 1332 rl = &dinfo->resources; 1333 rle = resource_list_find(rl, type, rid); 1334 if (rle) { 1335 if (rle->res) { 1336 if (rle->res->r_dev != dev || 1337 rman_get_flags(rle->res) & RF_ACTIVE) { 1338 device_printf(dev, "delete_resource: " 1339 "Resource still owned by child, oops. " 1340 "(type=%d, rid=%d, addr=%lx)\n", 1341 rle->type, rle->rid, 1342 rman_get_start(rle->res)); 1343 return; 1344 } 1345 bus_release_resource(dev, type, rid, rle->res); 1346 } 1347 resource_list_delete(rl, type, rid); 1348 } 1349 /* 1350 * Why do we turn off the PCI configuration BAR when we delete a 1351 * resource? -- imp 1352 */ 1353 pci_write_config(child, rid, 0, 4); 1354 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1355} 1356 1357struct resource_list * 1358pci_get_resource_list (device_t dev, device_t child) 1359{ 1360 struct pci_devinfo * dinfo = device_get_ivars(child); 1361 struct resource_list * rl = &dinfo->resources; 1362 1363 if (!rl) 1364 return (NULL); 1365 1366 return (rl); 1367} 1368 1369u_int32_t 1370pci_read_config_method(device_t dev, device_t child, int reg, int width) 1371{ 1372 struct pci_devinfo *dinfo = device_get_ivars(child); 1373 pcicfgregs *cfg = &dinfo->cfg; 1374 1375 return (PCIB_READ_CONFIG(device_get_parent(dev), 1376 cfg->bus, cfg->slot, cfg->func, reg, width)); 1377} 1378 1379void 1380pci_write_config_method(device_t dev, device_t child, int reg, 1381 u_int32_t val, int width) 1382{ 1383 struct pci_devinfo *dinfo = device_get_ivars(child); 1384 pcicfgregs *cfg = &dinfo->cfg; 1385 1386 PCIB_WRITE_CONFIG(device_get_parent(dev), 1387 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1388} 1389 1390static int 1391pci_modevent(module_t mod, int what, void *arg) 1392{ 1393 static dev_t pci_cdev; 1394 1395 switch (what) { 1396 case MOD_LOAD: 1397 STAILQ_INIT(&pci_devq); 1398 pci_generation = 0; 1399 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1400 "pci"); 1401 pci_load_vendor_data(); 1402 break; 1403 1404 case MOD_UNLOAD: 1405 destroy_dev(pci_cdev); 1406 break; 1407 } 1408 1409 return (0); 1410} 1411