151973Smsmith/*- 251973Smsmith * Copyright (c) 1999 Michael Smith 351973Smsmith * All rights reserved. 451973Smsmith * 551973Smsmith * Redistribution and use in source and binary forms, with or without 651973Smsmith * modification, are permitted provided that the following conditions 751973Smsmith * are met: 851973Smsmith * 1. Redistributions of source code must retain the above copyright 951973Smsmith * notice, this list of conditions and the following disclaimer. 1051973Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1151973Smsmith * notice, this list of conditions and the following disclaimer in the 1251973Smsmith * documentation and/or other materials provided with the distribution. 1351973Smsmith * 1451973Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1551973Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1651973Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1751973Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1851973Smsmith * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1951973Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2051973Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2151973Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2251973Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2351973Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2451973Smsmith * SUCH DAMAGE. 2551973Smsmith * 2651973Smsmith * $FreeBSD$ 2751973Smsmith */ 2851973Smsmith 2952544Smsmith#define MLX_BLKSIZE 512 /* fixed feature */ 30138090Sscottl#define MLX_PAGE_SIZE 4096 /* controller, not cpu, attribute */ 3152544Smsmith 3251973Smsmith/* 3351973Smsmith * Selected command codes. 3451973Smsmith */ 3558188Smsmith#define MLX_CMD_ENQUIRY_OLD 0x05 3651973Smsmith#define MLX_CMD_ENQUIRY 0x53 3751973Smsmith#define MLX_CMD_ENQUIRY2 0x1c 3851973Smsmith#define MLX_CMD_ENQSYSDRIVE 0x19 3958188Smsmith#define MLX_CMD_READSG 0xb6 4058188Smsmith#define MLX_CMD_WRITESG 0xb7 4158188Smsmith#define MLX_CMD_READSG_OLD 0x82 4258188Smsmith#define MLX_CMD_WRITESG_OLD 0x83 4351973Smsmith#define MLX_CMD_FLUSH 0x0a 4451973Smsmith#define MLX_CMD_LOGOP 0x72 4551973Smsmith#define MLX_CMD_REBUILDASYNC 0x16 4651973Smsmith#define MLX_CMD_CHECKASYNC 0x1e 4751973Smsmith#define MLX_CMD_REBUILDSTAT 0x0c 4851973Smsmith#define MLX_CMD_STOPCHANNEL 0x13 4951973Smsmith#define MLX_CMD_STARTCHANNEL 0x12 5058188Smsmith#define MLX_CMD_READ_CONFIG 0x4e 5158188Smsmith#define MLX_CMD_DIRECT_CDB 0x04 5259136Smsmith#define MLX_CMD_DEVICE_STATE 0x50 5351973Smsmith 5458188Smsmith#ifdef _KERNEL 5558188Smsmith 5658188Smsmith#define MLX_CFG_BASE0 0x10 /* first region */ 5758188Smsmith#define MLX_CFG_BASE1 0x14 /* second region (type 3 only) */ 5858188Smsmith 5951973Smsmith/* 6051973Smsmith * Status values. 6151973Smsmith */ 6251973Smsmith#define MLX_STATUS_OK 0x0000 6351973Smsmith#define MLX_STATUS_RDWROFFLINE 0x0002 /* read/write claims drive is offline */ 6451973Smsmith#define MLX_STATUS_WEDGED 0xdead /* controller not listening */ 6554419Smsmith#define MLX_STATUS_LOST 0xbeef /* never came back */ 6651973Smsmith#define MLX_STATUS_BUSY 0xffff /* command is in controller */ 6751973Smsmith 6851973Smsmith/* 6952225Smsmith * Accessor defines for the V3 interface. 7052225Smsmith */ 7152225Smsmith#define MLX_V3_MAILBOX 0x00 7252225Smsmith#define MLX_V3_STATUS_IDENT 0x0d 7352225Smsmith#define MLX_V3_STATUS 0x0e 7452225Smsmith#define MLX_V3_IDBR 0x40 7552225Smsmith#define MLX_V3_ODBR 0x41 7652225Smsmith#define MLX_V3_IER 0x43 7758188Smsmith#define MLX_V3_FWERROR 0x3f 7858188Smsmith#define MLX_V3_FWERROR_PARAM1 0x00 7958188Smsmith#define MLX_V3_FWERROR_PARAM2 0x01 8052225Smsmith 81240608Sjhb#define MLX_V3_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V3_MAILBOX + idx, val) 82240608Sjhb#define MLX_V3_GET_STATUS_IDENT(sc) bus_read_1 (sc->mlx_mem, MLX_V3_STATUS_IDENT) 83240608Sjhb#define MLX_V3_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V3_STATUS) 84240608Sjhb#define MLX_V3_GET_IDBR(sc) bus_read_1 (sc->mlx_mem, MLX_V3_IDBR) 85240608Sjhb#define MLX_V3_PUT_IDBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_IDBR, val) 86240608Sjhb#define MLX_V3_GET_ODBR(sc) bus_read_1 (sc->mlx_mem, MLX_V3_ODBR) 87240608Sjhb#define MLX_V3_PUT_ODBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_ODBR, val) 88240608Sjhb#define MLX_V3_PUT_IER(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_IER, val) 89240608Sjhb#define MLX_V3_GET_FWERROR(sc) bus_read_1 (sc->mlx_mem, MLX_V3_FWERROR) 90240608Sjhb#define MLX_V3_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_FWERROR, val) 91240608Sjhb#define MLX_V3_GET_FWERROR_PARAM1(sc) bus_read_1 (sc->mlx_mem, MLX_V3_FWERROR_PARAM1) 92240608Sjhb#define MLX_V3_GET_FWERROR_PARAM2(sc) bus_read_1 (sc->mlx_mem, MLX_V3_FWERROR_PARAM2) 9352225Smsmith 9452225Smsmith#define MLX_V3_IDB_FULL (1<<0) /* mailbox is full */ 9558188Smsmith#define MLX_V3_IDB_INIT_BUSY (1<<1) /* initialisation in progress */ 9658188Smsmith 9752225Smsmith#define MLX_V3_IDB_SACK (1<<1) /* acknowledge status read */ 9852225Smsmith 9952225Smsmith#define MLX_V3_ODB_SAVAIL (1<<0) /* status is available */ 10052225Smsmith 10158188Smsmith#define MLX_V3_FWERROR_PEND (1<<2) /* firmware error pending */ 10258188Smsmith 10352225Smsmith/* 10452225Smsmith * Accessor defines for the V4 interface. 10552225Smsmith */ 10652225Smsmith#define MLX_V4_MAILBOX 0x1000 10758188Smsmith#define MLX_V4_MAILBOX_LENGTH 16 10858188Smsmith#define MLX_V4_STATUS_IDENT 0x1018 10952225Smsmith#define MLX_V4_STATUS 0x101a 11052225Smsmith#define MLX_V4_IDBR 0x0020 11152225Smsmith#define MLX_V4_ODBR 0x002c 11252225Smsmith#define MLX_V4_IER 0x0034 11358188Smsmith#define MLX_V4_FWERROR 0x103f 11458188Smsmith#define MLX_V4_FWERROR_PARAM1 0x1000 11558188Smsmith#define MLX_V4_FWERROR_PARAM2 0x1001 11652225Smsmith 11752225Smsmith/* use longword access? */ 118240608Sjhb#define MLX_V4_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V4_MAILBOX + idx, val) 119240608Sjhb#define MLX_V4_GET_STATUS_IDENT(sc) bus_read_1 (sc->mlx_mem, MLX_V4_STATUS_IDENT) 120240608Sjhb#define MLX_V4_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V4_STATUS) 121240608Sjhb#define MLX_V4_GET_IDBR(sc) bus_read_4 (sc->mlx_mem, MLX_V4_IDBR) 122240608Sjhb#define MLX_V4_PUT_IDBR(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_IDBR, val) 123240608Sjhb#define MLX_V4_GET_ODBR(sc) bus_read_4 (sc->mlx_mem, MLX_V4_ODBR) 124240608Sjhb#define MLX_V4_PUT_ODBR(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_ODBR, val) 125240608Sjhb#define MLX_V4_PUT_IER(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_IER, val) 126240608Sjhb#define MLX_V4_GET_FWERROR(sc) bus_read_1 (sc->mlx_mem, MLX_V4_FWERROR) 127240608Sjhb#define MLX_V4_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V4_FWERROR, val) 128240608Sjhb#define MLX_V4_GET_FWERROR_PARAM1(sc) bus_read_1 (sc->mlx_mem, MLX_V4_FWERROR_PARAM1) 129240608Sjhb#define MLX_V4_GET_FWERROR_PARAM2(sc) bus_read_1 (sc->mlx_mem, MLX_V4_FWERROR_PARAM2) 13052225Smsmith 13152225Smsmith#define MLX_V4_IDB_FULL (1<<0) /* mailbox is full */ 13258188Smsmith#define MLX_V4_IDB_INIT_BUSY (1<<1) /* initialisation in progress */ 13352225Smsmith 13452225Smsmith#define MLX_V4_IDB_HWMBOX_CMD (1<<0) /* posted hardware mailbox command */ 13552225Smsmith#define MLX_V4_IDB_SACK (1<<1) /* acknowledge status read */ 13652225Smsmith#define MLX_V4_IDB_MEMMBOX_CMD (1<<4) /* posted memory mailbox command */ 13752225Smsmith 13852225Smsmith#define MLX_V4_ODB_HWSAVAIL (1<<0) /* status is available for hardware mailbox */ 13952225Smsmith#define MLX_V4_ODB_MEMSAVAIL (1<<1) /* status is available for memory mailbox */ 14052225Smsmith 14152225Smsmith#define MLX_V4_ODB_HWMBOX_ACK (1<<0) /* ack status read from hardware mailbox */ 14252225Smsmith#define MLX_V4_ODB_MEMMBOX_ACK (1<<1) /* ack status read from memory mailbox */ 14352225Smsmith 14452225Smsmith#define MLX_V4_IER_MASK 0xfb /* message unit interrupt mask */ 14552225Smsmith#define MLX_V4_IER_DISINT (1<<2) /* interrupt disable bit */ 14652225Smsmith 14758188Smsmith#define MLX_V4_FWERROR_PEND (1<<2) /* firmware error pending */ 14858188Smsmith 14952225Smsmith/* 15054419Smsmith * Accessor defines for the V5 interface 15154419Smsmith */ 15254419Smsmith#define MLX_V5_MAILBOX 0x50 15358188Smsmith#define MLX_V5_MAILBOX_LENGTH 16 15454419Smsmith#define MLX_V5_STATUS_IDENT 0x5d 15554419Smsmith#define MLX_V5_STATUS 0x5e 15654419Smsmith#define MLX_V5_IDBR 0x60 15754419Smsmith#define MLX_V5_ODBR 0x61 15854419Smsmith#define MLX_V5_IER 0x34 15958188Smsmith#define MLX_V5_FWERROR 0x63 16058188Smsmith#define MLX_V5_FWERROR_PARAM1 0x50 16158188Smsmith#define MLX_V5_FWERROR_PARAM2 0x51 16254419Smsmith 163240608Sjhb#define MLX_V5_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V5_MAILBOX + idx, val) 164240608Sjhb#define MLX_V5_GET_STATUS_IDENT(sc) bus_read_1 (sc->mlx_mem, MLX_V5_STATUS_IDENT) 165240608Sjhb#define MLX_V5_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V5_STATUS) 166240608Sjhb#define MLX_V5_GET_IDBR(sc) bus_read_1 (sc->mlx_mem, MLX_V5_IDBR) 167240608Sjhb#define MLX_V5_PUT_IDBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_IDBR, val) 168240608Sjhb#define MLX_V5_GET_ODBR(sc) bus_read_1 (sc->mlx_mem, MLX_V5_ODBR) 169240608Sjhb#define MLX_V5_PUT_ODBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_ODBR, val) 170240608Sjhb#define MLX_V5_PUT_IER(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_IER, val) 171240608Sjhb#define MLX_V5_GET_FWERROR(sc) bus_read_1 (sc->mlx_mem, MLX_V5_FWERROR) 172240608Sjhb#define MLX_V5_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_FWERROR, val) 173240608Sjhb#define MLX_V5_GET_FWERROR_PARAM1(sc) bus_read_1 (sc->mlx_mem, MLX_V5_FWERROR_PARAM1) 174240608Sjhb#define MLX_V5_GET_FWERROR_PARAM2(sc) bus_read_1 (sc->mlx_mem, MLX_V5_FWERROR_PARAM2) 17554419Smsmith 17654419Smsmith#define MLX_V5_IDB_EMPTY (1<<0) /* mailbox is empty */ 17758188Smsmith#define MLX_V5_IDB_INIT_DONE (1<<1) /* initialisation has completed */ 17854419Smsmith 17954419Smsmith#define MLX_V5_IDB_HWMBOX_CMD (1<<0) /* posted hardware mailbox command */ 18054419Smsmith#define MLX_V5_IDB_SACK (1<<1) /* acknowledge status read */ 18158188Smsmith#define MLX_V5_IDB_RESET (1<<3) /* reset request */ 18254419Smsmith#define MLX_V5_IDB_MEMMBOX_CMD (1<<4) /* posted memory mailbox command */ 18354419Smsmith 18454419Smsmith#define MLX_V5_ODB_HWSAVAIL (1<<0) /* status is available for hardware mailbox */ 18554419Smsmith#define MLX_V5_ODB_MEMSAVAIL (1<<1) /* status is available for memory mailbox */ 18654419Smsmith 18754419Smsmith#define MLX_V5_ODB_HWMBOX_ACK (1<<0) /* ack status read from hardware mailbox */ 18854419Smsmith#define MLX_V5_ODB_MEMMBOX_ACK (1<<1) /* ack status read from memory mailbox */ 18954419Smsmith 19054419Smsmith#define MLX_V5_IER_DISINT (1<<2) /* interrupt disable bit */ 19154419Smsmith 19258188Smsmith#define MLX_V5_FWERROR_PEND (1<<2) /* firmware error pending */ 19354419Smsmith 19458188Smsmith#endif /* _KERNEL */ 19558188Smsmith 19654419Smsmith/* 19751973Smsmith * Scatter-gather list format, type 1, kind 00. 19851973Smsmith */ 19951973Smsmithstruct mlx_sgentry 20051973Smsmith{ 20151973Smsmith u_int32_t sg_addr; 20251973Smsmith u_int32_t sg_count; 203103870Salfred} __packed; 20451973Smsmith 20551973Smsmith/* 20651973Smsmith * Command result buffers, as placed in system memory by the controller. 20751973Smsmith */ 20858188Smsmith 20958188Smsmithstruct mlx_enquiry_old /* MLX_CMD_ENQUIRY_OLD */ 21058188Smsmith{ 21158188Smsmith u_int8_t me_num_sys_drvs; 21258188Smsmith u_int8_t res1[3]; 21358188Smsmith u_int32_t me_drvsize[8]; 21458188Smsmith u_int16_t me_flash_age; 21558188Smsmith u_int8_t me_status_flags; 21658188Smsmith u_int8_t me_free_state_change_count; 21758188Smsmith u_int8_t me_fwminor; 21858188Smsmith u_int8_t me_fwmajor; 21958188Smsmith u_int8_t me_rebuild_flag; 22058188Smsmith u_int8_t me_max_commands; 22158188Smsmith u_int8_t me_offline_sd_count; 22258188Smsmith u_int8_t res3; 22358188Smsmith u_int8_t me_critical_sd_count; 22458188Smsmith u_int8_t res4[3]; 22558188Smsmith u_int8_t me_dead_count; 22658188Smsmith u_int8_t res5; 22758188Smsmith u_int8_t me_rebuild_count; 22858188Smsmith u_int8_t me_misc_flags; 22958188Smsmith struct 23058188Smsmith { 23158188Smsmith u_int8_t dd_targ; 23258188Smsmith u_int8_t dd_chan; 233103870Salfred } __packed me_dead[20]; 234103870Salfred} __packed; 23558188Smsmith 23651973Smsmithstruct mlx_enquiry /* MLX_CMD_ENQUIRY */ 23751973Smsmith{ 23851973Smsmith u_int8_t me_num_sys_drvs; 23951973Smsmith u_int8_t res1[3]; 24051973Smsmith u_int32_t me_drvsize[32]; 24151973Smsmith u_int16_t me_flash_age; 24251973Smsmith u_int8_t me_status_flags; 24351973Smsmith#define MLX_ENQ_SFLAG_DEFWRERR (1<<0) /* deferred write error indicator */ 24451973Smsmith#define MLX_ENQ_SFLAG_BATTLOW (1<<1) /* battery low */ 24551973Smsmith u_int8_t res2; 24651973Smsmith u_int8_t me_fwminor; 24751973Smsmith u_int8_t me_fwmajor; 24851973Smsmith u_int8_t me_rebuild_flag; 24951973Smsmith u_int8_t me_max_commands; 25051973Smsmith u_int8_t me_offline_sd_count; 25151973Smsmith u_int8_t res3; 25251973Smsmith u_int16_t me_event_log_seq_num; 25351973Smsmith u_int8_t me_critical_sd_count; 25451973Smsmith u_int8_t res4[3]; 25551973Smsmith u_int8_t me_dead_count; 25651973Smsmith u_int8_t res5; 25751973Smsmith u_int8_t me_rebuild_count; 25851973Smsmith u_int8_t me_misc_flags; 25951973Smsmith#define MLX_ENQ_MISC_BBU (1<<3) /* battery backup present */ 26051973Smsmith struct 26151973Smsmith { 26251973Smsmith u_int8_t dd_targ; 26351973Smsmith u_int8_t dd_chan; 264103870Salfred } __packed me_dead[20]; 265103870Salfred} __packed; 26651973Smsmith 26751973Smsmithstruct mlx_enquiry2 /* MLX_CMD_ENQUIRY2 */ 26851973Smsmith{ 26951973Smsmith u_int32_t me_hardware_id; 27051973Smsmith u_int32_t me_firmware_id; 27151973Smsmith u_int32_t res1; 27251973Smsmith u_int8_t me_configured_channels; 27351973Smsmith u_int8_t me_actual_channels; 27451973Smsmith u_int8_t me_max_targets; 27551973Smsmith u_int8_t me_max_tags; 27651973Smsmith u_int8_t me_max_sys_drives; 27751973Smsmith u_int8_t me_max_arms; 27851973Smsmith u_int8_t me_max_spans; 27951973Smsmith u_int8_t res2; 28051973Smsmith u_int32_t res3; 28151973Smsmith u_int32_t me_mem_size; 28251973Smsmith u_int32_t me_cache_size; 28351973Smsmith u_int32_t me_flash_size; 28451973Smsmith u_int32_t me_nvram_size; 28551973Smsmith u_int16_t me_mem_type; 28651973Smsmith u_int16_t me_clock_speed; 28751973Smsmith u_int16_t me_mem_speed; 28851973Smsmith u_int16_t me_hardware_speed; 28954979Smsmith u_int8_t res4[12]; 29051973Smsmith u_int16_t me_max_commands; 29151973Smsmith u_int16_t me_max_sg; 29251973Smsmith u_int16_t me_max_dp; 29351973Smsmith u_int16_t me_max_iod; 29451973Smsmith u_int16_t me_max_comb; 29551973Smsmith u_int8_t me_latency; 29651973Smsmith u_int8_t res5; 29751973Smsmith u_int8_t me_scsi_timeout; 29851973Smsmith u_int8_t res6; 29951973Smsmith u_int16_t me_min_freelines; 30051973Smsmith u_int8_t res7[8]; 30151973Smsmith u_int8_t me_rate_const; 30251973Smsmith u_int8_t res8[11]; 30351973Smsmith u_int16_t me_physblk; 30451973Smsmith u_int16_t me_logblk; 30551973Smsmith u_int16_t me_maxblk; 30651973Smsmith u_int16_t me_blocking_factor; 30751973Smsmith u_int16_t me_cacheline; 30851973Smsmith u_int8_t me_scsi_cap; 30951973Smsmith u_int8_t res9[5]; 31054979Smsmith u_int16_t me_firmware_build; 31151973Smsmith u_int8_t me_fault_mgmt_type; 31251973Smsmith u_int8_t res10; 31351973Smsmith u_int32_t me_firmware_features; 31451973Smsmith u_int8_t res11[8]; 315103870Salfred} __packed; 31651973Smsmith 31751973Smsmithstruct mlx_enq_sys_drive /* MLX_CMD_ENQSYSDRIVE returns an array of 32 of these */ 31851973Smsmith{ 31951973Smsmith u_int32_t sd_size; 32051973Smsmith u_int8_t sd_state; 32151973Smsmith u_int8_t sd_raidlevel; 32251973Smsmith u_int16_t res1; 323103870Salfred} __packed; 32451973Smsmith 32551973Smsmithstruct mlx_eventlog_entry /* MLX_CMD_LOGOP/MLX_LOGOP_GET */ 32651973Smsmith{ 32751973Smsmith u_int8_t el_type; 32851973Smsmith u_int8_t el_length; 32951973Smsmith u_char el_target:5; 33051973Smsmith u_char el_channel:3; 33151973Smsmith u_char el_lun:6; 33251973Smsmith u_char res1:2; 33351973Smsmith u_int16_t el_seqno; 33451973Smsmith u_char el_errorcode:7; 33551973Smsmith u_char el_valid:1; 33651973Smsmith u_int8_t el_segment; 33751973Smsmith u_char el_sensekey:4; 33851973Smsmith u_char res2:1; 33951973Smsmith u_char el_ILI:1; 34051973Smsmith u_char el_EOM:1; 34151973Smsmith u_char el_filemark:1; 34251973Smsmith u_int8_t el_information[4]; 34351973Smsmith u_int8_t el_addsense; 34451973Smsmith u_int8_t el_csi[4]; 34551973Smsmith u_int8_t el_asc; 34651973Smsmith u_int8_t el_asq; 34751973Smsmith u_int8_t res3[12]; 348103870Salfred} __packed; 34951973Smsmith 35051973Smsmith#define MLX_LOGOP_GET 0x00 /* operation codes for MLX_CMD_LOGOP */ 35151973Smsmith#define MLX_LOGMSG_SENSE 0x00 /* log message contents codes */ 35251973Smsmith 35351973Smsmithstruct mlx_rebuild_stat /* MLX_CMD_REBUILDSTAT */ 35451973Smsmith{ 35551973Smsmith u_int32_t rb_drive; 35651973Smsmith u_int32_t rb_size; 35751973Smsmith u_int32_t rb_remaining; 358103870Salfred} __packed; 35951973Smsmith 36058188Smsmithstruct mlx_config2 36158188Smsmith{ 36258188Smsmith u_int16_t cf_flags1; 36358188Smsmith#define MLX_CF2_ACTV_NEG (1<<1) 36458188Smsmith#define MLX_CF2_NORSTRTRY (1<<7) 36558188Smsmith#define MLX_CF2_STRGWRK (1<<8) 36658188Smsmith#define MLX_CF2_HPSUPP (1<<9) 36758188Smsmith#define MLX_CF2_NODISCN (1<<10) 36858188Smsmith#define MLX_CF2_ARM (1<<13) 36958188Smsmith#define MLX_CF2_OFM (1<<15) 37058188Smsmith#define MLX_CF2_AEMI (MLX_CF2_ARM | MLX_CF2_OFM) 37158188Smsmith u_int8_t cf_oemid; 37258188Smsmith u_int8_t cf_oem_model; 37358188Smsmith u_int8_t cf_physical_sector; 37458188Smsmith u_int8_t cf_logical_sector; 37558188Smsmith u_int8_t cf_blockfactor; 37658188Smsmith u_int8_t cf_flags2; 37758188Smsmith#define MLX_CF2_READAH (1<<0) 37858188Smsmith#define MLX_CF2_BIOSDLY (1<<1) 37958188Smsmith#define MLX_CF2_REASS1S (1<<4) 38058188Smsmith#define MLX_CF2_FUAENABL (1<<6) 38158188Smsmith#define MLX_CF2_R5ALLS (1<<7) 38258188Smsmith u_int8_t cf_rcrate; 38358188Smsmith u_int8_t cf_res1; 38458188Smsmith u_int8_t cf_blocks_per_cache_line; 38558188Smsmith u_int8_t cf_blocks_per_stripe; 38658188Smsmith u_int8_t cf_scsi_param_0; 38758188Smsmith u_int8_t cf_scsi_param_1; 38858188Smsmith u_int8_t cf_scsi_param_2; 38958188Smsmith u_int8_t cf_scsi_param_3; 39058188Smsmith u_int8_t cf_scsi_param_4; 39158188Smsmith u_int8_t cf_scsi_param_5; 39258188Smsmith u_int8_t cf_scsi_initiator_id; 39358188Smsmith u_int8_t cf_res2; 39458188Smsmith u_int8_t cf_startup_mode; 39558188Smsmith u_int8_t cf_simultaneous_spinup_devices; 39658188Smsmith u_int8_t cf_delay_between_spinups; 39758188Smsmith u_int8_t cf_res3; 39858188Smsmith u_int16_t cf_checksum; 399103870Salfred} __packed; 40058188Smsmith 40158188Smsmithstruct mlx_sys_drv_span 40258188Smsmith{ 40358188Smsmith u_int32_t sp_start_lba; 40458188Smsmith u_int32_t sp_nblks; 40558188Smsmith u_int8_t sp_arm[8]; 406103870Salfred} __packed; 40758188Smsmith 40858188Smsmithstruct mlx_sys_drv 40958188Smsmith{ 41058188Smsmith u_int8_t sd_status; 41158188Smsmith u_int8_t sd_ext_status; 41258188Smsmith u_int8_t sd_mod1; 41358188Smsmith u_int8_t sd_mod2; 41458188Smsmith u_int8_t sd_raidlevel; 41558188Smsmith#define MLX_SYS_DRV_WRITEBACK (1<<7) 41658188Smsmith#define MLX_SYS_DRV_RAID0 0 41758188Smsmith#define MLX_SYS_DRV_RAID1 1 41858188Smsmith#define MLX_SYS_DRV_RAID3 3 41958188Smsmith#define MLX_SYS_DRV_RAID5 5 42058188Smsmith#define MLX_SYS_DRV_RAID6 6 42158188Smsmith#define MLX_SYS_DRV_JBOD 7 42258188Smsmith u_int8_t sd_valid_arms; 42358188Smsmith u_int8_t sd_valid_spans; 42458188Smsmith u_int8_t sd_init_state; 42558188Smsmith#define MLX_SYS_DRV_INITTED 0x81; 42658188Smsmith struct mlx_sys_drv_span sd_span[4]; 427103870Salfred} __packed; 42858188Smsmith 42958188Smsmithstruct mlx_phys_drv 43058188Smsmith{ 43158188Smsmith u_int8_t pd_flags1; 43258188Smsmith#define MLX_PHYS_DRV_PRESENT (1<<0) 43358188Smsmith u_int8_t pd_flags2; 43458188Smsmith#define MLX_PHYS_DRV_OTHER 0x00 43558188Smsmith#define MLX_PHYS_DRV_DISK 0x01 43658188Smsmith#define MLX_PHYS_DRV_SEQUENTIAL 0x02 43758188Smsmith#define MLX_PHYS_DRV_CDROM 0x03 43858188Smsmith#define MLX_PHYS_DRV_FAST20 (1<<3) 43958188Smsmith#define MLX_PHYS_DRV_SYNC (1<<4) 44058188Smsmith#define MLX_PHYS_DRV_FAST (1<<5) 44158188Smsmith#define MLX_PHYS_DRV_WIDE (1<<6) 44258188Smsmith#define MLX_PHYS_DRV_TAG (1<<7) 44358188Smsmith u_int8_t pd_status; 44458188Smsmith#define MLX_PHYS_DRV_DEAD 0x00 44558188Smsmith#define MLX_PHYS_DRV_WRONLY 0x02 44658188Smsmith#define MLX_PHYS_DRV_ONLINE 0x03 44758188Smsmith#define MLX_PHYS_DRV_STANDBY 0x10 44858188Smsmith u_int8_t pd_res1; 44958188Smsmith u_int8_t pd_period; 45058188Smsmith u_int8_t pd_offset; 45158188Smsmith u_int32_t pd_config_size; 452103870Salfred} __packed; 45358188Smsmith 45458188Smsmithstruct mlx_core_cfg 45558188Smsmith{ 45658188Smsmith u_int8_t cc_num_sys_drives; 45758188Smsmith u_int8_t cc_res1[3]; 45858188Smsmith struct mlx_sys_drv cc_sys_drives[32]; 45958188Smsmith struct mlx_phys_drv cc_phys_drives[5 * 16]; 460103870Salfred} __packed; 46158188Smsmith 46258188Smsmithstruct mlx_dcdb 46358188Smsmith{ 46458188Smsmith u_int8_t dcdb_target:4; 46558188Smsmith u_int8_t dcdb_channel:4; 46658188Smsmith u_int8_t dcdb_flags; 46758188Smsmith#define MLX_DCDB_NO_DATA 0x00 46858188Smsmith#define MLX_DCDB_DATA_IN 0x01 46958188Smsmith#define MLX_DCDB_DATA_OUT 0x02 47058188Smsmith#define MLX_DCDB_EARLY_STATUS (1<<2) 47158188Smsmith#define MLX_DCDB_TIMEOUT_10S 0x10 47258188Smsmith#define MLX_DCDB_TIMEOUT_60S 0x20 47358188Smsmith#define MLX_DCDB_TIMEOUT_20M 0x30 47458188Smsmith#define MLX_DCDB_TIMEOUT_24H 0x40 47558188Smsmith#define MLX_DCDB_NO_AUTO_SENSE (1<<6) 47658188Smsmith#define MLX_DCDB_DISCONNECT (1<<7) 47758188Smsmith u_int16_t dcdb_datasize; 47858188Smsmith u_int32_t dcdb_physaddr; 47958188Smsmith u_int8_t dcdb_cdb_length:4; 48058188Smsmith u_int8_t dcdb_datasize_high:4; 48158188Smsmith u_int8_t dcdb_sense_length; 48258188Smsmith u_int8_t dcdb_cdb[12]; 48358188Smsmith u_int8_t dcdb_sense[64]; 48458188Smsmith u_int8_t dcdb_status; 48558188Smsmith u_int8_t res1; 486103870Salfred} __packed; 48758188Smsmith 48859136Smsmithstruct mlx_bbtable_entry 48959136Smsmith{ 49059136Smsmith u_int32_t bbt_block_number; 49159136Smsmith u_int8_t bbt_extent; 49259136Smsmith u_int8_t res1; 49359136Smsmith u_int8_t bbt_entry_type; 49459136Smsmith u_int8_t bbt_system_drive:5; 49559136Smsmith u_int8_t res2:3; 496103870Salfred} __packed; 49759136Smsmith 49858188Smsmith#ifdef _KERNEL 49952544Smsmith/* 50052544Smsmith * Inlines to build various command structures 50152544Smsmith */ 50252544Smsmithstatic __inline void 50352544Smsmithmlx_make_type1(struct mlx_command *mc, 50452544Smsmith u_int8_t code, 50552544Smsmith u_int16_t f1, 50652544Smsmith u_int32_t f2, 50752544Smsmith u_int8_t f3, 50852544Smsmith u_int32_t f4, 50952544Smsmith u_int8_t f5) 51052544Smsmith{ 51152544Smsmith mc->mc_mailbox[0x0] = code; 51252544Smsmith mc->mc_mailbox[0x2] = f1 & 0xff; 51352544Smsmith mc->mc_mailbox[0x3] = (((f2 >> 24) & 0x3) << 6) | ((f1 >> 8) & 0x3f); 51452544Smsmith mc->mc_mailbox[0x4] = f2 & 0xff; 51552544Smsmith mc->mc_mailbox[0x5] = (f2 >> 8) & 0xff; 51652544Smsmith mc->mc_mailbox[0x6] = (f2 >> 16) & 0xff; 51752544Smsmith mc->mc_mailbox[0x7] = f3; 51852544Smsmith mc->mc_mailbox[0x8] = f4 & 0xff; 51952544Smsmith mc->mc_mailbox[0x9] = (f4 >> 8) & 0xff; 52052544Smsmith mc->mc_mailbox[0xa] = (f4 >> 16) & 0xff; 52152544Smsmith mc->mc_mailbox[0xb] = (f4 >> 24) & 0xff; 52252544Smsmith mc->mc_mailbox[0xc] = f5; 52352544Smsmith} 52452544Smsmith 52552544Smsmithstatic __inline void 52652544Smsmithmlx_make_type2(struct mlx_command *mc, 52752544Smsmith u_int8_t code, 52852544Smsmith u_int8_t f1, 52952544Smsmith u_int8_t f2, 53052544Smsmith u_int8_t f3, 53152544Smsmith u_int8_t f4, 53252544Smsmith u_int8_t f5, 53352544Smsmith u_int8_t f6, 53452544Smsmith u_int32_t f7, 53552544Smsmith u_int8_t f8) 53652544Smsmith{ 53752544Smsmith mc->mc_mailbox[0x0] = code; 53852544Smsmith mc->mc_mailbox[0x2] = f1; 53952544Smsmith mc->mc_mailbox[0x3] = f2; 54052544Smsmith mc->mc_mailbox[0x4] = f3; 54152544Smsmith mc->mc_mailbox[0x5] = f4; 54252544Smsmith mc->mc_mailbox[0x6] = f5; 54352544Smsmith mc->mc_mailbox[0x7] = f6; 54452544Smsmith mc->mc_mailbox[0x8] = f7 & 0xff; 54552544Smsmith mc->mc_mailbox[0x9] = (f7 >> 8) & 0xff; 54652544Smsmith mc->mc_mailbox[0xa] = (f7 >> 16) & 0xff; 54752544Smsmith mc->mc_mailbox[0xb] = (f7 >> 24) & 0xff; 54852544Smsmith mc->mc_mailbox[0xc] = f8; 54952544Smsmith} 55052544Smsmith 55152544Smsmithstatic __inline void 55252544Smsmithmlx_make_type3(struct mlx_command *mc, 55352544Smsmith u_int8_t code, 55452544Smsmith u_int8_t f1, 55552544Smsmith u_int8_t f2, 55652544Smsmith u_int16_t f3, 55752544Smsmith u_int8_t f4, 55852544Smsmith u_int8_t f5, 55952544Smsmith u_int32_t f6, 56052544Smsmith u_int8_t f7) 56152544Smsmith{ 56252544Smsmith mc->mc_mailbox[0x0] = code; 56352544Smsmith mc->mc_mailbox[0x2] = f1; 56452544Smsmith mc->mc_mailbox[0x3] = f2; 56552544Smsmith mc->mc_mailbox[0x4] = f3 & 0xff; 56652544Smsmith mc->mc_mailbox[0x5] = (f3 >> 8) & 0xff; 56752544Smsmith mc->mc_mailbox[0x6] = f4; 56852544Smsmith mc->mc_mailbox[0x7] = f5; 56952544Smsmith mc->mc_mailbox[0x8] = f6 & 0xff; 57052544Smsmith mc->mc_mailbox[0x9] = (f6 >> 8) & 0xff; 57152544Smsmith mc->mc_mailbox[0xa] = (f6 >> 16) & 0xff; 57252544Smsmith mc->mc_mailbox[0xb] = (f6 >> 24) & 0xff; 57352544Smsmith mc->mc_mailbox[0xc] = f7; 57452544Smsmith} 57552544Smsmith 57652544Smsmithstatic __inline void 57752544Smsmithmlx_make_type4(struct mlx_command *mc, 57852544Smsmith u_int8_t code, 57952544Smsmith u_int16_t f1, 58052544Smsmith u_int32_t f2, 58152544Smsmith u_int32_t f3, 58252544Smsmith u_int8_t f4) 58352544Smsmith{ 58452544Smsmith mc->mc_mailbox[0x0] = code; 58552544Smsmith mc->mc_mailbox[0x2] = f1 & 0xff; 58652544Smsmith mc->mc_mailbox[0x3] = (f1 >> 8) & 0xff; 58752544Smsmith mc->mc_mailbox[0x4] = f2 & 0xff; 58852544Smsmith mc->mc_mailbox[0x5] = (f2 >> 8) & 0xff; 58952544Smsmith mc->mc_mailbox[0x6] = (f2 >> 16) & 0xff; 59052544Smsmith mc->mc_mailbox[0x7] = (f2 >> 24) & 0xff; 59152544Smsmith mc->mc_mailbox[0x8] = f3 & 0xff; 59252544Smsmith mc->mc_mailbox[0x9] = (f3 >> 8) & 0xff; 59352544Smsmith mc->mc_mailbox[0xa] = (f3 >> 16) & 0xff; 59452544Smsmith mc->mc_mailbox[0xb] = (f3 >> 24) & 0xff; 59552544Smsmith mc->mc_mailbox[0xc] = f4; 59652544Smsmith} 59752544Smsmith 59852544Smsmithstatic __inline void 59952544Smsmithmlx_make_type5(struct mlx_command *mc, 60052544Smsmith u_int8_t code, 60152544Smsmith u_int8_t f1, 60252544Smsmith u_int8_t f2, 60352544Smsmith u_int32_t f3, 60452544Smsmith u_int32_t f4, 60552544Smsmith u_int8_t f5) 60652544Smsmith{ 60752544Smsmith mc->mc_mailbox[0x0] = code; 60852544Smsmith mc->mc_mailbox[0x2] = f1; 60952544Smsmith mc->mc_mailbox[0x3] = f2; 61052544Smsmith mc->mc_mailbox[0x4] = f3 & 0xff; 61152544Smsmith mc->mc_mailbox[0x5] = (f3 >> 8) & 0xff; 61252544Smsmith mc->mc_mailbox[0x6] = (f3 >> 16) & 0xff; 61352544Smsmith mc->mc_mailbox[0x7] = (f3 >> 24) & 0xff; 61452544Smsmith mc->mc_mailbox[0x8] = f4 & 0xff; 61552544Smsmith mc->mc_mailbox[0x9] = (f4 >> 8) & 0xff; 61652544Smsmith mc->mc_mailbox[0xa] = (f4 >> 16) & 0xff; 61752544Smsmith mc->mc_mailbox[0xb] = (f4 >> 24) & 0xff; 61852544Smsmith mc->mc_mailbox[0xc] = f5; 61952544Smsmith} 62058188Smsmith 62158188Smsmith#endif /* _KERNEL */ 622