195663Sphk/* $NetBSD: mii.h,v 1.9 2001/05/31 03:07:14 thorpej Exp $ */ 2213878Smarius 3139749Simp/*- 450120Swpaul * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 550120Swpaul * 650120Swpaul * Modification to match BSD/OS 3.0 MII interface by Jason R. Thorpe, 750120Swpaul * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 850120Swpaul * 950120Swpaul * Redistribution and use in source and binary forms, with or without 1050120Swpaul * modification, are permitted provided that the following conditions 1150120Swpaul * are met: 1250120Swpaul * 1. Redistributions of source code must retain the above copyright 1350120Swpaul * notice, this list of conditions and the following disclaimer. 1450120Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1550120Swpaul * notice, this list of conditions and the following disclaimer in the 1650120Swpaul * documentation and/or other materials provided with the distribution. 1750120Swpaul * 1850120Swpaul * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1950120Swpaul * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2050120Swpaul * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2150120Swpaul * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2250120Swpaul * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2350120Swpaul * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2450120Swpaul * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2550120Swpaul * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2650120Swpaul * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2750120Swpaul * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2850120Swpaul * 2950477Speter * $FreeBSD$ 3050120Swpaul */ 3150120Swpaul 3250120Swpaul#ifndef _DEV_MII_MII_H_ 3350120Swpaul#define _DEV_MII_MII_H_ 3450120Swpaul 3550120Swpaul/* 3650120Swpaul * Registers common to all PHYs. 3750120Swpaul */ 3850120Swpaul 3950120Swpaul#define MII_NPHY 32 /* max # of PHYs per MII */ 4050120Swpaul 4150120Swpaul/* 4250120Swpaul * MII commands, used if a device must drive the MII lines 4350120Swpaul * manually. 4450120Swpaul */ 4550120Swpaul#define MII_COMMAND_START 0x01 4650120Swpaul#define MII_COMMAND_READ 0x02 4750120Swpaul#define MII_COMMAND_WRITE 0x01 4850120Swpaul#define MII_COMMAND_ACK 0x02 4950120Swpaul 50213878Smarius#define MII_BMCR 0x00 /* Basic mode control register (rw) */ 5150120Swpaul#define BMCR_RESET 0x8000 /* reset */ 5250120Swpaul#define BMCR_LOOP 0x4000 /* loopback */ 5395663Sphk#define BMCR_SPEED0 0x2000 /* speed selection (LSB) */ 5450120Swpaul#define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 5550120Swpaul#define BMCR_PDOWN 0x0800 /* power down */ 5650120Swpaul#define BMCR_ISO 0x0400 /* isolate */ 5750120Swpaul#define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 5850120Swpaul#define BMCR_FDX 0x0100 /* Set duplex mode */ 5950120Swpaul#define BMCR_CTEST 0x0080 /* collision test */ 6095663Sphk#define BMCR_SPEED1 0x0040 /* speed selection (MSB) */ 6150120Swpaul 6295663Sphk#define BMCR_S10 0x0000 /* 10 Mb/s */ 6395663Sphk#define BMCR_S100 BMCR_SPEED0 /* 100 Mb/s */ 6495663Sphk#define BMCR_S1000 BMCR_SPEED1 /* 1000 Mb/s */ 6595663Sphk 6695663Sphk#define BMCR_SPEED(x) ((x) & (BMCR_SPEED0|BMCR_SPEED1)) 6795663Sphk 6850120Swpaul#define MII_BMSR 0x01 /* Basic mode status register (ro) */ 6950120Swpaul#define BMSR_100T4 0x8000 /* 100 base T4 capable */ 7050120Swpaul#define BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */ 7150120Swpaul#define BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */ 7250120Swpaul#define BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */ 7350120Swpaul#define BMSR_10THDX 0x0800 /* 10 base T half duplex capable */ 7495663Sphk#define BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */ 7595663Sphk#define BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */ 7695663Sphk#define BMSR_EXTSTAT 0x0100 /* Extended status in register 15 */ 7795663Sphk#define BMSR_MFPS 0x0040 /* MII Frame Preamble Suppression */ 7850120Swpaul#define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ 7950120Swpaul#define BMSR_RFAULT 0x0010 /* Link partner fault */ 8050120Swpaul#define BMSR_ANEG 0x0008 /* Autonegotiation capable */ 8150120Swpaul#define BMSR_LINK 0x0004 /* Link status */ 8250120Swpaul#define BMSR_JABBER 0x0002 /* Jabber detected */ 8395663Sphk#define BMSR_EXTCAP 0x0001 /* Extended capability */ 8450120Swpaul 85213878Smarius#define BMSR_DEFCAPMASK 0xffffffff 86213878Smarius 8795663Sphk/* 8895663Sphk * Note that the EXTSTAT bit indicates that there is extended status 8995663Sphk * info available in register 15, but 802.3 section 22.2.4.3 also 9095663Sphk * states that that all 1000 Mb/s capable PHYs will set this bit to 1. 9195663Sphk */ 9250120Swpaul 9395663Sphk#define BMSR_MEDIAMASK (BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX| \ 9495663Sphk BMSR_10TFDX|BMSR_10THDX|BMSR_100T2FDX|BMSR_100T2HDX) 9595663Sphk 9650120Swpaul/* 9750120Swpaul * Convert BMSR media capabilities to ANAR bits for autonegotiation. 9850120Swpaul * Note the shift chopps off the BMSR_ANEG bit. 9950120Swpaul */ 10050120Swpaul#define BMSR_MEDIA_TO_ANAR(x) (((x) & BMSR_MEDIAMASK) >> 6) 10150120Swpaul 10250120Swpaul#define MII_PHYIDR1 0x02 /* ID register 1 (ro) */ 10350120Swpaul 10450120Swpaul#define MII_PHYIDR2 0x03 /* ID register 2 (ro) */ 10550120Swpaul#define IDR2_OUILSB 0xfc00 /* OUI LSB */ 10650120Swpaul#define IDR2_MODEL 0x03f0 /* vendor model */ 10750120Swpaul#define IDR2_REV 0x000f /* vendor revision */ 10850120Swpaul 10950120Swpaul#define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */ 11095663Sphk /* section 28.2.4.1 and 37.2.6.1 */ 11150120Swpaul#define ANAR_NP 0x8000 /* Next page (ro) */ 11250120Swpaul#define ANAR_ACK 0x4000 /* link partner abilities acknowledged (ro) */ 11350120Swpaul#define ANAR_RF 0x2000 /* remote fault (ro) */ 11495663Sphk#define ANAR_FC 0x0400 /* local device supports PAUSE */ 11550120Swpaul#define ANAR_T4 0x0200 /* local device supports 100bT4 */ 11650120Swpaul#define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 11750120Swpaul#define ANAR_TX 0x0080 /* local device supports 100bTx */ 11850120Swpaul#define ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 11950120Swpaul#define ANAR_10 0x0020 /* local device supports 10bT */ 12050120Swpaul#define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 121215297Smarius#define ANAR_PAUSE_NONE (0 << 10) 122215297Smarius#define ANAR_PAUSE_SYM (1 << 10) 123215297Smarius#define ANAR_PAUSE_ASYM (2 << 10) 124215297Smarius#define ANAR_PAUSE_TOWARDS (3 << 10) 12550120Swpaul 12695663Sphk#define ANAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */ 12795663Sphk#define ANAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */ 12895663Sphk#define ANAR_X_PAUSE_NONE (0 << 7) 12995663Sphk#define ANAR_X_PAUSE_SYM (1 << 7) 13095663Sphk#define ANAR_X_PAUSE_ASYM (2 << 7) 13195663Sphk#define ANAR_X_PAUSE_TOWARDS (3 << 7) 13295663Sphk 13350120Swpaul#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ 13495663Sphk /* section 28.2.4.1 and 37.2.6.1 */ 13550120Swpaul#define ANLPAR_NP 0x8000 /* Next page (ro) */ 13650120Swpaul#define ANLPAR_ACK 0x4000 /* link partner accepted ACK (ro) */ 13750120Swpaul#define ANLPAR_RF 0x2000 /* remote fault (ro) */ 13895663Sphk#define ANLPAR_FC 0x0400 /* link partner supports PAUSE */ 13950120Swpaul#define ANLPAR_T4 0x0200 /* link partner supports 100bT4 */ 14050120Swpaul#define ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */ 14150120Swpaul#define ANLPAR_TX 0x0080 /* link partner supports 100bTx */ 14250120Swpaul#define ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */ 14350120Swpaul#define ANLPAR_10 0x0020 /* link partner supports 10bT */ 14450120Swpaul#define ANLPAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 145215297Smarius#define ANLPAR_PAUSE_MASK (3 << 10) 146215297Smarius#define ANLPAR_PAUSE_NONE (0 << 10) 147215297Smarius#define ANLPAR_PAUSE_SYM (1 << 10) 148215297Smarius#define ANLPAR_PAUSE_ASYM (2 << 10) 149215297Smarius#define ANLPAR_PAUSE_TOWARDS (3 << 10) 15050120Swpaul 15195663Sphk#define ANLPAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */ 15295663Sphk#define ANLPAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */ 15395663Sphk#define ANLPAR_X_PAUSE_MASK (3 << 7) 15495663Sphk#define ANLPAR_X_PAUSE_NONE (0 << 7) 15595663Sphk#define ANLPAR_X_PAUSE_SYM (1 << 7) 15695663Sphk#define ANLPAR_X_PAUSE_ASYM (2 << 7) 15795663Sphk#define ANLPAR_X_PAUSE_TOWARDS (3 << 7) 15895663Sphk 15950120Swpaul#define MII_ANER 0x06 /* Autonegotiation expansion (ro) */ 16095663Sphk /* section 28.2.4.1 and 37.2.6.1 */ 16150120Swpaul#define ANER_MLF 0x0010 /* multiple link detection fault */ 16250120Swpaul#define ANER_LPNP 0x0008 /* link parter next page-able */ 16350120Swpaul#define ANER_NP 0x0004 /* next page-able */ 16450120Swpaul#define ANER_PAGE_RX 0x0002 /* Page received */ 16550120Swpaul#define ANER_LPAN 0x0001 /* link parter autoneg-able */ 16650120Swpaul 16795663Sphk#define MII_ANNP 0x07 /* Autonegotiation next page */ 16895663Sphk /* section 28.2.4.1 and 37.2.6.1 */ 16995663Sphk 17095663Sphk#define MII_ANLPRNP 0x08 /* Autonegotiation link partner rx next page */ 17195663Sphk /* section 32.5.1 and 37.2.6.1 */ 17295663Sphk 17395663Sphk /* This is also the 1000baseT control register */ 17495663Sphk#define MII_100T2CR 0x09 /* 100base-T2 control register */ 17595663Sphk#define GTCR_TEST_MASK 0xe000 /* see 802.3ab ss. 40.6.1.1.2 */ 17695663Sphk#define GTCR_MAN_MS 0x1000 /* enable manual master/slave control */ 17795663Sphk#define GTCR_ADV_MS 0x0800 /* 1 = adv. master, 0 = adv. slave */ 17895663Sphk#define GTCR_PORT_TYPE 0x0400 /* 1 = DCE, 0 = DTE (NIC) */ 17995663Sphk#define GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */ 18095663Sphk#define GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */ 18195663Sphk 18295663Sphk /* This is also the 1000baseT status register */ 18395663Sphk#define MII_100T2SR 0x0a /* 100base-T2 status register */ 18495663Sphk#define GTSR_MAN_MS_FLT 0x8000 /* master/slave config fault */ 18595663Sphk#define GTSR_MS_RES 0x4000 /* result: 1 = master, 0 = slave */ 18695663Sphk#define GTSR_LRS 0x2000 /* local rx status, 1 = ok */ 18795663Sphk#define GTSR_RRS 0x1000 /* remove rx status, 1 = ok */ 18895663Sphk#define GTSR_LP_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */ 18995663Sphk#define GTSR_LP_1000THDX 0x0400 /* link partner 1000baseT HDX capable */ 19095663Sphk#define GTSR_LP_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */ 19195663Sphk#define GTSR_IDLE_ERR 0x00ff /* IDLE error count */ 19295663Sphk 19395663Sphk#define MII_EXTSR 0x0f /* Extended status register */ 19495663Sphk#define EXTSR_1000XFDX 0x8000 /* 1000X full-duplex capable */ 19595663Sphk#define EXTSR_1000XHDX 0x4000 /* 1000X half-duplex capable */ 19695663Sphk#define EXTSR_1000TFDX 0x2000 /* 1000T full-duplex capable */ 19795663Sphk#define EXTSR_1000THDX 0x1000 /* 1000T half-duplex capable */ 19895663Sphk 19995663Sphk#define EXTSR_MEDIAMASK (EXTSR_1000XFDX|EXTSR_1000XHDX| \ 20095663Sphk EXTSR_1000TFDX|EXTSR_1000THDX) 20195663Sphk 20250120Swpaul#endif /* _DEV_MII_MII_H_ */ 203