1270631Sjfv/****************************************************************************** 2270631Sjfv 3270631Sjfv Copyright (c) 2013-2014, Intel Corporation 4270631Sjfv All rights reserved. 5270631Sjfv 6270631Sjfv Redistribution and use in source and binary forms, with or without 7270631Sjfv modification, are permitted provided that the following conditions are met: 8270631Sjfv 9270631Sjfv 1. Redistributions of source code must retain the above copyright notice, 10270631Sjfv this list of conditions and the following disclaimer. 11270631Sjfv 12270631Sjfv 2. Redistributions in binary form must reproduce the above copyright 13270631Sjfv notice, this list of conditions and the following disclaimer in the 14270631Sjfv documentation and/or other materials provided with the distribution. 15270631Sjfv 16270631Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17270631Sjfv contributors may be used to endorse or promote products derived from 18270631Sjfv this software without specific prior written permission. 19270631Sjfv 20270631Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21270631Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22270631Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23270631Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24270631Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25270631Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26270631Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27270631Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28270631Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29270631Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30270631Sjfv POSSIBILITY OF SUCH DAMAGE. 31270631Sjfv 32270631Sjfv******************************************************************************/ 33270631Sjfv/*$FreeBSD$*/ 34270631Sjfv 35270631Sjfv#include "i40e_type.h" 36270631Sjfv#include "i40e_adminq.h" 37270631Sjfv#include "i40e_prototype.h" 38270631Sjfv#include "i40e_virtchnl.h" 39270631Sjfv 40270631Sjfv/** 41270631Sjfv * i40e_set_mac_type - Sets MAC type 42270631Sjfv * @hw: pointer to the HW structure 43270631Sjfv * 44270631Sjfv * This function sets the mac type of the adapter based on the 45270631Sjfv * vendor ID and device ID stored in the hw structure. 46270631Sjfv **/ 47270631Sjfvenum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 48270631Sjfv{ 49270631Sjfv enum i40e_status_code status = I40E_SUCCESS; 50270631Sjfv 51270631Sjfv DEBUGFUNC("i40e_set_mac_type\n"); 52270631Sjfv 53270631Sjfv if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 54270631Sjfv switch (hw->device_id) { 55270631Sjfv case I40E_DEV_ID_SFP_XL710: 56270631Sjfv case I40E_DEV_ID_QEMU: 57270631Sjfv case I40E_DEV_ID_KX_A: 58270631Sjfv case I40E_DEV_ID_KX_B: 59270631Sjfv case I40E_DEV_ID_KX_C: 60270631Sjfv case I40E_DEV_ID_QSFP_A: 61270631Sjfv case I40E_DEV_ID_QSFP_B: 62270631Sjfv case I40E_DEV_ID_QSFP_C: 63270631Sjfv case I40E_DEV_ID_10G_BASE_T: 64270631Sjfv hw->mac.type = I40E_MAC_XL710; 65270631Sjfv break; 66270631Sjfv case I40E_DEV_ID_VF: 67270631Sjfv case I40E_DEV_ID_VF_HV: 68270631Sjfv hw->mac.type = I40E_MAC_VF; 69270631Sjfv break; 70270631Sjfv default: 71270631Sjfv hw->mac.type = I40E_MAC_GENERIC; 72270631Sjfv break; 73270631Sjfv } 74270631Sjfv } else { 75270631Sjfv status = I40E_ERR_DEVICE_NOT_SUPPORTED; 76270631Sjfv } 77270631Sjfv 78270631Sjfv DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 79270631Sjfv hw->mac.type, status); 80270631Sjfv return status; 81270631Sjfv} 82270631Sjfv 83270631Sjfv/** 84270631Sjfv * i40e_debug_aq 85270631Sjfv * @hw: debug mask related to admin queue 86270631Sjfv * @mask: debug mask 87270631Sjfv * @desc: pointer to admin queue descriptor 88270631Sjfv * @buffer: pointer to command buffer 89270631Sjfv * @buf_len: max length of buffer 90270631Sjfv * 91270631Sjfv * Dumps debug log about adminq command with descriptor contents. 92270631Sjfv **/ 93270631Sjfvvoid i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 94270631Sjfv void *buffer, u16 buf_len) 95270631Sjfv{ 96270631Sjfv struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 97270631Sjfv u16 len = LE16_TO_CPU(aq_desc->datalen); 98270631Sjfv u8 *aq_buffer = (u8 *)buffer; 99270631Sjfv u32 data[4]; 100270631Sjfv u32 i = 0; 101270631Sjfv 102270631Sjfv if ((!(mask & hw->debug_mask)) || (desc == NULL)) 103270631Sjfv return; 104270631Sjfv 105270631Sjfv i40e_debug(hw, mask, 106270631Sjfv "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 107270631Sjfv aq_desc->opcode, aq_desc->flags, aq_desc->datalen, 108270631Sjfv aq_desc->retval); 109270631Sjfv i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 110270631Sjfv aq_desc->cookie_high, aq_desc->cookie_low); 111270631Sjfv i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 112270631Sjfv aq_desc->params.internal.param0, 113270631Sjfv aq_desc->params.internal.param1); 114270631Sjfv i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 115270631Sjfv aq_desc->params.external.addr_high, 116270631Sjfv aq_desc->params.external.addr_low); 117270631Sjfv 118270631Sjfv if ((buffer != NULL) && (aq_desc->datalen != 0)) { 119270631Sjfv i40e_memset(data, 0, sizeof(data), I40E_NONDMA_MEM); 120270631Sjfv i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 121270631Sjfv if (buf_len < len) 122270631Sjfv len = buf_len; 123270631Sjfv for (i = 0; i < len; i++) { 124270631Sjfv data[((i % 16) / 4)] |= 125270631Sjfv ((u32)aq_buffer[i]) << (8 * (i % 4)); 126270631Sjfv if ((i % 16) == 15) { 127270631Sjfv i40e_debug(hw, mask, 128270631Sjfv "\t0x%04X %08X %08X %08X %08X\n", 129270631Sjfv i - 15, data[0], data[1], data[2], 130270631Sjfv data[3]); 131270631Sjfv i40e_memset(data, 0, sizeof(data), 132270631Sjfv I40E_NONDMA_MEM); 133270631Sjfv } 134270631Sjfv } 135270631Sjfv if ((i % 16) != 0) 136270631Sjfv i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n", 137270631Sjfv i - (i % 16), data[0], data[1], data[2], 138270631Sjfv data[3]); 139270631Sjfv } 140270631Sjfv} 141270631Sjfv 142270631Sjfv/** 143270631Sjfv * i40e_check_asq_alive 144270631Sjfv * @hw: pointer to the hw struct 145270631Sjfv * 146270631Sjfv * Returns TRUE if Queue is enabled else FALSE. 147270631Sjfv **/ 148270631Sjfvbool i40e_check_asq_alive(struct i40e_hw *hw) 149270631Sjfv{ 150270631Sjfv if (hw->aq.asq.len) 151270631Sjfv return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK); 152270631Sjfv else 153270631Sjfv return FALSE; 154270631Sjfv} 155270631Sjfv 156270631Sjfv/** 157270631Sjfv * i40e_aq_queue_shutdown 158270631Sjfv * @hw: pointer to the hw struct 159270631Sjfv * @unloading: is the driver unloading itself 160270631Sjfv * 161270631Sjfv * Tell the Firmware that we're shutting down the AdminQ and whether 162270631Sjfv * or not the driver is unloading as well. 163270631Sjfv **/ 164270631Sjfvenum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 165270631Sjfv bool unloading) 166270631Sjfv{ 167270631Sjfv struct i40e_aq_desc desc; 168270631Sjfv struct i40e_aqc_queue_shutdown *cmd = 169270631Sjfv (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 170270631Sjfv enum i40e_status_code status; 171270631Sjfv 172270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 173270631Sjfv i40e_aqc_opc_queue_shutdown); 174270631Sjfv 175270631Sjfv if (unloading) 176270631Sjfv cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 177270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 178270631Sjfv 179270631Sjfv return status; 180270631Sjfv} 181270631Sjfv 182270631Sjfv/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 183270631Sjfv * hardware to a bit-field that can be used by SW to more easily determine the 184270631Sjfv * packet type. 185270631Sjfv * 186270631Sjfv * Macros are used to shorten the table lines and make this table human 187270631Sjfv * readable. 188270631Sjfv * 189270631Sjfv * We store the PTYPE in the top byte of the bit field - this is just so that 190270631Sjfv * we can check that the table doesn't have a row missing, as the index into 191270631Sjfv * the table should be the PTYPE. 192270631Sjfv * 193270631Sjfv * Typical work flow: 194270631Sjfv * 195270631Sjfv * IF NOT i40e_ptype_lookup[ptype].known 196270631Sjfv * THEN 197270631Sjfv * Packet is unknown 198270631Sjfv * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 199270631Sjfv * Use the rest of the fields to look at the tunnels, inner protocols, etc 200270631Sjfv * ELSE 201270631Sjfv * Use the enum i40e_rx_l2_ptype to decode the packet type 202270631Sjfv * ENDIF 203270631Sjfv */ 204270631Sjfv 205270631Sjfv/* macro to make the table lines short */ 206270631Sjfv#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 207270631Sjfv { PTYPE, \ 208270631Sjfv 1, \ 209270631Sjfv I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 210270631Sjfv I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 211270631Sjfv I40E_RX_PTYPE_##OUTER_FRAG, \ 212270631Sjfv I40E_RX_PTYPE_TUNNEL_##T, \ 213270631Sjfv I40E_RX_PTYPE_TUNNEL_END_##TE, \ 214270631Sjfv I40E_RX_PTYPE_##TEF, \ 215270631Sjfv I40E_RX_PTYPE_INNER_PROT_##I, \ 216270631Sjfv I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 217270631Sjfv 218270631Sjfv#define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 219270631Sjfv { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 220270631Sjfv 221270631Sjfv/* shorter macros makes the table fit but are terse */ 222270631Sjfv#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 223270631Sjfv#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 224270631Sjfv#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 225270631Sjfv 226270631Sjfv/* Lookup table mapping the HW PTYPE to the bit field for decoding */ 227270631Sjfvstruct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 228270631Sjfv /* L2 Packet types */ 229270631Sjfv I40E_PTT_UNUSED_ENTRY(0), 230270631Sjfv I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 231270631Sjfv I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 232270631Sjfv I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 233270631Sjfv I40E_PTT_UNUSED_ENTRY(4), 234270631Sjfv I40E_PTT_UNUSED_ENTRY(5), 235270631Sjfv I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 236270631Sjfv I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 237270631Sjfv I40E_PTT_UNUSED_ENTRY(8), 238270631Sjfv I40E_PTT_UNUSED_ENTRY(9), 239270631Sjfv I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 240270631Sjfv I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 241270631Sjfv I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 242270631Sjfv I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 243270631Sjfv I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 244270631Sjfv I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 245270631Sjfv I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 246270631Sjfv I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 247270631Sjfv I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 248270631Sjfv I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 249270631Sjfv I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 250270631Sjfv I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 251270631Sjfv 252270631Sjfv /* Non Tunneled IPv4 */ 253270631Sjfv I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 254270631Sjfv I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 255270631Sjfv I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 256270631Sjfv I40E_PTT_UNUSED_ENTRY(25), 257270631Sjfv I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 258270631Sjfv I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 259270631Sjfv I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 260270631Sjfv 261270631Sjfv /* IPv4 --> IPv4 */ 262270631Sjfv I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 263270631Sjfv I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 264270631Sjfv I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 265270631Sjfv I40E_PTT_UNUSED_ENTRY(32), 266270631Sjfv I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 267270631Sjfv I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 268270631Sjfv I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 269270631Sjfv 270270631Sjfv /* IPv4 --> IPv6 */ 271270631Sjfv I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 272270631Sjfv I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 273270631Sjfv I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 274270631Sjfv I40E_PTT_UNUSED_ENTRY(39), 275270631Sjfv I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 276270631Sjfv I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 277270631Sjfv I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 278270631Sjfv 279270631Sjfv /* IPv4 --> GRE/NAT */ 280270631Sjfv I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 281270631Sjfv 282270631Sjfv /* IPv4 --> GRE/NAT --> IPv4 */ 283270631Sjfv I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 284270631Sjfv I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 285270631Sjfv I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 286270631Sjfv I40E_PTT_UNUSED_ENTRY(47), 287270631Sjfv I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 288270631Sjfv I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 289270631Sjfv I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 290270631Sjfv 291270631Sjfv /* IPv4 --> GRE/NAT --> IPv6 */ 292270631Sjfv I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 293270631Sjfv I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 294270631Sjfv I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 295270631Sjfv I40E_PTT_UNUSED_ENTRY(54), 296270631Sjfv I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 297270631Sjfv I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 298270631Sjfv I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 299270631Sjfv 300270631Sjfv /* IPv4 --> GRE/NAT --> MAC */ 301270631Sjfv I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 302270631Sjfv 303270631Sjfv /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 304270631Sjfv I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 305270631Sjfv I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 306270631Sjfv I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 307270631Sjfv I40E_PTT_UNUSED_ENTRY(62), 308270631Sjfv I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 309270631Sjfv I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 310270631Sjfv I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 311270631Sjfv 312270631Sjfv /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 313270631Sjfv I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 314270631Sjfv I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 315270631Sjfv I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 316270631Sjfv I40E_PTT_UNUSED_ENTRY(69), 317270631Sjfv I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 318270631Sjfv I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 319270631Sjfv I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 320270631Sjfv 321270631Sjfv /* IPv4 --> GRE/NAT --> MAC/VLAN */ 322270631Sjfv I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 323270631Sjfv 324270631Sjfv /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 325270631Sjfv I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 326270631Sjfv I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 327270631Sjfv I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 328270631Sjfv I40E_PTT_UNUSED_ENTRY(77), 329270631Sjfv I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 330270631Sjfv I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 331270631Sjfv I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 332270631Sjfv 333270631Sjfv /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 334270631Sjfv I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 335270631Sjfv I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 336270631Sjfv I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 337270631Sjfv I40E_PTT_UNUSED_ENTRY(84), 338270631Sjfv I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 339270631Sjfv I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 340270631Sjfv I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 341270631Sjfv 342270631Sjfv /* Non Tunneled IPv6 */ 343270631Sjfv I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 344270631Sjfv I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 345270631Sjfv I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 346270631Sjfv I40E_PTT_UNUSED_ENTRY(91), 347270631Sjfv I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 348270631Sjfv I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 349270631Sjfv I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 350270631Sjfv 351270631Sjfv /* IPv6 --> IPv4 */ 352270631Sjfv I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 353270631Sjfv I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 354270631Sjfv I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 355270631Sjfv I40E_PTT_UNUSED_ENTRY(98), 356270631Sjfv I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 357270631Sjfv I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 358270631Sjfv I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 359270631Sjfv 360270631Sjfv /* IPv6 --> IPv6 */ 361270631Sjfv I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 362270631Sjfv I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 363270631Sjfv I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 364270631Sjfv I40E_PTT_UNUSED_ENTRY(105), 365270631Sjfv I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 366270631Sjfv I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 367270631Sjfv I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 368270631Sjfv 369270631Sjfv /* IPv6 --> GRE/NAT */ 370270631Sjfv I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 371270631Sjfv 372270631Sjfv /* IPv6 --> GRE/NAT -> IPv4 */ 373270631Sjfv I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 374270631Sjfv I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 375270631Sjfv I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 376270631Sjfv I40E_PTT_UNUSED_ENTRY(113), 377270631Sjfv I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 378270631Sjfv I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 379270631Sjfv I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 380270631Sjfv 381270631Sjfv /* IPv6 --> GRE/NAT -> IPv6 */ 382270631Sjfv I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 383270631Sjfv I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 384270631Sjfv I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 385270631Sjfv I40E_PTT_UNUSED_ENTRY(120), 386270631Sjfv I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 387270631Sjfv I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 388270631Sjfv I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 389270631Sjfv 390270631Sjfv /* IPv6 --> GRE/NAT -> MAC */ 391270631Sjfv I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 392270631Sjfv 393270631Sjfv /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 394270631Sjfv I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 395270631Sjfv I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 396270631Sjfv I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 397270631Sjfv I40E_PTT_UNUSED_ENTRY(128), 398270631Sjfv I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 399270631Sjfv I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 400270631Sjfv I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 401270631Sjfv 402270631Sjfv /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 403270631Sjfv I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 404270631Sjfv I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 405270631Sjfv I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 406270631Sjfv I40E_PTT_UNUSED_ENTRY(135), 407270631Sjfv I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 408270631Sjfv I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 409270631Sjfv I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 410270631Sjfv 411270631Sjfv /* IPv6 --> GRE/NAT -> MAC/VLAN */ 412270631Sjfv I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 413270631Sjfv 414270631Sjfv /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 415270631Sjfv I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 416270631Sjfv I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 417270631Sjfv I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 418270631Sjfv I40E_PTT_UNUSED_ENTRY(143), 419270631Sjfv I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 420270631Sjfv I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 421270631Sjfv I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 422270631Sjfv 423270631Sjfv /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 424270631Sjfv I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 425270631Sjfv I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 426270631Sjfv I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 427270631Sjfv I40E_PTT_UNUSED_ENTRY(150), 428270631Sjfv I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 429270631Sjfv I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 430270631Sjfv I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 431270631Sjfv 432270631Sjfv /* unused entries */ 433270631Sjfv I40E_PTT_UNUSED_ENTRY(154), 434270631Sjfv I40E_PTT_UNUSED_ENTRY(155), 435270631Sjfv I40E_PTT_UNUSED_ENTRY(156), 436270631Sjfv I40E_PTT_UNUSED_ENTRY(157), 437270631Sjfv I40E_PTT_UNUSED_ENTRY(158), 438270631Sjfv I40E_PTT_UNUSED_ENTRY(159), 439270631Sjfv 440270631Sjfv I40E_PTT_UNUSED_ENTRY(160), 441270631Sjfv I40E_PTT_UNUSED_ENTRY(161), 442270631Sjfv I40E_PTT_UNUSED_ENTRY(162), 443270631Sjfv I40E_PTT_UNUSED_ENTRY(163), 444270631Sjfv I40E_PTT_UNUSED_ENTRY(164), 445270631Sjfv I40E_PTT_UNUSED_ENTRY(165), 446270631Sjfv I40E_PTT_UNUSED_ENTRY(166), 447270631Sjfv I40E_PTT_UNUSED_ENTRY(167), 448270631Sjfv I40E_PTT_UNUSED_ENTRY(168), 449270631Sjfv I40E_PTT_UNUSED_ENTRY(169), 450270631Sjfv 451270631Sjfv I40E_PTT_UNUSED_ENTRY(170), 452270631Sjfv I40E_PTT_UNUSED_ENTRY(171), 453270631Sjfv I40E_PTT_UNUSED_ENTRY(172), 454270631Sjfv I40E_PTT_UNUSED_ENTRY(173), 455270631Sjfv I40E_PTT_UNUSED_ENTRY(174), 456270631Sjfv I40E_PTT_UNUSED_ENTRY(175), 457270631Sjfv I40E_PTT_UNUSED_ENTRY(176), 458270631Sjfv I40E_PTT_UNUSED_ENTRY(177), 459270631Sjfv I40E_PTT_UNUSED_ENTRY(178), 460270631Sjfv I40E_PTT_UNUSED_ENTRY(179), 461270631Sjfv 462270631Sjfv I40E_PTT_UNUSED_ENTRY(180), 463270631Sjfv I40E_PTT_UNUSED_ENTRY(181), 464270631Sjfv I40E_PTT_UNUSED_ENTRY(182), 465270631Sjfv I40E_PTT_UNUSED_ENTRY(183), 466270631Sjfv I40E_PTT_UNUSED_ENTRY(184), 467270631Sjfv I40E_PTT_UNUSED_ENTRY(185), 468270631Sjfv I40E_PTT_UNUSED_ENTRY(186), 469270631Sjfv I40E_PTT_UNUSED_ENTRY(187), 470270631Sjfv I40E_PTT_UNUSED_ENTRY(188), 471270631Sjfv I40E_PTT_UNUSED_ENTRY(189), 472270631Sjfv 473270631Sjfv I40E_PTT_UNUSED_ENTRY(190), 474270631Sjfv I40E_PTT_UNUSED_ENTRY(191), 475270631Sjfv I40E_PTT_UNUSED_ENTRY(192), 476270631Sjfv I40E_PTT_UNUSED_ENTRY(193), 477270631Sjfv I40E_PTT_UNUSED_ENTRY(194), 478270631Sjfv I40E_PTT_UNUSED_ENTRY(195), 479270631Sjfv I40E_PTT_UNUSED_ENTRY(196), 480270631Sjfv I40E_PTT_UNUSED_ENTRY(197), 481270631Sjfv I40E_PTT_UNUSED_ENTRY(198), 482270631Sjfv I40E_PTT_UNUSED_ENTRY(199), 483270631Sjfv 484270631Sjfv I40E_PTT_UNUSED_ENTRY(200), 485270631Sjfv I40E_PTT_UNUSED_ENTRY(201), 486270631Sjfv I40E_PTT_UNUSED_ENTRY(202), 487270631Sjfv I40E_PTT_UNUSED_ENTRY(203), 488270631Sjfv I40E_PTT_UNUSED_ENTRY(204), 489270631Sjfv I40E_PTT_UNUSED_ENTRY(205), 490270631Sjfv I40E_PTT_UNUSED_ENTRY(206), 491270631Sjfv I40E_PTT_UNUSED_ENTRY(207), 492270631Sjfv I40E_PTT_UNUSED_ENTRY(208), 493270631Sjfv I40E_PTT_UNUSED_ENTRY(209), 494270631Sjfv 495270631Sjfv I40E_PTT_UNUSED_ENTRY(210), 496270631Sjfv I40E_PTT_UNUSED_ENTRY(211), 497270631Sjfv I40E_PTT_UNUSED_ENTRY(212), 498270631Sjfv I40E_PTT_UNUSED_ENTRY(213), 499270631Sjfv I40E_PTT_UNUSED_ENTRY(214), 500270631Sjfv I40E_PTT_UNUSED_ENTRY(215), 501270631Sjfv I40E_PTT_UNUSED_ENTRY(216), 502270631Sjfv I40E_PTT_UNUSED_ENTRY(217), 503270631Sjfv I40E_PTT_UNUSED_ENTRY(218), 504270631Sjfv I40E_PTT_UNUSED_ENTRY(219), 505270631Sjfv 506270631Sjfv I40E_PTT_UNUSED_ENTRY(220), 507270631Sjfv I40E_PTT_UNUSED_ENTRY(221), 508270631Sjfv I40E_PTT_UNUSED_ENTRY(222), 509270631Sjfv I40E_PTT_UNUSED_ENTRY(223), 510270631Sjfv I40E_PTT_UNUSED_ENTRY(224), 511270631Sjfv I40E_PTT_UNUSED_ENTRY(225), 512270631Sjfv I40E_PTT_UNUSED_ENTRY(226), 513270631Sjfv I40E_PTT_UNUSED_ENTRY(227), 514270631Sjfv I40E_PTT_UNUSED_ENTRY(228), 515270631Sjfv I40E_PTT_UNUSED_ENTRY(229), 516270631Sjfv 517270631Sjfv I40E_PTT_UNUSED_ENTRY(230), 518270631Sjfv I40E_PTT_UNUSED_ENTRY(231), 519270631Sjfv I40E_PTT_UNUSED_ENTRY(232), 520270631Sjfv I40E_PTT_UNUSED_ENTRY(233), 521270631Sjfv I40E_PTT_UNUSED_ENTRY(234), 522270631Sjfv I40E_PTT_UNUSED_ENTRY(235), 523270631Sjfv I40E_PTT_UNUSED_ENTRY(236), 524270631Sjfv I40E_PTT_UNUSED_ENTRY(237), 525270631Sjfv I40E_PTT_UNUSED_ENTRY(238), 526270631Sjfv I40E_PTT_UNUSED_ENTRY(239), 527270631Sjfv 528270631Sjfv I40E_PTT_UNUSED_ENTRY(240), 529270631Sjfv I40E_PTT_UNUSED_ENTRY(241), 530270631Sjfv I40E_PTT_UNUSED_ENTRY(242), 531270631Sjfv I40E_PTT_UNUSED_ENTRY(243), 532270631Sjfv I40E_PTT_UNUSED_ENTRY(244), 533270631Sjfv I40E_PTT_UNUSED_ENTRY(245), 534270631Sjfv I40E_PTT_UNUSED_ENTRY(246), 535270631Sjfv I40E_PTT_UNUSED_ENTRY(247), 536270631Sjfv I40E_PTT_UNUSED_ENTRY(248), 537270631Sjfv I40E_PTT_UNUSED_ENTRY(249), 538270631Sjfv 539270631Sjfv I40E_PTT_UNUSED_ENTRY(250), 540270631Sjfv I40E_PTT_UNUSED_ENTRY(251), 541270631Sjfv I40E_PTT_UNUSED_ENTRY(252), 542270631Sjfv I40E_PTT_UNUSED_ENTRY(253), 543270631Sjfv I40E_PTT_UNUSED_ENTRY(254), 544270631Sjfv I40E_PTT_UNUSED_ENTRY(255) 545270631Sjfv}; 546270631Sjfv 547270631Sjfv 548270631Sjfv/** 549270631Sjfv * i40e_init_shared_code - Initialize the shared code 550270631Sjfv * @hw: pointer to hardware structure 551270631Sjfv * 552270631Sjfv * This assigns the MAC type and PHY code and inits the NVM. 553270631Sjfv * Does not touch the hardware. This function must be called prior to any 554270631Sjfv * other function in the shared code. The i40e_hw structure should be 555270631Sjfv * memset to 0 prior to calling this function. The following fields in 556270631Sjfv * hw structure should be filled in prior to calling this function: 557270631Sjfv * hw_addr, back, device_id, vendor_id, subsystem_device_id, 558270631Sjfv * subsystem_vendor_id, and revision_id 559270631Sjfv **/ 560270631Sjfvenum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 561270631Sjfv{ 562270631Sjfv enum i40e_status_code status = I40E_SUCCESS; 563270631Sjfv u32 reg; 564270631Sjfv 565270631Sjfv DEBUGFUNC("i40e_init_shared_code"); 566270631Sjfv 567270631Sjfv i40e_set_mac_type(hw); 568270631Sjfv 569270631Sjfv switch (hw->mac.type) { 570270631Sjfv case I40E_MAC_XL710: 571270631Sjfv break; 572270631Sjfv default: 573270631Sjfv return I40E_ERR_DEVICE_NOT_SUPPORTED; 574270631Sjfv } 575270631Sjfv 576270631Sjfv hw->phy.get_link_info = TRUE; 577270631Sjfv 578270631Sjfv /* Determine port number */ 579270631Sjfv reg = rd32(hw, I40E_PFGEN_PORTNUM); 580270631Sjfv reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >> 581270631Sjfv I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT); 582270631Sjfv hw->port = (u8)reg; 583270631Sjfv 584270631Sjfv /* Determine the PF number based on the PCI fn */ 585270631Sjfv reg = rd32(hw, I40E_GLPCI_CAPSUP); 586270631Sjfv if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK) 587270631Sjfv hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func); 588270631Sjfv else 589270631Sjfv hw->pf_id = (u8)hw->bus.func; 590270631Sjfv 591270631Sjfv status = i40e_init_nvm(hw); 592270631Sjfv return status; 593270631Sjfv} 594270631Sjfv 595270631Sjfv/** 596270631Sjfv * i40e_aq_mac_address_read - Retrieve the MAC addresses 597270631Sjfv * @hw: pointer to the hw struct 598270631Sjfv * @flags: a return indicator of what addresses were added to the addr store 599270631Sjfv * @addrs: the requestor's mac addr store 600270631Sjfv * @cmd_details: pointer to command details structure or NULL 601270631Sjfv **/ 602270631Sjfvstatic enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 603270631Sjfv u16 *flags, 604270631Sjfv struct i40e_aqc_mac_address_read_data *addrs, 605270631Sjfv struct i40e_asq_cmd_details *cmd_details) 606270631Sjfv{ 607270631Sjfv struct i40e_aq_desc desc; 608270631Sjfv struct i40e_aqc_mac_address_read *cmd_data = 609270631Sjfv (struct i40e_aqc_mac_address_read *)&desc.params.raw; 610270631Sjfv enum i40e_status_code status; 611270631Sjfv 612270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 613270631Sjfv desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 614270631Sjfv 615270631Sjfv status = i40e_asq_send_command(hw, &desc, addrs, 616270631Sjfv sizeof(*addrs), cmd_details); 617270631Sjfv *flags = LE16_TO_CPU(cmd_data->command_flags); 618270631Sjfv 619270631Sjfv return status; 620270631Sjfv} 621270631Sjfv 622270631Sjfv/** 623270631Sjfv * i40e_aq_mac_address_write - Change the MAC addresses 624270631Sjfv * @hw: pointer to the hw struct 625270631Sjfv * @flags: indicates which MAC to be written 626270631Sjfv * @mac_addr: address to write 627270631Sjfv * @cmd_details: pointer to command details structure or NULL 628270631Sjfv **/ 629270631Sjfvenum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 630270631Sjfv u16 flags, u8 *mac_addr, 631270631Sjfv struct i40e_asq_cmd_details *cmd_details) 632270631Sjfv{ 633270631Sjfv struct i40e_aq_desc desc; 634270631Sjfv struct i40e_aqc_mac_address_write *cmd_data = 635270631Sjfv (struct i40e_aqc_mac_address_write *)&desc.params.raw; 636270631Sjfv enum i40e_status_code status; 637270631Sjfv 638270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 639270631Sjfv i40e_aqc_opc_mac_address_write); 640270631Sjfv cmd_data->command_flags = CPU_TO_LE16(flags); 641270631Sjfv cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 642270631Sjfv cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 643270631Sjfv ((u32)mac_addr[3] << 16) | 644270631Sjfv ((u32)mac_addr[4] << 8) | 645270631Sjfv mac_addr[5]); 646270631Sjfv 647270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 648270631Sjfv 649270631Sjfv return status; 650270631Sjfv} 651270631Sjfv 652270631Sjfv/** 653270631Sjfv * i40e_get_mac_addr - get MAC address 654270631Sjfv * @hw: pointer to the HW structure 655270631Sjfv * @mac_addr: pointer to MAC address 656270631Sjfv * 657270631Sjfv * Reads the adapter's MAC address from register 658270631Sjfv **/ 659270631Sjfvenum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 660270631Sjfv{ 661270631Sjfv struct i40e_aqc_mac_address_read_data addrs; 662270631Sjfv enum i40e_status_code status; 663270631Sjfv u16 flags = 0; 664270631Sjfv 665270631Sjfv status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 666270631Sjfv 667270631Sjfv if (flags & I40E_AQC_LAN_ADDR_VALID) 668270631Sjfv memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); 669270631Sjfv 670270631Sjfv return status; 671270631Sjfv} 672270631Sjfv 673270631Sjfv/** 674270631Sjfv * i40e_get_port_mac_addr - get Port MAC address 675270631Sjfv * @hw: pointer to the HW structure 676270631Sjfv * @mac_addr: pointer to Port MAC address 677270631Sjfv * 678270631Sjfv * Reads the adapter's Port MAC address 679270631Sjfv **/ 680270631Sjfvenum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 681270631Sjfv{ 682270631Sjfv struct i40e_aqc_mac_address_read_data addrs; 683270631Sjfv enum i40e_status_code status; 684270631Sjfv u16 flags = 0; 685270631Sjfv 686270631Sjfv status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 687270631Sjfv if (status) 688270631Sjfv return status; 689270631Sjfv 690270631Sjfv if (flags & I40E_AQC_PORT_ADDR_VALID) 691270631Sjfv memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); 692270631Sjfv else 693270631Sjfv status = I40E_ERR_INVALID_MAC_ADDR; 694270631Sjfv 695270631Sjfv return status; 696270631Sjfv} 697270631Sjfv 698270631Sjfv/** 699270631Sjfv * i40e_pre_tx_queue_cfg - pre tx queue configure 700270631Sjfv * @hw: pointer to the HW structure 701270631Sjfv * @queue: target pf queue index 702270631Sjfv * @enable: state change request 703270631Sjfv * 704270631Sjfv * Handles hw requirement to indicate intention to enable 705270631Sjfv * or disable target queue. 706270631Sjfv **/ 707270631Sjfvvoid i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 708270631Sjfv{ 709270631Sjfv u32 abs_queue_idx = hw->func_caps.base_queue + queue; 710270631Sjfv u32 reg_block = 0; 711270631Sjfv u32 reg_val; 712270631Sjfv 713270631Sjfv if (abs_queue_idx >= 128) { 714270631Sjfv reg_block = abs_queue_idx / 128; 715270631Sjfv abs_queue_idx %= 128; 716270631Sjfv } 717270631Sjfv 718270631Sjfv reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 719270631Sjfv reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 720270631Sjfv reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 721270631Sjfv 722270631Sjfv if (enable) 723270631Sjfv reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 724270631Sjfv else 725270631Sjfv reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 726270631Sjfv 727270631Sjfv wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 728270631Sjfv} 729270631Sjfv 730270631Sjfv/** 731270631Sjfv * i40e_validate_mac_addr - Validate unicast MAC address 732270631Sjfv * @mac_addr: pointer to MAC address 733270631Sjfv * 734270631Sjfv * Tests a MAC address to ensure it is a valid Individual Address 735270631Sjfv **/ 736270631Sjfvenum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 737270631Sjfv{ 738270631Sjfv enum i40e_status_code status = I40E_SUCCESS; 739270631Sjfv 740270631Sjfv DEBUGFUNC("i40e_validate_mac_addr"); 741270631Sjfv 742270631Sjfv /* Broadcast addresses ARE multicast addresses 743270631Sjfv * Make sure it is not a multicast address 744270631Sjfv * Reject the zero address 745270631Sjfv */ 746270631Sjfv if (I40E_IS_MULTICAST(mac_addr) || 747270631Sjfv (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 748270631Sjfv mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 749270631Sjfv status = I40E_ERR_INVALID_MAC_ADDR; 750270631Sjfv 751270631Sjfv return status; 752270631Sjfv} 753270631Sjfv 754270631Sjfv/** 755270631Sjfv * i40e_get_media_type - Gets media type 756270631Sjfv * @hw: pointer to the hardware structure 757270631Sjfv **/ 758270631Sjfvstatic enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 759270631Sjfv{ 760270631Sjfv enum i40e_media_type media; 761270631Sjfv 762270631Sjfv switch (hw->phy.link_info.phy_type) { 763270631Sjfv case I40E_PHY_TYPE_10GBASE_SR: 764270631Sjfv case I40E_PHY_TYPE_10GBASE_LR: 765270631Sjfv case I40E_PHY_TYPE_1000BASE_SX: 766270631Sjfv case I40E_PHY_TYPE_1000BASE_LX: 767270631Sjfv case I40E_PHY_TYPE_40GBASE_SR4: 768270631Sjfv case I40E_PHY_TYPE_40GBASE_LR4: 769270631Sjfv media = I40E_MEDIA_TYPE_FIBER; 770270631Sjfv break; 771270631Sjfv case I40E_PHY_TYPE_100BASE_TX: 772270631Sjfv case I40E_PHY_TYPE_1000BASE_T: 773270631Sjfv case I40E_PHY_TYPE_10GBASE_T: 774270631Sjfv media = I40E_MEDIA_TYPE_BASET; 775270631Sjfv break; 776270631Sjfv case I40E_PHY_TYPE_10GBASE_CR1_CU: 777270631Sjfv case I40E_PHY_TYPE_40GBASE_CR4_CU: 778270631Sjfv case I40E_PHY_TYPE_10GBASE_CR1: 779270631Sjfv case I40E_PHY_TYPE_40GBASE_CR4: 780270631Sjfv case I40E_PHY_TYPE_10GBASE_SFPP_CU: 781270631Sjfv media = I40E_MEDIA_TYPE_DA; 782270631Sjfv break; 783270631Sjfv case I40E_PHY_TYPE_1000BASE_KX: 784270631Sjfv case I40E_PHY_TYPE_10GBASE_KX4: 785270631Sjfv case I40E_PHY_TYPE_10GBASE_KR: 786270631Sjfv case I40E_PHY_TYPE_40GBASE_KR4: 787270631Sjfv media = I40E_MEDIA_TYPE_BACKPLANE; 788270631Sjfv break; 789270631Sjfv case I40E_PHY_TYPE_SGMII: 790270631Sjfv case I40E_PHY_TYPE_XAUI: 791270631Sjfv case I40E_PHY_TYPE_XFI: 792270631Sjfv case I40E_PHY_TYPE_XLAUI: 793270631Sjfv case I40E_PHY_TYPE_XLPPI: 794270631Sjfv default: 795270631Sjfv media = I40E_MEDIA_TYPE_UNKNOWN; 796270631Sjfv break; 797270631Sjfv } 798270631Sjfv 799270631Sjfv return media; 800270631Sjfv} 801270631Sjfv 802270631Sjfv#define I40E_PF_RESET_WAIT_COUNT 100 803270631Sjfv/** 804270631Sjfv * i40e_pf_reset - Reset the PF 805270631Sjfv * @hw: pointer to the hardware structure 806270631Sjfv * 807270631Sjfv * Assuming someone else has triggered a global reset, 808270631Sjfv * assure the global reset is complete and then reset the PF 809270631Sjfv **/ 810270631Sjfvenum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 811270631Sjfv{ 812270631Sjfv u32 cnt = 0; 813270631Sjfv u32 cnt1 = 0; 814270631Sjfv u32 reg = 0; 815270631Sjfv u32 grst_del; 816270631Sjfv 817270631Sjfv /* Poll for Global Reset steady state in case of recent GRST. 818270631Sjfv * The grst delay value is in 100ms units, and we'll wait a 819270631Sjfv * couple counts longer to be sure we don't just miss the end. 820270631Sjfv */ 821270631Sjfv grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK 822270631Sjfv >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 823270631Sjfv for (cnt = 0; cnt < grst_del + 2; cnt++) { 824270631Sjfv reg = rd32(hw, I40E_GLGEN_RSTAT); 825270631Sjfv if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 826270631Sjfv break; 827270631Sjfv i40e_msec_delay(100); 828270631Sjfv } 829270631Sjfv if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 830270631Sjfv DEBUGOUT("Global reset polling failed to complete.\n"); 831270631Sjfv return I40E_ERR_RESET_FAILED; 832270631Sjfv } 833270631Sjfv 834270631Sjfv /* Now Wait for the FW to be ready */ 835270631Sjfv for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 836270631Sjfv reg = rd32(hw, I40E_GLNVM_ULD); 837270631Sjfv reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 838270631Sjfv I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 839270631Sjfv if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 840270631Sjfv I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 841270631Sjfv DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 842270631Sjfv break; 843270631Sjfv } 844270631Sjfv i40e_msec_delay(10); 845270631Sjfv } 846270631Sjfv if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 847270631Sjfv I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 848270631Sjfv DEBUGOUT("wait for FW Reset complete timedout\n"); 849270631Sjfv DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 850270631Sjfv return I40E_ERR_RESET_FAILED; 851270631Sjfv } 852270631Sjfv 853270631Sjfv /* If there was a Global Reset in progress when we got here, 854270631Sjfv * we don't need to do the PF Reset 855270631Sjfv */ 856270631Sjfv if (!cnt) { 857270631Sjfv reg = rd32(hw, I40E_PFGEN_CTRL); 858270631Sjfv wr32(hw, I40E_PFGEN_CTRL, 859270631Sjfv (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 860270631Sjfv for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 861270631Sjfv reg = rd32(hw, I40E_PFGEN_CTRL); 862270631Sjfv if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 863270631Sjfv break; 864270631Sjfv i40e_msec_delay(1); 865270631Sjfv } 866270631Sjfv if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 867270631Sjfv DEBUGOUT("PF reset polling failed to complete.\n"); 868270631Sjfv return I40E_ERR_RESET_FAILED; 869270631Sjfv } 870270631Sjfv } 871270631Sjfv 872270631Sjfv i40e_clear_pxe_mode(hw); 873270631Sjfv 874270631Sjfv 875270631Sjfv return I40E_SUCCESS; 876270631Sjfv} 877270631Sjfv 878270631Sjfv/** 879270631Sjfv * i40e_clear_hw - clear out any left over hw state 880270631Sjfv * @hw: pointer to the hw struct 881270631Sjfv * 882270631Sjfv * Clear queues and interrupts, typically called at init time, 883270631Sjfv * but after the capabilities have been found so we know how many 884270631Sjfv * queues and msix vectors have been allocated. 885270631Sjfv **/ 886270631Sjfvvoid i40e_clear_hw(struct i40e_hw *hw) 887270631Sjfv{ 888270631Sjfv u32 num_queues, base_queue; 889270631Sjfv u32 num_pf_int; 890270631Sjfv u32 num_vf_int; 891270631Sjfv u32 num_vfs; 892270631Sjfv u32 i, j; 893270631Sjfv u32 val; 894270631Sjfv u32 eol = 0x7ff; 895270631Sjfv 896270631Sjfv /* get number of interrupts, queues, and vfs */ 897270631Sjfv val = rd32(hw, I40E_GLPCI_CNF2); 898270631Sjfv num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 899270631Sjfv I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 900270631Sjfv num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 901270631Sjfv I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 902270631Sjfv 903270631Sjfv val = rd32(hw, I40E_PFLAN_QALLOC); 904270631Sjfv base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 905270631Sjfv I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 906270631Sjfv j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 907270631Sjfv I40E_PFLAN_QALLOC_LASTQ_SHIFT; 908270631Sjfv if (val & I40E_PFLAN_QALLOC_VALID_MASK) 909270631Sjfv num_queues = (j - base_queue) + 1; 910270631Sjfv else 911270631Sjfv num_queues = 0; 912270631Sjfv 913270631Sjfv val = rd32(hw, I40E_PF_VT_PFALLOC); 914270631Sjfv i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 915270631Sjfv I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 916270631Sjfv j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 917270631Sjfv I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 918270631Sjfv if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 919270631Sjfv num_vfs = (j - i) + 1; 920270631Sjfv else 921270631Sjfv num_vfs = 0; 922270631Sjfv 923270631Sjfv /* stop all the interrupts */ 924270631Sjfv wr32(hw, I40E_PFINT_ICR0_ENA, 0); 925270631Sjfv val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 926270631Sjfv for (i = 0; i < num_pf_int - 2; i++) 927270631Sjfv wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 928270631Sjfv 929270631Sjfv /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 930270631Sjfv val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 931270631Sjfv wr32(hw, I40E_PFINT_LNKLST0, val); 932270631Sjfv for (i = 0; i < num_pf_int - 2; i++) 933270631Sjfv wr32(hw, I40E_PFINT_LNKLSTN(i), val); 934270631Sjfv val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 935270631Sjfv for (i = 0; i < num_vfs; i++) 936270631Sjfv wr32(hw, I40E_VPINT_LNKLST0(i), val); 937270631Sjfv for (i = 0; i < num_vf_int - 2; i++) 938270631Sjfv wr32(hw, I40E_VPINT_LNKLSTN(i), val); 939270631Sjfv 940270631Sjfv /* warn the HW of the coming Tx disables */ 941270631Sjfv for (i = 0; i < num_queues; i++) { 942270631Sjfv u32 abs_queue_idx = base_queue + i; 943270631Sjfv u32 reg_block = 0; 944270631Sjfv 945270631Sjfv if (abs_queue_idx >= 128) { 946270631Sjfv reg_block = abs_queue_idx / 128; 947270631Sjfv abs_queue_idx %= 128; 948270631Sjfv } 949270631Sjfv 950270631Sjfv val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 951270631Sjfv val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 952270631Sjfv val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 953270631Sjfv val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 954270631Sjfv 955270631Sjfv wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 956270631Sjfv } 957270631Sjfv i40e_usec_delay(400); 958270631Sjfv 959270631Sjfv /* stop all the queues */ 960270631Sjfv for (i = 0; i < num_queues; i++) { 961270631Sjfv wr32(hw, I40E_QINT_TQCTL(i), 0); 962270631Sjfv wr32(hw, I40E_QTX_ENA(i), 0); 963270631Sjfv wr32(hw, I40E_QINT_RQCTL(i), 0); 964270631Sjfv wr32(hw, I40E_QRX_ENA(i), 0); 965270631Sjfv } 966270631Sjfv 967270631Sjfv /* short wait for all queue disables to settle */ 968270631Sjfv i40e_usec_delay(50); 969270631Sjfv} 970270631Sjfv 971270631Sjfv/** 972270631Sjfv * i40e_clear_pxe_mode - clear pxe operations mode 973270631Sjfv * @hw: pointer to the hw struct 974270631Sjfv * 975270631Sjfv * Make sure all PXE mode settings are cleared, including things 976270631Sjfv * like descriptor fetch/write-back mode. 977270631Sjfv **/ 978270631Sjfvvoid i40e_clear_pxe_mode(struct i40e_hw *hw) 979270631Sjfv{ 980270631Sjfv if (i40e_check_asq_alive(hw)) 981270631Sjfv i40e_aq_clear_pxe_mode(hw, NULL); 982270631Sjfv} 983270631Sjfv 984270631Sjfv/** 985270631Sjfv * i40e_led_is_mine - helper to find matching led 986270631Sjfv * @hw: pointer to the hw struct 987270631Sjfv * @idx: index into GPIO registers 988270631Sjfv * 989270631Sjfv * returns: 0 if no match, otherwise the value of the GPIO_CTL register 990270631Sjfv */ 991270631Sjfvstatic u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 992270631Sjfv{ 993270631Sjfv u32 gpio_val = 0; 994270631Sjfv u32 port; 995270631Sjfv 996270631Sjfv if (!hw->func_caps.led[idx]) 997270631Sjfv return 0; 998270631Sjfv 999270631Sjfv gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1000270631Sjfv port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1001270631Sjfv I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1002270631Sjfv 1003270631Sjfv /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1004270631Sjfv * if it is not our port then ignore 1005270631Sjfv */ 1006270631Sjfv if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1007270631Sjfv (port != hw->port)) 1008270631Sjfv return 0; 1009270631Sjfv 1010270631Sjfv return gpio_val; 1011270631Sjfv} 1012270631Sjfv 1013270631Sjfv#define I40E_LED0 22 1014270631Sjfv#define I40E_LINK_ACTIVITY 0xC 1015270631Sjfv 1016270631Sjfv/** 1017270631Sjfv * i40e_led_get - return current on/off mode 1018270631Sjfv * @hw: pointer to the hw struct 1019270631Sjfv * 1020270631Sjfv * The value returned is the 'mode' field as defined in the 1021270631Sjfv * GPIO register definitions: 0x0 = off, 0xf = on, and other 1022270631Sjfv * values are variations of possible behaviors relating to 1023270631Sjfv * blink, link, and wire. 1024270631Sjfv **/ 1025270631Sjfvu32 i40e_led_get(struct i40e_hw *hw) 1026270631Sjfv{ 1027270631Sjfv u32 mode = 0; 1028270631Sjfv int i; 1029270631Sjfv 1030270631Sjfv /* as per the documentation GPIO 22-29 are the LED 1031270631Sjfv * GPIO pins named LED0..LED7 1032270631Sjfv */ 1033270631Sjfv for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1034270631Sjfv u32 gpio_val = i40e_led_is_mine(hw, i); 1035270631Sjfv 1036270631Sjfv if (!gpio_val) 1037270631Sjfv continue; 1038270631Sjfv 1039270631Sjfv mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1040270631Sjfv I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1041270631Sjfv break; 1042270631Sjfv } 1043270631Sjfv 1044270631Sjfv return mode; 1045270631Sjfv} 1046270631Sjfv 1047270631Sjfv/** 1048270631Sjfv * i40e_led_set - set new on/off mode 1049270631Sjfv * @hw: pointer to the hw struct 1050270631Sjfv * @mode: 0=off, 0xf=on (else see manual for mode details) 1051270631Sjfv * @blink: TRUE if the LED should blink when on, FALSE if steady 1052270631Sjfv * 1053270631Sjfv * if this function is used to turn on the blink it should 1054270631Sjfv * be used to disable the blink when restoring the original state. 1055270631Sjfv **/ 1056270631Sjfvvoid i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1057270631Sjfv{ 1058270631Sjfv int i; 1059270631Sjfv 1060270631Sjfv if (mode & 0xfffffff0) 1061270631Sjfv DEBUGOUT1("invalid mode passed in %X\n", mode); 1062270631Sjfv 1063270631Sjfv /* as per the documentation GPIO 22-29 are the LED 1064270631Sjfv * GPIO pins named LED0..LED7 1065270631Sjfv */ 1066270631Sjfv for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1067270631Sjfv u32 gpio_val = i40e_led_is_mine(hw, i); 1068270631Sjfv 1069270631Sjfv if (!gpio_val) 1070270631Sjfv continue; 1071270631Sjfv 1072270631Sjfv gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1073270631Sjfv /* this & is a bit of paranoia, but serves as a range check */ 1074270631Sjfv gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1075270631Sjfv I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1076270631Sjfv 1077270631Sjfv if (mode == I40E_LINK_ACTIVITY) 1078270631Sjfv blink = FALSE; 1079270631Sjfv 1080270631Sjfv gpio_val |= (blink ? 1 : 0) << 1081270631Sjfv I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT; 1082270631Sjfv 1083270631Sjfv wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1084270631Sjfv break; 1085270631Sjfv } 1086270631Sjfv} 1087270631Sjfv 1088270631Sjfv/* Admin command wrappers */ 1089270631Sjfv 1090270631Sjfv/** 1091270631Sjfv * i40e_aq_get_phy_capabilities 1092270631Sjfv * @hw: pointer to the hw struct 1093270631Sjfv * @abilities: structure for PHY capabilities to be filled 1094270631Sjfv * @qualified_modules: report Qualified Modules 1095270631Sjfv * @report_init: report init capabilities (active are default) 1096270631Sjfv * @cmd_details: pointer to command details structure or NULL 1097270631Sjfv * 1098270631Sjfv * Returns the various PHY abilities supported on the Port. 1099270631Sjfv **/ 1100270631Sjfvenum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1101270631Sjfv bool qualified_modules, bool report_init, 1102270631Sjfv struct i40e_aq_get_phy_abilities_resp *abilities, 1103270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1104270631Sjfv{ 1105270631Sjfv struct i40e_aq_desc desc; 1106270631Sjfv enum i40e_status_code status; 1107270631Sjfv u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1108270631Sjfv 1109270631Sjfv if (!abilities) 1110270631Sjfv return I40E_ERR_PARAM; 1111270631Sjfv 1112270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1113270631Sjfv i40e_aqc_opc_get_phy_abilities); 1114270631Sjfv 1115270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1116270631Sjfv if (abilities_size > I40E_AQ_LARGE_BUF) 1117270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1118270631Sjfv 1119270631Sjfv if (qualified_modules) 1120270631Sjfv desc.params.external.param0 |= 1121270631Sjfv CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1122270631Sjfv 1123270631Sjfv if (report_init) 1124270631Sjfv desc.params.external.param0 |= 1125270631Sjfv CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1126270631Sjfv 1127270631Sjfv status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1128270631Sjfv cmd_details); 1129270631Sjfv 1130270631Sjfv if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1131270631Sjfv status = I40E_ERR_UNKNOWN_PHY; 1132270631Sjfv 1133270631Sjfv return status; 1134270631Sjfv} 1135270631Sjfv 1136270631Sjfv/** 1137270631Sjfv * i40e_aq_set_phy_config 1138270631Sjfv * @hw: pointer to the hw struct 1139270631Sjfv * @config: structure with PHY configuration to be set 1140270631Sjfv * @cmd_details: pointer to command details structure or NULL 1141270631Sjfv * 1142270631Sjfv * Set the various PHY configuration parameters 1143270631Sjfv * supported on the Port.One or more of the Set PHY config parameters may be 1144270631Sjfv * ignored in an MFP mode as the PF may not have the privilege to set some 1145270631Sjfv * of the PHY Config parameters. This status will be indicated by the 1146270631Sjfv * command response. 1147270631Sjfv **/ 1148270631Sjfvenum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1149270631Sjfv struct i40e_aq_set_phy_config *config, 1150270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1151270631Sjfv{ 1152270631Sjfv struct i40e_aq_desc desc; 1153270631Sjfv struct i40e_aq_set_phy_config *cmd = 1154270631Sjfv (struct i40e_aq_set_phy_config *)&desc.params.raw; 1155270631Sjfv enum i40e_status_code status; 1156270631Sjfv 1157270631Sjfv if (!config) 1158270631Sjfv return I40E_ERR_PARAM; 1159270631Sjfv 1160270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1161270631Sjfv i40e_aqc_opc_set_phy_config); 1162270631Sjfv 1163270631Sjfv *cmd = *config; 1164270631Sjfv 1165270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1166270631Sjfv 1167270631Sjfv return status; 1168270631Sjfv} 1169270631Sjfv 1170270631Sjfv/** 1171270631Sjfv * i40e_set_fc 1172270631Sjfv * @hw: pointer to the hw struct 1173270631Sjfv * 1174270631Sjfv * Set the requested flow control mode using set_phy_config. 1175270631Sjfv **/ 1176270631Sjfvenum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1177270631Sjfv bool atomic_restart) 1178270631Sjfv{ 1179270631Sjfv enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1180270631Sjfv struct i40e_aq_get_phy_abilities_resp abilities; 1181270631Sjfv struct i40e_aq_set_phy_config config; 1182270631Sjfv enum i40e_status_code status; 1183270631Sjfv u8 pause_mask = 0x0; 1184270631Sjfv 1185270631Sjfv *aq_failures = 0x0; 1186270631Sjfv 1187270631Sjfv switch (fc_mode) { 1188270631Sjfv case I40E_FC_FULL: 1189270631Sjfv pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1190270631Sjfv pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1191270631Sjfv break; 1192270631Sjfv case I40E_FC_RX_PAUSE: 1193270631Sjfv pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1194270631Sjfv break; 1195270631Sjfv case I40E_FC_TX_PAUSE: 1196270631Sjfv pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1197270631Sjfv break; 1198270631Sjfv default: 1199270631Sjfv break; 1200270631Sjfv } 1201270631Sjfv 1202270631Sjfv /* Get the current phy config */ 1203270631Sjfv status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1204270631Sjfv NULL); 1205270631Sjfv if (status) { 1206270631Sjfv *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1207270631Sjfv return status; 1208270631Sjfv } 1209270631Sjfv 1210270631Sjfv memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1211270631Sjfv /* clear the old pause settings */ 1212270631Sjfv config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1213270631Sjfv ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1214270631Sjfv /* set the new abilities */ 1215270631Sjfv config.abilities |= pause_mask; 1216270631Sjfv /* If the abilities have changed, then set the new config */ 1217270631Sjfv if (config.abilities != abilities.abilities) { 1218270631Sjfv /* Auto restart link so settings take effect */ 1219270631Sjfv if (atomic_restart) 1220270631Sjfv config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1221270631Sjfv /* Copy over all the old settings */ 1222270631Sjfv config.phy_type = abilities.phy_type; 1223270631Sjfv config.link_speed = abilities.link_speed; 1224270631Sjfv config.eee_capability = abilities.eee_capability; 1225270631Sjfv config.eeer = abilities.eeer_val; 1226270631Sjfv config.low_power_ctrl = abilities.d3_lpan; 1227270631Sjfv status = i40e_aq_set_phy_config(hw, &config, NULL); 1228270631Sjfv 1229270631Sjfv if (status) 1230270631Sjfv *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1231270631Sjfv } 1232270631Sjfv /* Update the link info */ 1233270631Sjfv status = i40e_update_link_info(hw, TRUE); 1234270631Sjfv if (status) { 1235270631Sjfv /* Wait a little bit (on 40G cards it sometimes takes a really 1236270631Sjfv * long time for link to come back from the atomic reset) 1237270631Sjfv * and try once more 1238270631Sjfv */ 1239270631Sjfv i40e_msec_delay(1000); 1240270631Sjfv status = i40e_update_link_info(hw, TRUE); 1241270631Sjfv } 1242270631Sjfv if (status) 1243270631Sjfv *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1244270631Sjfv 1245270631Sjfv return status; 1246270631Sjfv} 1247270631Sjfv 1248270631Sjfv/** 1249270631Sjfv * i40e_aq_set_mac_config 1250270631Sjfv * @hw: pointer to the hw struct 1251270631Sjfv * @max_frame_size: Maximum Frame Size to be supported by the port 1252270631Sjfv * @crc_en: Tell HW to append a CRC to outgoing frames 1253270631Sjfv * @pacing: Pacing configurations 1254270631Sjfv * @cmd_details: pointer to command details structure or NULL 1255270631Sjfv * 1256270631Sjfv * Configure MAC settings for frame size, jumbo frame support and the 1257270631Sjfv * addition of a CRC by the hardware. 1258270631Sjfv **/ 1259270631Sjfvenum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1260270631Sjfv u16 max_frame_size, 1261270631Sjfv bool crc_en, u16 pacing, 1262270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1263270631Sjfv{ 1264270631Sjfv struct i40e_aq_desc desc; 1265270631Sjfv struct i40e_aq_set_mac_config *cmd = 1266270631Sjfv (struct i40e_aq_set_mac_config *)&desc.params.raw; 1267270631Sjfv enum i40e_status_code status; 1268270631Sjfv 1269270631Sjfv if (max_frame_size == 0) 1270270631Sjfv return I40E_ERR_PARAM; 1271270631Sjfv 1272270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1273270631Sjfv i40e_aqc_opc_set_mac_config); 1274270631Sjfv 1275270631Sjfv cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1276270631Sjfv cmd->params = ((u8)pacing & 0x0F) << 3; 1277270631Sjfv if (crc_en) 1278270631Sjfv cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1279270631Sjfv 1280270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1281270631Sjfv 1282270631Sjfv return status; 1283270631Sjfv} 1284270631Sjfv 1285270631Sjfv/** 1286270631Sjfv * i40e_aq_clear_pxe_mode 1287270631Sjfv * @hw: pointer to the hw struct 1288270631Sjfv * @cmd_details: pointer to command details structure or NULL 1289270631Sjfv * 1290270631Sjfv * Tell the firmware that the driver is taking over from PXE 1291270631Sjfv **/ 1292270631Sjfvenum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1293270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1294270631Sjfv{ 1295270631Sjfv enum i40e_status_code status; 1296270631Sjfv struct i40e_aq_desc desc; 1297270631Sjfv struct i40e_aqc_clear_pxe *cmd = 1298270631Sjfv (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1299270631Sjfv 1300270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1301270631Sjfv i40e_aqc_opc_clear_pxe_mode); 1302270631Sjfv 1303270631Sjfv cmd->rx_cnt = 0x2; 1304270631Sjfv 1305270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1306270631Sjfv 1307270631Sjfv wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1308270631Sjfv 1309270631Sjfv return status; 1310270631Sjfv} 1311270631Sjfv 1312270631Sjfv/** 1313270631Sjfv * i40e_aq_set_link_restart_an 1314270631Sjfv * @hw: pointer to the hw struct 1315270631Sjfv * @enable_link: if TRUE: enable link, if FALSE: disable link 1316270631Sjfv * @cmd_details: pointer to command details structure or NULL 1317270631Sjfv * 1318270631Sjfv * Sets up the link and restarts the Auto-Negotiation over the link. 1319270631Sjfv **/ 1320270631Sjfvenum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1321270631Sjfv bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1322270631Sjfv{ 1323270631Sjfv struct i40e_aq_desc desc; 1324270631Sjfv struct i40e_aqc_set_link_restart_an *cmd = 1325270631Sjfv (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1326270631Sjfv enum i40e_status_code status; 1327270631Sjfv 1328270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1329270631Sjfv i40e_aqc_opc_set_link_restart_an); 1330270631Sjfv 1331270631Sjfv cmd->command = I40E_AQ_PHY_RESTART_AN; 1332270631Sjfv if (enable_link) 1333270631Sjfv cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1334270631Sjfv else 1335270631Sjfv cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1336270631Sjfv 1337270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1338270631Sjfv 1339270631Sjfv return status; 1340270631Sjfv} 1341270631Sjfv 1342270631Sjfv/** 1343270631Sjfv * i40e_aq_get_link_info 1344270631Sjfv * @hw: pointer to the hw struct 1345270631Sjfv * @enable_lse: enable/disable LinkStatusEvent reporting 1346270631Sjfv * @link: pointer to link status structure - optional 1347270631Sjfv * @cmd_details: pointer to command details structure or NULL 1348270631Sjfv * 1349270631Sjfv * Returns the link status of the adapter. 1350270631Sjfv **/ 1351270631Sjfvenum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1352270631Sjfv bool enable_lse, struct i40e_link_status *link, 1353270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1354270631Sjfv{ 1355270631Sjfv struct i40e_aq_desc desc; 1356270631Sjfv struct i40e_aqc_get_link_status *resp = 1357270631Sjfv (struct i40e_aqc_get_link_status *)&desc.params.raw; 1358270631Sjfv struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1359270631Sjfv enum i40e_status_code status; 1360270631Sjfv bool tx_pause, rx_pause; 1361270631Sjfv u16 command_flags; 1362270631Sjfv 1363270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1364270631Sjfv 1365270631Sjfv if (enable_lse) 1366270631Sjfv command_flags = I40E_AQ_LSE_ENABLE; 1367270631Sjfv else 1368270631Sjfv command_flags = I40E_AQ_LSE_DISABLE; 1369270631Sjfv resp->command_flags = CPU_TO_LE16(command_flags); 1370270631Sjfv 1371270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1372270631Sjfv 1373270631Sjfv if (status != I40E_SUCCESS) 1374270631Sjfv goto aq_get_link_info_exit; 1375270631Sjfv 1376270631Sjfv /* save off old link status information */ 1377270631Sjfv i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1378270631Sjfv sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA); 1379270631Sjfv 1380270631Sjfv /* update link status */ 1381270631Sjfv hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1382270631Sjfv hw->phy.media_type = i40e_get_media_type(hw); 1383270631Sjfv hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1384270631Sjfv hw_link_info->link_info = resp->link_info; 1385270631Sjfv hw_link_info->an_info = resp->an_info; 1386270631Sjfv hw_link_info->ext_info = resp->ext_info; 1387270631Sjfv hw_link_info->loopback = resp->loopback; 1388270631Sjfv hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1389270631Sjfv hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1390270631Sjfv 1391270631Sjfv /* update fc info */ 1392270631Sjfv tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1393270631Sjfv rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1394270631Sjfv if (tx_pause & rx_pause) 1395270631Sjfv hw->fc.current_mode = I40E_FC_FULL; 1396270631Sjfv else if (tx_pause) 1397270631Sjfv hw->fc.current_mode = I40E_FC_TX_PAUSE; 1398270631Sjfv else if (rx_pause) 1399270631Sjfv hw->fc.current_mode = I40E_FC_RX_PAUSE; 1400270631Sjfv else 1401270631Sjfv hw->fc.current_mode = I40E_FC_NONE; 1402270631Sjfv 1403270631Sjfv if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1404270631Sjfv hw_link_info->crc_enable = TRUE; 1405270631Sjfv else 1406270631Sjfv hw_link_info->crc_enable = FALSE; 1407270631Sjfv 1408270631Sjfv if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE)) 1409270631Sjfv hw_link_info->lse_enable = TRUE; 1410270631Sjfv else 1411270631Sjfv hw_link_info->lse_enable = FALSE; 1412270631Sjfv 1413270631Sjfv /* save link status information */ 1414270631Sjfv if (link) 1415270631Sjfv i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status), 1416270631Sjfv I40E_NONDMA_TO_NONDMA); 1417270631Sjfv 1418270631Sjfv /* flag cleared so helper functions don't call AQ again */ 1419270631Sjfv hw->phy.get_link_info = FALSE; 1420270631Sjfv 1421270631Sjfvaq_get_link_info_exit: 1422270631Sjfv return status; 1423270631Sjfv} 1424270631Sjfv 1425270631Sjfv/** 1426270631Sjfv * i40e_update_link_info 1427270631Sjfv * @hw: pointer to the hw struct 1428270631Sjfv * @enable_lse: enable/disable LinkStatusEvent reporting 1429270631Sjfv * 1430270631Sjfv * Returns the link status of the adapter 1431270631Sjfv **/ 1432270631Sjfvenum i40e_status_code i40e_update_link_info(struct i40e_hw *hw, 1433270631Sjfv bool enable_lse) 1434270631Sjfv{ 1435270631Sjfv struct i40e_aq_get_phy_abilities_resp abilities; 1436270631Sjfv enum i40e_status_code status; 1437270631Sjfv 1438270631Sjfv status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL); 1439270631Sjfv if (status) 1440270631Sjfv return status; 1441270631Sjfv 1442270631Sjfv status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 1443270631Sjfv &abilities, NULL); 1444270631Sjfv if (status) 1445270631Sjfv return status; 1446270631Sjfv 1447270631Sjfv if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED) 1448270631Sjfv hw->phy.link_info.an_enabled = TRUE; 1449270631Sjfv else 1450270631Sjfv hw->phy.link_info.an_enabled = FALSE; 1451270631Sjfv 1452270631Sjfv return status; 1453270631Sjfv} 1454270631Sjfv 1455270631Sjfv/** 1456270631Sjfv * i40e_aq_set_phy_int_mask 1457270631Sjfv * @hw: pointer to the hw struct 1458270631Sjfv * @mask: interrupt mask to be set 1459270631Sjfv * @cmd_details: pointer to command details structure or NULL 1460270631Sjfv * 1461270631Sjfv * Set link interrupt mask. 1462270631Sjfv **/ 1463270631Sjfvenum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1464270631Sjfv u16 mask, 1465270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1466270631Sjfv{ 1467270631Sjfv struct i40e_aq_desc desc; 1468270631Sjfv struct i40e_aqc_set_phy_int_mask *cmd = 1469270631Sjfv (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1470270631Sjfv enum i40e_status_code status; 1471270631Sjfv 1472270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1473270631Sjfv i40e_aqc_opc_set_phy_int_mask); 1474270631Sjfv 1475270631Sjfv cmd->event_mask = CPU_TO_LE16(mask); 1476270631Sjfv 1477270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1478270631Sjfv 1479270631Sjfv return status; 1480270631Sjfv} 1481270631Sjfv 1482270631Sjfv/** 1483270631Sjfv * i40e_aq_get_local_advt_reg 1484270631Sjfv * @hw: pointer to the hw struct 1485270631Sjfv * @advt_reg: local AN advertisement register value 1486270631Sjfv * @cmd_details: pointer to command details structure or NULL 1487270631Sjfv * 1488270631Sjfv * Get the Local AN advertisement register value. 1489270631Sjfv **/ 1490270631Sjfvenum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 1491270631Sjfv u64 *advt_reg, 1492270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1493270631Sjfv{ 1494270631Sjfv struct i40e_aq_desc desc; 1495270631Sjfv struct i40e_aqc_an_advt_reg *resp = 1496270631Sjfv (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1497270631Sjfv enum i40e_status_code status; 1498270631Sjfv 1499270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1500270631Sjfv i40e_aqc_opc_get_local_advt_reg); 1501270631Sjfv 1502270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1503270631Sjfv 1504270631Sjfv if (status != I40E_SUCCESS) 1505270631Sjfv goto aq_get_local_advt_reg_exit; 1506270631Sjfv 1507270631Sjfv *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1508270631Sjfv *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1509270631Sjfv 1510270631Sjfvaq_get_local_advt_reg_exit: 1511270631Sjfv return status; 1512270631Sjfv} 1513270631Sjfv 1514270631Sjfv/** 1515270631Sjfv * i40e_aq_set_local_advt_reg 1516270631Sjfv * @hw: pointer to the hw struct 1517270631Sjfv * @advt_reg: local AN advertisement register value 1518270631Sjfv * @cmd_details: pointer to command details structure or NULL 1519270631Sjfv * 1520270631Sjfv * Get the Local AN advertisement register value. 1521270631Sjfv **/ 1522270631Sjfvenum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 1523270631Sjfv u64 advt_reg, 1524270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1525270631Sjfv{ 1526270631Sjfv struct i40e_aq_desc desc; 1527270631Sjfv struct i40e_aqc_an_advt_reg *cmd = 1528270631Sjfv (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1529270631Sjfv enum i40e_status_code status; 1530270631Sjfv 1531270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1532270631Sjfv i40e_aqc_opc_get_local_advt_reg); 1533270631Sjfv 1534270631Sjfv cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 1535270631Sjfv cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 1536270631Sjfv 1537270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1538270631Sjfv 1539270631Sjfv return status; 1540270631Sjfv} 1541270631Sjfv 1542270631Sjfv/** 1543270631Sjfv * i40e_aq_get_partner_advt 1544270631Sjfv * @hw: pointer to the hw struct 1545270631Sjfv * @advt_reg: AN partner advertisement register value 1546270631Sjfv * @cmd_details: pointer to command details structure or NULL 1547270631Sjfv * 1548270631Sjfv * Get the link partner AN advertisement register value. 1549270631Sjfv **/ 1550270631Sjfvenum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 1551270631Sjfv u64 *advt_reg, 1552270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1553270631Sjfv{ 1554270631Sjfv struct i40e_aq_desc desc; 1555270631Sjfv struct i40e_aqc_an_advt_reg *resp = 1556270631Sjfv (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1557270631Sjfv enum i40e_status_code status; 1558270631Sjfv 1559270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1560270631Sjfv i40e_aqc_opc_get_partner_advt); 1561270631Sjfv 1562270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1563270631Sjfv 1564270631Sjfv if (status != I40E_SUCCESS) 1565270631Sjfv goto aq_get_partner_advt_exit; 1566270631Sjfv 1567270631Sjfv *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1568270631Sjfv *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1569270631Sjfv 1570270631Sjfvaq_get_partner_advt_exit: 1571270631Sjfv return status; 1572270631Sjfv} 1573270631Sjfv 1574270631Sjfv/** 1575270631Sjfv * i40e_aq_set_lb_modes 1576270631Sjfv * @hw: pointer to the hw struct 1577270631Sjfv * @lb_modes: loopback mode to be set 1578270631Sjfv * @cmd_details: pointer to command details structure or NULL 1579270631Sjfv * 1580270631Sjfv * Sets loopback modes. 1581270631Sjfv **/ 1582270631Sjfvenum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 1583270631Sjfv u16 lb_modes, 1584270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1585270631Sjfv{ 1586270631Sjfv struct i40e_aq_desc desc; 1587270631Sjfv struct i40e_aqc_set_lb_mode *cmd = 1588270631Sjfv (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 1589270631Sjfv enum i40e_status_code status; 1590270631Sjfv 1591270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1592270631Sjfv i40e_aqc_opc_set_lb_modes); 1593270631Sjfv 1594270631Sjfv cmd->lb_mode = CPU_TO_LE16(lb_modes); 1595270631Sjfv 1596270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1597270631Sjfv 1598270631Sjfv return status; 1599270631Sjfv} 1600270631Sjfv 1601270631Sjfv/** 1602270631Sjfv * i40e_aq_set_phy_debug 1603270631Sjfv * @hw: pointer to the hw struct 1604270631Sjfv * @cmd_flags: debug command flags 1605270631Sjfv * @cmd_details: pointer to command details structure or NULL 1606270631Sjfv * 1607270631Sjfv * Reset the external PHY. 1608270631Sjfv **/ 1609270631Sjfvenum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1610270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1611270631Sjfv{ 1612270631Sjfv struct i40e_aq_desc desc; 1613270631Sjfv struct i40e_aqc_set_phy_debug *cmd = 1614270631Sjfv (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1615270631Sjfv enum i40e_status_code status; 1616270631Sjfv 1617270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1618270631Sjfv i40e_aqc_opc_set_phy_debug); 1619270631Sjfv 1620270631Sjfv cmd->command_flags = cmd_flags; 1621270631Sjfv 1622270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1623270631Sjfv 1624270631Sjfv return status; 1625270631Sjfv} 1626270631Sjfv 1627270631Sjfv/** 1628270631Sjfv * i40e_aq_add_vsi 1629270631Sjfv * @hw: pointer to the hw struct 1630270631Sjfv * @vsi_ctx: pointer to a vsi context struct 1631270631Sjfv * @cmd_details: pointer to command details structure or NULL 1632270631Sjfv * 1633270631Sjfv * Add a VSI context to the hardware. 1634270631Sjfv**/ 1635270631Sjfvenum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 1636270631Sjfv struct i40e_vsi_context *vsi_ctx, 1637270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1638270631Sjfv{ 1639270631Sjfv struct i40e_aq_desc desc; 1640270631Sjfv struct i40e_aqc_add_get_update_vsi *cmd = 1641270631Sjfv (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1642270631Sjfv struct i40e_aqc_add_get_update_vsi_completion *resp = 1643270631Sjfv (struct i40e_aqc_add_get_update_vsi_completion *) 1644270631Sjfv &desc.params.raw; 1645270631Sjfv enum i40e_status_code status; 1646270631Sjfv 1647270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1648270631Sjfv i40e_aqc_opc_add_vsi); 1649270631Sjfv 1650270631Sjfv cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 1651270631Sjfv cmd->connection_type = vsi_ctx->connection_type; 1652270631Sjfv cmd->vf_id = vsi_ctx->vf_num; 1653270631Sjfv cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 1654270631Sjfv 1655270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1656270631Sjfv 1657270631Sjfv status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1658270631Sjfv sizeof(vsi_ctx->info), cmd_details); 1659270631Sjfv 1660270631Sjfv if (status != I40E_SUCCESS) 1661270631Sjfv goto aq_add_vsi_exit; 1662270631Sjfv 1663270631Sjfv vsi_ctx->seid = LE16_TO_CPU(resp->seid); 1664270631Sjfv vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 1665270631Sjfv vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 1666270631Sjfv vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 1667270631Sjfv 1668270631Sjfvaq_add_vsi_exit: 1669270631Sjfv return status; 1670270631Sjfv} 1671270631Sjfv 1672270631Sjfv/** 1673270631Sjfv * i40e_aq_set_default_vsi 1674270631Sjfv * @hw: pointer to the hw struct 1675270631Sjfv * @seid: vsi number 1676270631Sjfv * @cmd_details: pointer to command details structure or NULL 1677270631Sjfv **/ 1678270631Sjfvenum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 1679270631Sjfv u16 seid, 1680270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1681270631Sjfv{ 1682270631Sjfv struct i40e_aq_desc desc; 1683270631Sjfv struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1684270631Sjfv (struct i40e_aqc_set_vsi_promiscuous_modes *) 1685270631Sjfv &desc.params.raw; 1686270631Sjfv enum i40e_status_code status; 1687270631Sjfv 1688270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1689270631Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes); 1690270631Sjfv 1691270631Sjfv cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 1692270631Sjfv cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 1693270631Sjfv cmd->seid = CPU_TO_LE16(seid); 1694270631Sjfv 1695270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1696270631Sjfv 1697270631Sjfv return status; 1698270631Sjfv} 1699270631Sjfv 1700270631Sjfv/** 1701270631Sjfv * i40e_aq_set_vsi_unicast_promiscuous 1702270631Sjfv * @hw: pointer to the hw struct 1703270631Sjfv * @seid: vsi number 1704270631Sjfv * @set: set unicast promiscuous enable/disable 1705270631Sjfv * @cmd_details: pointer to command details structure or NULL 1706270631Sjfv **/ 1707270631Sjfvenum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1708270631Sjfv u16 seid, bool set, 1709270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1710270631Sjfv{ 1711270631Sjfv struct i40e_aq_desc desc; 1712270631Sjfv struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1713270631Sjfv (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1714270631Sjfv enum i40e_status_code status; 1715270631Sjfv u16 flags = 0; 1716270631Sjfv 1717270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1718270631Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes); 1719270631Sjfv 1720270631Sjfv if (set) 1721270631Sjfv flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1722270631Sjfv 1723270631Sjfv cmd->promiscuous_flags = CPU_TO_LE16(flags); 1724270631Sjfv 1725270631Sjfv cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1726270631Sjfv 1727270631Sjfv cmd->seid = CPU_TO_LE16(seid); 1728270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1729270631Sjfv 1730270631Sjfv return status; 1731270631Sjfv} 1732270631Sjfv 1733270631Sjfv/** 1734270631Sjfv * i40e_aq_set_vsi_multicast_promiscuous 1735270631Sjfv * @hw: pointer to the hw struct 1736270631Sjfv * @seid: vsi number 1737270631Sjfv * @set: set multicast promiscuous enable/disable 1738270631Sjfv * @cmd_details: pointer to command details structure or NULL 1739270631Sjfv **/ 1740270631Sjfvenum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1741270631Sjfv u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 1742270631Sjfv{ 1743270631Sjfv struct i40e_aq_desc desc; 1744270631Sjfv struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1745270631Sjfv (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1746270631Sjfv enum i40e_status_code status; 1747270631Sjfv u16 flags = 0; 1748270631Sjfv 1749270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1750270631Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes); 1751270631Sjfv 1752270631Sjfv if (set) 1753270631Sjfv flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1754270631Sjfv 1755270631Sjfv cmd->promiscuous_flags = CPU_TO_LE16(flags); 1756270631Sjfv 1757270631Sjfv cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1758270631Sjfv 1759270631Sjfv cmd->seid = CPU_TO_LE16(seid); 1760270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1761270631Sjfv 1762270631Sjfv return status; 1763270631Sjfv} 1764270631Sjfv 1765270631Sjfv/** 1766270631Sjfv * i40e_aq_set_vsi_broadcast 1767270631Sjfv * @hw: pointer to the hw struct 1768270631Sjfv * @seid: vsi number 1769270631Sjfv * @set_filter: TRUE to set filter, FALSE to clear filter 1770270631Sjfv * @cmd_details: pointer to command details structure or NULL 1771270631Sjfv * 1772270631Sjfv * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1773270631Sjfv **/ 1774270631Sjfvenum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1775270631Sjfv u16 seid, bool set_filter, 1776270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1777270631Sjfv{ 1778270631Sjfv struct i40e_aq_desc desc; 1779270631Sjfv struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1780270631Sjfv (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1781270631Sjfv enum i40e_status_code status; 1782270631Sjfv 1783270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1784270631Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes); 1785270631Sjfv 1786270631Sjfv if (set_filter) 1787270631Sjfv cmd->promiscuous_flags 1788270631Sjfv |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1789270631Sjfv else 1790270631Sjfv cmd->promiscuous_flags 1791270631Sjfv &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1792270631Sjfv 1793270631Sjfv cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1794270631Sjfv cmd->seid = CPU_TO_LE16(seid); 1795270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1796270631Sjfv 1797270631Sjfv return status; 1798270631Sjfv} 1799270631Sjfv 1800270631Sjfv/** 1801270631Sjfv * i40e_get_vsi_params - get VSI configuration info 1802270631Sjfv * @hw: pointer to the hw struct 1803270631Sjfv * @vsi_ctx: pointer to a vsi context struct 1804270631Sjfv * @cmd_details: pointer to command details structure or NULL 1805270631Sjfv **/ 1806270631Sjfvenum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 1807270631Sjfv struct i40e_vsi_context *vsi_ctx, 1808270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1809270631Sjfv{ 1810270631Sjfv struct i40e_aq_desc desc; 1811270631Sjfv struct i40e_aqc_add_get_update_vsi *cmd = 1812270631Sjfv (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1813270631Sjfv struct i40e_aqc_add_get_update_vsi_completion *resp = 1814270631Sjfv (struct i40e_aqc_add_get_update_vsi_completion *) 1815270631Sjfv &desc.params.raw; 1816270631Sjfv enum i40e_status_code status; 1817270631Sjfv 1818270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1819270631Sjfv i40e_aqc_opc_get_vsi_parameters); 1820270631Sjfv 1821270631Sjfv cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 1822270631Sjfv 1823270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1824270631Sjfv 1825270631Sjfv status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1826270631Sjfv sizeof(vsi_ctx->info), NULL); 1827270631Sjfv 1828270631Sjfv if (status != I40E_SUCCESS) 1829270631Sjfv goto aq_get_vsi_params_exit; 1830270631Sjfv 1831270631Sjfv vsi_ctx->seid = LE16_TO_CPU(resp->seid); 1832270631Sjfv vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 1833270631Sjfv vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 1834270631Sjfv vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 1835270631Sjfv 1836270631Sjfvaq_get_vsi_params_exit: 1837270631Sjfv return status; 1838270631Sjfv} 1839270631Sjfv 1840270631Sjfv/** 1841270631Sjfv * i40e_aq_update_vsi_params 1842270631Sjfv * @hw: pointer to the hw struct 1843270631Sjfv * @vsi_ctx: pointer to a vsi context struct 1844270631Sjfv * @cmd_details: pointer to command details structure or NULL 1845270631Sjfv * 1846270631Sjfv * Update a VSI context. 1847270631Sjfv **/ 1848270631Sjfvenum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 1849270631Sjfv struct i40e_vsi_context *vsi_ctx, 1850270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1851270631Sjfv{ 1852270631Sjfv struct i40e_aq_desc desc; 1853270631Sjfv struct i40e_aqc_add_get_update_vsi *cmd = 1854270631Sjfv (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1855270631Sjfv enum i40e_status_code status; 1856270631Sjfv 1857270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1858270631Sjfv i40e_aqc_opc_update_vsi_parameters); 1859270631Sjfv cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 1860270631Sjfv 1861270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1862270631Sjfv 1863270631Sjfv status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1864270631Sjfv sizeof(vsi_ctx->info), cmd_details); 1865270631Sjfv 1866270631Sjfv return status; 1867270631Sjfv} 1868270631Sjfv 1869270631Sjfv/** 1870270631Sjfv * i40e_aq_get_switch_config 1871270631Sjfv * @hw: pointer to the hardware structure 1872270631Sjfv * @buf: pointer to the result buffer 1873270631Sjfv * @buf_size: length of input buffer 1874270631Sjfv * @start_seid: seid to start for the report, 0 == beginning 1875270631Sjfv * @cmd_details: pointer to command details structure or NULL 1876270631Sjfv * 1877270631Sjfv * Fill the buf with switch configuration returned from AdminQ command 1878270631Sjfv **/ 1879270631Sjfvenum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 1880270631Sjfv struct i40e_aqc_get_switch_config_resp *buf, 1881270631Sjfv u16 buf_size, u16 *start_seid, 1882270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1883270631Sjfv{ 1884270631Sjfv struct i40e_aq_desc desc; 1885270631Sjfv struct i40e_aqc_switch_seid *scfg = 1886270631Sjfv (struct i40e_aqc_switch_seid *)&desc.params.raw; 1887270631Sjfv enum i40e_status_code status; 1888270631Sjfv 1889270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 1890270631Sjfv i40e_aqc_opc_get_switch_config); 1891270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1892270631Sjfv if (buf_size > I40E_AQ_LARGE_BUF) 1893270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1894270631Sjfv scfg->seid = CPU_TO_LE16(*start_seid); 1895270631Sjfv 1896270631Sjfv status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1897270631Sjfv *start_seid = LE16_TO_CPU(scfg->seid); 1898270631Sjfv 1899270631Sjfv return status; 1900270631Sjfv} 1901270631Sjfv 1902270631Sjfv/** 1903270631Sjfv * i40e_aq_get_firmware_version 1904270631Sjfv * @hw: pointer to the hw struct 1905270631Sjfv * @fw_major_version: firmware major version 1906270631Sjfv * @fw_minor_version: firmware minor version 1907270631Sjfv * @api_major_version: major queue version 1908270631Sjfv * @api_minor_version: minor queue version 1909270631Sjfv * @cmd_details: pointer to command details structure or NULL 1910270631Sjfv * 1911270631Sjfv * Get the firmware version from the admin queue commands 1912270631Sjfv **/ 1913270631Sjfvenum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 1914270631Sjfv u16 *fw_major_version, u16 *fw_minor_version, 1915270631Sjfv u16 *api_major_version, u16 *api_minor_version, 1916270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1917270631Sjfv{ 1918270631Sjfv struct i40e_aq_desc desc; 1919270631Sjfv struct i40e_aqc_get_version *resp = 1920270631Sjfv (struct i40e_aqc_get_version *)&desc.params.raw; 1921270631Sjfv enum i40e_status_code status; 1922270631Sjfv 1923270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1924270631Sjfv 1925270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1926270631Sjfv 1927270631Sjfv if (status == I40E_SUCCESS) { 1928270631Sjfv if (fw_major_version != NULL) 1929270631Sjfv *fw_major_version = LE16_TO_CPU(resp->fw_major); 1930270631Sjfv if (fw_minor_version != NULL) 1931270631Sjfv *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 1932270631Sjfv if (api_major_version != NULL) 1933270631Sjfv *api_major_version = LE16_TO_CPU(resp->api_major); 1934270631Sjfv if (api_minor_version != NULL) 1935270631Sjfv *api_minor_version = LE16_TO_CPU(resp->api_minor); 1936270631Sjfv 1937270631Sjfv /* A workaround to fix the API version in SW */ 1938270631Sjfv if (api_major_version && api_minor_version && 1939270631Sjfv fw_major_version && fw_minor_version && 1940270631Sjfv ((*api_major_version == 1) && (*api_minor_version == 1)) && 1941270631Sjfv (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 1942270631Sjfv (*fw_major_version > 4))) 1943270631Sjfv *api_minor_version = 2; 1944270631Sjfv } 1945270631Sjfv 1946270631Sjfv return status; 1947270631Sjfv} 1948270631Sjfv 1949270631Sjfv/** 1950270631Sjfv * i40e_aq_send_driver_version 1951270631Sjfv * @hw: pointer to the hw struct 1952270631Sjfv * @dv: driver's major, minor version 1953270631Sjfv * @cmd_details: pointer to command details structure or NULL 1954270631Sjfv * 1955270631Sjfv * Send the driver version to the firmware 1956270631Sjfv **/ 1957270631Sjfvenum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 1958270631Sjfv struct i40e_driver_version *dv, 1959270631Sjfv struct i40e_asq_cmd_details *cmd_details) 1960270631Sjfv{ 1961270631Sjfv struct i40e_aq_desc desc; 1962270631Sjfv struct i40e_aqc_driver_version *cmd = 1963270631Sjfv (struct i40e_aqc_driver_version *)&desc.params.raw; 1964270631Sjfv enum i40e_status_code status; 1965270631Sjfv u16 len; 1966270631Sjfv 1967270631Sjfv if (dv == NULL) 1968270631Sjfv return I40E_ERR_PARAM; 1969270631Sjfv 1970270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 1971270631Sjfv 1972270631Sjfv desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_SI); 1973270631Sjfv cmd->driver_major_ver = dv->major_version; 1974270631Sjfv cmd->driver_minor_ver = dv->minor_version; 1975270631Sjfv cmd->driver_build_ver = dv->build_version; 1976270631Sjfv cmd->driver_subbuild_ver = dv->subbuild_version; 1977270631Sjfv 1978270631Sjfv len = 0; 1979270631Sjfv while (len < sizeof(dv->driver_string) && 1980270631Sjfv (dv->driver_string[len] < 0x80) && 1981270631Sjfv dv->driver_string[len]) 1982270631Sjfv len++; 1983270631Sjfv status = i40e_asq_send_command(hw, &desc, dv->driver_string, 1984270631Sjfv len, cmd_details); 1985270631Sjfv 1986270631Sjfv return status; 1987270631Sjfv} 1988270631Sjfv 1989270631Sjfv/** 1990270631Sjfv * i40e_get_link_status - get status of the HW network link 1991270631Sjfv * @hw: pointer to the hw struct 1992270631Sjfv * 1993270631Sjfv * Returns TRUE if link is up, FALSE if link is down. 1994270631Sjfv * 1995270631Sjfv * Side effect: LinkStatusEvent reporting becomes enabled 1996270631Sjfv **/ 1997270631Sjfvbool i40e_get_link_status(struct i40e_hw *hw) 1998270631Sjfv{ 1999270631Sjfv enum i40e_status_code status = I40E_SUCCESS; 2000270631Sjfv bool link_status = FALSE; 2001270631Sjfv 2002270631Sjfv if (hw->phy.get_link_info) { 2003270631Sjfv status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2004270631Sjfv 2005270631Sjfv if (status != I40E_SUCCESS) 2006270631Sjfv goto i40e_get_link_status_exit; 2007270631Sjfv } 2008270631Sjfv 2009270631Sjfv link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2010270631Sjfv 2011270631Sjfvi40e_get_link_status_exit: 2012270631Sjfv return link_status; 2013270631Sjfv} 2014270631Sjfv 2015270631Sjfv/** 2016270631Sjfv * i40e_get_link_speed 2017270631Sjfv * @hw: pointer to the hw struct 2018270631Sjfv * 2019270631Sjfv * Returns the link speed of the adapter. 2020270631Sjfv **/ 2021270631Sjfvenum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2022270631Sjfv{ 2023270631Sjfv enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2024270631Sjfv enum i40e_status_code status = I40E_SUCCESS; 2025270631Sjfv 2026270631Sjfv if (hw->phy.get_link_info) { 2027270631Sjfv status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2028270631Sjfv 2029270631Sjfv if (status != I40E_SUCCESS) 2030270631Sjfv goto i40e_link_speed_exit; 2031270631Sjfv } 2032270631Sjfv 2033270631Sjfv speed = hw->phy.link_info.link_speed; 2034270631Sjfv 2035270631Sjfvi40e_link_speed_exit: 2036270631Sjfv return speed; 2037270631Sjfv} 2038270631Sjfv 2039270631Sjfv/** 2040270631Sjfv * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2041270631Sjfv * @hw: pointer to the hw struct 2042270631Sjfv * @uplink_seid: the MAC or other gizmo SEID 2043270631Sjfv * @downlink_seid: the VSI SEID 2044270631Sjfv * @enabled_tc: bitmap of TCs to be enabled 2045270631Sjfv * @default_port: TRUE for default port VSI, FALSE for control port 2046270631Sjfv * @enable_l2_filtering: TRUE to add L2 filter table rules to regular forwarding rules for cloud support 2047270631Sjfv * @veb_seid: pointer to where to put the resulting VEB SEID 2048270631Sjfv * @cmd_details: pointer to command details structure or NULL 2049270631Sjfv * 2050270631Sjfv * This asks the FW to add a VEB between the uplink and downlink 2051270631Sjfv * elements. If the uplink SEID is 0, this will be a floating VEB. 2052270631Sjfv **/ 2053270631Sjfvenum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2054270631Sjfv u16 downlink_seid, u8 enabled_tc, 2055270631Sjfv bool default_port, bool enable_l2_filtering, 2056270631Sjfv u16 *veb_seid, 2057270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2058270631Sjfv{ 2059270631Sjfv struct i40e_aq_desc desc; 2060270631Sjfv struct i40e_aqc_add_veb *cmd = 2061270631Sjfv (struct i40e_aqc_add_veb *)&desc.params.raw; 2062270631Sjfv struct i40e_aqc_add_veb_completion *resp = 2063270631Sjfv (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2064270631Sjfv enum i40e_status_code status; 2065270631Sjfv u16 veb_flags = 0; 2066270631Sjfv 2067270631Sjfv /* SEIDs need to either both be set or both be 0 for floating VEB */ 2068270631Sjfv if (!!uplink_seid != !!downlink_seid) 2069270631Sjfv return I40E_ERR_PARAM; 2070270631Sjfv 2071270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2072270631Sjfv 2073270631Sjfv cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2074270631Sjfv cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2075270631Sjfv cmd->enable_tcs = enabled_tc; 2076270631Sjfv if (!uplink_seid) 2077270631Sjfv veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2078270631Sjfv if (default_port) 2079270631Sjfv veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2080270631Sjfv else 2081270631Sjfv veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2082270631Sjfv 2083270631Sjfv if (enable_l2_filtering) 2084270631Sjfv veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; 2085270631Sjfv 2086270631Sjfv cmd->veb_flags = CPU_TO_LE16(veb_flags); 2087270631Sjfv 2088270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2089270631Sjfv 2090270631Sjfv if (!status && veb_seid) 2091270631Sjfv *veb_seid = LE16_TO_CPU(resp->veb_seid); 2092270631Sjfv 2093270631Sjfv return status; 2094270631Sjfv} 2095270631Sjfv 2096270631Sjfv/** 2097270631Sjfv * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2098270631Sjfv * @hw: pointer to the hw struct 2099270631Sjfv * @veb_seid: the SEID of the VEB to query 2100270631Sjfv * @switch_id: the uplink switch id 2101270631Sjfv * @floating: set to TRUE if the VEB is floating 2102270631Sjfv * @statistic_index: index of the stats counter block for this VEB 2103270631Sjfv * @vebs_used: number of VEB's used by function 2104270631Sjfv * @vebs_free: total VEB's not reserved by any function 2105270631Sjfv * @cmd_details: pointer to command details structure or NULL 2106270631Sjfv * 2107270631Sjfv * This retrieves the parameters for a particular VEB, specified by 2108270631Sjfv * uplink_seid, and returns them to the caller. 2109270631Sjfv **/ 2110270631Sjfvenum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2111270631Sjfv u16 veb_seid, u16 *switch_id, 2112270631Sjfv bool *floating, u16 *statistic_index, 2113270631Sjfv u16 *vebs_used, u16 *vebs_free, 2114270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2115270631Sjfv{ 2116270631Sjfv struct i40e_aq_desc desc; 2117270631Sjfv struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2118270631Sjfv (struct i40e_aqc_get_veb_parameters_completion *) 2119270631Sjfv &desc.params.raw; 2120270631Sjfv enum i40e_status_code status; 2121270631Sjfv 2122270631Sjfv if (veb_seid == 0) 2123270631Sjfv return I40E_ERR_PARAM; 2124270631Sjfv 2125270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 2126270631Sjfv i40e_aqc_opc_get_veb_parameters); 2127270631Sjfv cmd_resp->seid = CPU_TO_LE16(veb_seid); 2128270631Sjfv 2129270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2130270631Sjfv if (status) 2131270631Sjfv goto get_veb_exit; 2132270631Sjfv 2133270631Sjfv if (switch_id) 2134270631Sjfv *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2135270631Sjfv if (statistic_index) 2136270631Sjfv *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2137270631Sjfv if (vebs_used) 2138270631Sjfv *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2139270631Sjfv if (vebs_free) 2140270631Sjfv *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2141270631Sjfv if (floating) { 2142270631Sjfv u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2143270631Sjfv if (flags & I40E_AQC_ADD_VEB_FLOATING) 2144270631Sjfv *floating = TRUE; 2145270631Sjfv else 2146270631Sjfv *floating = FALSE; 2147270631Sjfv } 2148270631Sjfv 2149270631Sjfvget_veb_exit: 2150270631Sjfv return status; 2151270631Sjfv} 2152270631Sjfv 2153270631Sjfv/** 2154270631Sjfv * i40e_aq_add_macvlan 2155270631Sjfv * @hw: pointer to the hw struct 2156270631Sjfv * @seid: VSI for the mac address 2157270631Sjfv * @mv_list: list of macvlans to be added 2158270631Sjfv * @count: length of the list 2159270631Sjfv * @cmd_details: pointer to command details structure or NULL 2160270631Sjfv * 2161270631Sjfv * Add MAC/VLAN addresses to the HW filtering 2162270631Sjfv **/ 2163270631Sjfvenum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2164270631Sjfv struct i40e_aqc_add_macvlan_element_data *mv_list, 2165270631Sjfv u16 count, struct i40e_asq_cmd_details *cmd_details) 2166270631Sjfv{ 2167270631Sjfv struct i40e_aq_desc desc; 2168270631Sjfv struct i40e_aqc_macvlan *cmd = 2169270631Sjfv (struct i40e_aqc_macvlan *)&desc.params.raw; 2170270631Sjfv enum i40e_status_code status; 2171270631Sjfv u16 buf_size; 2172270631Sjfv 2173270631Sjfv if (count == 0 || !mv_list || !hw) 2174270631Sjfv return I40E_ERR_PARAM; 2175270631Sjfv 2176270631Sjfv buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data); 2177270631Sjfv 2178270631Sjfv /* prep the rest of the request */ 2179270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2180270631Sjfv cmd->num_addresses = CPU_TO_LE16(count); 2181270631Sjfv cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2182270631Sjfv cmd->seid[1] = 0; 2183270631Sjfv cmd->seid[2] = 0; 2184270631Sjfv 2185270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2186270631Sjfv if (buf_size > I40E_AQ_LARGE_BUF) 2187270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2188270631Sjfv 2189270631Sjfv status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2190270631Sjfv cmd_details); 2191270631Sjfv 2192270631Sjfv return status; 2193270631Sjfv} 2194270631Sjfv 2195270631Sjfv/** 2196270631Sjfv * i40e_aq_remove_macvlan 2197270631Sjfv * @hw: pointer to the hw struct 2198270631Sjfv * @seid: VSI for the mac address 2199270631Sjfv * @mv_list: list of macvlans to be removed 2200270631Sjfv * @count: length of the list 2201270631Sjfv * @cmd_details: pointer to command details structure or NULL 2202270631Sjfv * 2203270631Sjfv * Remove MAC/VLAN addresses from the HW filtering 2204270631Sjfv **/ 2205270631Sjfvenum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2206270631Sjfv struct i40e_aqc_remove_macvlan_element_data *mv_list, 2207270631Sjfv u16 count, struct i40e_asq_cmd_details *cmd_details) 2208270631Sjfv{ 2209270631Sjfv struct i40e_aq_desc desc; 2210270631Sjfv struct i40e_aqc_macvlan *cmd = 2211270631Sjfv (struct i40e_aqc_macvlan *)&desc.params.raw; 2212270631Sjfv enum i40e_status_code status; 2213270631Sjfv u16 buf_size; 2214270631Sjfv 2215270631Sjfv if (count == 0 || !mv_list || !hw) 2216270631Sjfv return I40E_ERR_PARAM; 2217270631Sjfv 2218270631Sjfv buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data); 2219270631Sjfv 2220270631Sjfv /* prep the rest of the request */ 2221270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2222270631Sjfv cmd->num_addresses = CPU_TO_LE16(count); 2223270631Sjfv cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2224270631Sjfv cmd->seid[1] = 0; 2225270631Sjfv cmd->seid[2] = 0; 2226270631Sjfv 2227270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2228270631Sjfv if (buf_size > I40E_AQ_LARGE_BUF) 2229270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2230270631Sjfv 2231270631Sjfv status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2232270631Sjfv cmd_details); 2233270631Sjfv 2234270631Sjfv return status; 2235270631Sjfv} 2236270631Sjfv 2237270631Sjfv/** 2238270631Sjfv * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 2239270631Sjfv * @hw: pointer to the hw struct 2240270631Sjfv * @seid: VSI for the vlan filters 2241270631Sjfv * @v_list: list of vlan filters to be added 2242270631Sjfv * @count: length of the list 2243270631Sjfv * @cmd_details: pointer to command details structure or NULL 2244270631Sjfv **/ 2245270631Sjfvenum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 2246270631Sjfv struct i40e_aqc_add_remove_vlan_element_data *v_list, 2247270631Sjfv u8 count, struct i40e_asq_cmd_details *cmd_details) 2248270631Sjfv{ 2249270631Sjfv struct i40e_aq_desc desc; 2250270631Sjfv struct i40e_aqc_macvlan *cmd = 2251270631Sjfv (struct i40e_aqc_macvlan *)&desc.params.raw; 2252270631Sjfv enum i40e_status_code status; 2253270631Sjfv u16 buf_size; 2254270631Sjfv 2255270631Sjfv if (count == 0 || !v_list || !hw) 2256270631Sjfv return I40E_ERR_PARAM; 2257270631Sjfv 2258270631Sjfv buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data); 2259270631Sjfv 2260270631Sjfv /* prep the rest of the request */ 2261270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 2262270631Sjfv cmd->num_addresses = CPU_TO_LE16(count); 2263270631Sjfv cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2264270631Sjfv cmd->seid[1] = 0; 2265270631Sjfv cmd->seid[2] = 0; 2266270631Sjfv 2267270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2268270631Sjfv if (buf_size > I40E_AQ_LARGE_BUF) 2269270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2270270631Sjfv 2271270631Sjfv status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2272270631Sjfv cmd_details); 2273270631Sjfv 2274270631Sjfv return status; 2275270631Sjfv} 2276270631Sjfv 2277270631Sjfv/** 2278270631Sjfv * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 2279270631Sjfv * @hw: pointer to the hw struct 2280270631Sjfv * @seid: VSI for the vlan filters 2281270631Sjfv * @v_list: list of macvlans to be removed 2282270631Sjfv * @count: length of the list 2283270631Sjfv * @cmd_details: pointer to command details structure or NULL 2284270631Sjfv **/ 2285270631Sjfvenum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 2286270631Sjfv struct i40e_aqc_add_remove_vlan_element_data *v_list, 2287270631Sjfv u8 count, struct i40e_asq_cmd_details *cmd_details) 2288270631Sjfv{ 2289270631Sjfv struct i40e_aq_desc desc; 2290270631Sjfv struct i40e_aqc_macvlan *cmd = 2291270631Sjfv (struct i40e_aqc_macvlan *)&desc.params.raw; 2292270631Sjfv enum i40e_status_code status; 2293270631Sjfv u16 buf_size; 2294270631Sjfv 2295270631Sjfv if (count == 0 || !v_list || !hw) 2296270631Sjfv return I40E_ERR_PARAM; 2297270631Sjfv 2298270631Sjfv buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data); 2299270631Sjfv 2300270631Sjfv /* prep the rest of the request */ 2301270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 2302270631Sjfv cmd->num_addresses = CPU_TO_LE16(count); 2303270631Sjfv cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2304270631Sjfv cmd->seid[1] = 0; 2305270631Sjfv cmd->seid[2] = 0; 2306270631Sjfv 2307270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2308270631Sjfv if (buf_size > I40E_AQ_LARGE_BUF) 2309270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2310270631Sjfv 2311270631Sjfv status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2312270631Sjfv cmd_details); 2313270631Sjfv 2314270631Sjfv return status; 2315270631Sjfv} 2316270631Sjfv 2317270631Sjfv/** 2318270631Sjfv * i40e_aq_send_msg_to_vf 2319270631Sjfv * @hw: pointer to the hardware structure 2320270631Sjfv * @vfid: vf id to send msg 2321270631Sjfv * @v_opcode: opcodes for VF-PF communication 2322270631Sjfv * @v_retval: return error code 2323270631Sjfv * @msg: pointer to the msg buffer 2324270631Sjfv * @msglen: msg length 2325270631Sjfv * @cmd_details: pointer to command details 2326270631Sjfv * 2327270631Sjfv * send msg to vf 2328270631Sjfv **/ 2329270631Sjfvenum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2330270631Sjfv u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2331270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2332270631Sjfv{ 2333270631Sjfv struct i40e_aq_desc desc; 2334270631Sjfv struct i40e_aqc_pf_vf_message *cmd = 2335270631Sjfv (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2336270631Sjfv enum i40e_status_code status; 2337270631Sjfv 2338270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2339270631Sjfv cmd->id = CPU_TO_LE32(vfid); 2340270631Sjfv desc.cookie_high = CPU_TO_LE32(v_opcode); 2341270631Sjfv desc.cookie_low = CPU_TO_LE32(v_retval); 2342270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 2343270631Sjfv if (msglen) { 2344270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 2345270631Sjfv I40E_AQ_FLAG_RD)); 2346270631Sjfv if (msglen > I40E_AQ_LARGE_BUF) 2347270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2348270631Sjfv desc.datalen = CPU_TO_LE16(msglen); 2349270631Sjfv } 2350270631Sjfv status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2351270631Sjfv 2352270631Sjfv return status; 2353270631Sjfv} 2354270631Sjfv 2355270631Sjfv/** 2356270631Sjfv * i40e_aq_debug_write_register 2357270631Sjfv * @hw: pointer to the hw struct 2358270631Sjfv * @reg_addr: register address 2359270631Sjfv * @reg_val: register value 2360270631Sjfv * @cmd_details: pointer to command details structure or NULL 2361270631Sjfv * 2362270631Sjfv * Write to a register using the admin queue commands 2363270631Sjfv **/ 2364270631Sjfvenum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 2365270631Sjfv u32 reg_addr, u64 reg_val, 2366270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2367270631Sjfv{ 2368270631Sjfv struct i40e_aq_desc desc; 2369270631Sjfv struct i40e_aqc_debug_reg_read_write *cmd = 2370270631Sjfv (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2371270631Sjfv enum i40e_status_code status; 2372270631Sjfv 2373270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2374270631Sjfv 2375270631Sjfv cmd->address = CPU_TO_LE32(reg_addr); 2376270631Sjfv cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 2377270631Sjfv cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 2378270631Sjfv 2379270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2380270631Sjfv 2381270631Sjfv return status; 2382270631Sjfv} 2383270631Sjfv 2384270631Sjfv/** 2385270631Sjfv * i40e_aq_get_hmc_resource_profile 2386270631Sjfv * @hw: pointer to the hw struct 2387270631Sjfv * @profile: type of profile the HMC is to be set as 2388270631Sjfv * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2389270631Sjfv * @cmd_details: pointer to command details structure or NULL 2390270631Sjfv * 2391270631Sjfv * query the HMC profile of the device. 2392270631Sjfv **/ 2393270631Sjfvenum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw, 2394270631Sjfv enum i40e_aq_hmc_profile *profile, 2395270631Sjfv u8 *pe_vf_enabled_count, 2396270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2397270631Sjfv{ 2398270631Sjfv struct i40e_aq_desc desc; 2399270631Sjfv struct i40e_aq_get_set_hmc_resource_profile *resp = 2400270631Sjfv (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2401270631Sjfv enum i40e_status_code status; 2402270631Sjfv 2403270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 2404270631Sjfv i40e_aqc_opc_query_hmc_resource_profile); 2405270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2406270631Sjfv 2407270631Sjfv *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile & 2408270631Sjfv I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK); 2409270631Sjfv *pe_vf_enabled_count = resp->pe_vf_enabled & 2410270631Sjfv I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK; 2411270631Sjfv 2412270631Sjfv return status; 2413270631Sjfv} 2414270631Sjfv 2415270631Sjfv/** 2416270631Sjfv * i40e_aq_set_hmc_resource_profile 2417270631Sjfv * @hw: pointer to the hw struct 2418270631Sjfv * @profile: type of profile the HMC is to be set as 2419270631Sjfv * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2420270631Sjfv * @cmd_details: pointer to command details structure or NULL 2421270631Sjfv * 2422270631Sjfv * set the HMC profile of the device. 2423270631Sjfv **/ 2424270631Sjfvenum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 2425270631Sjfv enum i40e_aq_hmc_profile profile, 2426270631Sjfv u8 pe_vf_enabled_count, 2427270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2428270631Sjfv{ 2429270631Sjfv struct i40e_aq_desc desc; 2430270631Sjfv struct i40e_aq_get_set_hmc_resource_profile *cmd = 2431270631Sjfv (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2432270631Sjfv enum i40e_status_code status; 2433270631Sjfv 2434270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 2435270631Sjfv i40e_aqc_opc_set_hmc_resource_profile); 2436270631Sjfv 2437270631Sjfv cmd->pm_profile = (u8)profile; 2438270631Sjfv cmd->pe_vf_enabled = pe_vf_enabled_count; 2439270631Sjfv 2440270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2441270631Sjfv 2442270631Sjfv return status; 2443270631Sjfv} 2444270631Sjfv 2445270631Sjfv/** 2446270631Sjfv * i40e_aq_request_resource 2447270631Sjfv * @hw: pointer to the hw struct 2448270631Sjfv * @resource: resource id 2449270631Sjfv * @access: access type 2450270631Sjfv * @sdp_number: resource number 2451270631Sjfv * @timeout: the maximum time in ms that the driver may hold the resource 2452270631Sjfv * @cmd_details: pointer to command details structure or NULL 2453270631Sjfv * 2454270631Sjfv * requests common resource using the admin queue commands 2455270631Sjfv **/ 2456270631Sjfvenum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 2457270631Sjfv enum i40e_aq_resources_ids resource, 2458270631Sjfv enum i40e_aq_resource_access_type access, 2459270631Sjfv u8 sdp_number, u64 *timeout, 2460270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2461270631Sjfv{ 2462270631Sjfv struct i40e_aq_desc desc; 2463270631Sjfv struct i40e_aqc_request_resource *cmd_resp = 2464270631Sjfv (struct i40e_aqc_request_resource *)&desc.params.raw; 2465270631Sjfv enum i40e_status_code status; 2466270631Sjfv 2467270631Sjfv DEBUGFUNC("i40e_aq_request_resource"); 2468270631Sjfv 2469270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2470270631Sjfv 2471270631Sjfv cmd_resp->resource_id = CPU_TO_LE16(resource); 2472270631Sjfv cmd_resp->access_type = CPU_TO_LE16(access); 2473270631Sjfv cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 2474270631Sjfv 2475270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2476270631Sjfv /* The completion specifies the maximum time in ms that the driver 2477270631Sjfv * may hold the resource in the Timeout field. 2478270631Sjfv * If the resource is held by someone else, the command completes with 2479270631Sjfv * busy return value and the timeout field indicates the maximum time 2480270631Sjfv * the current owner of the resource has to free it. 2481270631Sjfv */ 2482270631Sjfv if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2483270631Sjfv *timeout = LE32_TO_CPU(cmd_resp->timeout); 2484270631Sjfv 2485270631Sjfv return status; 2486270631Sjfv} 2487270631Sjfv 2488270631Sjfv/** 2489270631Sjfv * i40e_aq_release_resource 2490270631Sjfv * @hw: pointer to the hw struct 2491270631Sjfv * @resource: resource id 2492270631Sjfv * @sdp_number: resource number 2493270631Sjfv * @cmd_details: pointer to command details structure or NULL 2494270631Sjfv * 2495270631Sjfv * release common resource using the admin queue commands 2496270631Sjfv **/ 2497270631Sjfvenum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 2498270631Sjfv enum i40e_aq_resources_ids resource, 2499270631Sjfv u8 sdp_number, 2500270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2501270631Sjfv{ 2502270631Sjfv struct i40e_aq_desc desc; 2503270631Sjfv struct i40e_aqc_request_resource *cmd = 2504270631Sjfv (struct i40e_aqc_request_resource *)&desc.params.raw; 2505270631Sjfv enum i40e_status_code status; 2506270631Sjfv 2507270631Sjfv DEBUGFUNC("i40e_aq_release_resource"); 2508270631Sjfv 2509270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2510270631Sjfv 2511270631Sjfv cmd->resource_id = CPU_TO_LE16(resource); 2512270631Sjfv cmd->resource_number = CPU_TO_LE32(sdp_number); 2513270631Sjfv 2514270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2515270631Sjfv 2516270631Sjfv return status; 2517270631Sjfv} 2518270631Sjfv 2519270631Sjfv/** 2520270631Sjfv * i40e_aq_read_nvm 2521270631Sjfv * @hw: pointer to the hw struct 2522270631Sjfv * @module_pointer: module pointer location in words from the NVM beginning 2523270631Sjfv * @offset: byte offset from the module beginning 2524270631Sjfv * @length: length of the section to be read (in bytes from the offset) 2525270631Sjfv * @data: command buffer (size [bytes] = length) 2526270631Sjfv * @last_command: tells if this is the last command in a series 2527270631Sjfv * @cmd_details: pointer to command details structure or NULL 2528270631Sjfv * 2529270631Sjfv * Read the NVM using the admin queue commands 2530270631Sjfv **/ 2531270631Sjfvenum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2532270631Sjfv u32 offset, u16 length, void *data, 2533270631Sjfv bool last_command, 2534270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2535270631Sjfv{ 2536270631Sjfv struct i40e_aq_desc desc; 2537270631Sjfv struct i40e_aqc_nvm_update *cmd = 2538270631Sjfv (struct i40e_aqc_nvm_update *)&desc.params.raw; 2539270631Sjfv enum i40e_status_code status; 2540270631Sjfv 2541270631Sjfv DEBUGFUNC("i40e_aq_read_nvm"); 2542270631Sjfv 2543270631Sjfv /* In offset the highest byte must be zeroed. */ 2544270631Sjfv if (offset & 0xFF000000) { 2545270631Sjfv status = I40E_ERR_PARAM; 2546270631Sjfv goto i40e_aq_read_nvm_exit; 2547270631Sjfv } 2548270631Sjfv 2549270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2550270631Sjfv 2551270631Sjfv /* If this is the last command in a series, set the proper flag. */ 2552270631Sjfv if (last_command) 2553270631Sjfv cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2554270631Sjfv cmd->module_pointer = module_pointer; 2555270631Sjfv cmd->offset = CPU_TO_LE32(offset); 2556270631Sjfv cmd->length = CPU_TO_LE16(length); 2557270631Sjfv 2558270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2559270631Sjfv if (length > I40E_AQ_LARGE_BUF) 2560270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2561270631Sjfv 2562270631Sjfv status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2563270631Sjfv 2564270631Sjfvi40e_aq_read_nvm_exit: 2565270631Sjfv return status; 2566270631Sjfv} 2567270631Sjfv 2568270631Sjfv/** 2569270631Sjfv * i40e_aq_erase_nvm 2570270631Sjfv * @hw: pointer to the hw struct 2571270631Sjfv * @module_pointer: module pointer location in words from the NVM beginning 2572270631Sjfv * @offset: offset in the module (expressed in 4 KB from module's beginning) 2573270631Sjfv * @length: length of the section to be erased (expressed in 4 KB) 2574270631Sjfv * @last_command: tells if this is the last command in a series 2575270631Sjfv * @cmd_details: pointer to command details structure or NULL 2576270631Sjfv * 2577270631Sjfv * Erase the NVM sector using the admin queue commands 2578270631Sjfv **/ 2579270631Sjfvenum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2580270631Sjfv u32 offset, u16 length, bool last_command, 2581270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2582270631Sjfv{ 2583270631Sjfv struct i40e_aq_desc desc; 2584270631Sjfv struct i40e_aqc_nvm_update *cmd = 2585270631Sjfv (struct i40e_aqc_nvm_update *)&desc.params.raw; 2586270631Sjfv enum i40e_status_code status; 2587270631Sjfv 2588270631Sjfv DEBUGFUNC("i40e_aq_erase_nvm"); 2589270631Sjfv 2590270631Sjfv /* In offset the highest byte must be zeroed. */ 2591270631Sjfv if (offset & 0xFF000000) { 2592270631Sjfv status = I40E_ERR_PARAM; 2593270631Sjfv goto i40e_aq_erase_nvm_exit; 2594270631Sjfv } 2595270631Sjfv 2596270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2597270631Sjfv 2598270631Sjfv /* If this is the last command in a series, set the proper flag. */ 2599270631Sjfv if (last_command) 2600270631Sjfv cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2601270631Sjfv cmd->module_pointer = module_pointer; 2602270631Sjfv cmd->offset = CPU_TO_LE32(offset); 2603270631Sjfv cmd->length = CPU_TO_LE16(length); 2604270631Sjfv 2605270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2606270631Sjfv 2607270631Sjfvi40e_aq_erase_nvm_exit: 2608270631Sjfv return status; 2609270631Sjfv} 2610270631Sjfv 2611270631Sjfv#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01 2612270631Sjfv#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02 2613270631Sjfv#define I40E_DEV_FUNC_CAP_NPAR 0x03 2614270631Sjfv#define I40E_DEV_FUNC_CAP_OS2BMC 0x04 2615270631Sjfv#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 2616270631Sjfv#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 2617270631Sjfv#define I40E_DEV_FUNC_CAP_VF 0x13 2618270631Sjfv#define I40E_DEV_FUNC_CAP_VMDQ 0x14 2619270631Sjfv#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15 2620270631Sjfv#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16 2621270631Sjfv#define I40E_DEV_FUNC_CAP_VSI 0x17 2622270631Sjfv#define I40E_DEV_FUNC_CAP_DCB 0x18 2623270631Sjfv#define I40E_DEV_FUNC_CAP_FCOE 0x21 2624270631Sjfv#define I40E_DEV_FUNC_CAP_RSS 0x40 2625270631Sjfv#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 2626270631Sjfv#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42 2627270631Sjfv#define I40E_DEV_FUNC_CAP_MSIX 0x43 2628270631Sjfv#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44 2629270631Sjfv#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45 2630270631Sjfv#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46 2631270631Sjfv#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1 2632270631Sjfv#define I40E_DEV_FUNC_CAP_CEM 0xF2 2633270631Sjfv#define I40E_DEV_FUNC_CAP_IWARP 0x51 2634270631Sjfv#define I40E_DEV_FUNC_CAP_LED 0x61 2635270631Sjfv#define I40E_DEV_FUNC_CAP_SDP 0x62 2636270631Sjfv#define I40E_DEV_FUNC_CAP_MDIO 0x63 2637270631Sjfv 2638270631Sjfv/** 2639270631Sjfv * i40e_parse_discover_capabilities 2640270631Sjfv * @hw: pointer to the hw struct 2641270631Sjfv * @buff: pointer to a buffer containing device/function capability records 2642270631Sjfv * @cap_count: number of capability records in the list 2643270631Sjfv * @list_type_opc: type of capabilities list to parse 2644270631Sjfv * 2645270631Sjfv * Parse the device/function capabilities list. 2646270631Sjfv **/ 2647270631Sjfvstatic void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2648270631Sjfv u32 cap_count, 2649270631Sjfv enum i40e_admin_queue_opc list_type_opc) 2650270631Sjfv{ 2651270631Sjfv struct i40e_aqc_list_capabilities_element_resp *cap; 2652270631Sjfv u32 number, logical_id, phys_id; 2653270631Sjfv struct i40e_hw_capabilities *p; 2654270631Sjfv u32 i = 0; 2655270631Sjfv u16 id; 2656270631Sjfv 2657270631Sjfv cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2658270631Sjfv 2659270631Sjfv if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2660270631Sjfv p = (struct i40e_hw_capabilities *)&hw->dev_caps; 2661270631Sjfv else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2662270631Sjfv p = (struct i40e_hw_capabilities *)&hw->func_caps; 2663270631Sjfv else 2664270631Sjfv return; 2665270631Sjfv 2666270631Sjfv for (i = 0; i < cap_count; i++, cap++) { 2667270631Sjfv id = LE16_TO_CPU(cap->id); 2668270631Sjfv number = LE32_TO_CPU(cap->number); 2669270631Sjfv logical_id = LE32_TO_CPU(cap->logical_id); 2670270631Sjfv phys_id = LE32_TO_CPU(cap->phys_id); 2671270631Sjfv 2672270631Sjfv switch (id) { 2673270631Sjfv case I40E_DEV_FUNC_CAP_SWITCH_MODE: 2674270631Sjfv p->switch_mode = number; 2675270631Sjfv break; 2676270631Sjfv case I40E_DEV_FUNC_CAP_MGMT_MODE: 2677270631Sjfv p->management_mode = number; 2678270631Sjfv break; 2679270631Sjfv case I40E_DEV_FUNC_CAP_NPAR: 2680270631Sjfv p->npar_enable = number; 2681270631Sjfv break; 2682270631Sjfv case I40E_DEV_FUNC_CAP_OS2BMC: 2683270631Sjfv p->os2bmc = number; 2684270631Sjfv break; 2685270631Sjfv case I40E_DEV_FUNC_CAP_VALID_FUNC: 2686270631Sjfv p->valid_functions = number; 2687270631Sjfv break; 2688270631Sjfv case I40E_DEV_FUNC_CAP_SRIOV_1_1: 2689270631Sjfv if (number == 1) 2690270631Sjfv p->sr_iov_1_1 = TRUE; 2691270631Sjfv break; 2692270631Sjfv case I40E_DEV_FUNC_CAP_VF: 2693270631Sjfv p->num_vfs = number; 2694270631Sjfv p->vf_base_id = logical_id; 2695270631Sjfv break; 2696270631Sjfv case I40E_DEV_FUNC_CAP_VMDQ: 2697270631Sjfv if (number == 1) 2698270631Sjfv p->vmdq = TRUE; 2699270631Sjfv break; 2700270631Sjfv case I40E_DEV_FUNC_CAP_802_1_QBG: 2701270631Sjfv if (number == 1) 2702270631Sjfv p->evb_802_1_qbg = TRUE; 2703270631Sjfv break; 2704270631Sjfv case I40E_DEV_FUNC_CAP_802_1_QBH: 2705270631Sjfv if (number == 1) 2706270631Sjfv p->evb_802_1_qbh = TRUE; 2707270631Sjfv break; 2708270631Sjfv case I40E_DEV_FUNC_CAP_VSI: 2709270631Sjfv p->num_vsis = number; 2710270631Sjfv break; 2711270631Sjfv case I40E_DEV_FUNC_CAP_DCB: 2712270631Sjfv if (number == 1) { 2713270631Sjfv p->dcb = TRUE; 2714270631Sjfv p->enabled_tcmap = logical_id; 2715270631Sjfv p->maxtc = phys_id; 2716270631Sjfv } 2717270631Sjfv break; 2718270631Sjfv case I40E_DEV_FUNC_CAP_FCOE: 2719270631Sjfv if (number == 1) 2720270631Sjfv p->fcoe = TRUE; 2721270631Sjfv break; 2722270631Sjfv case I40E_DEV_FUNC_CAP_RSS: 2723270631Sjfv p->rss = TRUE; 2724270631Sjfv p->rss_table_size = number; 2725270631Sjfv p->rss_table_entry_width = logical_id; 2726270631Sjfv break; 2727270631Sjfv case I40E_DEV_FUNC_CAP_RX_QUEUES: 2728270631Sjfv p->num_rx_qp = number; 2729270631Sjfv p->base_queue = phys_id; 2730270631Sjfv break; 2731270631Sjfv case I40E_DEV_FUNC_CAP_TX_QUEUES: 2732270631Sjfv p->num_tx_qp = number; 2733270631Sjfv p->base_queue = phys_id; 2734270631Sjfv break; 2735270631Sjfv case I40E_DEV_FUNC_CAP_MSIX: 2736270631Sjfv p->num_msix_vectors = number; 2737270631Sjfv break; 2738270631Sjfv case I40E_DEV_FUNC_CAP_MSIX_VF: 2739270631Sjfv p->num_msix_vectors_vf = number; 2740270631Sjfv break; 2741270631Sjfv case I40E_DEV_FUNC_CAP_MFP_MODE_1: 2742270631Sjfv if (number == 1) 2743270631Sjfv p->mfp_mode_1 = TRUE; 2744270631Sjfv break; 2745270631Sjfv case I40E_DEV_FUNC_CAP_CEM: 2746270631Sjfv if (number == 1) 2747270631Sjfv p->mgmt_cem = TRUE; 2748270631Sjfv break; 2749270631Sjfv case I40E_DEV_FUNC_CAP_IWARP: 2750270631Sjfv if (number == 1) 2751270631Sjfv p->iwarp = TRUE; 2752270631Sjfv break; 2753270631Sjfv case I40E_DEV_FUNC_CAP_LED: 2754270631Sjfv if (phys_id < I40E_HW_CAP_MAX_GPIO) 2755270631Sjfv p->led[phys_id] = TRUE; 2756270631Sjfv break; 2757270631Sjfv case I40E_DEV_FUNC_CAP_SDP: 2758270631Sjfv if (phys_id < I40E_HW_CAP_MAX_GPIO) 2759270631Sjfv p->sdp[phys_id] = TRUE; 2760270631Sjfv break; 2761270631Sjfv case I40E_DEV_FUNC_CAP_MDIO: 2762270631Sjfv if (number == 1) { 2763270631Sjfv p->mdio_port_num = phys_id; 2764270631Sjfv p->mdio_port_mode = logical_id; 2765270631Sjfv } 2766270631Sjfv break; 2767270631Sjfv case I40E_DEV_FUNC_CAP_IEEE_1588: 2768270631Sjfv if (number == 1) 2769270631Sjfv p->ieee_1588 = TRUE; 2770270631Sjfv break; 2771270631Sjfv case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR: 2772270631Sjfv p->fd = TRUE; 2773270631Sjfv p->fd_filters_guaranteed = number; 2774270631Sjfv p->fd_filters_best_effort = logical_id; 2775270631Sjfv break; 2776270631Sjfv default: 2777270631Sjfv break; 2778270631Sjfv } 2779270631Sjfv } 2780270631Sjfv 2781270631Sjfv /* Software override ensuring FCoE is disabled if npar or mfp 2782270631Sjfv * mode because it is not supported in these modes. 2783270631Sjfv */ 2784270631Sjfv if (p->npar_enable || p->mfp_mode_1) 2785270631Sjfv p->fcoe = FALSE; 2786270631Sjfv 2787270631Sjfv /* additional HW specific goodies that might 2788270631Sjfv * someday be HW version specific 2789270631Sjfv */ 2790270631Sjfv p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 2791270631Sjfv} 2792270631Sjfv 2793270631Sjfv/** 2794270631Sjfv * i40e_aq_discover_capabilities 2795270631Sjfv * @hw: pointer to the hw struct 2796270631Sjfv * @buff: a virtual buffer to hold the capabilities 2797270631Sjfv * @buff_size: Size of the virtual buffer 2798270631Sjfv * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 2799270631Sjfv * @list_type_opc: capabilities type to discover - pass in the command opcode 2800270631Sjfv * @cmd_details: pointer to command details structure or NULL 2801270631Sjfv * 2802270631Sjfv * Get the device capabilities descriptions from the firmware 2803270631Sjfv **/ 2804270631Sjfvenum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 2805270631Sjfv void *buff, u16 buff_size, u16 *data_size, 2806270631Sjfv enum i40e_admin_queue_opc list_type_opc, 2807270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2808270631Sjfv{ 2809270631Sjfv struct i40e_aqc_list_capabilites *cmd; 2810270631Sjfv struct i40e_aq_desc desc; 2811270631Sjfv enum i40e_status_code status = I40E_SUCCESS; 2812270631Sjfv 2813270631Sjfv cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 2814270631Sjfv 2815270631Sjfv if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 2816270631Sjfv list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 2817270631Sjfv status = I40E_ERR_PARAM; 2818270631Sjfv goto exit; 2819270631Sjfv } 2820270631Sjfv 2821270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 2822270631Sjfv 2823270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2824270631Sjfv if (buff_size > I40E_AQ_LARGE_BUF) 2825270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2826270631Sjfv 2827270631Sjfv status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2828270631Sjfv *data_size = LE16_TO_CPU(desc.datalen); 2829270631Sjfv 2830270631Sjfv if (status) 2831270631Sjfv goto exit; 2832270631Sjfv 2833270631Sjfv i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 2834270631Sjfv list_type_opc); 2835270631Sjfv 2836270631Sjfvexit: 2837270631Sjfv return status; 2838270631Sjfv} 2839270631Sjfv 2840270631Sjfv/** 2841270631Sjfv * i40e_aq_update_nvm 2842270631Sjfv * @hw: pointer to the hw struct 2843270631Sjfv * @module_pointer: module pointer location in words from the NVM beginning 2844270631Sjfv * @offset: byte offset from the module beginning 2845270631Sjfv * @length: length of the section to be written (in bytes from the offset) 2846270631Sjfv * @data: command buffer (size [bytes] = length) 2847270631Sjfv * @last_command: tells if this is the last command in a series 2848270631Sjfv * @cmd_details: pointer to command details structure or NULL 2849270631Sjfv * 2850270631Sjfv * Update the NVM using the admin queue commands 2851270631Sjfv **/ 2852270631Sjfvenum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 2853270631Sjfv u32 offset, u16 length, void *data, 2854270631Sjfv bool last_command, 2855270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2856270631Sjfv{ 2857270631Sjfv struct i40e_aq_desc desc; 2858270631Sjfv struct i40e_aqc_nvm_update *cmd = 2859270631Sjfv (struct i40e_aqc_nvm_update *)&desc.params.raw; 2860270631Sjfv enum i40e_status_code status; 2861270631Sjfv 2862270631Sjfv DEBUGFUNC("i40e_aq_update_nvm"); 2863270631Sjfv 2864270631Sjfv /* In offset the highest byte must be zeroed. */ 2865270631Sjfv if (offset & 0xFF000000) { 2866270631Sjfv status = I40E_ERR_PARAM; 2867270631Sjfv goto i40e_aq_update_nvm_exit; 2868270631Sjfv } 2869270631Sjfv 2870270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 2871270631Sjfv 2872270631Sjfv /* If this is the last command in a series, set the proper flag. */ 2873270631Sjfv if (last_command) 2874270631Sjfv cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2875270631Sjfv cmd->module_pointer = module_pointer; 2876270631Sjfv cmd->offset = CPU_TO_LE32(offset); 2877270631Sjfv cmd->length = CPU_TO_LE16(length); 2878270631Sjfv 2879270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2880270631Sjfv if (length > I40E_AQ_LARGE_BUF) 2881270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2882270631Sjfv 2883270631Sjfv status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2884270631Sjfv 2885270631Sjfvi40e_aq_update_nvm_exit: 2886270631Sjfv return status; 2887270631Sjfv} 2888270631Sjfv 2889270631Sjfv/** 2890270631Sjfv * i40e_aq_get_lldp_mib 2891270631Sjfv * @hw: pointer to the hw struct 2892270631Sjfv * @bridge_type: type of bridge requested 2893270631Sjfv * @mib_type: Local, Remote or both Local and Remote MIBs 2894270631Sjfv * @buff: pointer to a user supplied buffer to store the MIB block 2895270631Sjfv * @buff_size: size of the buffer (in bytes) 2896270631Sjfv * @local_len : length of the returned Local LLDP MIB 2897270631Sjfv * @remote_len: length of the returned Remote LLDP MIB 2898270631Sjfv * @cmd_details: pointer to command details structure or NULL 2899270631Sjfv * 2900270631Sjfv * Requests the complete LLDP MIB (entire packet). 2901270631Sjfv **/ 2902270631Sjfvenum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 2903270631Sjfv u8 mib_type, void *buff, u16 buff_size, 2904270631Sjfv u16 *local_len, u16 *remote_len, 2905270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2906270631Sjfv{ 2907270631Sjfv struct i40e_aq_desc desc; 2908270631Sjfv struct i40e_aqc_lldp_get_mib *cmd = 2909270631Sjfv (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2910270631Sjfv struct i40e_aqc_lldp_get_mib *resp = 2911270631Sjfv (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2912270631Sjfv enum i40e_status_code status; 2913270631Sjfv 2914270631Sjfv if (buff_size == 0 || !buff) 2915270631Sjfv return I40E_ERR_PARAM; 2916270631Sjfv 2917270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 2918270631Sjfv /* Indirect Command */ 2919270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2920270631Sjfv 2921270631Sjfv cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 2922270631Sjfv cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 2923270631Sjfv I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 2924270631Sjfv 2925270631Sjfv desc.datalen = CPU_TO_LE16(buff_size); 2926270631Sjfv 2927270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2928270631Sjfv if (buff_size > I40E_AQ_LARGE_BUF) 2929270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2930270631Sjfv 2931270631Sjfv status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2932270631Sjfv if (!status) { 2933270631Sjfv if (local_len != NULL) 2934270631Sjfv *local_len = LE16_TO_CPU(resp->local_len); 2935270631Sjfv if (remote_len != NULL) 2936270631Sjfv *remote_len = LE16_TO_CPU(resp->remote_len); 2937270631Sjfv } 2938270631Sjfv 2939270631Sjfv return status; 2940270631Sjfv} 2941270631Sjfv 2942270631Sjfv/** 2943270631Sjfv * i40e_aq_cfg_lldp_mib_change_event 2944270631Sjfv * @hw: pointer to the hw struct 2945270631Sjfv * @enable_update: Enable or Disable event posting 2946270631Sjfv * @cmd_details: pointer to command details structure or NULL 2947270631Sjfv * 2948270631Sjfv * Enable or Disable posting of an event on ARQ when LLDP MIB 2949270631Sjfv * associated with the interface changes 2950270631Sjfv **/ 2951270631Sjfvenum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 2952270631Sjfv bool enable_update, 2953270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2954270631Sjfv{ 2955270631Sjfv struct i40e_aq_desc desc; 2956270631Sjfv struct i40e_aqc_lldp_update_mib *cmd = 2957270631Sjfv (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 2958270631Sjfv enum i40e_status_code status; 2959270631Sjfv 2960270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 2961270631Sjfv 2962270631Sjfv if (!enable_update) 2963270631Sjfv cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 2964270631Sjfv 2965270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2966270631Sjfv 2967270631Sjfv return status; 2968270631Sjfv} 2969270631Sjfv 2970270631Sjfv/** 2971270631Sjfv * i40e_aq_add_lldp_tlv 2972270631Sjfv * @hw: pointer to the hw struct 2973270631Sjfv * @bridge_type: type of bridge 2974270631Sjfv * @buff: buffer with TLV to add 2975270631Sjfv * @buff_size: length of the buffer 2976270631Sjfv * @tlv_len: length of the TLV to be added 2977270631Sjfv * @mib_len: length of the LLDP MIB returned in response 2978270631Sjfv * @cmd_details: pointer to command details structure or NULL 2979270631Sjfv * 2980270631Sjfv * Add the specified TLV to LLDP Local MIB for the given bridge type, 2981270631Sjfv * it is responsibility of the caller to make sure that the TLV is not 2982270631Sjfv * already present in the LLDPDU. 2983270631Sjfv * In return firmware will write the complete LLDP MIB with the newly 2984270631Sjfv * added TLV in the response buffer. 2985270631Sjfv **/ 2986270631Sjfvenum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 2987270631Sjfv void *buff, u16 buff_size, u16 tlv_len, 2988270631Sjfv u16 *mib_len, 2989270631Sjfv struct i40e_asq_cmd_details *cmd_details) 2990270631Sjfv{ 2991270631Sjfv struct i40e_aq_desc desc; 2992270631Sjfv struct i40e_aqc_lldp_add_tlv *cmd = 2993270631Sjfv (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 2994270631Sjfv enum i40e_status_code status; 2995270631Sjfv 2996270631Sjfv if (buff_size == 0 || !buff || tlv_len == 0) 2997270631Sjfv return I40E_ERR_PARAM; 2998270631Sjfv 2999270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 3000270631Sjfv 3001270631Sjfv /* Indirect Command */ 3002270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3003270631Sjfv if (buff_size > I40E_AQ_LARGE_BUF) 3004270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3005270631Sjfv desc.datalen = CPU_TO_LE16(buff_size); 3006270631Sjfv 3007270631Sjfv cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3008270631Sjfv I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3009270631Sjfv cmd->len = CPU_TO_LE16(tlv_len); 3010270631Sjfv 3011270631Sjfv status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3012270631Sjfv if (!status) { 3013270631Sjfv if (mib_len != NULL) 3014270631Sjfv *mib_len = LE16_TO_CPU(desc.datalen); 3015270631Sjfv } 3016270631Sjfv 3017270631Sjfv return status; 3018270631Sjfv} 3019270631Sjfv 3020270631Sjfv/** 3021270631Sjfv * i40e_aq_update_lldp_tlv 3022270631Sjfv * @hw: pointer to the hw struct 3023270631Sjfv * @bridge_type: type of bridge 3024270631Sjfv * @buff: buffer with TLV to update 3025270631Sjfv * @buff_size: size of the buffer holding original and updated TLVs 3026270631Sjfv * @old_len: Length of the Original TLV 3027270631Sjfv * @new_len: Length of the Updated TLV 3028270631Sjfv * @offset: offset of the updated TLV in the buff 3029270631Sjfv * @mib_len: length of the returned LLDP MIB 3030270631Sjfv * @cmd_details: pointer to command details structure or NULL 3031270631Sjfv * 3032270631Sjfv * Update the specified TLV to the LLDP Local MIB for the given bridge type. 3033270631Sjfv * Firmware will place the complete LLDP MIB in response buffer with the 3034270631Sjfv * updated TLV. 3035270631Sjfv **/ 3036270631Sjfvenum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 3037270631Sjfv u8 bridge_type, void *buff, u16 buff_size, 3038270631Sjfv u16 old_len, u16 new_len, u16 offset, 3039270631Sjfv u16 *mib_len, 3040270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3041270631Sjfv{ 3042270631Sjfv struct i40e_aq_desc desc; 3043270631Sjfv struct i40e_aqc_lldp_update_tlv *cmd = 3044270631Sjfv (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 3045270631Sjfv enum i40e_status_code status; 3046270631Sjfv 3047270631Sjfv if (buff_size == 0 || !buff || offset == 0 || 3048270631Sjfv old_len == 0 || new_len == 0) 3049270631Sjfv return I40E_ERR_PARAM; 3050270631Sjfv 3051270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 3052270631Sjfv 3053270631Sjfv /* Indirect Command */ 3054270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3055270631Sjfv if (buff_size > I40E_AQ_LARGE_BUF) 3056270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3057270631Sjfv desc.datalen = CPU_TO_LE16(buff_size); 3058270631Sjfv 3059270631Sjfv cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3060270631Sjfv I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3061270631Sjfv cmd->old_len = CPU_TO_LE16(old_len); 3062270631Sjfv cmd->new_offset = CPU_TO_LE16(offset); 3063270631Sjfv cmd->new_len = CPU_TO_LE16(new_len); 3064270631Sjfv 3065270631Sjfv status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3066270631Sjfv if (!status) { 3067270631Sjfv if (mib_len != NULL) 3068270631Sjfv *mib_len = LE16_TO_CPU(desc.datalen); 3069270631Sjfv } 3070270631Sjfv 3071270631Sjfv return status; 3072270631Sjfv} 3073270631Sjfv 3074270631Sjfv/** 3075270631Sjfv * i40e_aq_delete_lldp_tlv 3076270631Sjfv * @hw: pointer to the hw struct 3077270631Sjfv * @bridge_type: type of bridge 3078270631Sjfv * @buff: pointer to a user supplied buffer that has the TLV 3079270631Sjfv * @buff_size: length of the buffer 3080270631Sjfv * @tlv_len: length of the TLV to be deleted 3081270631Sjfv * @mib_len: length of the returned LLDP MIB 3082270631Sjfv * @cmd_details: pointer to command details structure or NULL 3083270631Sjfv * 3084270631Sjfv * Delete the specified TLV from LLDP Local MIB for the given bridge type. 3085270631Sjfv * The firmware places the entire LLDP MIB in the response buffer. 3086270631Sjfv **/ 3087270631Sjfvenum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 3088270631Sjfv u8 bridge_type, void *buff, u16 buff_size, 3089270631Sjfv u16 tlv_len, u16 *mib_len, 3090270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3091270631Sjfv{ 3092270631Sjfv struct i40e_aq_desc desc; 3093270631Sjfv struct i40e_aqc_lldp_add_tlv *cmd = 3094270631Sjfv (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 3095270631Sjfv enum i40e_status_code status; 3096270631Sjfv 3097270631Sjfv if (buff_size == 0 || !buff) 3098270631Sjfv return I40E_ERR_PARAM; 3099270631Sjfv 3100270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 3101270631Sjfv 3102270631Sjfv /* Indirect Command */ 3103270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3104270631Sjfv if (buff_size > I40E_AQ_LARGE_BUF) 3105270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3106270631Sjfv desc.datalen = CPU_TO_LE16(buff_size); 3107270631Sjfv cmd->len = CPU_TO_LE16(tlv_len); 3108270631Sjfv cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3109270631Sjfv I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3110270631Sjfv 3111270631Sjfv status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3112270631Sjfv if (!status) { 3113270631Sjfv if (mib_len != NULL) 3114270631Sjfv *mib_len = LE16_TO_CPU(desc.datalen); 3115270631Sjfv } 3116270631Sjfv 3117270631Sjfv return status; 3118270631Sjfv} 3119270631Sjfv 3120270631Sjfv/** 3121270631Sjfv * i40e_aq_stop_lldp 3122270631Sjfv * @hw: pointer to the hw struct 3123270631Sjfv * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3124270631Sjfv * @cmd_details: pointer to command details structure or NULL 3125270631Sjfv * 3126270631Sjfv * Stop or Shutdown the embedded LLDP Agent 3127270631Sjfv **/ 3128270631Sjfvenum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3129270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3130270631Sjfv{ 3131270631Sjfv struct i40e_aq_desc desc; 3132270631Sjfv struct i40e_aqc_lldp_stop *cmd = 3133270631Sjfv (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3134270631Sjfv enum i40e_status_code status; 3135270631Sjfv 3136270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3137270631Sjfv 3138270631Sjfv if (shutdown_agent) 3139270631Sjfv cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3140270631Sjfv 3141270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3142270631Sjfv 3143270631Sjfv return status; 3144270631Sjfv} 3145270631Sjfv 3146270631Sjfv/** 3147270631Sjfv * i40e_aq_start_lldp 3148270631Sjfv * @hw: pointer to the hw struct 3149270631Sjfv * @cmd_details: pointer to command details structure or NULL 3150270631Sjfv * 3151270631Sjfv * Start the embedded LLDP Agent on all ports. 3152270631Sjfv **/ 3153270631Sjfvenum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 3154270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3155270631Sjfv{ 3156270631Sjfv struct i40e_aq_desc desc; 3157270631Sjfv struct i40e_aqc_lldp_start *cmd = 3158270631Sjfv (struct i40e_aqc_lldp_start *)&desc.params.raw; 3159270631Sjfv enum i40e_status_code status; 3160270631Sjfv 3161270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3162270631Sjfv 3163270631Sjfv cmd->command = I40E_AQ_LLDP_AGENT_START; 3164270631Sjfv 3165270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3166270631Sjfv 3167270631Sjfv return status; 3168270631Sjfv} 3169270631Sjfv 3170270631Sjfv/** 3171270631Sjfv * i40e_aq_add_udp_tunnel 3172270631Sjfv * @hw: pointer to the hw struct 3173270631Sjfv * @udp_port: the UDP port to add 3174270631Sjfv * @header_len: length of the tunneling header length in DWords 3175270631Sjfv * @protocol_index: protocol index type 3176270631Sjfv * @filter_index: pointer to filter index 3177270631Sjfv * @cmd_details: pointer to command details structure or NULL 3178270631Sjfv **/ 3179270631Sjfvenum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3180270631Sjfv u16 udp_port, u8 protocol_index, 3181270631Sjfv u8 *filter_index, 3182270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3183270631Sjfv{ 3184270631Sjfv struct i40e_aq_desc desc; 3185270631Sjfv struct i40e_aqc_add_udp_tunnel *cmd = 3186270631Sjfv (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3187270631Sjfv struct i40e_aqc_del_udp_tunnel_completion *resp = 3188270631Sjfv (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3189270631Sjfv enum i40e_status_code status; 3190270631Sjfv 3191270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3192270631Sjfv 3193270631Sjfv cmd->udp_port = CPU_TO_LE16(udp_port); 3194270631Sjfv cmd->protocol_type = protocol_index; 3195270631Sjfv 3196270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3197270631Sjfv 3198270631Sjfv if (!status) 3199270631Sjfv *filter_index = resp->index; 3200270631Sjfv 3201270631Sjfv return status; 3202270631Sjfv} 3203270631Sjfv 3204270631Sjfv/** 3205270631Sjfv * i40e_aq_del_udp_tunnel 3206270631Sjfv * @hw: pointer to the hw struct 3207270631Sjfv * @index: filter index 3208270631Sjfv * @cmd_details: pointer to command details structure or NULL 3209270631Sjfv **/ 3210270631Sjfvenum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3211270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3212270631Sjfv{ 3213270631Sjfv struct i40e_aq_desc desc; 3214270631Sjfv struct i40e_aqc_remove_udp_tunnel *cmd = 3215270631Sjfv (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3216270631Sjfv enum i40e_status_code status; 3217270631Sjfv 3218270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3219270631Sjfv 3220270631Sjfv cmd->index = index; 3221270631Sjfv 3222270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3223270631Sjfv 3224270631Sjfv return status; 3225270631Sjfv} 3226270631Sjfv 3227270631Sjfv/** 3228270631Sjfv * i40e_aq_get_switch_resource_alloc (0x0204) 3229270631Sjfv * @hw: pointer to the hw struct 3230270631Sjfv * @num_entries: pointer to u8 to store the number of resource entries returned 3231270631Sjfv * @buf: pointer to a user supplied buffer. This buffer must be large enough 3232270631Sjfv * to store the resource information for all resource types. Each 3233270631Sjfv * resource type is a i40e_aqc_switch_resource_alloc_data structure. 3234270631Sjfv * @count: size, in bytes, of the buffer provided 3235270631Sjfv * @cmd_details: pointer to command details structure or NULL 3236270631Sjfv * 3237270631Sjfv * Query the resources allocated to a function. 3238270631Sjfv **/ 3239270631Sjfvenum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 3240270631Sjfv u8 *num_entries, 3241270631Sjfv struct i40e_aqc_switch_resource_alloc_element_resp *buf, 3242270631Sjfv u16 count, 3243270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3244270631Sjfv{ 3245270631Sjfv struct i40e_aq_desc desc; 3246270631Sjfv struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 3247270631Sjfv (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 3248270631Sjfv enum i40e_status_code status; 3249270631Sjfv u16 length = count 3250270631Sjfv * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp); 3251270631Sjfv 3252270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 3253270631Sjfv i40e_aqc_opc_get_switch_resource_alloc); 3254270631Sjfv 3255270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3256270631Sjfv if (length > I40E_AQ_LARGE_BUF) 3257270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3258270631Sjfv 3259270631Sjfv status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 3260270631Sjfv 3261270631Sjfv if (!status) 3262270631Sjfv *num_entries = cmd_resp->num_entries; 3263270631Sjfv 3264270631Sjfv return status; 3265270631Sjfv} 3266270631Sjfv 3267270631Sjfv/** 3268270631Sjfv * i40e_aq_delete_element - Delete switch element 3269270631Sjfv * @hw: pointer to the hw struct 3270270631Sjfv * @seid: the SEID to delete from the switch 3271270631Sjfv * @cmd_details: pointer to command details structure or NULL 3272270631Sjfv * 3273270631Sjfv * This deletes a switch element from the switch. 3274270631Sjfv **/ 3275270631Sjfvenum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3276270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3277270631Sjfv{ 3278270631Sjfv struct i40e_aq_desc desc; 3279270631Sjfv struct i40e_aqc_switch_seid *cmd = 3280270631Sjfv (struct i40e_aqc_switch_seid *)&desc.params.raw; 3281270631Sjfv enum i40e_status_code status; 3282270631Sjfv 3283270631Sjfv if (seid == 0) 3284270631Sjfv return I40E_ERR_PARAM; 3285270631Sjfv 3286270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3287270631Sjfv 3288270631Sjfv cmd->seid = CPU_TO_LE16(seid); 3289270631Sjfv 3290270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3291270631Sjfv 3292270631Sjfv return status; 3293270631Sjfv} 3294270631Sjfv 3295270631Sjfv/** 3296270631Sjfv * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port 3297270631Sjfv * @hw: pointer to the hw struct 3298270631Sjfv * @flags: component flags 3299270631Sjfv * @mac_seid: uplink seid (MAC SEID) 3300270631Sjfv * @vsi_seid: connected vsi seid 3301270631Sjfv * @ret_seid: seid of create pv component 3302270631Sjfv * 3303270631Sjfv * This instantiates an i40e port virtualizer with specified flags. 3304270631Sjfv * Depending on specified flags the port virtualizer can act as a 3305270631Sjfv * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 3306270631Sjfv */ 3307270631Sjfvenum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 3308270631Sjfv u16 mac_seid, u16 vsi_seid, 3309270631Sjfv u16 *ret_seid) 3310270631Sjfv{ 3311270631Sjfv struct i40e_aq_desc desc; 3312270631Sjfv struct i40e_aqc_add_update_pv *cmd = 3313270631Sjfv (struct i40e_aqc_add_update_pv *)&desc.params.raw; 3314270631Sjfv struct i40e_aqc_add_update_pv_completion *resp = 3315270631Sjfv (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 3316270631Sjfv enum i40e_status_code status; 3317270631Sjfv 3318270631Sjfv if (vsi_seid == 0) 3319270631Sjfv return I40E_ERR_PARAM; 3320270631Sjfv 3321270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 3322270631Sjfv cmd->command_flags = CPU_TO_LE16(flags); 3323270631Sjfv cmd->uplink_seid = CPU_TO_LE16(mac_seid); 3324270631Sjfv cmd->connected_seid = CPU_TO_LE16(vsi_seid); 3325270631Sjfv 3326270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3327270631Sjfv if (!status && ret_seid) 3328270631Sjfv *ret_seid = LE16_TO_CPU(resp->pv_seid); 3329270631Sjfv 3330270631Sjfv return status; 3331270631Sjfv} 3332270631Sjfv 3333270631Sjfv/** 3334270631Sjfv * i40e_aq_add_tag - Add an S/E-tag 3335270631Sjfv * @hw: pointer to the hw struct 3336270631Sjfv * @direct_to_queue: should s-tag direct flow to a specific queue 3337270631Sjfv * @vsi_seid: VSI SEID to use this tag 3338270631Sjfv * @tag: value of the tag 3339270631Sjfv * @queue_num: queue number, only valid is direct_to_queue is TRUE 3340270631Sjfv * @tags_used: return value, number of tags in use by this PF 3341270631Sjfv * @tags_free: return value, number of unallocated tags 3342270631Sjfv * @cmd_details: pointer to command details structure or NULL 3343270631Sjfv * 3344270631Sjfv * This associates an S- or E-tag to a VSI in the switch complex. It returns 3345270631Sjfv * the number of tags allocated by the PF, and the number of unallocated 3346270631Sjfv * tags available. 3347270631Sjfv **/ 3348270631Sjfvenum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 3349270631Sjfv u16 vsi_seid, u16 tag, u16 queue_num, 3350270631Sjfv u16 *tags_used, u16 *tags_free, 3351270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3352270631Sjfv{ 3353270631Sjfv struct i40e_aq_desc desc; 3354270631Sjfv struct i40e_aqc_add_tag *cmd = 3355270631Sjfv (struct i40e_aqc_add_tag *)&desc.params.raw; 3356270631Sjfv struct i40e_aqc_add_remove_tag_completion *resp = 3357270631Sjfv (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 3358270631Sjfv enum i40e_status_code status; 3359270631Sjfv 3360270631Sjfv if (vsi_seid == 0) 3361270631Sjfv return I40E_ERR_PARAM; 3362270631Sjfv 3363270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 3364270631Sjfv 3365270631Sjfv cmd->seid = CPU_TO_LE16(vsi_seid); 3366270631Sjfv cmd->tag = CPU_TO_LE16(tag); 3367270631Sjfv if (direct_to_queue) { 3368270631Sjfv cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 3369270631Sjfv cmd->queue_number = CPU_TO_LE16(queue_num); 3370270631Sjfv } 3371270631Sjfv 3372270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3373270631Sjfv 3374270631Sjfv if (!status) { 3375270631Sjfv if (tags_used != NULL) 3376270631Sjfv *tags_used = LE16_TO_CPU(resp->tags_used); 3377270631Sjfv if (tags_free != NULL) 3378270631Sjfv *tags_free = LE16_TO_CPU(resp->tags_free); 3379270631Sjfv } 3380270631Sjfv 3381270631Sjfv return status; 3382270631Sjfv} 3383270631Sjfv 3384270631Sjfv/** 3385270631Sjfv * i40e_aq_remove_tag - Remove an S- or E-tag 3386270631Sjfv * @hw: pointer to the hw struct 3387270631Sjfv * @vsi_seid: VSI SEID this tag is associated with 3388270631Sjfv * @tag: value of the S-tag to delete 3389270631Sjfv * @tags_used: return value, number of tags in use by this PF 3390270631Sjfv * @tags_free: return value, number of unallocated tags 3391270631Sjfv * @cmd_details: pointer to command details structure or NULL 3392270631Sjfv * 3393270631Sjfv * This deletes an S- or E-tag from a VSI in the switch complex. It returns 3394270631Sjfv * the number of tags allocated by the PF, and the number of unallocated 3395270631Sjfv * tags available. 3396270631Sjfv **/ 3397270631Sjfvenum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 3398270631Sjfv u16 tag, u16 *tags_used, u16 *tags_free, 3399270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3400270631Sjfv{ 3401270631Sjfv struct i40e_aq_desc desc; 3402270631Sjfv struct i40e_aqc_remove_tag *cmd = 3403270631Sjfv (struct i40e_aqc_remove_tag *)&desc.params.raw; 3404270631Sjfv struct i40e_aqc_add_remove_tag_completion *resp = 3405270631Sjfv (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 3406270631Sjfv enum i40e_status_code status; 3407270631Sjfv 3408270631Sjfv if (vsi_seid == 0) 3409270631Sjfv return I40E_ERR_PARAM; 3410270631Sjfv 3411270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 3412270631Sjfv 3413270631Sjfv cmd->seid = CPU_TO_LE16(vsi_seid); 3414270631Sjfv cmd->tag = CPU_TO_LE16(tag); 3415270631Sjfv 3416270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3417270631Sjfv 3418270631Sjfv if (!status) { 3419270631Sjfv if (tags_used != NULL) 3420270631Sjfv *tags_used = LE16_TO_CPU(resp->tags_used); 3421270631Sjfv if (tags_free != NULL) 3422270631Sjfv *tags_free = LE16_TO_CPU(resp->tags_free); 3423270631Sjfv } 3424270631Sjfv 3425270631Sjfv return status; 3426270631Sjfv} 3427270631Sjfv 3428270631Sjfv/** 3429270631Sjfv * i40e_aq_add_mcast_etag - Add a multicast E-tag 3430270631Sjfv * @hw: pointer to the hw struct 3431270631Sjfv * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 3432270631Sjfv * @etag: value of E-tag to add 3433270631Sjfv * @num_tags_in_buf: number of unicast E-tags in indirect buffer 3434270631Sjfv * @buf: address of indirect buffer 3435270631Sjfv * @tags_used: return value, number of E-tags in use by this port 3436270631Sjfv * @tags_free: return value, number of unallocated M-tags 3437270631Sjfv * @cmd_details: pointer to command details structure or NULL 3438270631Sjfv * 3439270631Sjfv * This associates a multicast E-tag to a port virtualizer. It will return 3440270631Sjfv * the number of tags allocated by the PF, and the number of unallocated 3441270631Sjfv * tags available. 3442270631Sjfv * 3443270631Sjfv * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 3444270631Sjfv * num_tags_in_buf long. 3445270631Sjfv **/ 3446270631Sjfvenum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 3447270631Sjfv u16 etag, u8 num_tags_in_buf, void *buf, 3448270631Sjfv u16 *tags_used, u16 *tags_free, 3449270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3450270631Sjfv{ 3451270631Sjfv struct i40e_aq_desc desc; 3452270631Sjfv struct i40e_aqc_add_remove_mcast_etag *cmd = 3453270631Sjfv (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 3454270631Sjfv struct i40e_aqc_add_remove_mcast_etag_completion *resp = 3455270631Sjfv (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 3456270631Sjfv enum i40e_status_code status; 3457270631Sjfv u16 length = sizeof(u16) * num_tags_in_buf; 3458270631Sjfv 3459270631Sjfv if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 3460270631Sjfv return I40E_ERR_PARAM; 3461270631Sjfv 3462270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 3463270631Sjfv i40e_aqc_opc_add_multicast_etag); 3464270631Sjfv 3465270631Sjfv cmd->pv_seid = CPU_TO_LE16(pv_seid); 3466270631Sjfv cmd->etag = CPU_TO_LE16(etag); 3467270631Sjfv cmd->num_unicast_etags = num_tags_in_buf; 3468270631Sjfv 3469270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3470270631Sjfv if (length > I40E_AQ_LARGE_BUF) 3471270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3472270631Sjfv 3473270631Sjfv status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 3474270631Sjfv 3475270631Sjfv if (!status) { 3476270631Sjfv if (tags_used != NULL) 3477270631Sjfv *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 3478270631Sjfv if (tags_free != NULL) 3479270631Sjfv *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 3480270631Sjfv } 3481270631Sjfv 3482270631Sjfv return status; 3483270631Sjfv} 3484270631Sjfv 3485270631Sjfv/** 3486270631Sjfv * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 3487270631Sjfv * @hw: pointer to the hw struct 3488270631Sjfv * @pv_seid: Port Virtualizer SEID this M-tag is associated with 3489270631Sjfv * @etag: value of the E-tag to remove 3490270631Sjfv * @tags_used: return value, number of tags in use by this port 3491270631Sjfv * @tags_free: return value, number of unallocated tags 3492270631Sjfv * @cmd_details: pointer to command details structure or NULL 3493270631Sjfv * 3494270631Sjfv * This deletes an E-tag from the port virtualizer. It will return 3495270631Sjfv * the number of tags allocated by the port, and the number of unallocated 3496270631Sjfv * tags available. 3497270631Sjfv **/ 3498270631Sjfvenum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 3499270631Sjfv u16 etag, u16 *tags_used, u16 *tags_free, 3500270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3501270631Sjfv{ 3502270631Sjfv struct i40e_aq_desc desc; 3503270631Sjfv struct i40e_aqc_add_remove_mcast_etag *cmd = 3504270631Sjfv (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 3505270631Sjfv struct i40e_aqc_add_remove_mcast_etag_completion *resp = 3506270631Sjfv (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 3507270631Sjfv enum i40e_status_code status; 3508270631Sjfv 3509270631Sjfv 3510270631Sjfv if (pv_seid == 0) 3511270631Sjfv return I40E_ERR_PARAM; 3512270631Sjfv 3513270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 3514270631Sjfv i40e_aqc_opc_remove_multicast_etag); 3515270631Sjfv 3516270631Sjfv cmd->pv_seid = CPU_TO_LE16(pv_seid); 3517270631Sjfv cmd->etag = CPU_TO_LE16(etag); 3518270631Sjfv 3519270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3520270631Sjfv 3521270631Sjfv if (!status) { 3522270631Sjfv if (tags_used != NULL) 3523270631Sjfv *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 3524270631Sjfv if (tags_free != NULL) 3525270631Sjfv *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 3526270631Sjfv } 3527270631Sjfv 3528270631Sjfv return status; 3529270631Sjfv} 3530270631Sjfv 3531270631Sjfv/** 3532270631Sjfv * i40e_aq_update_tag - Update an S/E-tag 3533270631Sjfv * @hw: pointer to the hw struct 3534270631Sjfv * @vsi_seid: VSI SEID using this S-tag 3535270631Sjfv * @old_tag: old tag value 3536270631Sjfv * @new_tag: new tag value 3537270631Sjfv * @tags_used: return value, number of tags in use by this PF 3538270631Sjfv * @tags_free: return value, number of unallocated tags 3539270631Sjfv * @cmd_details: pointer to command details structure or NULL 3540270631Sjfv * 3541270631Sjfv * This updates the value of the tag currently attached to this VSI 3542270631Sjfv * in the switch complex. It will return the number of tags allocated 3543270631Sjfv * by the PF, and the number of unallocated tags available. 3544270631Sjfv **/ 3545270631Sjfvenum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 3546270631Sjfv u16 old_tag, u16 new_tag, u16 *tags_used, 3547270631Sjfv u16 *tags_free, 3548270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3549270631Sjfv{ 3550270631Sjfv struct i40e_aq_desc desc; 3551270631Sjfv struct i40e_aqc_update_tag *cmd = 3552270631Sjfv (struct i40e_aqc_update_tag *)&desc.params.raw; 3553270631Sjfv struct i40e_aqc_update_tag_completion *resp = 3554270631Sjfv (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 3555270631Sjfv enum i40e_status_code status; 3556270631Sjfv 3557270631Sjfv if (vsi_seid == 0) 3558270631Sjfv return I40E_ERR_PARAM; 3559270631Sjfv 3560270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 3561270631Sjfv 3562270631Sjfv cmd->seid = CPU_TO_LE16(vsi_seid); 3563270631Sjfv cmd->old_tag = CPU_TO_LE16(old_tag); 3564270631Sjfv cmd->new_tag = CPU_TO_LE16(new_tag); 3565270631Sjfv 3566270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3567270631Sjfv 3568270631Sjfv if (!status) { 3569270631Sjfv if (tags_used != NULL) 3570270631Sjfv *tags_used = LE16_TO_CPU(resp->tags_used); 3571270631Sjfv if (tags_free != NULL) 3572270631Sjfv *tags_free = LE16_TO_CPU(resp->tags_free); 3573270631Sjfv } 3574270631Sjfv 3575270631Sjfv return status; 3576270631Sjfv} 3577270631Sjfv 3578270631Sjfv/** 3579270631Sjfv * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 3580270631Sjfv * @hw: pointer to the hw struct 3581270631Sjfv * @tcmap: TC map for request/release any ignore PFC condition 3582270631Sjfv * @request: request or release ignore PFC condition 3583270631Sjfv * @tcmap_ret: return TCs for which PFC is currently ignored 3584270631Sjfv * @cmd_details: pointer to command details structure or NULL 3585270631Sjfv * 3586270631Sjfv * This sends out request/release to ignore PFC condition for a TC. 3587270631Sjfv * It will return the TCs for which PFC is currently ignored. 3588270631Sjfv **/ 3589270631Sjfvenum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 3590270631Sjfv bool request, u8 *tcmap_ret, 3591270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3592270631Sjfv{ 3593270631Sjfv struct i40e_aq_desc desc; 3594270631Sjfv struct i40e_aqc_pfc_ignore *cmd_resp = 3595270631Sjfv (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 3596270631Sjfv enum i40e_status_code status; 3597270631Sjfv 3598270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 3599270631Sjfv 3600270631Sjfv if (request) 3601270631Sjfv cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 3602270631Sjfv 3603270631Sjfv cmd_resp->tc_bitmap = tcmap; 3604270631Sjfv 3605270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3606270631Sjfv 3607270631Sjfv if (!status) { 3608270631Sjfv if (tcmap_ret != NULL) 3609270631Sjfv *tcmap_ret = cmd_resp->tc_bitmap; 3610270631Sjfv } 3611270631Sjfv 3612270631Sjfv return status; 3613270631Sjfv} 3614270631Sjfv 3615270631Sjfv/** 3616270631Sjfv * i40e_aq_dcb_updated - DCB Updated Command 3617270631Sjfv * @hw: pointer to the hw struct 3618270631Sjfv * @cmd_details: pointer to command details structure or NULL 3619270631Sjfv * 3620270631Sjfv * When LLDP is handled in PF this command is used by the PF 3621270631Sjfv * to notify EMP that a DCB setting is modified. 3622270631Sjfv * When LLDP is handled in EMP this command is used by the PF 3623270631Sjfv * to notify EMP whenever one of the following parameters get 3624270631Sjfv * modified: 3625270631Sjfv * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 3626270631Sjfv * - PCIRTT in PRTDCB_GENC.PCIRTT 3627270631Sjfv * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 3628270631Sjfv * EMP will return when the shared RPB settings have been 3629270631Sjfv * recomputed and modified. The retval field in the descriptor 3630270631Sjfv * will be set to 0 when RPB is modified. 3631270631Sjfv **/ 3632270631Sjfvenum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 3633270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3634270631Sjfv{ 3635270631Sjfv struct i40e_aq_desc desc; 3636270631Sjfv enum i40e_status_code status; 3637270631Sjfv 3638270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3639270631Sjfv 3640270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3641270631Sjfv 3642270631Sjfv return status; 3643270631Sjfv} 3644270631Sjfv 3645270631Sjfv/** 3646270631Sjfv * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 3647270631Sjfv * @hw: pointer to the hw struct 3648270631Sjfv * @seid: defines the SEID of the switch for which the stats are requested 3649270631Sjfv * @vlan_id: the VLAN ID for which the statistics are requested 3650270631Sjfv * @stat_index: index of the statistics counters block assigned to this VLAN 3651270631Sjfv * @cmd_details: pointer to command details structure or NULL 3652270631Sjfv * 3653270631Sjfv * XL710 supports 128 smonVlanStats counters.This command is used to 3654270631Sjfv * allocate a set of smonVlanStats counters to a specific VLAN in a specific 3655270631Sjfv * switch. 3656270631Sjfv **/ 3657270631Sjfvenum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 3658270631Sjfv u16 vlan_id, u16 *stat_index, 3659270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3660270631Sjfv{ 3661270631Sjfv struct i40e_aq_desc desc; 3662270631Sjfv struct i40e_aqc_add_remove_statistics *cmd_resp = 3663270631Sjfv (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 3664270631Sjfv enum i40e_status_code status; 3665270631Sjfv 3666270631Sjfv if ((seid == 0) || (stat_index == NULL)) 3667270631Sjfv return I40E_ERR_PARAM; 3668270631Sjfv 3669270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 3670270631Sjfv 3671270631Sjfv cmd_resp->seid = CPU_TO_LE16(seid); 3672270631Sjfv cmd_resp->vlan = CPU_TO_LE16(vlan_id); 3673270631Sjfv 3674270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3675270631Sjfv 3676270631Sjfv if (!status) 3677270631Sjfv *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 3678270631Sjfv 3679270631Sjfv return status; 3680270631Sjfv} 3681270631Sjfv 3682270631Sjfv/** 3683270631Sjfv * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 3684270631Sjfv * @hw: pointer to the hw struct 3685270631Sjfv * @seid: defines the SEID of the switch for which the stats are requested 3686270631Sjfv * @vlan_id: the VLAN ID for which the statistics are requested 3687270631Sjfv * @stat_index: index of the statistics counters block assigned to this VLAN 3688270631Sjfv * @cmd_details: pointer to command details structure or NULL 3689270631Sjfv * 3690270631Sjfv * XL710 supports 128 smonVlanStats counters.This command is used to 3691270631Sjfv * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 3692270631Sjfv * switch. 3693270631Sjfv **/ 3694270631Sjfvenum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 3695270631Sjfv u16 vlan_id, u16 stat_index, 3696270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3697270631Sjfv{ 3698270631Sjfv struct i40e_aq_desc desc; 3699270631Sjfv struct i40e_aqc_add_remove_statistics *cmd = 3700270631Sjfv (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 3701270631Sjfv enum i40e_status_code status; 3702270631Sjfv 3703270631Sjfv if (seid == 0) 3704270631Sjfv return I40E_ERR_PARAM; 3705270631Sjfv 3706270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 3707270631Sjfv i40e_aqc_opc_remove_statistics); 3708270631Sjfv 3709270631Sjfv cmd->seid = CPU_TO_LE16(seid); 3710270631Sjfv cmd->vlan = CPU_TO_LE16(vlan_id); 3711270631Sjfv cmd->stat_index = CPU_TO_LE16(stat_index); 3712270631Sjfv 3713270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3714270631Sjfv 3715270631Sjfv return status; 3716270631Sjfv} 3717270631Sjfv 3718270631Sjfv/** 3719270631Sjfv * i40e_aq_set_port_parameters - set physical port parameters. 3720270631Sjfv * @hw: pointer to the hw struct 3721270631Sjfv * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 3722270631Sjfv * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 3723270631Sjfv * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 3724270631Sjfv * @double_vlan: if set double VLAN is enabled 3725270631Sjfv * @cmd_details: pointer to command details structure or NULL 3726270631Sjfv **/ 3727270631Sjfvenum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 3728270631Sjfv u16 bad_frame_vsi, bool save_bad_pac, 3729270631Sjfv bool pad_short_pac, bool double_vlan, 3730270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3731270631Sjfv{ 3732270631Sjfv struct i40e_aqc_set_port_parameters *cmd; 3733270631Sjfv enum i40e_status_code status; 3734270631Sjfv struct i40e_aq_desc desc; 3735270631Sjfv u16 command_flags = 0; 3736270631Sjfv 3737270631Sjfv cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 3738270631Sjfv 3739270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 3740270631Sjfv i40e_aqc_opc_set_port_parameters); 3741270631Sjfv 3742270631Sjfv cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 3743270631Sjfv if (save_bad_pac) 3744270631Sjfv command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 3745270631Sjfv if (pad_short_pac) 3746270631Sjfv command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 3747270631Sjfv if (double_vlan) 3748270631Sjfv command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3749270631Sjfv cmd->command_flags = CPU_TO_LE16(command_flags); 3750270631Sjfv 3751270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3752270631Sjfv 3753270631Sjfv return status; 3754270631Sjfv} 3755270631Sjfv 3756270631Sjfv/** 3757270631Sjfv * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3758270631Sjfv * @hw: pointer to the hw struct 3759270631Sjfv * @seid: seid for the physical port/switching component/vsi 3760270631Sjfv * @buff: Indirect buffer to hold data parameters and response 3761270631Sjfv * @buff_size: Indirect buffer size 3762270631Sjfv * @opcode: Tx scheduler AQ command opcode 3763270631Sjfv * @cmd_details: pointer to command details structure or NULL 3764270631Sjfv * 3765270631Sjfv * Generic command handler for Tx scheduler AQ commands 3766270631Sjfv **/ 3767270631Sjfvstatic enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3768270631Sjfv void *buff, u16 buff_size, 3769270631Sjfv enum i40e_admin_queue_opc opcode, 3770270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3771270631Sjfv{ 3772270631Sjfv struct i40e_aq_desc desc; 3773270631Sjfv struct i40e_aqc_tx_sched_ind *cmd = 3774270631Sjfv (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3775270631Sjfv enum i40e_status_code status; 3776270631Sjfv bool cmd_param_flag = FALSE; 3777270631Sjfv 3778270631Sjfv switch (opcode) { 3779270631Sjfv case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3780270631Sjfv case i40e_aqc_opc_configure_vsi_tc_bw: 3781270631Sjfv case i40e_aqc_opc_enable_switching_comp_ets: 3782270631Sjfv case i40e_aqc_opc_modify_switching_comp_ets: 3783270631Sjfv case i40e_aqc_opc_disable_switching_comp_ets: 3784270631Sjfv case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3785270631Sjfv case i40e_aqc_opc_configure_switching_comp_bw_config: 3786270631Sjfv cmd_param_flag = TRUE; 3787270631Sjfv break; 3788270631Sjfv case i40e_aqc_opc_query_vsi_bw_config: 3789270631Sjfv case i40e_aqc_opc_query_vsi_ets_sla_config: 3790270631Sjfv case i40e_aqc_opc_query_switching_comp_ets_config: 3791270631Sjfv case i40e_aqc_opc_query_port_ets_config: 3792270631Sjfv case i40e_aqc_opc_query_switching_comp_bw_config: 3793270631Sjfv cmd_param_flag = FALSE; 3794270631Sjfv break; 3795270631Sjfv default: 3796270631Sjfv return I40E_ERR_PARAM; 3797270631Sjfv } 3798270631Sjfv 3799270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, opcode); 3800270631Sjfv 3801270631Sjfv /* Indirect command */ 3802270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3803270631Sjfv if (cmd_param_flag) 3804270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 3805270631Sjfv if (buff_size > I40E_AQ_LARGE_BUF) 3806270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3807270631Sjfv 3808270631Sjfv desc.datalen = CPU_TO_LE16(buff_size); 3809270631Sjfv 3810270631Sjfv cmd->vsi_seid = CPU_TO_LE16(seid); 3811270631Sjfv 3812270631Sjfv status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3813270631Sjfv 3814270631Sjfv return status; 3815270631Sjfv} 3816270631Sjfv 3817270631Sjfv/** 3818270631Sjfv * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3819270631Sjfv * @hw: pointer to the hw struct 3820270631Sjfv * @seid: VSI seid 3821270631Sjfv * @credit: BW limit credits (0 = disabled) 3822270631Sjfv * @max_credit: Max BW limit credits 3823270631Sjfv * @cmd_details: pointer to command details structure or NULL 3824270631Sjfv **/ 3825270631Sjfvenum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3826270631Sjfv u16 seid, u16 credit, u8 max_credit, 3827270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3828270631Sjfv{ 3829270631Sjfv struct i40e_aq_desc desc; 3830270631Sjfv struct i40e_aqc_configure_vsi_bw_limit *cmd = 3831270631Sjfv (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3832270631Sjfv enum i40e_status_code status; 3833270631Sjfv 3834270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 3835270631Sjfv i40e_aqc_opc_configure_vsi_bw_limit); 3836270631Sjfv 3837270631Sjfv cmd->vsi_seid = CPU_TO_LE16(seid); 3838270631Sjfv cmd->credit = CPU_TO_LE16(credit); 3839270631Sjfv cmd->max_credit = max_credit; 3840270631Sjfv 3841270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3842270631Sjfv 3843270631Sjfv return status; 3844270631Sjfv} 3845270631Sjfv 3846270631Sjfv/** 3847270631Sjfv * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 3848270631Sjfv * @hw: pointer to the hw struct 3849270631Sjfv * @seid: switching component seid 3850270631Sjfv * @credit: BW limit credits (0 = disabled) 3851270631Sjfv * @max_bw: Max BW limit credits 3852270631Sjfv * @cmd_details: pointer to command details structure or NULL 3853270631Sjfv **/ 3854270631Sjfvenum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 3855270631Sjfv u16 seid, u16 credit, u8 max_bw, 3856270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3857270631Sjfv{ 3858270631Sjfv struct i40e_aq_desc desc; 3859270631Sjfv struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 3860270631Sjfv (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 3861270631Sjfv enum i40e_status_code status; 3862270631Sjfv 3863270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 3864270631Sjfv i40e_aqc_opc_configure_switching_comp_bw_limit); 3865270631Sjfv 3866270631Sjfv cmd->seid = CPU_TO_LE16(seid); 3867270631Sjfv cmd->credit = CPU_TO_LE16(credit); 3868270631Sjfv cmd->max_bw = max_bw; 3869270631Sjfv 3870270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3871270631Sjfv 3872270631Sjfv return status; 3873270631Sjfv} 3874270631Sjfv 3875270631Sjfv/** 3876270631Sjfv * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 3877270631Sjfv * @hw: pointer to the hw struct 3878270631Sjfv * @seid: VSI seid 3879270631Sjfv * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 3880270631Sjfv * @cmd_details: pointer to command details structure or NULL 3881270631Sjfv **/ 3882270631Sjfvenum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 3883270631Sjfv u16 seid, 3884270631Sjfv struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 3885270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3886270631Sjfv{ 3887270631Sjfv return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3888270631Sjfv i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 3889270631Sjfv cmd_details); 3890270631Sjfv} 3891270631Sjfv 3892270631Sjfv/** 3893270631Sjfv * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3894270631Sjfv * @hw: pointer to the hw struct 3895270631Sjfv * @seid: VSI seid 3896270631Sjfv * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3897270631Sjfv * @cmd_details: pointer to command details structure or NULL 3898270631Sjfv **/ 3899270631Sjfvenum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3900270631Sjfv u16 seid, 3901270631Sjfv struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3902270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3903270631Sjfv{ 3904270631Sjfv return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3905270631Sjfv i40e_aqc_opc_configure_vsi_tc_bw, 3906270631Sjfv cmd_details); 3907270631Sjfv} 3908270631Sjfv 3909270631Sjfv/** 3910270631Sjfv * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 3911270631Sjfv * @hw: pointer to the hw struct 3912270631Sjfv * @seid: seid of the switching component 3913270631Sjfv * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 3914270631Sjfv * @cmd_details: pointer to command details structure or NULL 3915270631Sjfv **/ 3916270631Sjfvenum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 3917270631Sjfv struct i40e_hw *hw, u16 seid, 3918270631Sjfv struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 3919270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3920270631Sjfv{ 3921270631Sjfv return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3922270631Sjfv i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 3923270631Sjfv cmd_details); 3924270631Sjfv} 3925270631Sjfv 3926270631Sjfv/** 3927270631Sjfv * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3928270631Sjfv * @hw: pointer to the hw struct 3929270631Sjfv * @seid: seid of the VSI 3930270631Sjfv * @bw_data: Buffer to hold VSI BW configuration 3931270631Sjfv * @cmd_details: pointer to command details structure or NULL 3932270631Sjfv **/ 3933270631Sjfvenum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3934270631Sjfv u16 seid, 3935270631Sjfv struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3936270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3937270631Sjfv{ 3938270631Sjfv return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3939270631Sjfv i40e_aqc_opc_query_vsi_bw_config, 3940270631Sjfv cmd_details); 3941270631Sjfv} 3942270631Sjfv 3943270631Sjfv/** 3944270631Sjfv * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3945270631Sjfv * @hw: pointer to the hw struct 3946270631Sjfv * @seid: seid of the VSI 3947270631Sjfv * @bw_data: Buffer to hold VSI BW configuration per TC 3948270631Sjfv * @cmd_details: pointer to command details structure or NULL 3949270631Sjfv **/ 3950270631Sjfvenum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3951270631Sjfv u16 seid, 3952270631Sjfv struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3953270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3954270631Sjfv{ 3955270631Sjfv return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3956270631Sjfv i40e_aqc_opc_query_vsi_ets_sla_config, 3957270631Sjfv cmd_details); 3958270631Sjfv} 3959270631Sjfv 3960270631Sjfv/** 3961270631Sjfv * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3962270631Sjfv * @hw: pointer to the hw struct 3963270631Sjfv * @seid: seid of the switching component 3964270631Sjfv * @bw_data: Buffer to hold switching component's per TC BW config 3965270631Sjfv * @cmd_details: pointer to command details structure or NULL 3966270631Sjfv **/ 3967270631Sjfvenum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3968270631Sjfv u16 seid, 3969270631Sjfv struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3970270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3971270631Sjfv{ 3972270631Sjfv return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3973270631Sjfv i40e_aqc_opc_query_switching_comp_ets_config, 3974270631Sjfv cmd_details); 3975270631Sjfv} 3976270631Sjfv 3977270631Sjfv/** 3978270631Sjfv * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3979270631Sjfv * @hw: pointer to the hw struct 3980270631Sjfv * @seid: seid of the VSI or switching component connected to Physical Port 3981270631Sjfv * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3982270631Sjfv * @cmd_details: pointer to command details structure or NULL 3983270631Sjfv **/ 3984270631Sjfvenum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3985270631Sjfv u16 seid, 3986270631Sjfv struct i40e_aqc_query_port_ets_config_resp *bw_data, 3987270631Sjfv struct i40e_asq_cmd_details *cmd_details) 3988270631Sjfv{ 3989270631Sjfv return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3990270631Sjfv i40e_aqc_opc_query_port_ets_config, 3991270631Sjfv cmd_details); 3992270631Sjfv} 3993270631Sjfv 3994270631Sjfv/** 3995270631Sjfv * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3996270631Sjfv * @hw: pointer to the hw struct 3997270631Sjfv * @seid: seid of the switching component 3998270631Sjfv * @bw_data: Buffer to hold switching component's BW configuration 3999270631Sjfv * @cmd_details: pointer to command details structure or NULL 4000270631Sjfv **/ 4001270631Sjfvenum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 4002270631Sjfv u16 seid, 4003270631Sjfv struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 4004270631Sjfv struct i40e_asq_cmd_details *cmd_details) 4005270631Sjfv{ 4006270631Sjfv return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4007270631Sjfv i40e_aqc_opc_query_switching_comp_bw_config, 4008270631Sjfv cmd_details); 4009270631Sjfv} 4010270631Sjfv 4011270631Sjfv/** 4012270631Sjfv * i40e_validate_filter_settings 4013270631Sjfv * @hw: pointer to the hardware structure 4014270631Sjfv * @settings: Filter control settings 4015270631Sjfv * 4016270631Sjfv * Check and validate the filter control settings passed. 4017270631Sjfv * The function checks for the valid filter/context sizes being 4018270631Sjfv * passed for FCoE and PE. 4019270631Sjfv * 4020270631Sjfv * Returns I40E_SUCCESS if the values passed are valid and within 4021270631Sjfv * range else returns an error. 4022270631Sjfv **/ 4023270631Sjfvstatic enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 4024270631Sjfv struct i40e_filter_control_settings *settings) 4025270631Sjfv{ 4026270631Sjfv u32 fcoe_cntx_size, fcoe_filt_size; 4027270631Sjfv u32 pe_cntx_size, pe_filt_size; 4028270631Sjfv u32 fcoe_fmax; 4029270631Sjfv 4030270631Sjfv u32 val; 4031270631Sjfv 4032270631Sjfv /* Validate FCoE settings passed */ 4033270631Sjfv switch (settings->fcoe_filt_num) { 4034270631Sjfv case I40E_HASH_FILTER_SIZE_1K: 4035270631Sjfv case I40E_HASH_FILTER_SIZE_2K: 4036270631Sjfv case I40E_HASH_FILTER_SIZE_4K: 4037270631Sjfv case I40E_HASH_FILTER_SIZE_8K: 4038270631Sjfv case I40E_HASH_FILTER_SIZE_16K: 4039270631Sjfv case I40E_HASH_FILTER_SIZE_32K: 4040270631Sjfv fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4041270631Sjfv fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4042270631Sjfv break; 4043270631Sjfv default: 4044270631Sjfv return I40E_ERR_PARAM; 4045270631Sjfv } 4046270631Sjfv 4047270631Sjfv switch (settings->fcoe_cntx_num) { 4048270631Sjfv case I40E_DMA_CNTX_SIZE_512: 4049270631Sjfv case I40E_DMA_CNTX_SIZE_1K: 4050270631Sjfv case I40E_DMA_CNTX_SIZE_2K: 4051270631Sjfv case I40E_DMA_CNTX_SIZE_4K: 4052270631Sjfv fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4053270631Sjfv fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4054270631Sjfv break; 4055270631Sjfv default: 4056270631Sjfv return I40E_ERR_PARAM; 4057270631Sjfv } 4058270631Sjfv 4059270631Sjfv /* Validate PE settings passed */ 4060270631Sjfv switch (settings->pe_filt_num) { 4061270631Sjfv case I40E_HASH_FILTER_SIZE_1K: 4062270631Sjfv case I40E_HASH_FILTER_SIZE_2K: 4063270631Sjfv case I40E_HASH_FILTER_SIZE_4K: 4064270631Sjfv case I40E_HASH_FILTER_SIZE_8K: 4065270631Sjfv case I40E_HASH_FILTER_SIZE_16K: 4066270631Sjfv case I40E_HASH_FILTER_SIZE_32K: 4067270631Sjfv case I40E_HASH_FILTER_SIZE_64K: 4068270631Sjfv case I40E_HASH_FILTER_SIZE_128K: 4069270631Sjfv case I40E_HASH_FILTER_SIZE_256K: 4070270631Sjfv case I40E_HASH_FILTER_SIZE_512K: 4071270631Sjfv case I40E_HASH_FILTER_SIZE_1M: 4072270631Sjfv pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4073270631Sjfv pe_filt_size <<= (u32)settings->pe_filt_num; 4074270631Sjfv break; 4075270631Sjfv default: 4076270631Sjfv return I40E_ERR_PARAM; 4077270631Sjfv } 4078270631Sjfv 4079270631Sjfv switch (settings->pe_cntx_num) { 4080270631Sjfv case I40E_DMA_CNTX_SIZE_512: 4081270631Sjfv case I40E_DMA_CNTX_SIZE_1K: 4082270631Sjfv case I40E_DMA_CNTX_SIZE_2K: 4083270631Sjfv case I40E_DMA_CNTX_SIZE_4K: 4084270631Sjfv case I40E_DMA_CNTX_SIZE_8K: 4085270631Sjfv case I40E_DMA_CNTX_SIZE_16K: 4086270631Sjfv case I40E_DMA_CNTX_SIZE_32K: 4087270631Sjfv case I40E_DMA_CNTX_SIZE_64K: 4088270631Sjfv case I40E_DMA_CNTX_SIZE_128K: 4089270631Sjfv case I40E_DMA_CNTX_SIZE_256K: 4090270631Sjfv pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4091270631Sjfv pe_cntx_size <<= (u32)settings->pe_cntx_num; 4092270631Sjfv break; 4093270631Sjfv default: 4094270631Sjfv return I40E_ERR_PARAM; 4095270631Sjfv } 4096270631Sjfv 4097270631Sjfv /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4098270631Sjfv val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4099270631Sjfv fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4100270631Sjfv >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4101270631Sjfv if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4102270631Sjfv return I40E_ERR_INVALID_SIZE; 4103270631Sjfv 4104270631Sjfv return I40E_SUCCESS; 4105270631Sjfv} 4106270631Sjfv 4107270631Sjfv/** 4108270631Sjfv * i40e_set_filter_control 4109270631Sjfv * @hw: pointer to the hardware structure 4110270631Sjfv * @settings: Filter control settings 4111270631Sjfv * 4112270631Sjfv * Set the Queue Filters for PE/FCoE and enable filters required 4113270631Sjfv * for a single PF. It is expected that these settings are programmed 4114270631Sjfv * at the driver initialization time. 4115270631Sjfv **/ 4116270631Sjfvenum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 4117270631Sjfv struct i40e_filter_control_settings *settings) 4118270631Sjfv{ 4119270631Sjfv enum i40e_status_code ret = I40E_SUCCESS; 4120270631Sjfv u32 hash_lut_size = 0; 4121270631Sjfv u32 val; 4122270631Sjfv 4123270631Sjfv if (!settings) 4124270631Sjfv return I40E_ERR_PARAM; 4125270631Sjfv 4126270631Sjfv /* Validate the input settings */ 4127270631Sjfv ret = i40e_validate_filter_settings(hw, settings); 4128270631Sjfv if (ret) 4129270631Sjfv return ret; 4130270631Sjfv 4131270631Sjfv /* Read the PF Queue Filter control register */ 4132270631Sjfv val = rd32(hw, I40E_PFQF_CTL_0); 4133270631Sjfv 4134270631Sjfv /* Program required PE hash buckets for the PF */ 4135270631Sjfv val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4136270631Sjfv val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4137270631Sjfv I40E_PFQF_CTL_0_PEHSIZE_MASK; 4138270631Sjfv /* Program required PE contexts for the PF */ 4139270631Sjfv val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4140270631Sjfv val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4141270631Sjfv I40E_PFQF_CTL_0_PEDSIZE_MASK; 4142270631Sjfv 4143270631Sjfv /* Program required FCoE hash buckets for the PF */ 4144270631Sjfv val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4145270631Sjfv val |= ((u32)settings->fcoe_filt_num << 4146270631Sjfv I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4147270631Sjfv I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4148270631Sjfv /* Program required FCoE DDP contexts for the PF */ 4149270631Sjfv val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4150270631Sjfv val |= ((u32)settings->fcoe_cntx_num << 4151270631Sjfv I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4152270631Sjfv I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4153270631Sjfv 4154270631Sjfv /* Program Hash LUT size for the PF */ 4155270631Sjfv val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4156270631Sjfv if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4157270631Sjfv hash_lut_size = 1; 4158270631Sjfv val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4159270631Sjfv I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4160270631Sjfv 4161270631Sjfv /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4162270631Sjfv if (settings->enable_fdir) 4163270631Sjfv val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4164270631Sjfv if (settings->enable_ethtype) 4165270631Sjfv val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4166270631Sjfv if (settings->enable_macvlan) 4167270631Sjfv val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4168270631Sjfv 4169270631Sjfv wr32(hw, I40E_PFQF_CTL_0, val); 4170270631Sjfv 4171270631Sjfv return I40E_SUCCESS; 4172270631Sjfv} 4173270631Sjfv 4174270631Sjfv/** 4175270631Sjfv * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4176270631Sjfv * @hw: pointer to the hw struct 4177270631Sjfv * @mac_addr: MAC address to use in the filter 4178270631Sjfv * @ethtype: Ethertype to use in the filter 4179270631Sjfv * @flags: Flags that needs to be applied to the filter 4180270631Sjfv * @vsi_seid: seid of the control VSI 4181270631Sjfv * @queue: VSI queue number to send the packet to 4182270631Sjfv * @is_add: Add control packet filter if True else remove 4183270631Sjfv * @stats: Structure to hold information on control filter counts 4184270631Sjfv * @cmd_details: pointer to command details structure or NULL 4185270631Sjfv * 4186270631Sjfv * This command will Add or Remove control packet filter for a control VSI. 4187270631Sjfv * In return it will update the total number of perfect filter count in 4188270631Sjfv * the stats member. 4189270631Sjfv **/ 4190270631Sjfvenum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4191270631Sjfv u8 *mac_addr, u16 ethtype, u16 flags, 4192270631Sjfv u16 vsi_seid, u16 queue, bool is_add, 4193270631Sjfv struct i40e_control_filter_stats *stats, 4194270631Sjfv struct i40e_asq_cmd_details *cmd_details) 4195270631Sjfv{ 4196270631Sjfv struct i40e_aq_desc desc; 4197270631Sjfv struct i40e_aqc_add_remove_control_packet_filter *cmd = 4198270631Sjfv (struct i40e_aqc_add_remove_control_packet_filter *) 4199270631Sjfv &desc.params.raw; 4200270631Sjfv struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4201270631Sjfv (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4202270631Sjfv &desc.params.raw; 4203270631Sjfv enum i40e_status_code status; 4204270631Sjfv 4205270631Sjfv if (vsi_seid == 0) 4206270631Sjfv return I40E_ERR_PARAM; 4207270631Sjfv 4208270631Sjfv if (is_add) { 4209270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 4210270631Sjfv i40e_aqc_opc_add_control_packet_filter); 4211270631Sjfv cmd->queue = CPU_TO_LE16(queue); 4212270631Sjfv } else { 4213270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 4214270631Sjfv i40e_aqc_opc_remove_control_packet_filter); 4215270631Sjfv } 4216270631Sjfv 4217270631Sjfv if (mac_addr) 4218270631Sjfv i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS, 4219270631Sjfv I40E_NONDMA_TO_NONDMA); 4220270631Sjfv 4221270631Sjfv cmd->etype = CPU_TO_LE16(ethtype); 4222270631Sjfv cmd->flags = CPU_TO_LE16(flags); 4223270631Sjfv cmd->seid = CPU_TO_LE16(vsi_seid); 4224270631Sjfv 4225270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4226270631Sjfv 4227270631Sjfv if (!status && stats) { 4228270631Sjfv stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 4229270631Sjfv stats->etype_used = LE16_TO_CPU(resp->etype_used); 4230270631Sjfv stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 4231270631Sjfv stats->etype_free = LE16_TO_CPU(resp->etype_free); 4232270631Sjfv } 4233270631Sjfv 4234270631Sjfv return status; 4235270631Sjfv} 4236270631Sjfv 4237270631Sjfv/** 4238270631Sjfv * i40e_aq_add_cloud_filters 4239270631Sjfv * @hw: pointer to the hardware structure 4240270631Sjfv * @seid: VSI seid to add cloud filters from 4241270631Sjfv * @filters: Buffer which contains the filters to be added 4242270631Sjfv * @filter_count: number of filters contained in the buffer 4243270631Sjfv * 4244270631Sjfv * Set the cloud filters for a given VSI. The contents of the 4245270631Sjfv * i40e_aqc_add_remove_cloud_filters_element_data are filled 4246270631Sjfv * in by the caller of the function. 4247270631Sjfv * 4248270631Sjfv **/ 4249270631Sjfvenum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 4250270631Sjfv u16 seid, 4251270631Sjfv struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 4252270631Sjfv u8 filter_count) 4253270631Sjfv{ 4254270631Sjfv struct i40e_aq_desc desc; 4255270631Sjfv struct i40e_aqc_add_remove_cloud_filters *cmd = 4256270631Sjfv (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 4257270631Sjfv u16 buff_len; 4258270631Sjfv enum i40e_status_code status; 4259270631Sjfv 4260270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 4261270631Sjfv i40e_aqc_opc_add_cloud_filters); 4262270631Sjfv 4263270631Sjfv buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) * 4264270631Sjfv filter_count; 4265270631Sjfv desc.datalen = CPU_TO_LE16(buff_len); 4266270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4267270631Sjfv cmd->num_filters = filter_count; 4268270631Sjfv cmd->seid = CPU_TO_LE16(seid); 4269270631Sjfv 4270270631Sjfv status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 4271270631Sjfv 4272270631Sjfv return status; 4273270631Sjfv} 4274270631Sjfv 4275270631Sjfv/** 4276270631Sjfv * i40e_aq_remove_cloud_filters 4277270631Sjfv * @hw: pointer to the hardware structure 4278270631Sjfv * @seid: VSI seid to remove cloud filters from 4279270631Sjfv * @filters: Buffer which contains the filters to be removed 4280270631Sjfv * @filter_count: number of filters contained in the buffer 4281270631Sjfv * 4282270631Sjfv * Remove the cloud filters for a given VSI. The contents of the 4283270631Sjfv * i40e_aqc_add_remove_cloud_filters_element_data are filled 4284270631Sjfv * in by the caller of the function. 4285270631Sjfv * 4286270631Sjfv **/ 4287270631Sjfvenum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 4288270631Sjfv u16 seid, 4289270631Sjfv struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 4290270631Sjfv u8 filter_count) 4291270631Sjfv{ 4292270631Sjfv struct i40e_aq_desc desc; 4293270631Sjfv struct i40e_aqc_add_remove_cloud_filters *cmd = 4294270631Sjfv (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 4295270631Sjfv enum i40e_status_code status; 4296270631Sjfv u16 buff_len; 4297270631Sjfv 4298270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 4299270631Sjfv i40e_aqc_opc_remove_cloud_filters); 4300270631Sjfv 4301270631Sjfv buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) * 4302270631Sjfv filter_count; 4303270631Sjfv desc.datalen = CPU_TO_LE16(buff_len); 4304270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4305270631Sjfv cmd->num_filters = filter_count; 4306270631Sjfv cmd->seid = CPU_TO_LE16(seid); 4307270631Sjfv 4308270631Sjfv status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 4309270631Sjfv 4310270631Sjfv return status; 4311270631Sjfv} 4312270631Sjfv 4313270631Sjfv/** 4314270631Sjfv * i40e_aq_alternate_write 4315270631Sjfv * @hw: pointer to the hardware structure 4316270631Sjfv * @reg_addr0: address of first dword to be read 4317270631Sjfv * @reg_val0: value to be written under 'reg_addr0' 4318270631Sjfv * @reg_addr1: address of second dword to be read 4319270631Sjfv * @reg_val1: value to be written under 'reg_addr1' 4320270631Sjfv * 4321270631Sjfv * Write one or two dwords to alternate structure. Fields are indicated 4322270631Sjfv * by 'reg_addr0' and 'reg_addr1' register numbers. 4323270631Sjfv * 4324270631Sjfv **/ 4325270631Sjfvenum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 4326270631Sjfv u32 reg_addr0, u32 reg_val0, 4327270631Sjfv u32 reg_addr1, u32 reg_val1) 4328270631Sjfv{ 4329270631Sjfv struct i40e_aq_desc desc; 4330270631Sjfv struct i40e_aqc_alternate_write *cmd_resp = 4331270631Sjfv (struct i40e_aqc_alternate_write *)&desc.params.raw; 4332270631Sjfv enum i40e_status_code status; 4333270631Sjfv 4334270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 4335270631Sjfv cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 4336270631Sjfv cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 4337270631Sjfv cmd_resp->data0 = CPU_TO_LE32(reg_val0); 4338270631Sjfv cmd_resp->data1 = CPU_TO_LE32(reg_val1); 4339270631Sjfv 4340270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4341270631Sjfv 4342270631Sjfv return status; 4343270631Sjfv} 4344270631Sjfv 4345270631Sjfv/** 4346270631Sjfv * i40e_aq_alternate_write_indirect 4347270631Sjfv * @hw: pointer to the hardware structure 4348270631Sjfv * @addr: address of a first register to be modified 4349270631Sjfv * @dw_count: number of alternate structure fields to write 4350270631Sjfv * @buffer: pointer to the command buffer 4351270631Sjfv * 4352270631Sjfv * Write 'dw_count' dwords from 'buffer' to alternate structure 4353270631Sjfv * starting at 'addr'. 4354270631Sjfv * 4355270631Sjfv **/ 4356270631Sjfvenum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 4357270631Sjfv u32 addr, u32 dw_count, void *buffer) 4358270631Sjfv{ 4359270631Sjfv struct i40e_aq_desc desc; 4360270631Sjfv struct i40e_aqc_alternate_ind_write *cmd_resp = 4361270631Sjfv (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 4362270631Sjfv enum i40e_status_code status; 4363270631Sjfv 4364270631Sjfv if (buffer == NULL) 4365270631Sjfv return I40E_ERR_PARAM; 4366270631Sjfv 4367270631Sjfv /* Indirect command */ 4368270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 4369270631Sjfv i40e_aqc_opc_alternate_write_indirect); 4370270631Sjfv 4371270631Sjfv desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 4372270631Sjfv desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 4373270631Sjfv if (dw_count > (I40E_AQ_LARGE_BUF/4)) 4374270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4375270631Sjfv 4376270631Sjfv cmd_resp->address = CPU_TO_LE32(addr); 4377270631Sjfv cmd_resp->length = CPU_TO_LE32(dw_count); 4378272313Sbz cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer)); 4379272313Sbz cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer)); 4380270631Sjfv 4381270631Sjfv status = i40e_asq_send_command(hw, &desc, buffer, 4382270631Sjfv I40E_LO_DWORD(4*dw_count), NULL); 4383270631Sjfv 4384270631Sjfv return status; 4385270631Sjfv} 4386270631Sjfv 4387270631Sjfv/** 4388270631Sjfv * i40e_aq_alternate_read 4389270631Sjfv * @hw: pointer to the hardware structure 4390270631Sjfv * @reg_addr0: address of first dword to be read 4391270631Sjfv * @reg_val0: pointer for data read from 'reg_addr0' 4392270631Sjfv * @reg_addr1: address of second dword to be read 4393270631Sjfv * @reg_val1: pointer for data read from 'reg_addr1' 4394270631Sjfv * 4395270631Sjfv * Read one or two dwords from alternate structure. Fields are indicated 4396270631Sjfv * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4397270631Sjfv * is not passed then only register at 'reg_addr0' is read. 4398270631Sjfv * 4399270631Sjfv **/ 4400270631Sjfvenum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 4401270631Sjfv u32 reg_addr0, u32 *reg_val0, 4402270631Sjfv u32 reg_addr1, u32 *reg_val1) 4403270631Sjfv{ 4404270631Sjfv struct i40e_aq_desc desc; 4405270631Sjfv struct i40e_aqc_alternate_write *cmd_resp = 4406270631Sjfv (struct i40e_aqc_alternate_write *)&desc.params.raw; 4407270631Sjfv enum i40e_status_code status; 4408270631Sjfv 4409270631Sjfv if (reg_val0 == NULL) 4410270631Sjfv return I40E_ERR_PARAM; 4411270631Sjfv 4412270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4413270631Sjfv cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 4414270631Sjfv cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 4415270631Sjfv 4416270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4417270631Sjfv 4418270631Sjfv if (status == I40E_SUCCESS) { 4419270631Sjfv *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 4420270631Sjfv 4421270631Sjfv if (reg_val1 != NULL) 4422270631Sjfv *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 4423270631Sjfv } 4424270631Sjfv 4425270631Sjfv return status; 4426270631Sjfv} 4427270631Sjfv 4428270631Sjfv/** 4429270631Sjfv * i40e_aq_alternate_read_indirect 4430270631Sjfv * @hw: pointer to the hardware structure 4431270631Sjfv * @addr: address of the alternate structure field 4432270631Sjfv * @dw_count: number of alternate structure fields to read 4433270631Sjfv * @buffer: pointer to the command buffer 4434270631Sjfv * 4435270631Sjfv * Read 'dw_count' dwords from alternate structure starting at 'addr' and 4436270631Sjfv * place them in 'buffer'. The buffer should be allocated by caller. 4437270631Sjfv * 4438270631Sjfv **/ 4439270631Sjfvenum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 4440270631Sjfv u32 addr, u32 dw_count, void *buffer) 4441270631Sjfv{ 4442270631Sjfv struct i40e_aq_desc desc; 4443270631Sjfv struct i40e_aqc_alternate_ind_write *cmd_resp = 4444270631Sjfv (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 4445270631Sjfv enum i40e_status_code status; 4446270631Sjfv 4447270631Sjfv if (buffer == NULL) 4448270631Sjfv return I40E_ERR_PARAM; 4449270631Sjfv 4450270631Sjfv /* Indirect command */ 4451270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 4452270631Sjfv i40e_aqc_opc_alternate_read_indirect); 4453270631Sjfv 4454270631Sjfv desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 4455270631Sjfv desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 4456270631Sjfv if (dw_count > (I40E_AQ_LARGE_BUF/4)) 4457270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4458270631Sjfv 4459270631Sjfv cmd_resp->address = CPU_TO_LE32(addr); 4460270631Sjfv cmd_resp->length = CPU_TO_LE32(dw_count); 4461272313Sbz cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer)); 4462272313Sbz cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer)); 4463270631Sjfv 4464270631Sjfv status = i40e_asq_send_command(hw, &desc, buffer, 4465270631Sjfv I40E_LO_DWORD(4*dw_count), NULL); 4466270631Sjfv 4467270631Sjfv return status; 4468270631Sjfv} 4469270631Sjfv 4470270631Sjfv/** 4471270631Sjfv * i40e_aq_alternate_clear 4472270631Sjfv * @hw: pointer to the HW structure. 4473270631Sjfv * 4474270631Sjfv * Clear the alternate structures of the port from which the function 4475270631Sjfv * is called. 4476270631Sjfv * 4477270631Sjfv **/ 4478270631Sjfvenum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 4479270631Sjfv{ 4480270631Sjfv struct i40e_aq_desc desc; 4481270631Sjfv enum i40e_status_code status; 4482270631Sjfv 4483270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 4484270631Sjfv i40e_aqc_opc_alternate_clear_port); 4485270631Sjfv 4486270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4487270631Sjfv 4488270631Sjfv return status; 4489270631Sjfv} 4490270631Sjfv 4491270631Sjfv/** 4492270631Sjfv * i40e_aq_alternate_write_done 4493270631Sjfv * @hw: pointer to the HW structure. 4494270631Sjfv * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 4495270631Sjfv * @reset_needed: indicates the SW should trigger GLOBAL reset 4496270631Sjfv * 4497270631Sjfv * Indicates to the FW that alternate structures have been changed. 4498270631Sjfv * 4499270631Sjfv **/ 4500270631Sjfvenum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 4501270631Sjfv u8 bios_mode, bool *reset_needed) 4502270631Sjfv{ 4503270631Sjfv struct i40e_aq_desc desc; 4504270631Sjfv struct i40e_aqc_alternate_write_done *cmd = 4505270631Sjfv (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 4506270631Sjfv enum i40e_status_code status; 4507270631Sjfv 4508270631Sjfv if (reset_needed == NULL) 4509270631Sjfv return I40E_ERR_PARAM; 4510270631Sjfv 4511270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 4512270631Sjfv i40e_aqc_opc_alternate_write_done); 4513270631Sjfv 4514270631Sjfv cmd->cmd_flags = CPU_TO_LE16(bios_mode); 4515270631Sjfv 4516270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4517270631Sjfv if (!status) 4518270631Sjfv *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 4519270631Sjfv I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 4520270631Sjfv 4521270631Sjfv return status; 4522270631Sjfv} 4523270631Sjfv 4524270631Sjfv/** 4525270631Sjfv * i40e_aq_set_oem_mode 4526270631Sjfv * @hw: pointer to the HW structure. 4527270631Sjfv * @oem_mode: the OEM mode to be used 4528270631Sjfv * 4529270631Sjfv * Sets the device to a specific operating mode. Currently the only supported 4530270631Sjfv * mode is no_clp, which causes FW to refrain from using Alternate RAM. 4531270631Sjfv * 4532270631Sjfv **/ 4533270631Sjfvenum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 4534270631Sjfv u8 oem_mode) 4535270631Sjfv{ 4536270631Sjfv struct i40e_aq_desc desc; 4537270631Sjfv struct i40e_aqc_alternate_write_done *cmd = 4538270631Sjfv (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 4539270631Sjfv enum i40e_status_code status; 4540270631Sjfv 4541270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 4542270631Sjfv i40e_aqc_opc_alternate_set_mode); 4543270631Sjfv 4544270631Sjfv cmd->cmd_flags = CPU_TO_LE16(oem_mode); 4545270631Sjfv 4546270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4547270631Sjfv 4548270631Sjfv return status; 4549270631Sjfv} 4550270631Sjfv 4551270631Sjfv/** 4552270631Sjfv * i40e_aq_resume_port_tx 4553270631Sjfv * @hw: pointer to the hardware structure 4554270631Sjfv * @cmd_details: pointer to command details structure or NULL 4555270631Sjfv * 4556270631Sjfv * Resume port's Tx traffic 4557270631Sjfv **/ 4558270631Sjfvenum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 4559270631Sjfv struct i40e_asq_cmd_details *cmd_details) 4560270631Sjfv{ 4561270631Sjfv struct i40e_aq_desc desc; 4562270631Sjfv enum i40e_status_code status; 4563270631Sjfv 4564270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4565270631Sjfv 4566270631Sjfv status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4567270631Sjfv 4568270631Sjfv return status; 4569270631Sjfv} 4570270631Sjfv 4571270631Sjfv/** 4572270631Sjfv * i40e_set_pci_config_data - store PCI bus info 4573270631Sjfv * @hw: pointer to hardware structure 4574270631Sjfv * @link_status: the link status word from PCI config space 4575270631Sjfv * 4576270631Sjfv * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4577270631Sjfv **/ 4578270631Sjfvvoid i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4579270631Sjfv{ 4580270631Sjfv hw->bus.type = i40e_bus_type_pci_express; 4581270631Sjfv 4582270631Sjfv switch (link_status & I40E_PCI_LINK_WIDTH) { 4583270631Sjfv case I40E_PCI_LINK_WIDTH_1: 4584270631Sjfv hw->bus.width = i40e_bus_width_pcie_x1; 4585270631Sjfv break; 4586270631Sjfv case I40E_PCI_LINK_WIDTH_2: 4587270631Sjfv hw->bus.width = i40e_bus_width_pcie_x2; 4588270631Sjfv break; 4589270631Sjfv case I40E_PCI_LINK_WIDTH_4: 4590270631Sjfv hw->bus.width = i40e_bus_width_pcie_x4; 4591270631Sjfv break; 4592270631Sjfv case I40E_PCI_LINK_WIDTH_8: 4593270631Sjfv hw->bus.width = i40e_bus_width_pcie_x8; 4594270631Sjfv break; 4595270631Sjfv default: 4596270631Sjfv hw->bus.width = i40e_bus_width_unknown; 4597270631Sjfv break; 4598270631Sjfv } 4599270631Sjfv 4600270631Sjfv switch (link_status & I40E_PCI_LINK_SPEED) { 4601270631Sjfv case I40E_PCI_LINK_SPEED_2500: 4602270631Sjfv hw->bus.speed = i40e_bus_speed_2500; 4603270631Sjfv break; 4604270631Sjfv case I40E_PCI_LINK_SPEED_5000: 4605270631Sjfv hw->bus.speed = i40e_bus_speed_5000; 4606270631Sjfv break; 4607270631Sjfv case I40E_PCI_LINK_SPEED_8000: 4608270631Sjfv hw->bus.speed = i40e_bus_speed_8000; 4609270631Sjfv break; 4610270631Sjfv default: 4611270631Sjfv hw->bus.speed = i40e_bus_speed_unknown; 4612270631Sjfv break; 4613270631Sjfv } 4614270631Sjfv} 4615270631Sjfv 4616270631Sjfv/** 4617270631Sjfv * i40e_read_bw_from_alt_ram 4618270631Sjfv * @hw: pointer to the hardware structure 4619270631Sjfv * @max_bw: pointer for max_bw read 4620270631Sjfv * @min_bw: pointer for min_bw read 4621270631Sjfv * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 4622270631Sjfv * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 4623270631Sjfv * 4624270631Sjfv * Read bw from the alternate ram for the given pf 4625270631Sjfv **/ 4626270631Sjfvenum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4627270631Sjfv u32 *max_bw, u32 *min_bw, 4628270631Sjfv bool *min_valid, bool *max_valid) 4629270631Sjfv{ 4630270631Sjfv enum i40e_status_code status; 4631270631Sjfv u32 max_bw_addr, min_bw_addr; 4632270631Sjfv 4633270631Sjfv /* Calculate the address of the min/max bw registers */ 4634270631Sjfv max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4635270631Sjfv I40E_ALT_STRUCT_MAX_BW_OFFSET + 4636270631Sjfv (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id); 4637270631Sjfv min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4638270631Sjfv I40E_ALT_STRUCT_MIN_BW_OFFSET + 4639270631Sjfv (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id); 4640270631Sjfv 4641270631Sjfv /* Read the bandwidths from alt ram */ 4642270631Sjfv status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4643270631Sjfv min_bw_addr, min_bw); 4644270631Sjfv 4645270631Sjfv if (*min_bw & I40E_ALT_BW_VALID_MASK) 4646270631Sjfv *min_valid = TRUE; 4647270631Sjfv else 4648270631Sjfv *min_valid = FALSE; 4649270631Sjfv 4650270631Sjfv if (*max_bw & I40E_ALT_BW_VALID_MASK) 4651270631Sjfv *max_valid = TRUE; 4652270631Sjfv else 4653270631Sjfv *max_valid = FALSE; 4654270631Sjfv 4655270631Sjfv return status; 4656270631Sjfv} 4657270631Sjfv 4658270631Sjfv/** 4659270631Sjfv * i40e_aq_configure_partition_bw 4660270631Sjfv * @hw: pointer to the hardware structure 4661270631Sjfv * @bw_data: Buffer holding valid pfs and bw limits 4662270631Sjfv * @cmd_details: pointer to command details 4663270631Sjfv * 4664270631Sjfv * Configure partitions guaranteed/max bw 4665270631Sjfv **/ 4666270631Sjfvenum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4667270631Sjfv struct i40e_aqc_configure_partition_bw_data *bw_data, 4668270631Sjfv struct i40e_asq_cmd_details *cmd_details) 4669270631Sjfv{ 4670270631Sjfv enum i40e_status_code status; 4671270631Sjfv struct i40e_aq_desc desc; 4672270631Sjfv u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data); 4673270631Sjfv 4674270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, 4675270631Sjfv i40e_aqc_opc_configure_partition_bw); 4676270631Sjfv 4677270631Sjfv /* Indirect command */ 4678270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4679270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 4680270631Sjfv 4681270631Sjfv if (bwd_size > I40E_AQ_LARGE_BUF) 4682270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4683270631Sjfv 4684270631Sjfv desc.datalen = CPU_TO_LE16(bwd_size); 4685270631Sjfv 4686270631Sjfv status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 4687270631Sjfv 4688270631Sjfv return status; 4689270631Sjfv} 4690270631Sjfv 4691270631Sjfv/** 4692270631Sjfv * i40e_aq_send_msg_to_pf 4693270631Sjfv * @hw: pointer to the hardware structure 4694270631Sjfv * @v_opcode: opcodes for VF-PF communication 4695270631Sjfv * @v_retval: return error code 4696270631Sjfv * @msg: pointer to the msg buffer 4697270631Sjfv * @msglen: msg length 4698270631Sjfv * @cmd_details: pointer to command details 4699270631Sjfv * 4700270631Sjfv * Send message to PF driver using admin queue. By default, this message 4701270631Sjfv * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 4702270631Sjfv * completion before returning. 4703270631Sjfv **/ 4704270631Sjfvenum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 4705270631Sjfv enum i40e_virtchnl_ops v_opcode, 4706270631Sjfv enum i40e_status_code v_retval, 4707270631Sjfv u8 *msg, u16 msglen, 4708270631Sjfv struct i40e_asq_cmd_details *cmd_details) 4709270631Sjfv{ 4710270631Sjfv struct i40e_aq_desc desc; 4711270631Sjfv struct i40e_asq_cmd_details details; 4712270631Sjfv enum i40e_status_code status; 4713270631Sjfv 4714270631Sjfv i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 4715270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 4716270631Sjfv desc.cookie_high = CPU_TO_LE32(v_opcode); 4717270631Sjfv desc.cookie_low = CPU_TO_LE32(v_retval); 4718270631Sjfv if (msglen) { 4719270631Sjfv desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 4720270631Sjfv | I40E_AQ_FLAG_RD)); 4721270631Sjfv if (msglen > I40E_AQ_LARGE_BUF) 4722270631Sjfv desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4723270631Sjfv desc.datalen = CPU_TO_LE16(msglen); 4724270631Sjfv } 4725270631Sjfv if (!cmd_details) { 4726270631Sjfv i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 4727270631Sjfv details.async = TRUE; 4728270631Sjfv cmd_details = &details; 4729270631Sjfv } 4730270631Sjfv status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 4731270631Sjfv msglen, cmd_details); 4732270631Sjfv return status; 4733270631Sjfv} 4734270631Sjfv 4735270631Sjfv/** 4736270631Sjfv * i40e_vf_parse_hw_config 4737270631Sjfv * @hw: pointer to the hardware structure 4738270631Sjfv * @msg: pointer to the virtual channel VF resource structure 4739270631Sjfv * 4740270631Sjfv * Given a VF resource message from the PF, populate the hw struct 4741270631Sjfv * with appropriate information. 4742270631Sjfv **/ 4743270631Sjfvvoid i40e_vf_parse_hw_config(struct i40e_hw *hw, 4744270631Sjfv struct i40e_virtchnl_vf_resource *msg) 4745270631Sjfv{ 4746270631Sjfv struct i40e_virtchnl_vsi_resource *vsi_res; 4747270631Sjfv int i; 4748270631Sjfv 4749270631Sjfv vsi_res = &msg->vsi_res[0]; 4750270631Sjfv 4751270631Sjfv hw->dev_caps.num_vsis = msg->num_vsis; 4752270631Sjfv hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 4753270631Sjfv hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 4754270631Sjfv hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 4755270631Sjfv hw->dev_caps.dcb = msg->vf_offload_flags & 4756270631Sjfv I40E_VIRTCHNL_VF_OFFLOAD_L2; 4757270631Sjfv hw->dev_caps.fcoe = (msg->vf_offload_flags & 4758270631Sjfv I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0; 4759270631Sjfv hw->dev_caps.iwarp = (msg->vf_offload_flags & 4760270631Sjfv I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 4761270631Sjfv for (i = 0; i < msg->num_vsis; i++) { 4762270631Sjfv if (vsi_res->vsi_type == I40E_VSI_SRIOV) { 4763270631Sjfv i40e_memcpy(hw->mac.perm_addr, 4764270631Sjfv vsi_res->default_mac_addr, 4765270631Sjfv I40E_ETH_LENGTH_OF_ADDRESS, 4766270631Sjfv I40E_NONDMA_TO_NONDMA); 4767270631Sjfv i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 4768270631Sjfv I40E_ETH_LENGTH_OF_ADDRESS, 4769270631Sjfv I40E_NONDMA_TO_NONDMA); 4770270631Sjfv } 4771270631Sjfv vsi_res++; 4772270631Sjfv } 4773270631Sjfv} 4774270631Sjfv 4775270631Sjfv/** 4776270631Sjfv * i40e_vf_reset 4777270631Sjfv * @hw: pointer to the hardware structure 4778270631Sjfv * 4779270631Sjfv * Send a VF_RESET message to the PF. Does not wait for response from PF 4780270631Sjfv * as none will be forthcoming. Immediately after calling this function, 4781270631Sjfv * the admin queue should be shut down and (optionally) reinitialized. 4782270631Sjfv **/ 4783270631Sjfvenum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 4784270631Sjfv{ 4785270631Sjfv return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF, 4786270631Sjfv I40E_SUCCESS, NULL, 0, NULL); 4787270631Sjfv} 4788