1270631Sjfv/******************************************************************************
2270631Sjfv
3270631Sjfv  Copyright (c) 2013-2014, Intel Corporation
4270631Sjfv  All rights reserved.
5270631Sjfv
6270631Sjfv  Redistribution and use in source and binary forms, with or without
7270631Sjfv  modification, are permitted provided that the following conditions are met:
8270631Sjfv
9270631Sjfv   1. Redistributions of source code must retain the above copyright notice,
10270631Sjfv      this list of conditions and the following disclaimer.
11270631Sjfv
12270631Sjfv   2. Redistributions in binary form must reproduce the above copyright
13270631Sjfv      notice, this list of conditions and the following disclaimer in the
14270631Sjfv      documentation and/or other materials provided with the distribution.
15270631Sjfv
16270631Sjfv   3. Neither the name of the Intel Corporation nor the names of its
17270631Sjfv      contributors may be used to endorse or promote products derived from
18270631Sjfv      this software without specific prior written permission.
19270631Sjfv
20270631Sjfv  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21270631Sjfv  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22270631Sjfv  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23270631Sjfv  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24270631Sjfv  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25270631Sjfv  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26270631Sjfv  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27270631Sjfv  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28270631Sjfv  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29270631Sjfv  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30270631Sjfv  POSSIBILITY OF SUCH DAMAGE.
31270631Sjfv
32270631Sjfv******************************************************************************/
33270631Sjfv/*$FreeBSD$*/
34270631Sjfv
35270631Sjfv#ifndef _I40E_ADMINQ_H_
36270631Sjfv#define _I40E_ADMINQ_H_
37270631Sjfv
38270631Sjfv#include "i40e_osdep.h"
39270631Sjfv#include "i40e_adminq_cmd.h"
40270631Sjfv
41270631Sjfv#define I40E_ADMINQ_DESC(R, i)   \
42270631Sjfv	(&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
43270631Sjfv
44270631Sjfv#define I40E_ADMINQ_DESC_ALIGNMENT 4096
45270631Sjfv
46270631Sjfvstruct i40e_adminq_ring {
47270631Sjfv	struct i40e_virt_mem dma_head;	/* space for dma structures */
48270631Sjfv	struct i40e_dma_mem desc_buf;	/* descriptor ring memory */
49270631Sjfv	struct i40e_virt_mem cmd_buf;	/* command buffer memory */
50270631Sjfv
51270631Sjfv	union {
52270631Sjfv		struct i40e_dma_mem *asq_bi;
53270631Sjfv		struct i40e_dma_mem *arq_bi;
54270631Sjfv	} r;
55270631Sjfv
56270631Sjfv	u16 count;		/* Number of descriptors */
57270631Sjfv	u16 rx_buf_len;		/* Admin Receive Queue buffer length */
58270631Sjfv
59270631Sjfv	/* used for interrupt processing */
60270631Sjfv	u16 next_to_use;
61270631Sjfv	u16 next_to_clean;
62270631Sjfv
63270631Sjfv	/* used for queue tracking */
64270631Sjfv	u32 head;
65270631Sjfv	u32 tail;
66270631Sjfv	u32 len;
67270631Sjfv	u32 bah;
68270631Sjfv	u32 bal;
69270631Sjfv};
70270631Sjfv
71270631Sjfv/* ASQ transaction details */
72270631Sjfvstruct i40e_asq_cmd_details {
73270631Sjfv	void *callback; /* cast from type I40E_ADMINQ_CALLBACK */
74270631Sjfv	u64 cookie;
75270631Sjfv	u16 flags_ena;
76270631Sjfv	u16 flags_dis;
77270631Sjfv	bool async;
78270631Sjfv	bool postpone;
79270631Sjfv};
80270631Sjfv
81270631Sjfv#define I40E_ADMINQ_DETAILS(R, i)   \
82270631Sjfv	(&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
83270631Sjfv
84270631Sjfv/* ARQ event information */
85270631Sjfvstruct i40e_arq_event_info {
86270631Sjfv	struct i40e_aq_desc desc;
87270631Sjfv	u16 msg_len;
88270631Sjfv	u16 buf_len;
89270631Sjfv	u8 *msg_buf;
90270631Sjfv};
91270631Sjfv
92270631Sjfv/* Admin Queue information */
93270631Sjfvstruct i40e_adminq_info {
94270631Sjfv	struct i40e_adminq_ring arq;    /* receive queue */
95270631Sjfv	struct i40e_adminq_ring asq;    /* send queue */
96270631Sjfv	u32 asq_cmd_timeout;            /* send queue cmd write back timeout*/
97270631Sjfv	u16 num_arq_entries;            /* receive queue depth */
98270631Sjfv	u16 num_asq_entries;            /* send queue depth */
99270631Sjfv	u16 arq_buf_size;               /* receive queue buffer size */
100270631Sjfv	u16 asq_buf_size;               /* send queue buffer size */
101270631Sjfv	u16 fw_maj_ver;                 /* firmware major version */
102270631Sjfv	u16 fw_min_ver;                 /* firmware minor version */
103270631Sjfv	u16 api_maj_ver;                /* api major version */
104270631Sjfv	u16 api_min_ver;                /* api minor version */
105270631Sjfv	bool nvm_busy;
106270631Sjfv	bool nvm_release_on_done;
107270631Sjfv
108270631Sjfv	struct i40e_spinlock asq_spinlock; /* Send queue spinlock */
109270631Sjfv	struct i40e_spinlock arq_spinlock; /* Receive queue spinlock */
110270631Sjfv
111270631Sjfv	/* last status values on send and receive queues */
112270631Sjfv	enum i40e_admin_queue_err asq_last_status;
113270631Sjfv	enum i40e_admin_queue_err arq_last_status;
114270631Sjfv};
115270631Sjfv
116270631Sjfv/* general information */
117270631Sjfv#define I40E_AQ_LARGE_BUF		512
118270631Sjfv#define I40E_ASQ_CMD_TIMEOUT		100  /* msecs */
119270631Sjfv
120270631Sjfvvoid i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
121270631Sjfv				       u16 opcode);
122270631Sjfv
123270631Sjfv#endif /* _I40E_ADMINQ_H_ */
124