ixgbe.h revision 205720
1179055Sjfv/****************************************************************************** 2171384Sjfv 3205720Sjfv Copyright (c) 2001-2010, Intel Corporation 4179055Sjfv All rights reserved. 5179055Sjfv 6179055Sjfv Redistribution and use in source and binary forms, with or without 7179055Sjfv modification, are permitted provided that the following conditions are met: 8179055Sjfv 9179055Sjfv 1. Redistributions of source code must retain the above copyright notice, 10179055Sjfv this list of conditions and the following disclaimer. 11179055Sjfv 12179055Sjfv 2. Redistributions in binary form must reproduce the above copyright 13179055Sjfv notice, this list of conditions and the following disclaimer in the 14179055Sjfv documentation and/or other materials provided with the distribution. 15179055Sjfv 16179055Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17179055Sjfv contributors may be used to endorse or promote products derived from 18179055Sjfv this software without specific prior written permission. 19179055Sjfv 20179055Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21179055Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22179055Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23179055Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24179055Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25179055Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26179055Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27179055Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28179055Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29179055Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30179055Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 205720 2010-03-27 00:21:40Z jfv $*/ 34171384Sjfv 35185352Sjfv 36171384Sjfv#ifndef _IXGBE_H_ 37171384Sjfv#define _IXGBE_H_ 38171384Sjfv 39171384Sjfv 40171384Sjfv#include <sys/param.h> 41171384Sjfv#include <sys/systm.h> 42194875Sjfv#if __FreeBSD_version >= 800000 43194875Sjfv#include <sys/buf_ring.h> 44194875Sjfv#endif 45171384Sjfv#include <sys/mbuf.h> 46171384Sjfv#include <sys/protosw.h> 47171384Sjfv#include <sys/socket.h> 48171384Sjfv#include <sys/malloc.h> 49171384Sjfv#include <sys/kernel.h> 50171384Sjfv#include <sys/module.h> 51171384Sjfv#include <sys/sockio.h> 52171384Sjfv 53171384Sjfv#include <net/if.h> 54171384Sjfv#include <net/if_arp.h> 55171384Sjfv#include <net/bpf.h> 56171384Sjfv#include <net/ethernet.h> 57171384Sjfv#include <net/if_dl.h> 58171384Sjfv#include <net/if_media.h> 59171384Sjfv 60171384Sjfv#include <net/bpf.h> 61171384Sjfv#include <net/if_types.h> 62171384Sjfv#include <net/if_vlan_var.h> 63171384Sjfv 64171384Sjfv#include <netinet/in_systm.h> 65171384Sjfv#include <netinet/in.h> 66171384Sjfv#include <netinet/if_ether.h> 67171384Sjfv#include <netinet/ip.h> 68171384Sjfv#include <netinet/ip6.h> 69171384Sjfv#include <netinet/tcp.h> 70190873Sjfv#include <netinet/tcp_lro.h> 71171384Sjfv#include <netinet/udp.h> 72171384Sjfv 73171384Sjfv#include <machine/in_cksum.h> 74171384Sjfv 75171384Sjfv#include <sys/bus.h> 76171384Sjfv#include <machine/bus.h> 77171384Sjfv#include <sys/rman.h> 78171384Sjfv#include <machine/resource.h> 79171384Sjfv#include <vm/vm.h> 80171384Sjfv#include <vm/pmap.h> 81171384Sjfv#include <machine/clock.h> 82171384Sjfv#include <dev/pci/pcivar.h> 83171384Sjfv#include <dev/pci/pcireg.h> 84171384Sjfv#include <sys/proc.h> 85171384Sjfv#include <sys/sysctl.h> 86171384Sjfv#include <sys/endian.h> 87171384Sjfv#include <sys/taskqueue.h> 88179055Sjfv#include <sys/pcpu.h> 89194875Sjfv#include <sys/smp.h> 90194875Sjfv#include <machine/smp.h> 91171384Sjfv 92194875Sjfv#ifdef IXGBE_IEEE1588 93194875Sjfv#include <sys/ieee1588.h> 94190873Sjfv#endif 95190873Sjfv 96171384Sjfv#include "ixgbe_api.h" 97171384Sjfv 98171384Sjfv/* Tunables */ 99171384Sjfv 100171384Sjfv/* 101172043Sjfv * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 102171384Sjfv * number of transmit descriptors allocated by the driver. Increasing this 103171384Sjfv * value allows the driver to queue more transmits. Each descriptor is 16 104172043Sjfv * bytes. Performance tests have show the 2K value to be optimal for top 105172043Sjfv * performance. 106171384Sjfv */ 107190873Sjfv#define DEFAULT_TXD 1024 108172043Sjfv#define PERFORM_TXD 2048 109171384Sjfv#define MAX_TXD 4096 110171384Sjfv#define MIN_TXD 64 111171384Sjfv 112171384Sjfv/* 113172043Sjfv * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 114172043Sjfv * number of receive descriptors allocated for each RX queue. Increasing this 115171384Sjfv * value allows the driver to buffer more incoming packets. Each descriptor 116172043Sjfv * is 16 bytes. A receive buffer is also allocated for each descriptor. 117171384Sjfv * 118172043Sjfv * Note: with 8 rings and a dual port card, it is possible to bump up 119172043Sjfv * against the system mbuf pool limit, you can tune nmbclusters 120172043Sjfv * to adjust for this. 121171384Sjfv */ 122190873Sjfv#define DEFAULT_RXD 1024 123172043Sjfv#define PERFORM_RXD 2048 124171384Sjfv#define MAX_RXD 4096 125171384Sjfv#define MIN_RXD 64 126171384Sjfv 127172043Sjfv/* Alignment for rings */ 128172043Sjfv#define DBA_ALIGN 128 129172043Sjfv 130171384Sjfv/* 131171384Sjfv * This parameter controls the maximum no of times the driver will loop in 132171384Sjfv * the isr. Minimum Value = 1 133171384Sjfv */ 134185352Sjfv#define MAX_LOOP 10 135171384Sjfv 136171384Sjfv/* 137200239Sjfv * This is the max watchdog interval, ie. the time that can 138200239Sjfv * pass between any two TX clean operations, such only happening 139200239Sjfv * when the TX hardware is functioning. 140171384Sjfv */ 141200239Sjfv#define IXGBE_WATCHDOG (10 * hz) 142171384Sjfv 143171384Sjfv/* 144171384Sjfv * This parameters control when the driver calls the routine to reclaim 145171384Sjfv * transmit descriptors. 146171384Sjfv */ 147171384Sjfv#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 148171384Sjfv#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 149171384Sjfv 150171384Sjfv#define IXGBE_MAX_FRAME_SIZE 0x3F00 151171384Sjfv 152172043Sjfv/* Flow control constants */ 153200239Sjfv#define IXGBE_FC_PAUSE 0xFFFF 154172043Sjfv#define IXGBE_FC_HI 0x20000 155172043Sjfv#define IXGBE_FC_LO 0x10000 156171384Sjfv 157171384Sjfv/* Defines for printing debug information */ 158171384Sjfv#define DEBUG_INIT 0 159171384Sjfv#define DEBUG_IOCTL 0 160171384Sjfv#define DEBUG_HW 0 161171384Sjfv 162171384Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 163171384Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 164171384Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 165171384Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 166171384Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 167171384Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 168171384Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 169171384Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 170171384Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 171171384Sjfv 172171384Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 173190873Sjfv#define IXGBE_82598_SCATTER 100 174190873Sjfv#define IXGBE_82599_SCATTER 32 175185352Sjfv#define MSIX_82598_BAR 3 176185352Sjfv#define MSIX_82599_BAR 4 177171384Sjfv#define IXGBE_TSO_SIZE 65535 178171384Sjfv#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 179205720Sjfv#define IXGBE_RX_HDR 128 180194875Sjfv#define IXGBE_VFTA_SIZE 128 181194875Sjfv#define IXGBE_BR_SIZE 4096 182171384Sjfv#define CSUM_OFFLOAD 7 /* Bits in csum flags */ 183171384Sjfv 184172043Sjfv/* For 6.X code compatibility */ 185190873Sjfv#if !defined(ETHER_BPF_MTAP) 186190873Sjfv#define ETHER_BPF_MTAP BPF_MTAP 187190873Sjfv#endif 188190873Sjfv 189172043Sjfv#if __FreeBSD_version < 700000 190172043Sjfv#define CSUM_TSO 0 191172043Sjfv#define IFCAP_TSO4 0 192172043Sjfv#endif 193172043Sjfv 194171384Sjfv/* 195171384Sjfv * Interrupt Moderation parameters 196171384Sjfv */ 197185352Sjfv#define IXGBE_LOW_LATENCY 128 198185352Sjfv#define IXGBE_AVE_LATENCY 400 199185352Sjfv#define IXGBE_BULK_LATENCY 1200 200185352Sjfv#define IXGBE_LINK_ITR 2000 201171384Sjfv 202185352Sjfv/* Header split args for get_bug */ 203185352Sjfv#define IXGBE_CLEAN_HDR 1 204185352Sjfv#define IXGBE_CLEAN_PKT 2 205185352Sjfv#define IXGBE_CLEAN_ALL 3 206185352Sjfv 207171384Sjfv/* 208185352Sjfv ***************************************************************************** 209171384Sjfv * vendor_info_array 210171384Sjfv * 211171384Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 212171384Sjfv * should load. 213171384Sjfv * 214185352Sjfv ***************************************************************************** 215171384Sjfv */ 216171384Sjfvtypedef struct _ixgbe_vendor_info_t { 217171384Sjfv unsigned int vendor_id; 218171384Sjfv unsigned int device_id; 219171384Sjfv unsigned int subvendor_id; 220171384Sjfv unsigned int subdevice_id; 221171384Sjfv unsigned int index; 222185352Sjfv} ixgbe_vendor_info_t; 223171384Sjfv 224171384Sjfv 225171384Sjfvstruct ixgbe_tx_buf { 226190873Sjfv u32 eop_index; 227171384Sjfv struct mbuf *m_head; 228171384Sjfv bus_dmamap_t map; 229171384Sjfv}; 230171384Sjfv 231171384Sjfvstruct ixgbe_rx_buf { 232171384Sjfv struct mbuf *m_head; 233185352Sjfv struct mbuf *m_pack; 234205720Sjfv struct mbuf *fmp; 235185352Sjfv bus_dmamap_t map; 236171384Sjfv}; 237171384Sjfv 238171384Sjfv/* 239171384Sjfv * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 240171384Sjfv */ 241171384Sjfvstruct ixgbe_dma_alloc { 242171384Sjfv bus_addr_t dma_paddr; 243171384Sjfv caddr_t dma_vaddr; 244171384Sjfv bus_dma_tag_t dma_tag; 245171384Sjfv bus_dmamap_t dma_map; 246171384Sjfv bus_dma_segment_t dma_seg; 247171384Sjfv bus_size_t dma_size; 248171384Sjfv int dma_nseg; 249171384Sjfv}; 250171384Sjfv 251171384Sjfv/* 252205720Sjfv** Driver queue struct: this is the interrupt container 253205720Sjfv** for the associated tx and rx ring. 254205720Sjfv*/ 255205720Sjfvstruct ix_queue { 256205720Sjfv struct adapter *adapter; 257205720Sjfv u32 msix; /* This queue's MSIX vector */ 258205720Sjfv u32 eims; /* This queue's EIMS bit */ 259205720Sjfv u32 eitr_setting; 260205720Sjfv struct resource *res; 261205720Sjfv void *tag; 262205720Sjfv struct tx_ring *txr; 263205720Sjfv struct rx_ring *rxr; 264205720Sjfv struct task que_task; 265205720Sjfv struct taskqueue *tq; 266205720Sjfv u64 irqs; 267205720Sjfv}; 268205720Sjfv 269205720Sjfv/* 270205720Sjfv * The transmit ring, one per queue 271171384Sjfv */ 272171384Sjfvstruct tx_ring { 273171384Sjfv struct adapter *adapter; 274179055Sjfv struct mtx tx_mtx; 275171384Sjfv u32 me; 276200239Sjfv bool watchdog_check; 277200239Sjfv int watchdog_time; 278171384Sjfv union ixgbe_adv_tx_desc *tx_base; 279171384Sjfv struct ixgbe_dma_alloc txdma; 280200239Sjfv u32 next_avail_desc; 281200239Sjfv u32 next_to_clean; 282171384Sjfv struct ixgbe_tx_buf *tx_buffers; 283179055Sjfv volatile u16 tx_avail; 284179055Sjfv u32 txd_cmd; 285171384Sjfv bus_dma_tag_t txtag; 286185352Sjfv char mtx_name[16]; 287194875Sjfv#if __FreeBSD_version >= 800000 288194875Sjfv struct buf_ring *br; 289194875Sjfv#endif 290200239Sjfv#ifdef IXGBE_FDIR 291200239Sjfv u16 atr_sample; 292200239Sjfv u16 atr_count; 293200239Sjfv#endif 294205720Sjfv u32 bytes; /* used for AIM */ 295205720Sjfv u32 packets; 296179055Sjfv /* Soft Stats */ 297205720Sjfv u64 no_desc_avail; 298185352Sjfv u64 total_packets; 299171384Sjfv}; 300171384Sjfv 301171384Sjfv 302171384Sjfv/* 303171384Sjfv * The Receive ring, one per rx queue 304171384Sjfv */ 305171384Sjfvstruct rx_ring { 306179055Sjfv struct adapter *adapter; 307179055Sjfv struct mtx rx_mtx; 308179055Sjfv u32 me; 309179055Sjfv union ixgbe_adv_rx_desc *rx_base; 310179055Sjfv struct ixgbe_dma_alloc rxdma; 311179055Sjfv struct lro_ctrl lro; 312194875Sjfv bool lro_enabled; 313194875Sjfv bool hdr_split; 314200239Sjfv bool hw_rsc; 315205720Sjfv bool discard; 316205720Sjfv u32 next_to_refresh; 317205720Sjfv u32 next_to_check; 318205720Sjfv char mtx_name[16]; 319179055Sjfv struct ixgbe_rx_buf *rx_buffers; 320185352Sjfv bus_dma_tag_t rxtag; 321185352Sjfv bus_dmamap_t spare_map; 322185352Sjfv 323185352Sjfv u32 bytes; /* Used for AIM calc */ 324205720Sjfv u32 packets; 325185352Sjfv 326171384Sjfv /* Soft stats */ 327179055Sjfv u64 rx_irq; 328185352Sjfv u64 rx_split_packets; 329185352Sjfv u64 rx_packets; 330185352Sjfv u64 rx_bytes; 331205720Sjfv u64 rx_discarded; 332200239Sjfv u64 rsc_num; 333200239Sjfv#ifdef IXGBE_FDIR 334200239Sjfv u64 flm; 335200239Sjfv#endif 336171384Sjfv}; 337171384Sjfv 338171384Sjfv/* Our adapter structure */ 339171384Sjfvstruct adapter { 340205720Sjfv struct ifnet *ifp; 341205720Sjfv struct ixgbe_hw hw; 342171384Sjfv 343171384Sjfv struct ixgbe_osdep osdep; 344205720Sjfv struct device *dev; 345171384Sjfv 346205720Sjfv struct resource *pci_mem; 347205720Sjfv struct resource *msix_mem; 348179055Sjfv 349171384Sjfv /* 350194875Sjfv * Interrupt resources: this set is 351194875Sjfv * either used for legacy, or for Link 352194875Sjfv * when doing MSIX 353171384Sjfv */ 354205720Sjfv void *tag; 355205720Sjfv struct resource *res; 356171384Sjfv 357205720Sjfv struct ifmedia media; 358205720Sjfv struct callout timer; 359205720Sjfv int msix; 360205720Sjfv int if_flags; 361179055Sjfv 362205720Sjfv struct mtx core_mtx; 363179055Sjfv 364205720Sjfv eventhandler_tag vlan_attach; 365205720Sjfv eventhandler_tag vlan_detach; 366194875Sjfv 367205720Sjfv u16 num_vlans; 368205720Sjfv u16 num_queues; 369194875Sjfv 370171384Sjfv /* Info about the board itself */ 371205720Sjfv u32 optics; 372205720Sjfv bool link_active; 373205720Sjfv u16 max_frame_size; 374205720Sjfv u32 link_speed; 375205720Sjfv bool link_up; 376205720Sjfv u32 linkvec; 377171384Sjfv 378185352Sjfv /* Mbuf cluster size */ 379205720Sjfv u32 rx_mbuf_sz; 380171384Sjfv 381190873Sjfv /* Support for pluggable optics */ 382205720Sjfv bool sfp_probe; 383205720Sjfv struct task link_task; /* Link tasklet */ 384205720Sjfv struct task mod_task; /* SFP tasklet */ 385205720Sjfv struct task msf_task; /* Multispeed Fiber */ 386200239Sjfv#ifdef IXGBE_FDIR 387200239Sjfv int fdir_reinit; 388200239Sjfv struct task fdir_task; 389200239Sjfv#endif 390190873Sjfv struct taskqueue *tq; 391185352Sjfv 392171384Sjfv /* 393205720Sjfv ** Queues: 394205720Sjfv ** This is the irq holder, it has 395205720Sjfv ** and RX/TX pair or rings associated 396205720Sjfv ** with it. 397205720Sjfv */ 398205720Sjfv struct ix_queue *queues; 399205720Sjfv 400205720Sjfv /* 401171384Sjfv * Transmit rings: 402171384Sjfv * Allocated at run time, an array of rings. 403171384Sjfv */ 404205720Sjfv struct tx_ring *tx_rings; 405205720Sjfv int num_tx_desc; 406171384Sjfv 407171384Sjfv /* 408171384Sjfv * Receive rings: 409171384Sjfv * Allocated at run time, an array of rings. 410171384Sjfv */ 411205720Sjfv struct rx_ring *rx_rings; 412205720Sjfv int num_rx_desc; 413205720Sjfv u64 que_mask; 414205720Sjfv u32 rx_process_limit; 415171384Sjfv 416171384Sjfv /* Misc stats maintained by the driver */ 417205720Sjfv unsigned long dropped_pkts; 418205720Sjfv unsigned long mbuf_defrag_failed; 419205720Sjfv unsigned long mbuf_header_failed; 420205720Sjfv unsigned long mbuf_packet_failed; 421205720Sjfv unsigned long no_tx_map_avail; 422205720Sjfv unsigned long no_tx_dma_setup; 423205720Sjfv unsigned long watchdog_events; 424205720Sjfv unsigned long tso_tx; 425205720Sjfv unsigned long link_irq; 426171384Sjfv 427205720Sjfv struct ixgbe_hw_stats stats; 428171384Sjfv}; 429171384Sjfv 430190873Sjfv/* Precision Time Sync (IEEE 1588) defines */ 431190873Sjfv#define ETHERTYPE_IEEE1588 0x88F7 432190873Sjfv#define PICOSECS_PER_TICK 20833 433190873Sjfv#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 434190873Sjfv#define IXGBE_ADVTXD_TSTAMP 0x00080000 435190873Sjfv 436190873Sjfv 437179055Sjfv#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 438179055Sjfv mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 439179055Sjfv#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 440200239Sjfv#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 441200239Sjfv#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 442179055Sjfv#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 443200239Sjfv#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 444200239Sjfv#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 445200239Sjfv#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 446179055Sjfv#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 447179055Sjfv#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 448179055Sjfv#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 449179055Sjfv#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 450179055Sjfv#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 451179055Sjfv 452179055Sjfv 453190873Sjfvstatic inline bool 454190873Sjfvixgbe_is_sfp(struct ixgbe_hw *hw) 455190873Sjfv{ 456190873Sjfv switch (hw->phy.type) { 457190873Sjfv case ixgbe_phy_sfp_avago: 458190873Sjfv case ixgbe_phy_sfp_ftl: 459190873Sjfv case ixgbe_phy_sfp_intel: 460190873Sjfv case ixgbe_phy_sfp_unknown: 461205720Sjfv case ixgbe_phy_sfp_passive_tyco: 462205720Sjfv case ixgbe_phy_sfp_passive_unknown: 463190873Sjfv return TRUE; 464190873Sjfv default: 465190873Sjfv return FALSE; 466190873Sjfv } 467190873Sjfv} 468190873Sjfv 469171384Sjfv#endif /* _IXGBE_H_ */ 470