ixgbe.h revision 190873
1179055Sjfv/****************************************************************************** 2171384Sjfv 3190873Sjfv Copyright (c) 2001-2009, Intel Corporation 4179055Sjfv All rights reserved. 5179055Sjfv 6179055Sjfv Redistribution and use in source and binary forms, with or without 7179055Sjfv modification, are permitted provided that the following conditions are met: 8179055Sjfv 9179055Sjfv 1. Redistributions of source code must retain the above copyright notice, 10179055Sjfv this list of conditions and the following disclaimer. 11179055Sjfv 12179055Sjfv 2. Redistributions in binary form must reproduce the above copyright 13179055Sjfv notice, this list of conditions and the following disclaimer in the 14179055Sjfv documentation and/or other materials provided with the distribution. 15179055Sjfv 16179055Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17179055Sjfv contributors may be used to endorse or promote products derived from 18179055Sjfv this software without specific prior written permission. 19179055Sjfv 20179055Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21179055Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22179055Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23179055Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24179055Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25179055Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26179055Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27179055Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28179055Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29179055Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30179055Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 190873 2009-04-10 00:22:48Z jfv $*/ 34171384Sjfv 35185352Sjfv 36171384Sjfv#ifndef _IXGBE_H_ 37171384Sjfv#define _IXGBE_H_ 38171384Sjfv 39171384Sjfv 40171384Sjfv#include <sys/param.h> 41171384Sjfv#include <sys/systm.h> 42171384Sjfv#include <sys/mbuf.h> 43171384Sjfv#include <sys/protosw.h> 44171384Sjfv#include <sys/socket.h> 45171384Sjfv#include <sys/malloc.h> 46171384Sjfv#include <sys/kernel.h> 47171384Sjfv#include <sys/module.h> 48171384Sjfv#include <sys/sockio.h> 49171384Sjfv 50171384Sjfv#include <net/if.h> 51171384Sjfv#include <net/if_arp.h> 52171384Sjfv#include <net/bpf.h> 53171384Sjfv#include <net/ethernet.h> 54171384Sjfv#include <net/if_dl.h> 55171384Sjfv#include <net/if_media.h> 56171384Sjfv 57171384Sjfv#include <net/bpf.h> 58171384Sjfv#include <net/if_types.h> 59171384Sjfv#include <net/if_vlan_var.h> 60171384Sjfv 61171384Sjfv#include <netinet/in_systm.h> 62171384Sjfv#include <netinet/in.h> 63171384Sjfv#include <netinet/if_ether.h> 64171384Sjfv#include <netinet/ip.h> 65171384Sjfv#include <netinet/ip6.h> 66171384Sjfv#include <netinet/tcp.h> 67190873Sjfv#include <netinet/tcp_lro.h> 68171384Sjfv#include <netinet/udp.h> 69171384Sjfv 70171384Sjfv#include <machine/in_cksum.h> 71171384Sjfv 72171384Sjfv#include <sys/bus.h> 73171384Sjfv#include <machine/bus.h> 74171384Sjfv#include <sys/rman.h> 75171384Sjfv#include <machine/resource.h> 76171384Sjfv#include <vm/vm.h> 77171384Sjfv#include <vm/pmap.h> 78171384Sjfv#include <machine/clock.h> 79171384Sjfv#include <dev/pci/pcivar.h> 80171384Sjfv#include <dev/pci/pcireg.h> 81171384Sjfv#include <sys/proc.h> 82171384Sjfv#include <sys/sysctl.h> 83171384Sjfv#include <sys/endian.h> 84171384Sjfv#include <sys/taskqueue.h> 85179055Sjfv#include <sys/pcpu.h> 86171384Sjfv 87190873Sjfv#ifdef IXGBE_TIMESYNC 88190873Sjfv#include <sys/ioccom.h> 89190873Sjfv#include <sys/time.h> 90190873Sjfv#endif 91190873Sjfv 92171384Sjfv#include "ixgbe_api.h" 93171384Sjfv 94171384Sjfv/* Tunables */ 95171384Sjfv 96171384Sjfv/* 97172043Sjfv * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 98171384Sjfv * number of transmit descriptors allocated by the driver. Increasing this 99171384Sjfv * value allows the driver to queue more transmits. Each descriptor is 16 100172043Sjfv * bytes. Performance tests have show the 2K value to be optimal for top 101172043Sjfv * performance. 102171384Sjfv */ 103190873Sjfv#define DEFAULT_TXD 1024 104172043Sjfv#define PERFORM_TXD 2048 105171384Sjfv#define MAX_TXD 4096 106171384Sjfv#define MIN_TXD 64 107171384Sjfv 108171384Sjfv/* 109172043Sjfv * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 110172043Sjfv * number of receive descriptors allocated for each RX queue. Increasing this 111171384Sjfv * value allows the driver to buffer more incoming packets. Each descriptor 112172043Sjfv * is 16 bytes. A receive buffer is also allocated for each descriptor. 113171384Sjfv * 114172043Sjfv * Note: with 8 rings and a dual port card, it is possible to bump up 115172043Sjfv * against the system mbuf pool limit, you can tune nmbclusters 116172043Sjfv * to adjust for this. 117171384Sjfv */ 118190873Sjfv#define DEFAULT_RXD 1024 119172043Sjfv#define PERFORM_RXD 2048 120171384Sjfv#define MAX_RXD 4096 121171384Sjfv#define MIN_RXD 64 122171384Sjfv 123172043Sjfv/* Alignment for rings */ 124172043Sjfv#define DBA_ALIGN 128 125172043Sjfv 126171384Sjfv/* 127171384Sjfv * This parameter controls the maximum no of times the driver will loop in 128171384Sjfv * the isr. Minimum Value = 1 129171384Sjfv */ 130185352Sjfv#define MAX_LOOP 10 131171384Sjfv 132171384Sjfv/* 133171384Sjfv * This parameter controls the duration of transmit watchdog timer. 134171384Sjfv */ 135171384Sjfv#define IXGBE_TX_TIMEOUT 5 /* set to 5 seconds */ 136171384Sjfv 137171384Sjfv/* 138171384Sjfv * This parameters control when the driver calls the routine to reclaim 139171384Sjfv * transmit descriptors. 140171384Sjfv */ 141171384Sjfv#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 142171384Sjfv#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 143171384Sjfv 144171384Sjfv#define IXGBE_MAX_FRAME_SIZE 0x3F00 145171384Sjfv 146172043Sjfv/* Flow control constants */ 147172043Sjfv#define IXGBE_FC_PAUSE 0x680 148172043Sjfv#define IXGBE_FC_HI 0x20000 149172043Sjfv#define IXGBE_FC_LO 0x10000 150171384Sjfv 151171384Sjfv/* Defines for printing debug information */ 152171384Sjfv#define DEBUG_INIT 0 153171384Sjfv#define DEBUG_IOCTL 0 154171384Sjfv#define DEBUG_HW 0 155171384Sjfv 156171384Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 157171384Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 158171384Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 159171384Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 160171384Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 161171384Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 162171384Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 163171384Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 164171384Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 165171384Sjfv 166171384Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 167190873Sjfv#define IXGBE_82598_SCATTER 100 168190873Sjfv#define IXGBE_82599_SCATTER 32 169185352Sjfv#define MSIX_82598_BAR 3 170185352Sjfv#define MSIX_82599_BAR 4 171171384Sjfv#define IXGBE_TSO_SIZE 65535 172171384Sjfv#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 173185352Sjfv#define IXGBE_RX_HDR 128 174171384Sjfv#define CSUM_OFFLOAD 7 /* Bits in csum flags */ 175171384Sjfv 176171384Sjfv/* The number of MSIX messages the 82598 supports */ 177171384Sjfv#define IXGBE_MSGS 18 178171384Sjfv 179172043Sjfv/* For 6.X code compatibility */ 180190873Sjfv#if !defined(ETHER_BPF_MTAP) 181190873Sjfv#define ETHER_BPF_MTAP BPF_MTAP 182190873Sjfv#endif 183190873Sjfv 184172043Sjfv#if __FreeBSD_version < 700000 185172043Sjfv#define CSUM_TSO 0 186172043Sjfv#define IFCAP_TSO4 0 187172043Sjfv#endif 188172043Sjfv 189171384Sjfv/* 190171384Sjfv * Interrupt Moderation parameters 191171384Sjfv */ 192185352Sjfv#define IXGBE_LOW_LATENCY 128 193185352Sjfv#define IXGBE_AVE_LATENCY 400 194185352Sjfv#define IXGBE_BULK_LATENCY 1200 195185352Sjfv#define IXGBE_LINK_ITR 2000 196171384Sjfv 197185352Sjfv/* Header split args for get_bug */ 198185352Sjfv#define IXGBE_CLEAN_HDR 1 199185352Sjfv#define IXGBE_CLEAN_PKT 2 200185352Sjfv#define IXGBE_CLEAN_ALL 3 201185352Sjfv 202179055Sjfv/* Used for auto RX queue configuration */ 203179055Sjfvextern int mp_ncpus; 204179055Sjfv 205171384Sjfv/* 206185352Sjfv ***************************************************************************** 207171384Sjfv * vendor_info_array 208171384Sjfv * 209171384Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 210171384Sjfv * should load. 211171384Sjfv * 212185352Sjfv ***************************************************************************** 213171384Sjfv */ 214171384Sjfvtypedef struct _ixgbe_vendor_info_t { 215171384Sjfv unsigned int vendor_id; 216171384Sjfv unsigned int device_id; 217171384Sjfv unsigned int subvendor_id; 218171384Sjfv unsigned int subdevice_id; 219171384Sjfv unsigned int index; 220185352Sjfv} ixgbe_vendor_info_t; 221171384Sjfv 222171384Sjfv 223171384Sjfvstruct ixgbe_tx_buf { 224190873Sjfv u32 eop_index; 225171384Sjfv struct mbuf *m_head; 226171384Sjfv bus_dmamap_t map; 227171384Sjfv}; 228171384Sjfv 229171384Sjfvstruct ixgbe_rx_buf { 230171384Sjfv struct mbuf *m_head; 231185352Sjfv struct mbuf *m_pack; 232185352Sjfv bus_dmamap_t map; 233171384Sjfv}; 234171384Sjfv 235171384Sjfv/* 236171384Sjfv * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 237171384Sjfv */ 238171384Sjfvstruct ixgbe_dma_alloc { 239171384Sjfv bus_addr_t dma_paddr; 240171384Sjfv caddr_t dma_vaddr; 241171384Sjfv bus_dma_tag_t dma_tag; 242171384Sjfv bus_dmamap_t dma_map; 243171384Sjfv bus_dma_segment_t dma_seg; 244171384Sjfv bus_size_t dma_size; 245171384Sjfv int dma_nseg; 246171384Sjfv}; 247171384Sjfv 248171384Sjfv/* 249171384Sjfv * The transmit ring, one per tx queue 250171384Sjfv */ 251171384Sjfvstruct tx_ring { 252171384Sjfv struct adapter *adapter; 253179055Sjfv struct mtx tx_mtx; 254171384Sjfv u32 me; 255179055Sjfv u32 msix; 256179055Sjfv u32 eims; 257179055Sjfv u32 watchdog_timer; 258171384Sjfv union ixgbe_adv_tx_desc *tx_base; 259179055Sjfv volatile u32 tx_hwb; 260171384Sjfv struct ixgbe_dma_alloc txdma; 261179055Sjfv struct task tx_task; 262179055Sjfv struct taskqueue *tq; 263179055Sjfv u32 next_avail_tx_desc; 264179055Sjfv u32 next_tx_to_clean; 265171384Sjfv struct ixgbe_tx_buf *tx_buffers; 266179055Sjfv volatile u16 tx_avail; 267179055Sjfv u32 txd_cmd; 268171384Sjfv bus_dma_tag_t txtag; 269185352Sjfv char mtx_name[16]; 270179055Sjfv /* Soft Stats */ 271179055Sjfv u32 no_tx_desc_avail; 272179055Sjfv u32 no_tx_desc_late; 273179055Sjfv u64 tx_irq; 274185352Sjfv u64 total_packets; 275171384Sjfv}; 276171384Sjfv 277171384Sjfv 278171384Sjfv/* 279171384Sjfv * The Receive ring, one per rx queue 280171384Sjfv */ 281171384Sjfvstruct rx_ring { 282179055Sjfv struct adapter *adapter; 283179055Sjfv struct mtx rx_mtx; 284179055Sjfv u32 me; 285179055Sjfv u32 msix; 286179055Sjfv u32 eims; 287179055Sjfv u32 payload; 288179055Sjfv struct task rx_task; 289179055Sjfv struct taskqueue *tq; 290179055Sjfv union ixgbe_adv_rx_desc *rx_base; 291179055Sjfv struct ixgbe_dma_alloc rxdma; 292179055Sjfv struct lro_ctrl lro; 293179055Sjfv unsigned int last_cleaned; 294179055Sjfv unsigned int next_to_check; 295179055Sjfv struct ixgbe_rx_buf *rx_buffers; 296185352Sjfv bus_dma_tag_t rxtag; 297185352Sjfv bus_dmamap_t spare_map; 298179055Sjfv struct mbuf *fmp; 299179055Sjfv struct mbuf *lmp; 300185352Sjfv char mtx_name[16]; 301185352Sjfv 302185352Sjfv u32 bytes; /* Used for AIM calc */ 303185352Sjfv u32 eitr_setting; 304185352Sjfv 305171384Sjfv /* Soft stats */ 306179055Sjfv u64 rx_irq; 307185352Sjfv u64 rx_split_packets; 308185352Sjfv u64 rx_packets; 309185352Sjfv u64 rx_bytes; 310171384Sjfv}; 311171384Sjfv 312171384Sjfv/* Our adapter structure */ 313171384Sjfvstruct adapter { 314171384Sjfv struct ifnet *ifp; 315171384Sjfv struct ixgbe_hw hw; 316171384Sjfv 317171384Sjfv struct ixgbe_osdep osdep; 318171384Sjfv struct device *dev; 319171384Sjfv 320179055Sjfv struct resource *pci_mem; 321179055Sjfv struct resource *msix_mem; 322179055Sjfv 323171384Sjfv /* 324171384Sjfv * Interrupt resources: 325171384Sjfv */ 326171384Sjfv void *tag[IXGBE_MSGS]; 327171384Sjfv struct resource *res[IXGBE_MSGS]; 328171384Sjfv int rid[IXGBE_MSGS]; 329171384Sjfv 330171384Sjfv struct ifmedia media; 331171384Sjfv struct callout timer; 332171384Sjfv int msix; 333171384Sjfv int if_flags; 334179055Sjfv 335172043Sjfv struct mtx core_mtx; 336179055Sjfv 337171384Sjfv /* Info about the board itself */ 338179055Sjfv u32 part_num; 339185352Sjfv u32 optics; 340179055Sjfv bool link_active; 341179055Sjfv u16 max_frame_size; 342179055Sjfv u32 link_speed; 343190873Sjfv bool link_up; 344185352Sjfv u32 linkvec; 345179055Sjfv u32 tx_int_delay; 346179055Sjfv u32 tx_abs_int_delay; 347179055Sjfv u32 rx_int_delay; 348179055Sjfv u32 rx_abs_int_delay; 349171384Sjfv 350185352Sjfv /* Mbuf cluster size */ 351185352Sjfv u32 rx_mbuf_sz; 352171384Sjfv 353190873Sjfv /* Support for pluggable optics */ 354185352Sjfv bool sfp_probe; 355190873Sjfv struct task link_task; /* Link tasklet */ 356190873Sjfv struct task mod_task; /* SFP tasklet */ 357190873Sjfv struct task msf_task; /* Multispeed Fiber tasklet */ 358190873Sjfv struct taskqueue *tq; 359185352Sjfv 360171384Sjfv /* 361171384Sjfv * Transmit rings: 362171384Sjfv * Allocated at run time, an array of rings. 363171384Sjfv */ 364171384Sjfv struct tx_ring *tx_rings; 365171384Sjfv int num_tx_desc; 366171384Sjfv int num_tx_queues; 367171384Sjfv 368171384Sjfv /* 369171384Sjfv * Receive rings: 370171384Sjfv * Allocated at run time, an array of rings. 371171384Sjfv */ 372171384Sjfv struct rx_ring *rx_rings; 373171384Sjfv int num_rx_desc; 374171384Sjfv int num_rx_queues; 375185352Sjfv u32 rx_mask; 376179055Sjfv u32 rx_process_limit; 377171384Sjfv 378190873Sjfv#ifdef IXGBE_TIMESYNC 379190873Sjfv u64 last_stamp; 380190873Sjfv u64 last_sec; 381190873Sjfv u32 last_ns; 382190873Sjfv#endif 383190873Sjfv 384171384Sjfv /* Misc stats maintained by the driver */ 385171384Sjfv unsigned long dropped_pkts; 386185352Sjfv unsigned long mbuf_defrag_failed; 387185352Sjfv unsigned long mbuf_header_failed; 388185352Sjfv unsigned long mbuf_packet_failed; 389171384Sjfv unsigned long no_tx_map_avail; 390171384Sjfv unsigned long no_tx_dma_setup; 391171384Sjfv unsigned long watchdog_events; 392171384Sjfv unsigned long tso_tx; 393179055Sjfv unsigned long link_irq; 394171384Sjfv 395171384Sjfv struct ixgbe_hw_stats stats; 396171384Sjfv}; 397171384Sjfv 398190873Sjfv#ifdef IXGBE_TIMESYNC 399190873Sjfv/* Precision Time Sync (IEEE 1588) defines */ 400190873Sjfv#define ETHERTYPE_IEEE1588 0x88F7 401190873Sjfv#define PICOSECS_PER_TICK 20833 402190873Sjfv#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 403190873Sjfv#define IXGBE_ADVTXD_TSTAMP 0x00080000 404190873Sjfv 405190873Sjfv/* TIMESYNC IOCTL defines */ 406190873Sjfv#define IXGBE_TIMESYNC_READTS _IOWR('i', 127, struct ixgbe_tsync_read) 407190873Sjfv#define IXGBE_TIMESTAMP 5 /* A unique return value */ 408190873Sjfv 409190873Sjfv/* Used in the READTS IOCTL */ 410190873Sjfvstruct ixgbe_tsync_read { 411190873Sjfv int read_current_time; 412190873Sjfv struct timespec system_time; 413190873Sjfv u64 network_time; 414190873Sjfv u64 rx_stamp; 415190873Sjfv u64 tx_stamp; 416190873Sjfv u16 seqid; 417190873Sjfv unsigned char srcid[6]; 418190873Sjfv int rx_valid; 419190873Sjfv int tx_valid; 420190873Sjfv}; 421190873Sjfv 422190873Sjfv#endif /* IXGBE_TIMESYNC */ 423190873Sjfv 424179055Sjfv#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 425179055Sjfv mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 426179055Sjfv#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 427179055Sjfv#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 428179055Sjfv#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 429179055Sjfv#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 430179055Sjfv#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 431190873Sjfv#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 432179055Sjfv#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 433179055Sjfv#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 434179055Sjfv#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 435179055Sjfv#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 436179055Sjfv#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 437179055Sjfv#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 438179055Sjfv 439179055Sjfv 440190873Sjfvstatic inline bool 441190873Sjfvixgbe_is_sfp(struct ixgbe_hw *hw) 442190873Sjfv{ 443190873Sjfv switch (hw->phy.type) { 444190873Sjfv case ixgbe_phy_sfp_avago: 445190873Sjfv case ixgbe_phy_sfp_ftl: 446190873Sjfv case ixgbe_phy_sfp_intel: 447190873Sjfv case ixgbe_phy_sfp_unknown: 448190873Sjfv case ixgbe_phy_tw_tyco: 449190873Sjfv case ixgbe_phy_tw_unknown: 450190873Sjfv return TRUE; 451190873Sjfv default: 452190873Sjfv return FALSE; 453190873Sjfv } 454190873Sjfv} 455190873Sjfv 456171384Sjfv#endif /* _IXGBE_H_ */ 457