iicbus_if.m revision 41012
138774Snsouch#
238774Snsouch# Copyright (c) 1998 Nicolas Souchu
338774Snsouch# All rights reserved.
438774Snsouch#
538774Snsouch# Redistribution and use in source and binary forms, with or without
638774Snsouch# modification, are permitted provided that the following conditions
738774Snsouch# are met:
838774Snsouch# 1. Redistributions of source code must retain the above copyright
938774Snsouch#    notice, this list of conditions and the following disclaimer.
1038774Snsouch# 2. Redistributions in binary form must reproduce the above copyright
1138774Snsouch#    notice, this list of conditions and the following disclaimer in the
1238774Snsouch#    documentation and/or other materials provided with the distribution.
1338774Snsouch#
1438774Snsouch# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
1538774Snsouch# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1638774Snsouch# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1738774Snsouch# ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
1838774Snsouch# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
1938774Snsouch# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2038774Snsouch# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2138774Snsouch# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2238774Snsouch# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2338774Snsouch# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2438774Snsouch# SUCH DAMAGE.
2538774Snsouch#
2641012Snsouch#	$Id: iicbus_if.m,v 1.2 1998/10/31 11:31:07 nsouch Exp $
2738774Snsouch#
2838774Snsouch
2941012SnsouchINTERFACE iicbus;
3038774Snsouch
3138774Snsouch#
3240782Snsouch# Interpret interrupt
3338774Snsouch#
3438774SnsouchMETHOD int intr {
3538774Snsouch	device_t dev;
3638774Snsouch	int event;
3738774Snsouch	char *buf;
3838774Snsouch};
3938774Snsouch
4038774Snsouch#
4140782Snsouch# iicbus callback
4240782Snsouch#
4340782SnsouchMETHOD int callback {
4440782Snsouch	device_t dev;
4540782Snsouch	int index;
4640782Snsouch	caddr_t data;
4740782Snsouch};
4840782Snsouch
4940782Snsouch#
5038774Snsouch# Send REPEATED_START condition
5138774Snsouch#
5238774SnsouchMETHOD int repeated_start {
5338774Snsouch	device_t dev;
5438774Snsouch	u_char slave;
5540782Snsouch	int timeout;
5638774Snsouch};
5738774Snsouch
5838774Snsouch#
5938774Snsouch# Send START condition
6038774Snsouch#
6138774SnsouchMETHOD int start {
6238774Snsouch	device_t dev;
6338774Snsouch	u_char slave;
6440782Snsouch	int timeout;
6538774Snsouch};
6638774Snsouch
6738774Snsouch#
6838774Snsouch# Send STOP condition
6938774Snsouch#
7038774SnsouchMETHOD int stop {
7138774Snsouch	device_t dev;
7238774Snsouch};
7338774Snsouch
7438774Snsouch#
7538774Snsouch# Read from I2C bus
7638774Snsouch#
7738774SnsouchMETHOD int read {
7838774Snsouch	device_t dev;
7938774Snsouch	char *buf;
8038774Snsouch	int len;
8138774Snsouch	int *bytes;
8240782Snsouch	int last;
8340782Snsouch	int delay;
8438774Snsouch};
8538774Snsouch
8638774Snsouch#
8738774Snsouch# Write to the I2C bus
8838774Snsouch#
8938774SnsouchMETHOD int write {
9038774Snsouch	device_t dev;
9138774Snsouch	char *buf;
9238774Snsouch	int len;
9338774Snsouch	int *bytes;
9440782Snsouch	int timeout;
9538774Snsouch};
9638774Snsouch
9738774Snsouch#
9838774Snsouch# Reset I2C bus
9938774Snsouch#
10038774SnsouchMETHOD int reset {
10138774Snsouch	device_t dev;
10238774Snsouch	u_char speed;
10340782Snsouch	u_char addr;
10440782Snsouch	u_char *oldaddr;
10538774Snsouch};
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