1176772Sraj/*- 2176772Sraj * Copyright (c) 2006 Juniper Networks 3176772Sraj * All rights reserved. 4176772Sraj * 5176772Sraj * Redistribution and use in source and binary forms, with or without 6176772Sraj * modification, are permitted provided that the following conditions 7176772Sraj * are met: 8176772Sraj * 9176772Sraj * 1. Redistributions of source code must retain the above copyright 10176772Sraj * notice, this list of conditions and the following disclaimer. 11176772Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176772Sraj * notice, this list of conditions and the following disclaimer in the 13176772Sraj * documentation and/or other materials provided with the distribution. 14176772Sraj * 15176772Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176772Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176772Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18176772Sraj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19176772Sraj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20176772Sraj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21176772Sraj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22176772Sraj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23176772Sraj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24176772Sraj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176772Sraj * 26176772Sraj * $FreeBSD$ 27176772Sraj */ 28176772Sraj 29176772Sraj#ifndef _DEV_IC_QUICC_H_ 30176772Sraj#define _DEV_IC_QUICC_H_ 31176772Sraj 32176772Sraj/* 33176772Sraj * Device parameter RAM 34176772Sraj */ 35176772Sraj#define QUICC_PRAM_BASE 0x8000 36176772Sraj 37176772Sraj#define QUICC_PRAM_REV_NUM (QUICC_PRAM_BASE + 0xaf0) 38176772Sraj 39176772Sraj/* SCC parameter RAM. */ 40176772Sraj#define QUICC_PRAM_SIZE_SCC 256 41176772Sraj#define QUICC_PRAM_BASE_SCC(u) (QUICC_PRAM_BASE + QUICC_PRAM_SIZE_SCC * (u)) 42176772Sraj 43176772Sraj/* SCC parameters that are common for all modes. */ 44176772Sraj#define QUICC_PRAM_SCC_RBASE(u) (QUICC_PRAM_BASE_SCC(u) + 0x00) 45176772Sraj#define QUICC_PRAM_SCC_TBASE(u) (QUICC_PRAM_BASE_SCC(u) + 0x02) 46176772Sraj#define QUICC_PRAM_SCC_RFCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x04) 47176772Sraj#define QUICC_PRAM_SCC_TFCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x05) 48176772Sraj#define QUICC_PRAM_SCC_MRBLR(u) (QUICC_PRAM_BASE_SCC(u) + 0x06) 49176772Sraj#define QUICC_PRAM_SCC_RBPTR(u) (QUICC_PRAM_BASE_SCC(u) + 0x10) 50176772Sraj#define QUICC_PRAM_SCC_TBPTR(u) (QUICC_PRAM_BASE_SCC(u) + 0x20) 51176772Sraj 52176772Sraj/* 53176772Sraj * SCC parameters that are specific to UART/ASYNC mode. 54176772Sraj */ 55176772Sraj#define QUICC_PRAM_SIZE_SCC_UART 0x68 /* Rounded up. */ 56176772Sraj 57176772Sraj#define QUICC_PRAM_SCC_UART_MAX_IDL(u) (QUICC_PRAM_BASE_SCC(u) + 0x38) 58176772Sraj#define QUICC_PRAM_SCC_UART_IDLC(u) (QUICC_PRAM_BASE_SCC(u) + 0x3a) 59176772Sraj#define QUICC_PRAM_SCC_UART_BRKCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x3c) 60176772Sraj#define QUICC_PRAM_SCC_UART_PAREC(u) (QUICC_PRAM_BASE_SCC(u) + 0x3e) 61176772Sraj#define QUICC_PRAM_SCC_UART_FRMEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x40) 62176772Sraj#define QUICC_PRAM_SCC_UART_NOSEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x42) 63176772Sraj#define QUICC_PRAM_SCC_UART_BRKEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x44) 64176772Sraj#define QUICC_PRAM_SCC_UART_BRKLN(u) (QUICC_PRAM_BASE_SCC(u) + 0x46) 65176772Sraj#define QUICC_PRAM_SCC_UART_UADDR1(u) (QUICC_PRAM_BASE_SCC(u) + 0x48) 66176772Sraj#define QUICC_PRAM_SCC_UART_UADDR2(u) (QUICC_PRAM_BASE_SCC(u) + 0x4a) 67176772Sraj#define QUICC_PRAM_SCC_UART_TOSEQ(u) (QUICC_PRAM_BASE_SCC(u) + 0x4e) 68176772Sraj#define QUICC_PRAM_SCC_UART_CC(u,n) (QUICC_PRAM_BASE_SCC(u) + 0x50 + (n)*2) 69176772Sraj#define QUICC_PRAM_SCC_UART_RCCM(u) (QUICC_PRAM_BASE_SCC(u) + 0x60) 70176772Sraj#define QUICC_PRAM_SCC_UART_RCCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x62) 71176772Sraj#define QUICC_PRAM_SCC_UART_RLBC(u) (QUICC_PRAM_BASE_SCC(u) + 0x64) 72176772Sraj 73176772Sraj/* 74176772Sraj * Interrupt controller. 75176772Sraj */ 76176772Sraj#define QUICC_REG_SICR 0x10c00 77176772Sraj#define QUICC_REG_SIVEC 0x10c04 78176772Sraj#define QUICC_REG_SIPNR_H 0x10c08 79176772Sraj#define QUICC_REG_SIPNR_L 0x10c0c 80176772Sraj#define QUICC_REG_SCPRR_H 0x10c14 81176772Sraj#define QUICC_REG_SCPRR_L 0x10c18 82176772Sraj#define QUICC_REG_SIMR_H 0x10c1c 83176772Sraj#define QUICC_REG_SIMR_L 0x10c20 84176772Sraj#define QUICC_REG_SIEXR 0x10c24 85176772Sraj 86176772Sraj/* 87176772Sraj * System clock control register. 88176772Sraj */ 89176772Sraj#define QUICC_REG_SCCR 0x10c80 90176772Sraj 91176772Sraj/* 92176772Sraj * Baudrate generator registers. 93176772Sraj */ 94176772Sraj#define QUICC_REG_BRG(u) (0x119f0 + ((u) & 3) * 4 - ((u) & 4) * 0x100) 95176772Sraj 96176772Sraj/* 97176772Sraj * SCC registers. 98176772Sraj */ 99176772Sraj#define QUICC_REG_SIZE_SCC 0x20 100176772Sraj#define QUICC_REG_BASE_SCC(u) (0x11a00 + QUICC_REG_SIZE_SCC * (u)) 101176772Sraj 102176772Sraj#define QUICC_REG_SCC_GSMR_L(u) (QUICC_REG_BASE_SCC(u) + 0x00) 103176772Sraj#define QUICC_REG_SCC_GSMR_H(u) (QUICC_REG_BASE_SCC(u) + 0x04) 104176772Sraj#define QUICC_REG_SCC_PSMR(u) (QUICC_REG_BASE_SCC(u) + 0x08) 105176772Sraj#define QUICC_REG_SCC_TODR(u) (QUICC_REG_BASE_SCC(u) + 0x0c) 106176772Sraj#define QUICC_REG_SCC_DSR(u) (QUICC_REG_BASE_SCC(u) + 0x0e) 107176772Sraj#define QUICC_REG_SCC_SCCE(u) (QUICC_REG_BASE_SCC(u) + 0x10) 108176772Sraj#define QUICC_REG_SCC_SCCM(u) (QUICC_REG_BASE_SCC(u) + 0x14) 109176772Sraj#define QUICC_REG_SCC_SCCS(u) (QUICC_REG_BASE_SCC(u) + 0x17) 110176772Sraj 111176772Sraj#endif /* _DEV_IC_QUICC_H_ */ 112