hwpmc_intel.c revision 232366
165675Skris/*- 265675Skris * Copyright (c) 2008 Joseph Koshy 365675Skris * All rights reserved. 465675Skris * 574818Sru * Redistribution and use in source and binary forms, with or without 674818Sru * modification, are permitted provided that the following conditions 765675Skris * are met: 874818Sru * 1. Redistributions of source code must retain the above copyright 974818Sru * notice, this list of conditions and the following disclaimer. 1065675Skris * 2. Redistributions in binary form must reproduce the above copyright 1165675Skris * notice, this list of conditions and the following disclaimer in the 1265675Skris * documentation and/or other materials provided with the distribution. 1374818Sru * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Common code for handling Intel CPUs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_intel.c 232366 2012-03-01 21:23:26Z davide $"); 33 34#include <sys/param.h> 35#include <sys/pmc.h> 36#include <sys/pmckern.h> 37#include <sys/systm.h> 38 39#include <machine/cpu.h> 40#include <machine/cputypes.h> 41#include <machine/md_var.h> 42#include <machine/specialreg.h> 43 44static int 45intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 46{ 47 (void) pc; 48 49 PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 51 52 /* allow the RDPMC instruction if needed */ 53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 54 load_cr4(rcr4() | CR4_PCE); 55 56 PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 57 58 return 0; 59} 60 61static int 62intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 63{ 64 (void) pc; 65 (void) pp; /* can be NULL */ 66 67 PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 68 (uintmax_t) rcr4()); 69 70 /* always turn off the RDPMC instruction */ 71 load_cr4(rcr4() & ~CR4_PCE); 72 73 return 0; 74} 75 76struct pmc_mdep * 77pmc_intel_initialize(void) 78{ 79 struct pmc_mdep *pmc_mdep; 80 enum pmc_cputype cputype; 81 int error, model, nclasses, ncpus; 82 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 91 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 92 93 switch (cpu_id & 0xF00) { 94#if defined(__i386__) 95 case 0x500: /* Pentium family processors */ 96 cputype = PMC_CPU_INTEL_P5; 97 break; 98#endif 99 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 100 switch (model) { 101#if defined(__i386__) 102 case 0x1: 103 cputype = PMC_CPU_INTEL_P6; 104 break; 105 case 0x3: case 0x5: 106 cputype = PMC_CPU_INTEL_PII; 107 break; 108 case 0x6: case 0x16: 109 cputype = PMC_CPU_INTEL_CL; 110 break; 111 case 0x7: case 0x8: case 0xA: case 0xB: 112 cputype = PMC_CPU_INTEL_PIII; 113 break; 114 case 0x9: case 0xD: 115 cputype = PMC_CPU_INTEL_PM; 116 break; 117#endif 118 case 0xE: 119 cputype = PMC_CPU_INTEL_CORE; 120 break; 121 case 0xF: 122 cputype = PMC_CPU_INTEL_CORE2; 123 nclasses = 3; 124 break; 125 case 0x17: 126 cputype = PMC_CPU_INTEL_CORE2EXTREME; 127 nclasses = 3; 128 break; 129 case 0x1C: /* Per Intel document 320047-002. */ 130 cputype = PMC_CPU_INTEL_ATOM; 131 nclasses = 3; 132 break; 133 case 0x1A: 134 case 0x1E: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */ 135 case 0x1F: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */ 136 case 0x2E: 137 cputype = PMC_CPU_INTEL_COREI7; 138 nclasses = 5; 139 break; 140 case 0x25: /* Per Intel document 253669-033US 12/2009. */ 141 case 0x2C: /* Per Intel document 253669-033US 12/2009. */ 142 cputype = PMC_CPU_INTEL_WESTMERE; 143 nclasses = 5; 144 break; 145 case 0x2A: /* Per Intel document 253669-039US 05/2011. */ 146 case 0x2D: /* Per Intel document 253669-041US 12/2011. */ 147 cputype = PMC_CPU_INTEL_SANDYBRIDGE; 148 nclasses = 5; 149 break; 150 } 151 break; 152#if defined(__i386__) || defined(__amd64__) 153 case 0xF00: /* P4 */ 154 if (model >= 0 && model <= 6) /* known models */ 155 cputype = PMC_CPU_INTEL_PIV; 156 break; 157 } 158#endif 159 160 if ((int) cputype == -1) { 161 printf("pmc: Unknown Intel CPU.\n"); 162 return (NULL); 163 } 164 165 pmc_mdep = malloc(sizeof(struct pmc_mdep) + nclasses * 166 sizeof(struct pmc_classdep), M_PMC, M_WAITOK|M_ZERO); 167 168 pmc_mdep->pmd_cputype = cputype; 169 pmc_mdep->pmd_nclass = nclasses; 170 171 pmc_mdep->pmd_switch_in = intel_switch_in; 172 pmc_mdep->pmd_switch_out = intel_switch_out; 173 174 ncpus = pmc_cpu_max(); 175 176 error = pmc_tsc_initialize(pmc_mdep, ncpus); 177 if (error) 178 goto error; 179 180 switch (cputype) { 181#if defined(__i386__) || defined(__amd64__) 182 /* 183 * Intel Core, Core 2 and Atom processors. 184 */ 185 case PMC_CPU_INTEL_ATOM: 186 case PMC_CPU_INTEL_CORE: 187 case PMC_CPU_INTEL_CORE2: 188 case PMC_CPU_INTEL_CORE2EXTREME: 189 case PMC_CPU_INTEL_COREI7: 190 case PMC_CPU_INTEL_SANDYBRIDGE: 191 case PMC_CPU_INTEL_WESTMERE: 192 error = pmc_core_initialize(pmc_mdep, ncpus); 193 break; 194 195 /* 196 * Intel Pentium 4 Processors, and P4/EMT64 processors. 197 */ 198 199 case PMC_CPU_INTEL_PIV: 200 error = pmc_p4_initialize(pmc_mdep, ncpus); 201 202 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + P4_NPMCS, 203 ("[intel,%d] incorrect npmc count %d", __LINE__, 204 pmc_mdep->pmd_npmc)); 205 break; 206#endif 207 208#if defined(__i386__) 209 /* 210 * P6 Family Processors 211 */ 212 213 case PMC_CPU_INTEL_P6: 214 case PMC_CPU_INTEL_CL: 215 case PMC_CPU_INTEL_PII: 216 case PMC_CPU_INTEL_PIII: 217 case PMC_CPU_INTEL_PM: 218 error = pmc_p6_initialize(pmc_mdep, ncpus); 219 220 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + P6_NPMCS, 221 ("[intel,%d] incorrect npmc count %d", __LINE__, 222 pmc_mdep->pmd_npmc)); 223 break; 224 225 /* 226 * Intel Pentium PMCs. 227 */ 228 229 case PMC_CPU_INTEL_P5: 230 error = pmc_p5_initialize(pmc_mdep, ncpus); 231 232 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + PENTIUM_NPMCS, 233 ("[intel,%d] incorrect npmc count %d", __LINE__, 234 pmc_mdep->pmd_npmc)); 235 break; 236#endif 237 238 default: 239 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 240 } 241 242 /* 243 * Init the uncore class. 244 */ 245#if defined(__i386__) || defined(__amd64__) 246 switch (cputype) { 247 /* 248 * Intel Corei7 and Westmere processors. 249 */ 250 case PMC_CPU_INTEL_COREI7: 251 case PMC_CPU_INTEL_SANDYBRIDGE: 252 case PMC_CPU_INTEL_WESTMERE: 253 error = pmc_uncore_initialize(pmc_mdep, ncpus); 254 break; 255 default: 256 break; 257 } 258#endif 259 260 error: 261 if (error) { 262 free(pmc_mdep, M_PMC); 263 pmc_mdep = NULL; 264 } 265 266 return (pmc_mdep); 267} 268 269void 270pmc_intel_finalize(struct pmc_mdep *md) 271{ 272 pmc_tsc_finalize(md); 273 274 switch (md->pmd_cputype) { 275#if defined(__i386__) || defined(__amd64__) 276 case PMC_CPU_INTEL_ATOM: 277 case PMC_CPU_INTEL_CORE: 278 case PMC_CPU_INTEL_CORE2: 279 case PMC_CPU_INTEL_CORE2EXTREME: 280 case PMC_CPU_INTEL_COREI7: 281 case PMC_CPU_INTEL_SANDYBRIDGE: 282 case PMC_CPU_INTEL_WESTMERE: 283 pmc_core_finalize(md); 284 break; 285 286 case PMC_CPU_INTEL_PIV: 287 pmc_p4_finalize(md); 288 break; 289#endif 290#if defined(__i386__) 291 case PMC_CPU_INTEL_P6: 292 case PMC_CPU_INTEL_CL: 293 case PMC_CPU_INTEL_PII: 294 case PMC_CPU_INTEL_PIII: 295 case PMC_CPU_INTEL_PM: 296 pmc_p6_finalize(md); 297 break; 298 case PMC_CPU_INTEL_P5: 299 pmc_p5_finalize(md); 300 break; 301#endif 302 default: 303 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 304 } 305 306 /* 307 * Uncore. 308 */ 309#if defined(__i386__) || defined(__amd64__) 310 switch (md->pmd_cputype) { 311 case PMC_CPU_INTEL_COREI7: 312 case PMC_CPU_INTEL_SANDYBRIDGE: 313 case PMC_CPU_INTEL_WESTMERE: 314 pmc_uncore_finalize(md); 315 break; 316 default: 317 break; 318 } 319#endif 320} 321