hpt27xx_os_bsd.c revision 267457
1130803Smarcel/*- 2130803Smarcel * Copyright (c) 2011 HighPoint Technologies, Inc. 3130803Smarcel * All rights reserved. 4130803Smarcel * 5130803Smarcel * Redistribution and use in source and binary forms, with or without 6130803Smarcel * modification, are permitted provided that the following conditions 7130803Smarcel * are met: 8130803Smarcel * 1. Redistributions of source code must retain the above copyright 9130803Smarcel * notice, this list of conditions and the following disclaimer. 10130803Smarcel * 2. Redistributions in binary form must reproduce the above copyright 11130803Smarcel * notice, this list of conditions and the following disclaimer in the 12130803Smarcel * documentation and/or other materials provided with the distribution. 13130803Smarcel * 14130803Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15130803Smarcel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16130803Smarcel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17130803Smarcel * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18130803Smarcel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19130803Smarcel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20130803Smarcel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21130803Smarcel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22130803Smarcel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23130803Smarcel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24130803Smarcel * SUCH DAMAGE. 25130803Smarcel * 26130803Smarcel * $FreeBSD: stable/10/sys/dev/hpt27xx/hpt27xx_os_bsd.c 267457 2014-06-14 00:44:57Z delphij $ 27130803Smarcel */ 28130803Smarcel 29130803Smarcel#include <dev/hpt27xx/hpt27xx_config.h> 30130803Smarcel 31130803Smarcel#include <dev/hpt27xx/os_bsd.h> 32130803Smarcel 33130803Smarcel/* hardware access */ 34130803SmarcelHPT_U8 os_inb (void *port) { return inb((unsigned)(HPT_UPTR)port); } 35130803SmarcelHPT_U16 os_inw (void *port) { return inw((unsigned)(HPT_UPTR)port); } 36130803SmarcelHPT_U32 os_inl (void *port) { return inl((unsigned)(HPT_UPTR)port); } 37130803Smarcel 38130803Smarcelvoid os_outb (void *port, HPT_U8 value) { outb((unsigned)(HPT_UPTR)port, (value)); } 39130803Smarcelvoid os_outw (void *port, HPT_U16 value) { outw((unsigned)(HPT_UPTR)port, (value)); } 40130803Smarcelvoid os_outl (void *port, HPT_U32 value) { outl((unsigned)(HPT_UPTR)port, (value)); } 41130803Smarcel 42130803Smarcelvoid os_insw (void *port, HPT_U16 *buffer, HPT_U32 count) 43130803Smarcel{ insw((unsigned)(HPT_UPTR)port, (void *)buffer, count); } 44130803Smarcel 45130803Smarcelvoid os_outsw(void *port, HPT_U16 *buffer, HPT_U32 count) 46130803Smarcel{ outsw((unsigned)(HPT_UPTR)port, (void *)buffer, count); } 47130803Smarcel 48130803SmarcelHPT_U32 __dummy_reg = 0; 49130803Smarcel 50130803Smarcel/* PCI configuration space */ 51130803SmarcelHPT_U8 os_pci_readb (void *osext, HPT_U8 offset) 52130803Smarcel{ 53130803Smarcel return pci_read_config(((PHBA)osext)->pcidev, offset, 1); 54130803Smarcel} 55130803Smarcel 56130803SmarcelHPT_U16 os_pci_readw (void *osext, HPT_U8 offset) 57130803Smarcel{ 58130803Smarcel return pci_read_config(((PHBA)osext)->pcidev, offset, 2); 59130803Smarcel} 60130803Smarcel 61130803SmarcelHPT_U32 os_pci_readl (void *osext, HPT_U8 offset) 62130803Smarcel{ 63130803Smarcel return pci_read_config(((PHBA)osext)->pcidev, offset, 4); 64130803Smarcel} 65130803Smarcel 66130803Smarcelvoid os_pci_writeb (void *osext, HPT_U8 offset, HPT_U8 value) 67130803Smarcel{ 68130803Smarcel pci_write_config(((PHBA)osext)->pcidev, offset, value, 1); 69130803Smarcel} 70130803Smarcel 71130803Smarcelvoid os_pci_writew (void *osext, HPT_U8 offset, HPT_U16 value) 72130803Smarcel{ 73130803Smarcel pci_write_config(((PHBA)osext)->pcidev, offset, value, 2); 74130803Smarcel} 75130803Smarcel 76130803Smarcelvoid os_pci_writel (void *osext, HPT_U8 offset, HPT_U32 value) 77130803Smarcel{ 78130803Smarcel pci_write_config(((PHBA)osext)->pcidev, offset, value, 4); 79130803Smarcel} 80130803Smarcel 81130803Smarcel#if __FreeBSD_version < 500043 82130803Smarcel/* PCI space access */ 83130803SmarcelHPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg) 84130803Smarcel{ 85130803Smarcel HPT_U8 v; 86130803Smarcel pcicfgregs pciref; 87130803Smarcel 88130803Smarcel pciref.bus = bus; 89130803Smarcel pciref.slot = dev; 90130803Smarcel pciref.func = func; 91130803Smarcel 92130803Smarcel v = pci_cfgread(&pciref, reg, 1); 93130803Smarcel return v; 94130803Smarcel} 95130803SmarcelHPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg) 96130803Smarcel{ 97130803Smarcel HPT_U32 v; 98130803Smarcel pcicfgregs pciref; 99130803Smarcel 100130803Smarcel pciref.bus = bus; 101130803Smarcel pciref.slot = dev; 102 pciref.func = func; 103 104 v = pci_cfgread(&pciref, reg, 4); 105 return v; 106} 107void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v) 108{ 109 pcicfgregs pciref; 110 111 pciref.hose = -1; 112 pciref.bus = bus; 113 pciref.slot = dev; 114 pciref.func = func; 115 116 pci_cfgwrite(&pciref, reg, v, 1); 117} 118void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v) 119{ 120 pcicfgregs pciref; 121 122 pciref.hose = -1; 123 pciref.bus = bus; 124 pciref.slot = dev; 125 pciref.func = func; 126 127 pci_cfgwrite(&pciref, reg, v, 4); 128}/* PCI space access */ 129#else 130HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg) 131{ 132 return (HPT_U8)pci_cfgregread(bus, dev, func, reg, 1); 133} 134HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg) 135{ 136 return (HPT_U32)pci_cfgregread(bus, dev, func, reg, 4); 137} 138void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v) 139{ 140 pci_cfgregwrite(bus, dev, func, reg, v, 1); 141} 142void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v) 143{ 144 pci_cfgregwrite(bus, dev, func, reg, v, 4); 145}/* PCI space access */ 146#endif 147 148void *os_map_pci_bar( 149 void *osext, 150 int index, 151 HPT_U32 offset, 152 HPT_U32 length 153) 154{ 155 PHBA hba = (PHBA)osext; 156 HPT_U32 base; 157 158 hba->pcibar[index].rid = 0x10 + index * 4; 159 base = pci_read_config(hba->pcidev, hba->pcibar[index].rid, 4); 160 161 if (base & 1) { 162 hba->pcibar[index].type = SYS_RES_IOPORT; 163 hba->pcibar[index].res = bus_alloc_resource(hba->pcidev, 164 hba->pcibar[index].type, &hba->pcibar[index].rid, 0, ~0, length, RF_ACTIVE); 165 hba->pcibar[index].base = (void *)(unsigned long)(base & ~0x1); 166 } else { 167 hba->pcibar[index].type = SYS_RES_MEMORY; 168 hba->pcibar[index].res = bus_alloc_resource(hba->pcidev, 169 hba->pcibar[index].type, &hba->pcibar[index].rid, 0, ~0, length, RF_ACTIVE); 170 hba->pcibar[index].base = (char *)rman_get_virtual(hba->pcibar[index].res) + offset; 171 } 172 173 return hba->pcibar[index].base; 174} 175 176void os_unmap_pci_bar(void *osext, void *base) 177{ 178 PHBA hba = (PHBA)osext; 179 int index; 180 181 for (index=0; index<6; index++) { 182 if (hba->pcibar[index].base==base) { 183 bus_release_resource(hba->pcidev, hba->pcibar[index].type, 184 hba->pcibar[index].rid, hba->pcibar[index].res); 185 hba->pcibar[index].base = 0; 186 return; 187 } 188 } 189} 190 191void freelist_reserve(struct freelist *list, void *osext, HPT_UINT size, HPT_UINT count) 192{ 193 PVBUS_EXT vbus_ext = osext; 194 195 if (vbus_ext->ext_type!=EXT_TYPE_VBUS) 196 vbus_ext = ((PHBA)osext)->vbus_ext; 197 198 list->next = vbus_ext->freelist_head; 199 vbus_ext->freelist_head = list; 200 list->dma = 0; 201 list->size = size; 202 list->head = 0; 203#if DBG 204 list->reserved_count = 205#endif 206 list->count = count; 207} 208 209void *freelist_get(struct freelist *list) 210{ 211 void * result; 212 if (list->count) { 213 HPT_ASSERT(list->head); 214 result = list->head; 215 list->head = *(void **)result; 216 list->count--; 217 return result; 218 } 219 return 0; 220} 221 222void freelist_put(struct freelist * list, void *p) 223{ 224 HPT_ASSERT(list->dma==0); 225 list->count++; 226 *(void **)p = list->head; 227 list->head = p; 228} 229 230void freelist_reserve_dma(struct freelist *list, void *osext, HPT_UINT size, HPT_UINT alignment, HPT_UINT count) 231{ 232 PVBUS_EXT vbus_ext = osext; 233 234 if (vbus_ext->ext_type!=EXT_TYPE_VBUS) 235 vbus_ext = ((PHBA)osext)->vbus_ext; 236 237 list->next = vbus_ext->freelist_dma_head; 238 vbus_ext->freelist_dma_head = list; 239 list->dma = 1; 240 list->alignment = alignment; 241 list->size = size; 242 list->head = 0; 243#if DBG 244 list->reserved_count = 245#endif 246 list->count = count; 247} 248 249void *freelist_get_dma(struct freelist *list, BUS_ADDRESS *busaddr) 250{ 251 void *result; 252 HPT_ASSERT(list->dma); 253 result = freelist_get(list); 254 if (result) 255 *busaddr = *(BUS_ADDRESS *)((void **)result+1); 256 return result; 257} 258 259void freelist_put_dma(struct freelist *list, void *p, BUS_ADDRESS busaddr) 260{ 261 HPT_ASSERT(list->dma); 262 list->count++; 263 *(void **)p = list->head; 264 *(BUS_ADDRESS *)((void **)p+1) = busaddr; 265 list->head = p; 266} 267 268HPT_U32 os_get_stamp(void) 269{ 270 HPT_U32 stamp; 271 do { stamp = random(); } while (stamp==0); 272 return stamp; 273} 274 275void os_stallexec(HPT_U32 microseconds) 276{ 277 DELAY(microseconds); 278} 279 280static void os_timer_for_ldm(void *arg) 281{ 282 PVBUS_EXT vbus_ext = (PVBUS_EXT)arg; 283 ldm_on_timer((PVBUS)vbus_ext->vbus); 284} 285 286void os_request_timer(void * osext, HPT_U32 interval) 287{ 288 PVBUS_EXT vbus_ext = osext; 289 290 HPT_ASSERT(vbus_ext->ext_type==EXT_TYPE_VBUS); 291 292 untimeout(os_timer_for_ldm, vbus_ext, vbus_ext->timer); 293 vbus_ext->timer = timeout(os_timer_for_ldm, vbus_ext, interval * hz / 1000000); 294} 295 296HPT_TIME os_query_time(void) 297{ 298 return ticks * (1000000 / hz); 299} 300 301void os_schedule_task(void *osext, OSM_TASK *task) 302{ 303 PVBUS_EXT vbus_ext = osext; 304 305 HPT_ASSERT(task->next==0); 306 307 if (vbus_ext->tasks==0) 308 vbus_ext->tasks = task; 309 else { 310 OSM_TASK *t = vbus_ext->tasks; 311 while (t->next) t = t->next; 312 t->next = task; 313 } 314 315 if (vbus_ext->worker.ta_context) 316 TASK_ENQUEUE(&vbus_ext->worker); 317} 318 319int os_revalidate_device(void *osext, int id) 320{ 321 322 return 0; 323} 324 325int os_query_remove_device(void *osext, int id) 326{ 327 return 0; 328} 329 330HPT_U8 os_get_vbus_seq(void *osext) 331{ 332 return ((PVBUS_EXT)osext)->sim->path_id; 333} 334 335int os_printk(char *fmt, ...) 336{ 337 va_list args; 338 static char buf[512]; 339 340 va_start(args, fmt); 341 vsnprintf(buf, sizeof(buf), fmt, args); 342 va_end(args); 343 return printf("%s: %s\n", driver_name, buf); 344} 345 346#if DBG 347void os_check_stack(const char *location, int size){} 348 349void __os_dbgbreak(const char *file, int line) 350{ 351 printf("*** break at %s:%d ***", file, line); 352 while (1); 353} 354 355int hpt_dbg_level = 1; 356#endif 357