1104477Ssam/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 2104477Ssam 3139749Simp/*- 4104477Ssam * Invertex AEON / Hifn 7751 driver 5104477Ssam * Copyright (c) 1999 Invertex Inc. All rights reserved. 6104477Ssam * Copyright (c) 1999 Theo de Raadt 7104477Ssam * Copyright (c) 2000-2001 Network Security Technologies, Inc. 8104477Ssam * http://www.netsec.net 9120915Ssam * Copyright (c) 2003 Hifn Inc. 10104477Ssam * 11104477Ssam * This driver is based on a previous driver by Invertex, for which they 12104477Ssam * requested: Please send any comments, feedback, bug-fixes, or feature 13104477Ssam * requests to software@invertex.com. 14104477Ssam * 15104477Ssam * Redistribution and use in source and binary forms, with or without 16104477Ssam * modification, are permitted provided that the following conditions 17104477Ssam * are met: 18104477Ssam * 19104477Ssam * 1. Redistributions of source code must retain the above copyright 20104477Ssam * notice, this list of conditions and the following disclaimer. 21104477Ssam * 2. Redistributions in binary form must reproduce the above copyright 22104477Ssam * notice, this list of conditions and the following disclaimer in the 23104477Ssam * documentation and/or other materials provided with the distribution. 24104477Ssam * 3. The name of the author may not be used to endorse or promote products 25104477Ssam * derived from this software without specific prior written permission. 26104477Ssam * 27104477Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28104477Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29104477Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30104477Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31104477Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32104477Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33104477Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34104477Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35104477Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36104477Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37104477Ssam * 38104477Ssam * Effort sponsored in part by the Defense Advanced Research Projects 39104477Ssam * Agency (DARPA) and Air Force Research Laboratory, Air Force 40104477Ssam * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41104477Ssam */ 42104477Ssam 43119418Sobrien#include <sys/cdefs.h> 44119418Sobrien__FBSDID("$FreeBSD$"); 45119418Sobrien 46104477Ssam/* 47120915Ssam * Driver for various Hifn encryption processors. 48104477Ssam */ 49112124Ssam#include "opt_hifn.h" 50104477Ssam 51104477Ssam#include <sys/param.h> 52104477Ssam#include <sys/systm.h> 53104477Ssam#include <sys/proc.h> 54104477Ssam#include <sys/errno.h> 55104477Ssam#include <sys/malloc.h> 56104477Ssam#include <sys/kernel.h> 57129879Sphk#include <sys/module.h> 58104477Ssam#include <sys/mbuf.h> 59104477Ssam#include <sys/lock.h> 60104477Ssam#include <sys/mutex.h> 61104477Ssam#include <sys/sysctl.h> 62104477Ssam 63104477Ssam#include <vm/vm.h> 64104477Ssam#include <vm/pmap.h> 65104477Ssam 66104477Ssam#include <machine/bus.h> 67104477Ssam#include <machine/resource.h> 68104477Ssam#include <sys/bus.h> 69104477Ssam#include <sys/rman.h> 70104477Ssam 71104477Ssam#include <opencrypto/cryptodev.h> 72104477Ssam#include <sys/random.h> 73167755Ssam#include <sys/kobj.h> 74104477Ssam 75167755Ssam#include "cryptodev_if.h" 76167755Ssam 77119280Simp#include <dev/pci/pcivar.h> 78119280Simp#include <dev/pci/pcireg.h> 79112124Ssam 80112124Ssam#ifdef HIFN_RNDTEST 81112124Ssam#include <dev/rndtest/rndtest.h> 82112124Ssam#endif 83104477Ssam#include <dev/hifn/hifn7751reg.h> 84104477Ssam#include <dev/hifn/hifn7751var.h> 85104477Ssam 86167755Ssam#ifdef HIFN_VULCANDEV 87167755Ssam#include <sys/conf.h> 88167755Ssam#include <sys/uio.h> 89167755Ssam 90167755Ssamstatic struct cdevsw vulcanpk_cdevsw; /* forward declaration */ 91167755Ssam#endif 92167755Ssam 93104477Ssam/* 94104477Ssam * Prototypes and count for the pci_device structure 95104477Ssam */ 96104477Ssamstatic int hifn_probe(device_t); 97104477Ssamstatic int hifn_attach(device_t); 98104477Ssamstatic int hifn_detach(device_t); 99104477Ssamstatic int hifn_suspend(device_t); 100104477Ssamstatic int hifn_resume(device_t); 101188178Simpstatic int hifn_shutdown(device_t); 102104477Ssam 103167755Ssamstatic int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); 104167755Ssamstatic int hifn_freesession(device_t, u_int64_t); 105167755Ssamstatic int hifn_process(device_t, struct cryptop *, int); 106167755Ssam 107104477Ssamstatic device_method_t hifn_methods[] = { 108104477Ssam /* Device interface */ 109104477Ssam DEVMETHOD(device_probe, hifn_probe), 110104477Ssam DEVMETHOD(device_attach, hifn_attach), 111104477Ssam DEVMETHOD(device_detach, hifn_detach), 112104477Ssam DEVMETHOD(device_suspend, hifn_suspend), 113104477Ssam DEVMETHOD(device_resume, hifn_resume), 114104477Ssam DEVMETHOD(device_shutdown, hifn_shutdown), 115104477Ssam 116167755Ssam /* crypto device methods */ 117167755Ssam DEVMETHOD(cryptodev_newsession, hifn_newsession), 118167755Ssam DEVMETHOD(cryptodev_freesession,hifn_freesession), 119167755Ssam DEVMETHOD(cryptodev_process, hifn_process), 120167755Ssam 121227843Smarius DEVMETHOD_END 122104477Ssam}; 123104477Ssamstatic driver_t hifn_driver = { 124104477Ssam "hifn", 125104477Ssam hifn_methods, 126104477Ssam sizeof (struct hifn_softc) 127104477Ssam}; 128104477Ssamstatic devclass_t hifn_devclass; 129104477Ssam 130104477SsamDRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 131105251SmarkmMODULE_DEPEND(hifn, crypto, 1, 1, 1); 132112124Ssam#ifdef HIFN_RNDTEST 133112124SsamMODULE_DEPEND(hifn, rndtest, 1, 1, 1); 134112124Ssam#endif 135104477Ssam 136104477Ssamstatic void hifn_reset_board(struct hifn_softc *, int); 137104477Ssamstatic void hifn_reset_puc(struct hifn_softc *); 138104477Ssamstatic void hifn_puc_wait(struct hifn_softc *); 139104477Ssamstatic int hifn_enable_crypto(struct hifn_softc *); 140104477Ssamstatic void hifn_set_retry(struct hifn_softc *sc); 141104477Ssamstatic void hifn_init_dma(struct hifn_softc *); 142104477Ssamstatic void hifn_init_pci_registers(struct hifn_softc *); 143104477Ssamstatic int hifn_sramsize(struct hifn_softc *); 144104477Ssamstatic int hifn_dramsize(struct hifn_softc *); 145104477Ssamstatic int hifn_ramtype(struct hifn_softc *); 146104477Ssamstatic void hifn_sessions(struct hifn_softc *); 147104477Ssamstatic void hifn_intr(void *); 148104477Ssamstatic u_int hifn_write_command(struct hifn_command *, u_int8_t *); 149104477Ssamstatic u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 150104477Ssamstatic void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 151104477Ssamstatic int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 152104477Ssamstatic int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 153104477Ssamstatic int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 154104477Ssamstatic int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 155104477Ssamstatic int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 156104477Ssamstatic int hifn_init_pubrng(struct hifn_softc *); 157104477Ssamstatic void hifn_rng(void *); 158104477Ssamstatic void hifn_tick(void *); 159104477Ssamstatic void hifn_abort(struct hifn_softc *); 160104477Ssamstatic void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 161104477Ssam 162104477Ssamstatic void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 163104477Ssamstatic void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 164104477Ssam 165131575Sstefanfstatic __inline u_int32_t 166104477SsamREAD_REG_0(struct hifn_softc *sc, bus_size_t reg) 167104477Ssam{ 168104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 169104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 170104477Ssam return (v); 171104477Ssam} 172104477Ssam#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 173104477Ssam 174131575Sstefanfstatic __inline u_int32_t 175104477SsamREAD_REG_1(struct hifn_softc *sc, bus_size_t reg) 176104477Ssam{ 177104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 178104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 179104477Ssam return (v); 180104477Ssam} 181104477Ssam#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 182104477Ssam 183227309Sedstatic SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, 184227309Sed "Hifn driver parameters"); 185109596Ssam 186104477Ssam#ifdef HIFN_DEBUG 187104477Ssamstatic int hifn_debug = 0; 188109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 189109596Ssam 0, "control debugging msgs"); 190104477Ssam#endif 191104477Ssam 192104477Ssamstatic struct hifn_stats hifnstats; 193109596SsamSYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 194109596Ssam hifn_stats, "driver statistics"); 195112121Ssamstatic int hifn_maxbatch = 1; 196109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 197109596Ssam 0, "max ops to batch w/o interrupt"); 198104477Ssam 199104477Ssam/* 200104477Ssam * Probe for a supported device. The PCI vendor and device 201104477Ssam * IDs are used to detect devices we know how to handle. 202104477Ssam */ 203104477Ssamstatic int 204104477Ssamhifn_probe(device_t dev) 205104477Ssam{ 206104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 207104477Ssam pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 208143161Simp return (BUS_PROBE_DEFAULT); 209104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 210104477Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 211104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 212120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 213120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 || 214104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 215143161Simp return (BUS_PROBE_DEFAULT); 216104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 217104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 218143161Simp return (BUS_PROBE_DEFAULT); 219104477Ssam return (ENXIO); 220104477Ssam} 221104477Ssam 222104477Ssamstatic void 223104477Ssamhifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 224104477Ssam{ 225104477Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 226104477Ssam *paddr = segs->ds_addr; 227104477Ssam} 228104477Ssam 229104477Ssamstatic const char* 230104477Ssamhifn_partname(struct hifn_softc *sc) 231104477Ssam{ 232104477Ssam /* XXX sprintf numbers when not decoded */ 233104477Ssam switch (pci_get_vendor(sc->sc_dev)) { 234104477Ssam case PCI_VENDOR_HIFN: 235104477Ssam switch (pci_get_device(sc->sc_dev)) { 236104477Ssam case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 237104477Ssam case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 238104477Ssam case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 239104477Ssam case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 240120915Ssam case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; 241120915Ssam case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; 242104477Ssam } 243104477Ssam return "Hifn unknown-part"; 244104477Ssam case PCI_VENDOR_INVERTEX: 245104477Ssam switch (pci_get_device(sc->sc_dev)) { 246104477Ssam case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 247104477Ssam } 248104477Ssam return "Invertex unknown-part"; 249104477Ssam case PCI_VENDOR_NETSEC: 250104477Ssam switch (pci_get_device(sc->sc_dev)) { 251104477Ssam case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 252104477Ssam } 253104477Ssam return "NetSec unknown-part"; 254104477Ssam } 255104477Ssam return "Unknown-vendor unknown-part"; 256104477Ssam} 257104477Ssam 258112124Ssamstatic void 259112124Ssamdefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 260112124Ssam{ 261256381Smarkm random_harvest(buf, count, count*NBBY/2, RANDOM_PURE_HIFN); 262112124Ssam} 263112124Ssam 264140480Ssamstatic u_int 265140480Ssamcheckmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max) 266140480Ssam{ 267140480Ssam if (v > max) { 268140480Ssam device_printf(dev, "Warning, %s %u out of range, " 269140480Ssam "using max %u\n", what, v, max); 270140480Ssam v = max; 271140480Ssam } else if (v < min) { 272140480Ssam device_printf(dev, "Warning, %s %u out of range, " 273140480Ssam "using min %u\n", what, v, min); 274140480Ssam v = min; 275140480Ssam } 276140480Ssam return v; 277140480Ssam} 278140480Ssam 279104477Ssam/* 280140480Ssam * Select PLL configuration for 795x parts. This is complicated in 281140480Ssam * that we cannot determine the optimal parameters without user input. 282140480Ssam * The reference clock is derived from an external clock through a 283140480Ssam * multiplier. The external clock is either the host bus (i.e. PCI) 284140480Ssam * or an external clock generator. When using the PCI bus we assume 285140480Ssam * the clock is either 33 or 66 MHz; for an external source we cannot 286140480Ssam * tell the speed. 287140480Ssam * 288140480Ssam * PLL configuration is done with a string: "pci" for PCI bus, or "ext" 289140480Ssam * for an external source, followed by the frequency. We calculate 290140480Ssam * the appropriate multiplier and PLL register contents accordingly. 291140480Ssam * When no configuration is given we default to "pci66" since that 292140480Ssam * always will allow the card to work. If a card is using the PCI 293140480Ssam * bus clock and in a 33MHz slot then it will be operating at half 294140480Ssam * speed until the correct information is provided. 295167755Ssam * 296167755Ssam * We use a default setting of "ext66" because according to Mike Ham 297167755Ssam * of HiFn, almost every board in existence has an external crystal 298167755Ssam * populated at 66Mhz. Using PCI can be a problem on modern motherboards, 299167755Ssam * because PCI33 can have clocks from 0 to 33Mhz, and some have 300167755Ssam * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. 301140480Ssam */ 302140480Ssamstatic void 303140480Ssamhifn_getpllconfig(device_t dev, u_int *pll) 304140480Ssam{ 305140480Ssam const char *pllspec; 306140480Ssam u_int freq, mul, fl, fh; 307140480Ssam u_int32_t pllconfig; 308140480Ssam char *nxt; 309140480Ssam 310140480Ssam if (resource_string_value("hifn", device_get_unit(dev), 311140480Ssam "pllconfig", &pllspec)) 312167755Ssam pllspec = "ext66"; 313140480Ssam fl = 33, fh = 66; 314140480Ssam pllconfig = 0; 315140480Ssam if (strncmp(pllspec, "ext", 3) == 0) { 316140480Ssam pllspec += 3; 317140480Ssam pllconfig |= HIFN_PLL_REF_SEL; 318140480Ssam switch (pci_get_device(dev)) { 319140480Ssam case PCI_PRODUCT_HIFN_7955: 320140480Ssam case PCI_PRODUCT_HIFN_7956: 321140480Ssam fl = 20, fh = 100; 322140480Ssam break; 323140480Ssam#ifdef notyet 324140480Ssam case PCI_PRODUCT_HIFN_7954: 325140480Ssam fl = 20, fh = 66; 326140480Ssam break; 327140480Ssam#endif 328140480Ssam } 329140480Ssam } else if (strncmp(pllspec, "pci", 3) == 0) 330140480Ssam pllspec += 3; 331140480Ssam freq = strtoul(pllspec, &nxt, 10); 332140480Ssam if (nxt == pllspec) 333140480Ssam freq = 66; 334140480Ssam else 335140480Ssam freq = checkmaxmin(dev, "frequency", freq, fl, fh); 336140480Ssam /* 337140480Ssam * Calculate multiplier. We target a Fck of 266 MHz, 338140480Ssam * allowing only even values, possibly rounded down. 339140480Ssam * Multipliers > 8 must set the charge pump current. 340140480Ssam */ 341140480Ssam mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); 342140480Ssam pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; 343140480Ssam if (mul > 8) 344140480Ssam pllconfig |= HIFN_PLL_IS; 345140480Ssam *pll = pllconfig; 346140480Ssam} 347140480Ssam 348140480Ssam/* 349104477Ssam * Attach an interface that successfully probed. 350104477Ssam */ 351104477Ssamstatic int 352104477Ssamhifn_attach(device_t dev) 353104477Ssam{ 354104477Ssam struct hifn_softc *sc = device_get_softc(dev); 355104477Ssam caddr_t kva; 356104477Ssam int rseg, rid; 357104477Ssam char rbase; 358104477Ssam u_int16_t ena, rev; 359104477Ssam 360104477Ssam sc->sc_dev = dev; 361104477Ssam 362115748Ssam mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); 363104477Ssam 364104477Ssam /* XXX handle power management */ 365104477Ssam 366104477Ssam /* 367120915Ssam * The 7951 and 795x have a random number generator and 368104477Ssam * public key support; note this. 369104477Ssam */ 370104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 371120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 372120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 373120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) 374104477Ssam sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 375104477Ssam /* 376104477Ssam * The 7811 has a random number generator and 377104477Ssam * we also note it's identity 'cuz of some quirks. 378104477Ssam */ 379104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 380104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 381104477Ssam sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 382104477Ssam 383104477Ssam /* 384120915Ssam * The 795x parts support AES. 385120915Ssam */ 386120915Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 387120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 388140480Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { 389120915Ssam sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; 390140480Ssam /* 391140480Ssam * Select PLL configuration. This depends on the 392140480Ssam * bus and board design and must be manually configured 393140480Ssam * if the default setting is unacceptable. 394140480Ssam */ 395140480Ssam hifn_getpllconfig(dev, &sc->sc_pllconfig); 396140480Ssam } 397120915Ssam 398120915Ssam /* 399104477Ssam * Setup PCI resources. Note that we record the bus 400104477Ssam * tag and handle for each register mapping, this is 401104477Ssam * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 402104477Ssam * and WRITE_REG_1 macros throughout the driver. 403104477Ssam */ 404216519Stijl pci_enable_busmaster(dev); 405216519Stijl 406104477Ssam rid = HIFN_BAR0; 407127135Snjl sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 408127135Snjl RF_ACTIVE); 409104477Ssam if (sc->sc_bar0res == NULL) { 410104477Ssam device_printf(dev, "cannot map bar%d register space\n", 0); 411104477Ssam goto fail_pci; 412104477Ssam } 413104477Ssam sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 414104477Ssam sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 415104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 416104477Ssam 417104477Ssam rid = HIFN_BAR1; 418127135Snjl sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 419127135Snjl RF_ACTIVE); 420104477Ssam if (sc->sc_bar1res == NULL) { 421104477Ssam device_printf(dev, "cannot map bar%d register space\n", 1); 422104477Ssam goto fail_io0; 423104477Ssam } 424104477Ssam sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 425104477Ssam sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 426104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 427104477Ssam 428104477Ssam hifn_set_retry(sc); 429104477Ssam 430104477Ssam /* 431104477Ssam * Setup the area where the Hifn DMA's descriptors 432104477Ssam * and associated data structures. 433104477Ssam */ 434232854Sscottl if (bus_dma_tag_create(bus_get_dma_tag(dev), /* PCI parent */ 435104477Ssam 1, 0, /* alignment,boundary */ 436104477Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 437104477Ssam BUS_SPACE_MAXADDR, /* highaddr */ 438104477Ssam NULL, NULL, /* filter, filterarg */ 439104477Ssam HIFN_MAX_DMALEN, /* maxsize */ 440104477Ssam MAX_SCATTER, /* nsegments */ 441104477Ssam HIFN_MAX_SEGLEN, /* maxsegsize */ 442104477Ssam BUS_DMA_ALLOCNOW, /* flags */ 443117126Sscottl NULL, /* lockfunc */ 444117126Sscottl NULL, /* lockarg */ 445104477Ssam &sc->sc_dmat)) { 446104477Ssam device_printf(dev, "cannot allocate DMA tag\n"); 447104477Ssam goto fail_io1; 448104477Ssam } 449104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 450104477Ssam device_printf(dev, "cannot create dma map\n"); 451104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 452104477Ssam goto fail_io1; 453104477Ssam } 454104477Ssam if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 455104477Ssam device_printf(dev, "cannot alloc dma buffer\n"); 456104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 457104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 458104477Ssam goto fail_io1; 459104477Ssam } 460104477Ssam if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 461104477Ssam sizeof (*sc->sc_dma), 462104477Ssam hifn_dmamap_cb, &sc->sc_dma_physaddr, 463104477Ssam BUS_DMA_NOWAIT)) { 464104477Ssam device_printf(dev, "cannot load dma map\n"); 465104477Ssam bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 466104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 467104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 468104477Ssam goto fail_io1; 469104477Ssam } 470104477Ssam sc->sc_dma = (struct hifn_dma *)kva; 471104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 472104477Ssam 473123824Ssam KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!")); 474123824Ssam KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!")); 475123824Ssam KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!")); 476123824Ssam KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!")); 477104477Ssam 478104477Ssam /* 479104477Ssam * Reset the board and do the ``secret handshake'' 480104477Ssam * to enable the crypto support. Then complete the 481104477Ssam * initialization procedure by setting up the interrupt 482104477Ssam * and hooking in to the system crypto support so we'll 483104477Ssam * get used for system services like the crypto device, 484104477Ssam * IPsec, RNG device, etc. 485104477Ssam */ 486104477Ssam hifn_reset_board(sc, 0); 487104477Ssam 488104477Ssam if (hifn_enable_crypto(sc) != 0) { 489104477Ssam device_printf(dev, "crypto enabling failed\n"); 490104477Ssam goto fail_mem; 491104477Ssam } 492104477Ssam hifn_reset_puc(sc); 493104477Ssam 494104477Ssam hifn_init_dma(sc); 495104477Ssam hifn_init_pci_registers(sc); 496104477Ssam 497120915Ssam /* XXX can't dynamically determine ram type for 795x; force dram */ 498120915Ssam if (sc->sc_flags & HIFN_IS_7956) 499120915Ssam sc->sc_drammodel = 1; 500120915Ssam else if (hifn_ramtype(sc)) 501104477Ssam goto fail_mem; 502104477Ssam 503104477Ssam if (sc->sc_drammodel == 0) 504104477Ssam hifn_sramsize(sc); 505104477Ssam else 506104477Ssam hifn_dramsize(sc); 507104477Ssam 508104477Ssam /* 509104477Ssam * Workaround for NetSec 7751 rev A: half ram size because two 510104477Ssam * of the address lines were left floating 511104477Ssam */ 512104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 513104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 514104477Ssam pci_get_revid(dev) == 0x61) /*XXX???*/ 515104477Ssam sc->sc_ramsize >>= 1; 516104477Ssam 517104477Ssam /* 518104477Ssam * Arrange the interrupt line. 519104477Ssam */ 520104477Ssam rid = 0; 521127135Snjl sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 522127135Snjl RF_SHAREABLE|RF_ACTIVE); 523104477Ssam if (sc->sc_irq == NULL) { 524104477Ssam device_printf(dev, "could not map interrupt\n"); 525104477Ssam goto fail_mem; 526104477Ssam } 527104477Ssam /* 528104477Ssam * NB: Network code assumes we are blocked with splimp() 529104477Ssam * so make sure the IRQ is marked appropriately. 530104477Ssam */ 531115748Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 532166901Spiso NULL, hifn_intr, sc, &sc->sc_intrhand)) { 533104477Ssam device_printf(dev, "could not setup interrupt\n"); 534104477Ssam goto fail_intr2; 535104477Ssam } 536104477Ssam 537104477Ssam hifn_sessions(sc); 538104477Ssam 539104477Ssam /* 540104477Ssam * NB: Keep only the low 16 bits; this masks the chip id 541104477Ssam * from the 7951. 542104477Ssam */ 543104477Ssam rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 544104477Ssam 545104477Ssam rseg = sc->sc_ramsize / 1024; 546104477Ssam rbase = 'K'; 547104477Ssam if (sc->sc_ramsize >= (1024 * 1024)) { 548104477Ssam rbase = 'M'; 549104477Ssam rseg /= 1024; 550104477Ssam } 551140480Ssam device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", 552104477Ssam hifn_partname(sc), rev, 553136526Ssam rseg, rbase, sc->sc_drammodel ? 'd' : 's'); 554140480Ssam if (sc->sc_flags & HIFN_IS_7956) 555140480Ssam printf(", pll=0x%x<%s clk, %ux mult>", 556140480Ssam sc->sc_pllconfig, 557140480Ssam sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", 558140480Ssam 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); 559140480Ssam printf("\n"); 560104477Ssam 561167755Ssam sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 562104477Ssam if (sc->sc_cid < 0) { 563104477Ssam device_printf(dev, "could not get crypto driver id\n"); 564104477Ssam goto fail_intr; 565104477Ssam } 566104477Ssam 567104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, 568104477Ssam READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 569104477Ssam ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 570104477Ssam 571104477Ssam switch (ena) { 572104477Ssam case HIFN_PUSTAT_ENA_2: 573167755Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 574167755Ssam crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); 575120915Ssam if (sc->sc_flags & HIFN_HAS_AES) 576167755Ssam crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 577104477Ssam /*FALLTHROUGH*/ 578104477Ssam case HIFN_PUSTAT_ENA_1: 579167755Ssam crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); 580167755Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); 581167755Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 582167755Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 583167755Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 584104477Ssam break; 585104477Ssam } 586104477Ssam 587104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 588104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 589104477Ssam 590104477Ssam if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 591104477Ssam hifn_init_pubrng(sc); 592104477Ssam 593119137Ssam callout_init(&sc->sc_tickto, CALLOUT_MPSAFE); 594104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 595104477Ssam 596104477Ssam return (0); 597104477Ssam 598104477Ssamfail_intr: 599104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 600104477Ssamfail_intr2: 601104477Ssam /* XXX don't store rid */ 602104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 603104477Ssamfail_mem: 604104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 605104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 606104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 607104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 608104477Ssam 609104477Ssam /* Turn off DMA polling */ 610104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 611104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 612104477Ssamfail_io1: 613104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 614104477Ssamfail_io0: 615104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 616104477Ssamfail_pci: 617104477Ssam mtx_destroy(&sc->sc_mtx); 618104477Ssam return (ENXIO); 619104477Ssam} 620104477Ssam 621104477Ssam/* 622104477Ssam * Detach an interface that successfully probed. 623104477Ssam */ 624104477Ssamstatic int 625104477Ssamhifn_detach(device_t dev) 626104477Ssam{ 627104477Ssam struct hifn_softc *sc = device_get_softc(dev); 628104477Ssam 629104477Ssam KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 630104477Ssam 631115748Ssam /* disable interrupts */ 632115748Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); 633104477Ssam 634104477Ssam /*XXX other resources */ 635104477Ssam callout_stop(&sc->sc_tickto); 636104477Ssam callout_stop(&sc->sc_rngto); 637115848Ssam#ifdef HIFN_RNDTEST 638115848Ssam if (sc->sc_rndtest) 639115862Ssam rndtest_detach(sc->sc_rndtest); 640115848Ssam#endif 641104477Ssam 642104477Ssam /* Turn off DMA polling */ 643104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 644104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 645104477Ssam 646104477Ssam crypto_unregister_all(sc->sc_cid); 647104477Ssam 648104477Ssam bus_generic_detach(dev); /*XXX should be no children, right? */ 649104477Ssam 650104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 651104477Ssam /* XXX don't store rid */ 652104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 653104477Ssam 654104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 655104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 656104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 657104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 658104477Ssam 659104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 660104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 661104477Ssam 662104477Ssam mtx_destroy(&sc->sc_mtx); 663104477Ssam 664104477Ssam return (0); 665104477Ssam} 666104477Ssam 667104477Ssam/* 668104477Ssam * Stop all chip I/O so that the kernel's probe routines don't 669104477Ssam * get confused by errant DMAs when rebooting. 670104477Ssam */ 671188178Simpstatic int 672104477Ssamhifn_shutdown(device_t dev) 673104477Ssam{ 674104477Ssam#ifdef notyet 675104477Ssam hifn_stop(device_get_softc(dev)); 676104477Ssam#endif 677188178Simp return (0); 678104477Ssam} 679104477Ssam 680104477Ssam/* 681104477Ssam * Device suspend routine. Stop the interface and save some PCI 682104477Ssam * settings in case the BIOS doesn't restore them properly on 683104477Ssam * resume. 684104477Ssam */ 685104477Ssamstatic int 686104477Ssamhifn_suspend(device_t dev) 687104477Ssam{ 688104477Ssam struct hifn_softc *sc = device_get_softc(dev); 689104477Ssam#ifdef notyet 690104477Ssam hifn_stop(sc); 691104477Ssam#endif 692104477Ssam sc->sc_suspended = 1; 693104477Ssam 694104477Ssam return (0); 695104477Ssam} 696104477Ssam 697104477Ssam/* 698104477Ssam * Device resume routine. Restore some PCI settings in case the BIOS 699104477Ssam * doesn't, re-enable busmastering, and restart the interface if 700104477Ssam * appropriate. 701104477Ssam */ 702104477Ssamstatic int 703104477Ssamhifn_resume(device_t dev) 704104477Ssam{ 705104477Ssam struct hifn_softc *sc = device_get_softc(dev); 706104477Ssam#ifdef notyet 707104477Ssam /* reinitialize interface if necessary */ 708104477Ssam if (ifp->if_flags & IFF_UP) 709104477Ssam rl_init(sc); 710104477Ssam#endif 711104477Ssam sc->sc_suspended = 0; 712104477Ssam 713104477Ssam return (0); 714104477Ssam} 715104477Ssam 716104477Ssamstatic int 717104477Ssamhifn_init_pubrng(struct hifn_softc *sc) 718104477Ssam{ 719104477Ssam u_int32_t r; 720104477Ssam int i; 721104477Ssam 722112124Ssam#ifdef HIFN_RNDTEST 723112124Ssam sc->sc_rndtest = rndtest_attach(sc->sc_dev); 724112124Ssam if (sc->sc_rndtest) 725112124Ssam sc->sc_harvest = rndtest_harvest; 726112124Ssam else 727112124Ssam sc->sc_harvest = default_harvest; 728112124Ssam#else 729112124Ssam sc->sc_harvest = default_harvest; 730112124Ssam#endif 731104477Ssam if ((sc->sc_flags & HIFN_IS_7811) == 0) { 732104477Ssam /* Reset 7951 public key/rng engine */ 733104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_RESET, 734104477Ssam READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 735104477Ssam 736104477Ssam for (i = 0; i < 100; i++) { 737104477Ssam DELAY(1000); 738104477Ssam if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 739104477Ssam HIFN_PUBRST_RESET) == 0) 740104477Ssam break; 741104477Ssam } 742104477Ssam 743104477Ssam if (i == 100) { 744104477Ssam device_printf(sc->sc_dev, "public key init failed\n"); 745104477Ssam return (1); 746104477Ssam } 747104477Ssam } 748104477Ssam 749104477Ssam /* Enable the rng, if available */ 750104477Ssam if (sc->sc_flags & HIFN_HAS_RNG) { 751104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 752104477Ssam r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 753104477Ssam if (r & HIFN_7811_RNGENA_ENA) { 754104477Ssam r &= ~HIFN_7811_RNGENA_ENA; 755104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 756104477Ssam } 757104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 758104477Ssam HIFN_7811_RNGCFG_DEFL); 759104477Ssam r |= HIFN_7811_RNGENA_ENA; 760104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 761104477Ssam } else 762104477Ssam WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 763104477Ssam READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 764104477Ssam HIFN_RNGCFG_ENA); 765104477Ssam 766104477Ssam sc->sc_rngfirst = 1; 767104477Ssam if (hz >= 100) 768104477Ssam sc->sc_rnghz = hz / 100; 769104477Ssam else 770104477Ssam sc->sc_rnghz = 1; 771119137Ssam callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 772104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 773104477Ssam } 774104477Ssam 775104477Ssam /* Enable public key engine, if available */ 776104477Ssam if (sc->sc_flags & HIFN_HAS_PUBLIC) { 777104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 778104477Ssam sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 779104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 780167755Ssam#ifdef HIFN_VULCANDEV 781167755Ssam sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, 782167755Ssam UID_ROOT, GID_WHEEL, 0666, 783167755Ssam "vulcanpk"); 784167755Ssam sc->sc_pkdev->si_drv1 = sc; 785167755Ssam#endif 786104477Ssam } 787104477Ssam 788104477Ssam return (0); 789104477Ssam} 790104477Ssam 791104477Ssamstatic void 792104477Ssamhifn_rng(void *vsc) 793104477Ssam{ 794104477Ssam#define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 795104477Ssam struct hifn_softc *sc = vsc; 796104477Ssam u_int32_t sts, num[2]; 797104477Ssam int i; 798104477Ssam 799104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 800167755Ssam /* ONLY VALID ON 7811!!!! */ 801104477Ssam for (i = 0; i < 5; i++) { 802104477Ssam sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 803104477Ssam if (sts & HIFN_7811_RNGSTS_UFL) { 804104477Ssam device_printf(sc->sc_dev, 805104477Ssam "RNG underflow: disabling\n"); 806104477Ssam return; 807104477Ssam } 808104477Ssam if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 809104477Ssam break; 810104477Ssam 811104477Ssam /* 812104477Ssam * There are at least two words in the RNG FIFO 813104477Ssam * at this point. 814104477Ssam */ 815104477Ssam num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 816104477Ssam num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 817104477Ssam /* NB: discard first data read */ 818104477Ssam if (sc->sc_rngfirst) 819104477Ssam sc->sc_rngfirst = 0; 820104477Ssam else 821112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 822112124Ssam num, sizeof (num)); 823104477Ssam } 824104477Ssam } else { 825104477Ssam num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 826104477Ssam 827104477Ssam /* NB: discard first data read */ 828104477Ssam if (sc->sc_rngfirst) 829104477Ssam sc->sc_rngfirst = 0; 830104477Ssam else 831112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 832112124Ssam num, sizeof (num[0])); 833104477Ssam } 834104477Ssam 835104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 836104477Ssam#undef RANDOM_BITS 837104477Ssam} 838104477Ssam 839104477Ssamstatic void 840104477Ssamhifn_puc_wait(struct hifn_softc *sc) 841104477Ssam{ 842104477Ssam int i; 843167755Ssam int reg = HIFN_0_PUCTRL; 844104477Ssam 845167755Ssam if (sc->sc_flags & HIFN_IS_7956) { 846167755Ssam reg = HIFN_0_PUCTRL2; 847167755Ssam } 848167755Ssam 849104477Ssam for (i = 5000; i > 0; i--) { 850104477Ssam DELAY(1); 851167755Ssam if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) 852104477Ssam break; 853104477Ssam } 854104477Ssam if (!i) 855104477Ssam device_printf(sc->sc_dev, "proc unit did not reset\n"); 856104477Ssam} 857104477Ssam 858104477Ssam/* 859104477Ssam * Reset the processing unit. 860104477Ssam */ 861104477Ssamstatic void 862104477Ssamhifn_reset_puc(struct hifn_softc *sc) 863104477Ssam{ 864104477Ssam /* Reset processing unit */ 865167755Ssam int reg = HIFN_0_PUCTRL; 866167755Ssam 867167755Ssam if (sc->sc_flags & HIFN_IS_7956) { 868167755Ssam reg = HIFN_0_PUCTRL2; 869167755Ssam } 870167755Ssam WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); 871167755Ssam 872104477Ssam hifn_puc_wait(sc); 873104477Ssam} 874104477Ssam 875104477Ssam/* 876104477Ssam * Set the Retry and TRDY registers; note that we set them to 877104477Ssam * zero because the 7811 locks up when forced to retry (section 878104477Ssam * 3.6 of "Specification Update SU-0014-04". Not clear if we 879104477Ssam * should do this for all Hifn parts, but it doesn't seem to hurt. 880104477Ssam */ 881104477Ssamstatic void 882104477Ssamhifn_set_retry(struct hifn_softc *sc) 883104477Ssam{ 884104477Ssam /* NB: RETRY only responds to 8-bit reads/writes */ 885104477Ssam pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 886216519Stijl pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 1); 887104477Ssam} 888104477Ssam 889104477Ssam/* 890104477Ssam * Resets the board. Values in the regesters are left as is 891104477Ssam * from the reset (i.e. initial values are assigned elsewhere). 892104477Ssam */ 893104477Ssamstatic void 894104477Ssamhifn_reset_board(struct hifn_softc *sc, int full) 895104477Ssam{ 896104477Ssam u_int32_t reg; 897104477Ssam 898104477Ssam /* 899104477Ssam * Set polling in the DMA configuration register to zero. 0x7 avoids 900104477Ssam * resetting the board and zeros out the other fields. 901104477Ssam */ 902104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 903104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 904104477Ssam 905104477Ssam /* 906104477Ssam * Now that polling has been disabled, we have to wait 1 ms 907104477Ssam * before resetting the board. 908104477Ssam */ 909104477Ssam DELAY(1000); 910104477Ssam 911104477Ssam /* Reset the DMA unit */ 912104477Ssam if (full) { 913104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 914104477Ssam DELAY(1000); 915104477Ssam } else { 916104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 917104477Ssam HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 918104477Ssam hifn_reset_puc(sc); 919104477Ssam } 920104477Ssam 921104477Ssam KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 922104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 923104477Ssam 924104477Ssam /* Bring dma unit out of reset */ 925104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 926104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 927104477Ssam 928104477Ssam hifn_puc_wait(sc); 929104477Ssam hifn_set_retry(sc); 930104477Ssam 931104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 932104477Ssam for (reg = 0; reg < 1000; reg++) { 933104477Ssam if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 934104477Ssam HIFN_MIPSRST_CRAMINIT) 935104477Ssam break; 936104477Ssam DELAY(1000); 937104477Ssam } 938104477Ssam if (reg == 1000) 939104477Ssam printf(": cram init timeout\n"); 940167755Ssam } else { 941167755Ssam /* set up DMA configuration register #2 */ 942167755Ssam /* turn off all PK and BAR0 swaps */ 943167755Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, 944167755Ssam (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| 945167755Ssam (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| 946167755Ssam (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| 947167755Ssam (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); 948104477Ssam } 949167755Ssam 950104477Ssam} 951104477Ssam 952104477Ssamstatic u_int32_t 953104477Ssamhifn_next_signature(u_int32_t a, u_int cnt) 954104477Ssam{ 955104477Ssam int i; 956104477Ssam u_int32_t v; 957104477Ssam 958104477Ssam for (i = 0; i < cnt; i++) { 959104477Ssam 960104477Ssam /* get the parity */ 961104477Ssam v = a & 0x80080125; 962104477Ssam v ^= v >> 16; 963104477Ssam v ^= v >> 8; 964104477Ssam v ^= v >> 4; 965104477Ssam v ^= v >> 2; 966104477Ssam v ^= v >> 1; 967104477Ssam 968104477Ssam a = (v & 1) ^ (a << 1); 969104477Ssam } 970104477Ssam 971104477Ssam return a; 972104477Ssam} 973104477Ssam 974104477Ssamstruct pci2id { 975104477Ssam u_short pci_vendor; 976104477Ssam u_short pci_prod; 977104477Ssam char card_id[13]; 978104477Ssam}; 979104477Ssamstatic struct pci2id pci2id[] = { 980104477Ssam { 981104477Ssam PCI_VENDOR_HIFN, 982104477Ssam PCI_PRODUCT_HIFN_7951, 983104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 984104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 985104477Ssam }, { 986120915Ssam PCI_VENDOR_HIFN, 987120915Ssam PCI_PRODUCT_HIFN_7955, 988120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 989120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 990120915Ssam }, { 991120915Ssam PCI_VENDOR_HIFN, 992120915Ssam PCI_PRODUCT_HIFN_7956, 993120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 994120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 995120915Ssam }, { 996104477Ssam PCI_VENDOR_NETSEC, 997104477Ssam PCI_PRODUCT_NETSEC_7751, 998104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 999104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1000104477Ssam }, { 1001104477Ssam PCI_VENDOR_INVERTEX, 1002104477Ssam PCI_PRODUCT_INVERTEX_AEON, 1003104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1004104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1005104477Ssam }, { 1006104477Ssam PCI_VENDOR_HIFN, 1007104477Ssam PCI_PRODUCT_HIFN_7811, 1008104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1009104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1010104477Ssam }, { 1011104477Ssam /* 1012104477Ssam * Other vendors share this PCI ID as well, such as 1013104477Ssam * http://www.powercrypt.com, and obviously they also 1014104477Ssam * use the same key. 1015104477Ssam */ 1016104477Ssam PCI_VENDOR_HIFN, 1017104477Ssam PCI_PRODUCT_HIFN_7751, 1018104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1019104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1020104477Ssam }, 1021104477Ssam}; 1022104477Ssam 1023104477Ssam/* 1024104477Ssam * Checks to see if crypto is already enabled. If crypto isn't enable, 1025104477Ssam * "hifn_enable_crypto" is called to enable it. The check is important, 1026104477Ssam * as enabling crypto twice will lock the board. 1027104477Ssam */ 1028104477Ssamstatic int 1029104477Ssamhifn_enable_crypto(struct hifn_softc *sc) 1030104477Ssam{ 1031104477Ssam u_int32_t dmacfg, ramcfg, encl, addr, i; 1032104477Ssam char *offtbl = NULL; 1033104477Ssam 1034104477Ssam for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 1035104477Ssam if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 1036104477Ssam pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 1037104477Ssam offtbl = pci2id[i].card_id; 1038104477Ssam break; 1039104477Ssam } 1040104477Ssam } 1041104477Ssam if (offtbl == NULL) { 1042104477Ssam device_printf(sc->sc_dev, "Unknown card!\n"); 1043104477Ssam return (1); 1044104477Ssam } 1045104477Ssam 1046104477Ssam ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1047104477Ssam dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 1048104477Ssam 1049104477Ssam /* 1050104477Ssam * The RAM config register's encrypt level bit needs to be set before 1051104477Ssam * every read performed on the encryption level register. 1052104477Ssam */ 1053104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1054104477Ssam 1055104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1056104477Ssam 1057104477Ssam /* 1058104477Ssam * Make sure we don't re-unlock. Two unlocks kills chip until the 1059104477Ssam * next reboot. 1060104477Ssam */ 1061104477Ssam if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 1062104477Ssam#ifdef HIFN_DEBUG 1063104477Ssam if (hifn_debug) 1064104477Ssam device_printf(sc->sc_dev, 1065104477Ssam "Strong crypto already enabled!\n"); 1066104477Ssam#endif 1067104477Ssam goto report; 1068104477Ssam } 1069104477Ssam 1070104477Ssam if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 1071104477Ssam#ifdef HIFN_DEBUG 1072104477Ssam if (hifn_debug) 1073104477Ssam device_printf(sc->sc_dev, 1074104477Ssam "Unknown encryption level 0x%x\n", encl); 1075104477Ssam#endif 1076104477Ssam return 1; 1077104477Ssam } 1078104477Ssam 1079104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 1080104477Ssam HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 1081104477Ssam DELAY(1000); 1082104477Ssam addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 1083104477Ssam DELAY(1000); 1084104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 1085104477Ssam DELAY(1000); 1086104477Ssam 1087104477Ssam for (i = 0; i <= 12; i++) { 1088104477Ssam addr = hifn_next_signature(addr, offtbl[i] + 0x101); 1089104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 1090104477Ssam 1091104477Ssam DELAY(1000); 1092104477Ssam } 1093104477Ssam 1094104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1095104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1096104477Ssam 1097104477Ssam#ifdef HIFN_DEBUG 1098104477Ssam if (hifn_debug) { 1099104477Ssam if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 1100104477Ssam device_printf(sc->sc_dev, "Engine is permanently " 1101104477Ssam "locked until next system reset!\n"); 1102104477Ssam else 1103104477Ssam device_printf(sc->sc_dev, "Engine enabled " 1104104477Ssam "successfully!\n"); 1105104477Ssam } 1106104477Ssam#endif 1107104477Ssam 1108104477Ssamreport: 1109104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 1110104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 1111104477Ssam 1112104477Ssam switch (encl) { 1113104477Ssam case HIFN_PUSTAT_ENA_1: 1114104477Ssam case HIFN_PUSTAT_ENA_2: 1115104477Ssam break; 1116104477Ssam case HIFN_PUSTAT_ENA_0: 1117104477Ssam default: 1118104477Ssam device_printf(sc->sc_dev, "disabled"); 1119104477Ssam break; 1120104477Ssam } 1121104477Ssam 1122104477Ssam return 0; 1123104477Ssam} 1124104477Ssam 1125104477Ssam/* 1126104477Ssam * Give initial values to the registers listed in the "Register Space" 1127104477Ssam * section of the HIFN Software Development reference manual. 1128104477Ssam */ 1129104477Ssamstatic void 1130104477Ssamhifn_init_pci_registers(struct hifn_softc *sc) 1131104477Ssam{ 1132104477Ssam /* write fixed values needed by the Initialization registers */ 1133104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1134104477Ssam WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1135104477Ssam WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1136104477Ssam 1137104477Ssam /* write all 4 ring address registers */ 1138104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1139104477Ssam offsetof(struct hifn_dma, cmdr[0])); 1140104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1141104477Ssam offsetof(struct hifn_dma, srcr[0])); 1142104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1143104477Ssam offsetof(struct hifn_dma, dstr[0])); 1144104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1145104477Ssam offsetof(struct hifn_dma, resr[0])); 1146104477Ssam 1147104477Ssam DELAY(2000); 1148104477Ssam 1149104477Ssam /* write status register */ 1150104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1151104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1152104477Ssam HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1153104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1154104477Ssam HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1155104477Ssam HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1156104477Ssam HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1157104477Ssam HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1158104477Ssam HIFN_DMACSR_S_WAIT | 1159104477Ssam HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1160104477Ssam HIFN_DMACSR_C_WAIT | 1161104477Ssam HIFN_DMACSR_ENGINE | 1162104477Ssam ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1163104477Ssam HIFN_DMACSR_PUBDONE : 0) | 1164104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1165104477Ssam HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1166104477Ssam 1167104477Ssam sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1168104477Ssam sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1169104477Ssam HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1170104477Ssam HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1171104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1172104477Ssam HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1173104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1174104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1175104477Ssam 1176104477Ssam 1177120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1178140480Ssam u_int32_t pll; 1179140480Ssam 1180120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1181120915Ssam HIFN_PUCNFG_TCALLPHASES | 1182120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); 1183140480Ssam 1184140480Ssam /* turn off the clocks and insure bypass is set */ 1185140480Ssam pll = READ_REG_1(sc, HIFN_1_PLL); 1186140480Ssam pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) 1187167755Ssam | HIFN_PLL_BP | HIFN_PLL_MBSET; 1188140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1189140480Ssam DELAY(10*1000); /* 10ms */ 1190167755Ssam 1191140480Ssam /* change configuration */ 1192140480Ssam pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; 1193140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1194140480Ssam DELAY(10*1000); /* 10ms */ 1195167755Ssam 1196140480Ssam /* disable bypass */ 1197140480Ssam pll &= ~HIFN_PLL_BP; 1198140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1199140480Ssam /* enable clocks with new configuration */ 1200140480Ssam pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; 1201140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1202120915Ssam } else { 1203120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1204120915Ssam HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1205120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1206120915Ssam (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1207120915Ssam } 1208120915Ssam 1209104477Ssam WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1210104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1211104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1212104477Ssam ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1213104477Ssam ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1214104477Ssam} 1215104477Ssam 1216104477Ssam/* 1217104477Ssam * The maximum number of sessions supported by the card 1218104477Ssam * is dependent on the amount of context ram, which 1219104477Ssam * encryption algorithms are enabled, and how compression 1220104477Ssam * is configured. This should be configured before this 1221104477Ssam * routine is called. 1222104477Ssam */ 1223104477Ssamstatic void 1224104477Ssamhifn_sessions(struct hifn_softc *sc) 1225104477Ssam{ 1226104477Ssam u_int32_t pucnfg; 1227104477Ssam int ctxsize; 1228104477Ssam 1229104477Ssam pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1230104477Ssam 1231104477Ssam if (pucnfg & HIFN_PUCNFG_COMPSING) { 1232104477Ssam if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1233104477Ssam ctxsize = 128; 1234104477Ssam else 1235104477Ssam ctxsize = 512; 1236120915Ssam /* 1237120915Ssam * 7955/7956 has internal context memory of 32K 1238120915Ssam */ 1239120915Ssam if (sc->sc_flags & HIFN_IS_7956) 1240120915Ssam sc->sc_maxses = 32768 / ctxsize; 1241120915Ssam else 1242120915Ssam sc->sc_maxses = 1 + 1243120915Ssam ((sc->sc_ramsize - 32768) / ctxsize); 1244104477Ssam } else 1245104477Ssam sc->sc_maxses = sc->sc_ramsize / 16384; 1246104477Ssam 1247104477Ssam if (sc->sc_maxses > 2048) 1248104477Ssam sc->sc_maxses = 2048; 1249104477Ssam} 1250104477Ssam 1251104477Ssam/* 1252104477Ssam * Determine ram type (sram or dram). Board should be just out of a reset 1253104477Ssam * state when this is called. 1254104477Ssam */ 1255104477Ssamstatic int 1256104477Ssamhifn_ramtype(struct hifn_softc *sc) 1257104477Ssam{ 1258104477Ssam u_int8_t data[8], dataexpect[8]; 1259104477Ssam int i; 1260104477Ssam 1261104477Ssam for (i = 0; i < sizeof(data); i++) 1262104477Ssam data[i] = dataexpect[i] = 0x55; 1263104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1264104477Ssam return (-1); 1265104477Ssam if (hifn_readramaddr(sc, 0, data)) 1266104477Ssam return (-1); 1267104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1268104477Ssam sc->sc_drammodel = 1; 1269104477Ssam return (0); 1270104477Ssam } 1271104477Ssam 1272104477Ssam for (i = 0; i < sizeof(data); i++) 1273104477Ssam data[i] = dataexpect[i] = 0xaa; 1274104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1275104477Ssam return (-1); 1276104477Ssam if (hifn_readramaddr(sc, 0, data)) 1277104477Ssam return (-1); 1278104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1279104477Ssam sc->sc_drammodel = 1; 1280104477Ssam return (0); 1281104477Ssam } 1282104477Ssam 1283104477Ssam return (0); 1284104477Ssam} 1285104477Ssam 1286104477Ssam#define HIFN_SRAM_MAX (32 << 20) 1287104477Ssam#define HIFN_SRAM_STEP_SIZE 16384 1288104477Ssam#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1289104477Ssam 1290104477Ssamstatic int 1291104477Ssamhifn_sramsize(struct hifn_softc *sc) 1292104477Ssam{ 1293104477Ssam u_int32_t a; 1294104477Ssam u_int8_t data[8]; 1295104477Ssam u_int8_t dataexpect[sizeof(data)]; 1296104477Ssam int32_t i; 1297104477Ssam 1298104477Ssam for (i = 0; i < sizeof(data); i++) 1299104477Ssam data[i] = dataexpect[i] = i ^ 0x5a; 1300104477Ssam 1301104477Ssam for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1302104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1303104477Ssam bcopy(&i, data, sizeof(i)); 1304104477Ssam hifn_writeramaddr(sc, a, data); 1305104477Ssam } 1306104477Ssam 1307104477Ssam for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1308104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1309104477Ssam bcopy(&i, dataexpect, sizeof(i)); 1310104477Ssam if (hifn_readramaddr(sc, a, data) < 0) 1311104477Ssam return (0); 1312104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) 1313104477Ssam return (0); 1314104477Ssam sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1315104477Ssam } 1316104477Ssam 1317104477Ssam return (0); 1318104477Ssam} 1319104477Ssam 1320104477Ssam/* 1321104477Ssam * XXX For dram boards, one should really try all of the 1322104477Ssam * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1323104477Ssam * is already set up correctly. 1324104477Ssam */ 1325104477Ssamstatic int 1326104477Ssamhifn_dramsize(struct hifn_softc *sc) 1327104477Ssam{ 1328104477Ssam u_int32_t cnfg; 1329104477Ssam 1330120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1331120915Ssam /* 1332120915Ssam * 7955/7956 have a fixed internal ram of only 32K. 1333120915Ssam */ 1334120915Ssam sc->sc_ramsize = 32768; 1335120915Ssam } else { 1336120915Ssam cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1337120915Ssam HIFN_PUCNFG_DRAMMASK; 1338120915Ssam sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1339120915Ssam } 1340104477Ssam return (0); 1341104477Ssam} 1342104477Ssam 1343104477Ssamstatic void 1344104477Ssamhifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1345104477Ssam{ 1346104477Ssam struct hifn_dma *dma = sc->sc_dma; 1347104477Ssam 1348213091Sgonzo if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) { 1349213091Sgonzo sc->sc_cmdi = 0; 1350104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1351104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1352104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1353104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1354104477Ssam } 1355213091Sgonzo *cmdp = sc->sc_cmdi++; 1356213091Sgonzo sc->sc_cmdk = sc->sc_cmdi; 1357104477Ssam 1358213091Sgonzo if (sc->sc_srci == HIFN_D_SRC_RSIZE) { 1359213091Sgonzo sc->sc_srci = 0; 1360104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1361104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1362104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1363104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1364104477Ssam } 1365213091Sgonzo *srcp = sc->sc_srci++; 1366213091Sgonzo sc->sc_srck = sc->sc_srci; 1367104477Ssam 1368213091Sgonzo if (sc->sc_dsti == HIFN_D_DST_RSIZE) { 1369213091Sgonzo sc->sc_dsti = 0; 1370104477Ssam dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1371104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1372104477Ssam HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1373104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1374104477Ssam } 1375213091Sgonzo *dstp = sc->sc_dsti++; 1376213091Sgonzo sc->sc_dstk = sc->sc_dsti; 1377104477Ssam 1378213091Sgonzo if (sc->sc_resi == HIFN_D_RES_RSIZE) { 1379213091Sgonzo sc->sc_resi = 0; 1380104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1381104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1382104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1383104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1384104477Ssam } 1385213091Sgonzo *resp = sc->sc_resi++; 1386213091Sgonzo sc->sc_resk = sc->sc_resi; 1387104477Ssam} 1388104477Ssam 1389104477Ssamstatic int 1390104477Ssamhifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1391104477Ssam{ 1392104477Ssam struct hifn_dma *dma = sc->sc_dma; 1393104477Ssam hifn_base_command_t wc; 1394104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1395104477Ssam int r, cmdi, resi, srci, dsti; 1396104477Ssam 1397104477Ssam wc.masks = htole16(3 << 13); 1398104477Ssam wc.session_num = htole16(addr >> 14); 1399104477Ssam wc.total_source_count = htole16(8); 1400104477Ssam wc.total_dest_count = htole16(addr & 0x3fff); 1401104477Ssam 1402104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1403104477Ssam 1404104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1405104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1406104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1407104477Ssam 1408104477Ssam /* build write command */ 1409104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1410104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1411104477Ssam bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1412104477Ssam 1413104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1414104477Ssam + offsetof(struct hifn_dma, test_src)); 1415104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1416104477Ssam + offsetof(struct hifn_dma, test_dst)); 1417104477Ssam 1418104477Ssam dma->cmdr[cmdi].l = htole32(16 | masks); 1419104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1420104477Ssam dma->dstr[dsti].l = htole32(4 | masks); 1421104477Ssam dma->resr[resi].l = htole32(4 | masks); 1422104477Ssam 1423104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1424104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1425104477Ssam 1426104477Ssam for (r = 10000; r >= 0; r--) { 1427104477Ssam DELAY(10); 1428104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1429104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1430104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1431104477Ssam break; 1432104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1433104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1434104477Ssam } 1435104477Ssam if (r == 0) { 1436104477Ssam device_printf(sc->sc_dev, "writeramaddr -- " 1437104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1438104477Ssam r = -1; 1439104477Ssam return (-1); 1440104477Ssam } else 1441104477Ssam r = 0; 1442104477Ssam 1443104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1444104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1445104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1446104477Ssam 1447104477Ssam return (r); 1448104477Ssam} 1449104477Ssam 1450104477Ssamstatic int 1451104477Ssamhifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1452104477Ssam{ 1453104477Ssam struct hifn_dma *dma = sc->sc_dma; 1454104477Ssam hifn_base_command_t rc; 1455104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1456104477Ssam int r, cmdi, srci, dsti, resi; 1457104477Ssam 1458104477Ssam rc.masks = htole16(2 << 13); 1459104477Ssam rc.session_num = htole16(addr >> 14); 1460104477Ssam rc.total_source_count = htole16(addr & 0x3fff); 1461104477Ssam rc.total_dest_count = htole16(8); 1462104477Ssam 1463104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1464104477Ssam 1465104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1466104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1467104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1468104477Ssam 1469104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1470104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1471104477Ssam 1472104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1473104477Ssam offsetof(struct hifn_dma, test_src)); 1474104477Ssam dma->test_src = 0; 1475104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1476104477Ssam offsetof(struct hifn_dma, test_dst)); 1477104477Ssam dma->test_dst = 0; 1478104477Ssam dma->cmdr[cmdi].l = htole32(8 | masks); 1479104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1480104477Ssam dma->dstr[dsti].l = htole32(8 | masks); 1481104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1482104477Ssam 1483104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1484104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1485104477Ssam 1486104477Ssam for (r = 10000; r >= 0; r--) { 1487104477Ssam DELAY(10); 1488104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1489104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1490104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1491104477Ssam break; 1492104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1493104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1494104477Ssam } 1495104477Ssam if (r == 0) { 1496104477Ssam device_printf(sc->sc_dev, "readramaddr -- " 1497104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1498104477Ssam r = -1; 1499104477Ssam } else { 1500104477Ssam r = 0; 1501104477Ssam bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1502104477Ssam } 1503104477Ssam 1504104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1505104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1506104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1507104477Ssam 1508104477Ssam return (r); 1509104477Ssam} 1510104477Ssam 1511104477Ssam/* 1512104477Ssam * Initialize the descriptor rings. 1513104477Ssam */ 1514104477Ssamstatic void 1515104477Ssamhifn_init_dma(struct hifn_softc *sc) 1516104477Ssam{ 1517104477Ssam struct hifn_dma *dma = sc->sc_dma; 1518104477Ssam int i; 1519104477Ssam 1520104477Ssam hifn_set_retry(sc); 1521104477Ssam 1522104477Ssam /* initialize static pointer values */ 1523104477Ssam for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1524104477Ssam dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1525104477Ssam offsetof(struct hifn_dma, command_bufs[i][0])); 1526104477Ssam for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1527104477Ssam dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1528104477Ssam offsetof(struct hifn_dma, result_bufs[i][0])); 1529104477Ssam 1530104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].p = 1531104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1532104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].p = 1533104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1534104477Ssam dma->dstr[HIFN_D_DST_RSIZE].p = 1535104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1536104477Ssam dma->resr[HIFN_D_RES_RSIZE].p = 1537104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1538104477Ssam 1539213091Sgonzo sc->sc_cmdu = sc->sc_srcu = sc->sc_dstu = sc->sc_resu = 0; 1540213091Sgonzo sc->sc_cmdi = sc->sc_srci = sc->sc_dsti = sc->sc_resi = 0; 1541213091Sgonzo sc->sc_cmdk = sc->sc_srck = sc->sc_dstk = sc->sc_resk = 0; 1542104477Ssam} 1543104477Ssam 1544104477Ssam/* 1545104477Ssam * Writes out the raw command buffer space. Returns the 1546104477Ssam * command buffer size. 1547104477Ssam */ 1548104477Ssamstatic u_int 1549104477Ssamhifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1550104477Ssam{ 1551104477Ssam u_int8_t *buf_pos; 1552104477Ssam hifn_base_command_t *base_cmd; 1553104477Ssam hifn_mac_command_t *mac_cmd; 1554104477Ssam hifn_crypt_command_t *cry_cmd; 1555120915Ssam int using_mac, using_crypt, len, ivlen; 1556104477Ssam u_int32_t dlen, slen; 1557104477Ssam 1558104477Ssam buf_pos = buf; 1559104477Ssam using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1560104477Ssam using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1561104477Ssam 1562104477Ssam base_cmd = (hifn_base_command_t *)buf_pos; 1563104477Ssam base_cmd->masks = htole16(cmd->base_masks); 1564104477Ssam slen = cmd->src_mapsize; 1565104477Ssam if (cmd->sloplen) 1566104477Ssam dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1567104477Ssam else 1568104477Ssam dlen = cmd->dst_mapsize; 1569104477Ssam base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1570104477Ssam base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1571104477Ssam dlen >>= 16; 1572104477Ssam slen >>= 16; 1573136526Ssam base_cmd->session_num = htole16( 1574104477Ssam ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1575104477Ssam ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1576104477Ssam buf_pos += sizeof(hifn_base_command_t); 1577104477Ssam 1578104477Ssam if (using_mac) { 1579104477Ssam mac_cmd = (hifn_mac_command_t *)buf_pos; 1580104477Ssam dlen = cmd->maccrd->crd_len; 1581104477Ssam mac_cmd->source_count = htole16(dlen & 0xffff); 1582104477Ssam dlen >>= 16; 1583104477Ssam mac_cmd->masks = htole16(cmd->mac_masks | 1584104477Ssam ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1585104477Ssam mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1586104477Ssam mac_cmd->reserved = 0; 1587104477Ssam buf_pos += sizeof(hifn_mac_command_t); 1588104477Ssam } 1589104477Ssam 1590104477Ssam if (using_crypt) { 1591104477Ssam cry_cmd = (hifn_crypt_command_t *)buf_pos; 1592104477Ssam dlen = cmd->enccrd->crd_len; 1593104477Ssam cry_cmd->source_count = htole16(dlen & 0xffff); 1594104477Ssam dlen >>= 16; 1595104477Ssam cry_cmd->masks = htole16(cmd->cry_masks | 1596104477Ssam ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1597104477Ssam cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1598104477Ssam cry_cmd->reserved = 0; 1599104477Ssam buf_pos += sizeof(hifn_crypt_command_t); 1600104477Ssam } 1601104477Ssam 1602104477Ssam if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1603104477Ssam bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1604104477Ssam buf_pos += HIFN_MAC_KEY_LENGTH; 1605104477Ssam } 1606104477Ssam 1607104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1608104477Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1609104477Ssam case HIFN_CRYPT_CMD_ALG_3DES: 1610104477Ssam bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1611104477Ssam buf_pos += HIFN_3DES_KEY_LENGTH; 1612104477Ssam break; 1613104477Ssam case HIFN_CRYPT_CMD_ALG_DES: 1614104477Ssam bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1615120915Ssam buf_pos += HIFN_DES_KEY_LENGTH; 1616104477Ssam break; 1617104477Ssam case HIFN_CRYPT_CMD_ALG_RC4: 1618104477Ssam len = 256; 1619104477Ssam do { 1620104477Ssam int clen; 1621104477Ssam 1622104477Ssam clen = MIN(cmd->cklen, len); 1623104477Ssam bcopy(cmd->ck, buf_pos, clen); 1624104477Ssam len -= clen; 1625104477Ssam buf_pos += clen; 1626104477Ssam } while (len > 0); 1627104477Ssam bzero(buf_pos, 4); 1628104477Ssam buf_pos += 4; 1629104477Ssam break; 1630120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1631120915Ssam /* 1632120915Ssam * AES keys are variable 128, 192 and 1633120915Ssam * 256 bits (16, 24 and 32 bytes). 1634120915Ssam */ 1635120915Ssam bcopy(cmd->ck, buf_pos, cmd->cklen); 1636120915Ssam buf_pos += cmd->cklen; 1637120915Ssam break; 1638104477Ssam } 1639104477Ssam } 1640104477Ssam 1641104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1642120915Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1643120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1644120915Ssam ivlen = HIFN_AES_IV_LENGTH; 1645120915Ssam break; 1646120915Ssam default: 1647120915Ssam ivlen = HIFN_IV_LENGTH; 1648120915Ssam break; 1649120915Ssam } 1650120915Ssam bcopy(cmd->iv, buf_pos, ivlen); 1651120915Ssam buf_pos += ivlen; 1652104477Ssam } 1653104477Ssam 1654104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1655104477Ssam bzero(buf_pos, 8); 1656104477Ssam buf_pos += 8; 1657104477Ssam } 1658104477Ssam 1659104477Ssam return (buf_pos - buf); 1660104477Ssam} 1661104477Ssam 1662104477Ssamstatic int 1663104477Ssamhifn_dmamap_aligned(struct hifn_operand *op) 1664104477Ssam{ 1665104477Ssam int i; 1666104477Ssam 1667104477Ssam for (i = 0; i < op->nsegs; i++) { 1668104477Ssam if (op->segs[i].ds_addr & 3) 1669104477Ssam return (0); 1670104477Ssam if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1671104477Ssam return (0); 1672104477Ssam } 1673104477Ssam return (1); 1674104477Ssam} 1675104477Ssam 1676167755Ssamstatic __inline int 1677167755Ssamhifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) 1678167755Ssam{ 1679167755Ssam struct hifn_dma *dma = sc->sc_dma; 1680167755Ssam 1681167755Ssam if (++idx == HIFN_D_DST_RSIZE) { 1682167755Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1683167755Ssam HIFN_D_MASKDONEIRQ); 1684167755Ssam HIFN_DSTR_SYNC(sc, idx, 1685167755Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1686167755Ssam idx = 0; 1687167755Ssam } 1688167755Ssam return (idx); 1689167755Ssam} 1690167755Ssam 1691104477Ssamstatic int 1692104477Ssamhifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1693104477Ssam{ 1694104477Ssam struct hifn_dma *dma = sc->sc_dma; 1695104477Ssam struct hifn_operand *dst = &cmd->dst; 1696104477Ssam u_int32_t p, l; 1697104477Ssam int idx, used = 0, i; 1698104477Ssam 1699213091Sgonzo idx = sc->sc_dsti; 1700104477Ssam for (i = 0; i < dst->nsegs - 1; i++) { 1701104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1702104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1703104477Ssam HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1704104477Ssam HIFN_DSTR_SYNC(sc, idx, 1705104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1706104477Ssam used++; 1707104477Ssam 1708167755Ssam idx = hifn_dmamap_dstwrap(sc, idx); 1709104477Ssam } 1710104477Ssam 1711104477Ssam if (cmd->sloplen == 0) { 1712104477Ssam p = dst->segs[i].ds_addr; 1713104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1714104477Ssam dst->segs[i].ds_len; 1715104477Ssam } else { 1716104477Ssam p = sc->sc_dma_physaddr + 1717104477Ssam offsetof(struct hifn_dma, slop[cmd->slopidx]); 1718104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1719104477Ssam sizeof(u_int32_t); 1720104477Ssam 1721104477Ssam if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1722104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1723104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1724104477Ssam HIFN_D_MASKDONEIRQ | 1725104477Ssam (dst->segs[i].ds_len - cmd->sloplen)); 1726104477Ssam HIFN_DSTR_SYNC(sc, idx, 1727104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1728104477Ssam used++; 1729104477Ssam 1730167755Ssam idx = hifn_dmamap_dstwrap(sc, idx); 1731104477Ssam } 1732104477Ssam } 1733104477Ssam dma->dstr[idx].p = htole32(p); 1734104477Ssam dma->dstr[idx].l = htole32(l); 1735104477Ssam HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1736104477Ssam used++; 1737104477Ssam 1738167755Ssam idx = hifn_dmamap_dstwrap(sc, idx); 1739104477Ssam 1740213091Sgonzo sc->sc_dsti = idx; 1741213091Sgonzo sc->sc_dstu += used; 1742104477Ssam return (idx); 1743104477Ssam} 1744104477Ssam 1745167755Ssamstatic __inline int 1746167755Ssamhifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) 1747167755Ssam{ 1748167755Ssam struct hifn_dma *dma = sc->sc_dma; 1749167755Ssam 1750167755Ssam if (++idx == HIFN_D_SRC_RSIZE) { 1751167755Ssam dma->srcr[idx].l = htole32(HIFN_D_VALID | 1752167755Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1753167755Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1754167755Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1755167755Ssam idx = 0; 1756167755Ssam } 1757167755Ssam return (idx); 1758167755Ssam} 1759167755Ssam 1760104477Ssamstatic int 1761104477Ssamhifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1762104477Ssam{ 1763104477Ssam struct hifn_dma *dma = sc->sc_dma; 1764104477Ssam struct hifn_operand *src = &cmd->src; 1765104477Ssam int idx, i; 1766104477Ssam u_int32_t last = 0; 1767104477Ssam 1768213091Sgonzo idx = sc->sc_srci; 1769104477Ssam for (i = 0; i < src->nsegs; i++) { 1770104477Ssam if (i == src->nsegs - 1) 1771104477Ssam last = HIFN_D_LAST; 1772104477Ssam 1773104477Ssam dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1774104477Ssam dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1775104477Ssam HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1776104477Ssam HIFN_SRCR_SYNC(sc, idx, 1777104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1778104477Ssam 1779167755Ssam idx = hifn_dmamap_srcwrap(sc, idx); 1780104477Ssam } 1781213091Sgonzo sc->sc_srci = idx; 1782213091Sgonzo sc->sc_srcu += src->nsegs; 1783104477Ssam return (idx); 1784104477Ssam} 1785104477Ssam 1786104477Ssamstatic void 1787104477Ssamhifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1788104477Ssam{ 1789104477Ssam struct hifn_operand *op = arg; 1790104477Ssam 1791104477Ssam KASSERT(nsegs <= MAX_SCATTER, 1792104477Ssam ("hifn_op_cb: too many DMA segments (%u > %u) " 1793104477Ssam "returned when mapping operand", nsegs, MAX_SCATTER)); 1794104477Ssam op->mapsize = mapsize; 1795104477Ssam op->nsegs = nsegs; 1796104477Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1797104477Ssam} 1798104477Ssam 1799104477Ssamstatic int 1800104477Ssamhifn_crypto( 1801104477Ssam struct hifn_softc *sc, 1802104477Ssam struct hifn_command *cmd, 1803104477Ssam struct cryptop *crp, 1804104477Ssam int hint) 1805104477Ssam{ 1806104477Ssam struct hifn_dma *dma = sc->sc_dma; 1807167755Ssam u_int32_t cmdlen, csr; 1808104477Ssam int cmdi, resi, err = 0; 1809104477Ssam 1810104477Ssam /* 1811104477Ssam * need 1 cmd, and 1 res 1812104477Ssam * 1813104477Ssam * NB: check this first since it's easy. 1814104477Ssam */ 1815115748Ssam HIFN_LOCK(sc); 1816213091Sgonzo if ((sc->sc_cmdu + 1) > HIFN_D_CMD_RSIZE || 1817213091Sgonzo (sc->sc_resu + 1) > HIFN_D_RES_RSIZE) { 1818104477Ssam#ifdef HIFN_DEBUG 1819104477Ssam if (hifn_debug) { 1820104477Ssam device_printf(sc->sc_dev, 1821104477Ssam "cmd/result exhaustion, cmdu %u resu %u\n", 1822213091Sgonzo sc->sc_cmdu, sc->sc_resu); 1823104477Ssam } 1824104477Ssam#endif 1825104477Ssam hifnstats.hst_nomem_cr++; 1826115748Ssam HIFN_UNLOCK(sc); 1827104477Ssam return (ERESTART); 1828104477Ssam } 1829104477Ssam 1830104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1831104477Ssam hifnstats.hst_nomem_map++; 1832115748Ssam HIFN_UNLOCK(sc); 1833104477Ssam return (ENOMEM); 1834104477Ssam } 1835104477Ssam 1836104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1837104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1838104477Ssam cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1839104477Ssam hifnstats.hst_nomem_load++; 1840104477Ssam err = ENOMEM; 1841104477Ssam goto err_srcmap1; 1842104477Ssam } 1843104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1844104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1845104477Ssam cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1846104477Ssam hifnstats.hst_nomem_load++; 1847104477Ssam err = ENOMEM; 1848104477Ssam goto err_srcmap1; 1849104477Ssam } 1850104477Ssam } else { 1851104477Ssam err = EINVAL; 1852104477Ssam goto err_srcmap1; 1853104477Ssam } 1854104477Ssam 1855104477Ssam if (hifn_dmamap_aligned(&cmd->src)) { 1856104477Ssam cmd->sloplen = cmd->src_mapsize & 3; 1857104477Ssam cmd->dst = cmd->src; 1858104477Ssam } else { 1859104477Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1860104477Ssam err = EINVAL; 1861104477Ssam goto err_srcmap; 1862104477Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1863104477Ssam int totlen, len; 1864104477Ssam struct mbuf *m, *m0, *mlast; 1865104477Ssam 1866104477Ssam KASSERT(cmd->dst_m == cmd->src_m, 1867104477Ssam ("hifn_crypto: dst_m initialized improperly")); 1868104477Ssam hifnstats.hst_unaligned++; 1869104477Ssam /* 1870104477Ssam * Source is not aligned on a longword boundary. 1871104477Ssam * Copy the data to insure alignment. If we fail 1872104477Ssam * to allocate mbufs or clusters while doing this 1873104477Ssam * we return ERESTART so the operation is requeued 1874104477Ssam * at the crypto later, but only if there are 1875104477Ssam * ops already posted to the hardware; otherwise we 1876104477Ssam * have no guarantee that we'll be re-entered. 1877104477Ssam */ 1878104477Ssam totlen = cmd->src_mapsize; 1879104477Ssam if (cmd->src_m->m_flags & M_PKTHDR) { 1880104477Ssam len = MHLEN; 1881243857Sglebius MGETHDR(m0, M_NOWAIT, MT_DATA); 1882243857Sglebius if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_NOWAIT)) { 1883108466Ssam m_free(m0); 1884108466Ssam m0 = NULL; 1885108466Ssam } 1886104477Ssam } else { 1887104477Ssam len = MLEN; 1888243857Sglebius MGET(m0, M_NOWAIT, MT_DATA); 1889104477Ssam } 1890104477Ssam if (m0 == NULL) { 1891104477Ssam hifnstats.hst_nomem_mbuf++; 1892213091Sgonzo err = sc->sc_cmdu ? ERESTART : ENOMEM; 1893104477Ssam goto err_srcmap; 1894104477Ssam } 1895104477Ssam if (totlen >= MINCLSIZE) { 1896243857Sglebius MCLGET(m0, M_NOWAIT); 1897104477Ssam if ((m0->m_flags & M_EXT) == 0) { 1898104477Ssam hifnstats.hst_nomem_mcl++; 1899213091Sgonzo err = sc->sc_cmdu ? ERESTART : ENOMEM; 1900104477Ssam m_freem(m0); 1901104477Ssam goto err_srcmap; 1902104477Ssam } 1903104477Ssam len = MCLBYTES; 1904104477Ssam } 1905104477Ssam totlen -= len; 1906104477Ssam m0->m_pkthdr.len = m0->m_len = len; 1907104477Ssam mlast = m0; 1908104477Ssam 1909104477Ssam while (totlen > 0) { 1910243857Sglebius MGET(m, M_NOWAIT, MT_DATA); 1911104477Ssam if (m == NULL) { 1912104477Ssam hifnstats.hst_nomem_mbuf++; 1913213091Sgonzo err = sc->sc_cmdu ? ERESTART : ENOMEM; 1914104477Ssam m_freem(m0); 1915104477Ssam goto err_srcmap; 1916104477Ssam } 1917104477Ssam len = MLEN; 1918104477Ssam if (totlen >= MINCLSIZE) { 1919243857Sglebius MCLGET(m, M_NOWAIT); 1920104477Ssam if ((m->m_flags & M_EXT) == 0) { 1921104477Ssam hifnstats.hst_nomem_mcl++; 1922213091Sgonzo err = sc->sc_cmdu ? ERESTART : ENOMEM; 1923104477Ssam mlast->m_next = m; 1924104477Ssam m_freem(m0); 1925104477Ssam goto err_srcmap; 1926104477Ssam } 1927104477Ssam len = MCLBYTES; 1928104477Ssam } 1929104477Ssam 1930104477Ssam m->m_len = len; 1931104477Ssam m0->m_pkthdr.len += len; 1932104477Ssam totlen -= len; 1933104477Ssam 1934104477Ssam mlast->m_next = m; 1935104477Ssam mlast = m; 1936104477Ssam } 1937104477Ssam cmd->dst_m = m0; 1938104477Ssam } 1939104477Ssam } 1940104477Ssam 1941104477Ssam if (cmd->dst_map == NULL) { 1942104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1943104477Ssam hifnstats.hst_nomem_map++; 1944104477Ssam err = ENOMEM; 1945104477Ssam goto err_srcmap; 1946104477Ssam } 1947104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1948104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1949104477Ssam cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1950104477Ssam hifnstats.hst_nomem_map++; 1951104477Ssam err = ENOMEM; 1952104477Ssam goto err_dstmap1; 1953104477Ssam } 1954104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1955104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1956104477Ssam cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1957104477Ssam hifnstats.hst_nomem_load++; 1958104477Ssam err = ENOMEM; 1959104477Ssam goto err_dstmap1; 1960104477Ssam } 1961104477Ssam } 1962104477Ssam } 1963104477Ssam 1964104477Ssam#ifdef HIFN_DEBUG 1965104477Ssam if (hifn_debug) { 1966104477Ssam device_printf(sc->sc_dev, 1967104477Ssam "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1968104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1969104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER), 1970213091Sgonzo sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu, 1971104477Ssam cmd->src_nsegs, cmd->dst_nsegs); 1972104477Ssam } 1973104477Ssam#endif 1974104477Ssam 1975104477Ssam if (cmd->src_map == cmd->dst_map) { 1976104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1977104477Ssam BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1978104477Ssam } else { 1979104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1980104477Ssam BUS_DMASYNC_PREWRITE); 1981104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1982104477Ssam BUS_DMASYNC_PREREAD); 1983104477Ssam } 1984104477Ssam 1985104477Ssam /* 1986104477Ssam * need N src, and N dst 1987104477Ssam */ 1988213091Sgonzo if ((sc->sc_srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1989213091Sgonzo (sc->sc_dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1990104477Ssam#ifdef HIFN_DEBUG 1991104477Ssam if (hifn_debug) { 1992104477Ssam device_printf(sc->sc_dev, 1993104477Ssam "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1994213091Sgonzo sc->sc_srcu, cmd->src_nsegs, 1995213091Sgonzo sc->sc_dstu, cmd->dst_nsegs); 1996104477Ssam } 1997104477Ssam#endif 1998104477Ssam hifnstats.hst_nomem_sd++; 1999104477Ssam err = ERESTART; 2000104477Ssam goto err_dstmap; 2001104477Ssam } 2002104477Ssam 2003213091Sgonzo if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) { 2004213091Sgonzo sc->sc_cmdi = 0; 2005104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 2006104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 2007104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 2008104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2009104477Ssam } 2010213091Sgonzo cmdi = sc->sc_cmdi++; 2011104477Ssam cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 2012104477Ssam HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 2013104477Ssam 2014104477Ssam /* .p for command/result already set */ 2015104477Ssam dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 2016104477Ssam HIFN_D_MASKDONEIRQ); 2017104477Ssam HIFN_CMDR_SYNC(sc, cmdi, 2018104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2019213091Sgonzo sc->sc_cmdu++; 2020104477Ssam 2021104477Ssam /* 2022104477Ssam * We don't worry about missing an interrupt (which a "command wait" 2023104477Ssam * interrupt salvages us from), unless there is more than one command 2024104477Ssam * in the queue. 2025104477Ssam */ 2026213091Sgonzo if (sc->sc_cmdu > 1) { 2027104477Ssam sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 2028104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2029104477Ssam } 2030104477Ssam 2031104477Ssam hifnstats.hst_ipackets++; 2032104477Ssam hifnstats.hst_ibytes += cmd->src_mapsize; 2033104477Ssam 2034104477Ssam hifn_dmamap_load_src(sc, cmd); 2035104477Ssam 2036104477Ssam /* 2037104477Ssam * Unlike other descriptors, we don't mask done interrupt from 2038104477Ssam * result descriptor. 2039104477Ssam */ 2040104477Ssam#ifdef HIFN_DEBUG 2041104477Ssam if (hifn_debug) 2042104477Ssam printf("load res\n"); 2043104477Ssam#endif 2044213091Sgonzo if (sc->sc_resi == HIFN_D_RES_RSIZE) { 2045213091Sgonzo sc->sc_resi = 0; 2046104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 2047104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 2048104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 2049104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2050104477Ssam } 2051213091Sgonzo resi = sc->sc_resi++; 2052213091Sgonzo KASSERT(sc->sc_hifn_commands[resi] == NULL, 2053104477Ssam ("hifn_crypto: command slot %u busy", resi)); 2054213091Sgonzo sc->sc_hifn_commands[resi] = cmd; 2055104477Ssam HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 2056104477Ssam if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 2057104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 2058104477Ssam HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 2059104477Ssam sc->sc_curbatch++; 2060104477Ssam if (sc->sc_curbatch > hifnstats.hst_maxbatch) 2061104477Ssam hifnstats.hst_maxbatch = sc->sc_curbatch; 2062104477Ssam hifnstats.hst_totbatch++; 2063104477Ssam } else { 2064104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 2065104477Ssam HIFN_D_VALID | HIFN_D_LAST); 2066104477Ssam sc->sc_curbatch = 0; 2067104477Ssam } 2068104477Ssam HIFN_RESR_SYNC(sc, resi, 2069104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2070213091Sgonzo sc->sc_resu++; 2071104477Ssam 2072104477Ssam if (cmd->sloplen) 2073104477Ssam cmd->slopidx = resi; 2074104477Ssam 2075104477Ssam hifn_dmamap_load_dst(sc, cmd); 2076104477Ssam 2077167755Ssam csr = 0; 2078167755Ssam if (sc->sc_c_busy == 0) { 2079167755Ssam csr |= HIFN_DMACSR_C_CTRL_ENA; 2080167755Ssam sc->sc_c_busy = 1; 2081167755Ssam } 2082167755Ssam if (sc->sc_s_busy == 0) { 2083167755Ssam csr |= HIFN_DMACSR_S_CTRL_ENA; 2084167755Ssam sc->sc_s_busy = 1; 2085167755Ssam } 2086167755Ssam if (sc->sc_r_busy == 0) { 2087167755Ssam csr |= HIFN_DMACSR_R_CTRL_ENA; 2088167755Ssam sc->sc_r_busy = 1; 2089167755Ssam } 2090104477Ssam if (sc->sc_d_busy == 0) { 2091167755Ssam csr |= HIFN_DMACSR_D_CTRL_ENA; 2092104477Ssam sc->sc_d_busy = 1; 2093104477Ssam } 2094167755Ssam if (csr) 2095167755Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); 2096104477Ssam 2097104477Ssam#ifdef HIFN_DEBUG 2098104477Ssam if (hifn_debug) { 2099104477Ssam device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 2100104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 2101104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER)); 2102104477Ssam } 2103104477Ssam#endif 2104104477Ssam 2105104477Ssam sc->sc_active = 5; 2106115748Ssam HIFN_UNLOCK(sc); 2107104477Ssam KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 2108104477Ssam return (err); /* success */ 2109104477Ssam 2110104477Ssamerr_dstmap: 2111104477Ssam if (cmd->src_map != cmd->dst_map) 2112104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2113104477Ssamerr_dstmap1: 2114104477Ssam if (cmd->src_map != cmd->dst_map) 2115104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2116104477Ssamerr_srcmap: 2117104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2118104477Ssam if (cmd->src_m != cmd->dst_m) 2119104477Ssam m_freem(cmd->dst_m); 2120104477Ssam } 2121104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2122104477Ssamerr_srcmap1: 2123104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2124115748Ssam HIFN_UNLOCK(sc); 2125104477Ssam return (err); 2126104477Ssam} 2127104477Ssam 2128104477Ssamstatic void 2129104477Ssamhifn_tick(void* vsc) 2130104477Ssam{ 2131104477Ssam struct hifn_softc *sc = vsc; 2132104477Ssam 2133104477Ssam HIFN_LOCK(sc); 2134104477Ssam if (sc->sc_active == 0) { 2135104477Ssam u_int32_t r = 0; 2136104477Ssam 2137213091Sgonzo if (sc->sc_cmdu == 0 && sc->sc_c_busy) { 2138104477Ssam sc->sc_c_busy = 0; 2139104477Ssam r |= HIFN_DMACSR_C_CTRL_DIS; 2140104477Ssam } 2141213091Sgonzo if (sc->sc_srcu == 0 && sc->sc_s_busy) { 2142104477Ssam sc->sc_s_busy = 0; 2143104477Ssam r |= HIFN_DMACSR_S_CTRL_DIS; 2144104477Ssam } 2145213091Sgonzo if (sc->sc_dstu == 0 && sc->sc_d_busy) { 2146104477Ssam sc->sc_d_busy = 0; 2147104477Ssam r |= HIFN_DMACSR_D_CTRL_DIS; 2148104477Ssam } 2149213091Sgonzo if (sc->sc_resu == 0 && sc->sc_r_busy) { 2150104477Ssam sc->sc_r_busy = 0; 2151104477Ssam r |= HIFN_DMACSR_R_CTRL_DIS; 2152104477Ssam } 2153104477Ssam if (r) 2154104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 2155104477Ssam } else 2156104477Ssam sc->sc_active--; 2157104477Ssam HIFN_UNLOCK(sc); 2158104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 2159104477Ssam} 2160104477Ssam 2161104477Ssamstatic void 2162104477Ssamhifn_intr(void *arg) 2163104477Ssam{ 2164104477Ssam struct hifn_softc *sc = arg; 2165104477Ssam struct hifn_dma *dma; 2166104477Ssam u_int32_t dmacsr, restart; 2167104477Ssam int i, u; 2168104477Ssam 2169115748Ssam dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 2170115748Ssam 2171115748Ssam /* Nothing in the DMA unit interrupted */ 2172115748Ssam if ((dmacsr & sc->sc_dmaier) == 0) 2173115748Ssam return; 2174115748Ssam 2175104477Ssam HIFN_LOCK(sc); 2176115748Ssam 2177104477Ssam dma = sc->sc_dma; 2178104477Ssam 2179104477Ssam#ifdef HIFN_DEBUG 2180104477Ssam if (hifn_debug) { 2181104477Ssam device_printf(sc->sc_dev, 2182104477Ssam "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 2183104477Ssam dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 2184213091Sgonzo sc->sc_cmdi, sc->sc_srci, sc->sc_dsti, sc->sc_resi, 2185213091Sgonzo sc->sc_cmdk, sc->sc_srck, sc->sc_dstk, sc->sc_resk, 2186213091Sgonzo sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu); 2187104477Ssam } 2188104477Ssam#endif 2189104477Ssam 2190104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2191104477Ssam 2192104477Ssam if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2193104477Ssam (dmacsr & HIFN_DMACSR_PUBDONE)) 2194104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2195104477Ssam READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2196104477Ssam 2197104477Ssam restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2198104477Ssam if (restart) 2199104477Ssam device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2200104477Ssam 2201104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2202104477Ssam if (dmacsr & HIFN_DMACSR_ILLR) 2203104477Ssam device_printf(sc->sc_dev, "illegal read\n"); 2204104477Ssam if (dmacsr & HIFN_DMACSR_ILLW) 2205104477Ssam device_printf(sc->sc_dev, "illegal write\n"); 2206104477Ssam } 2207104477Ssam 2208104477Ssam restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2209104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2210104477Ssam if (restart) { 2211104477Ssam device_printf(sc->sc_dev, "abort, resetting.\n"); 2212104477Ssam hifnstats.hst_abort++; 2213104477Ssam hifn_abort(sc); 2214104477Ssam HIFN_UNLOCK(sc); 2215104477Ssam return; 2216104477Ssam } 2217104477Ssam 2218213091Sgonzo if ((dmacsr & HIFN_DMACSR_C_WAIT) && (sc->sc_cmdu == 0)) { 2219104477Ssam /* 2220104477Ssam * If no slots to process and we receive a "waiting on 2221104477Ssam * command" interrupt, we disable the "waiting on command" 2222104477Ssam * (by clearing it). 2223104477Ssam */ 2224104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2225104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2226104477Ssam } 2227104477Ssam 2228104477Ssam /* clear the rings */ 2229213091Sgonzo i = sc->sc_resk; u = sc->sc_resu; 2230104477Ssam while (u != 0) { 2231104477Ssam HIFN_RESR_SYNC(sc, i, 2232104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2233104477Ssam if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2234104477Ssam HIFN_RESR_SYNC(sc, i, 2235104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2236104477Ssam break; 2237104477Ssam } 2238104477Ssam 2239104477Ssam if (i != HIFN_D_RES_RSIZE) { 2240104477Ssam struct hifn_command *cmd; 2241104477Ssam u_int8_t *macbuf = NULL; 2242104477Ssam 2243104477Ssam HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2244213091Sgonzo cmd = sc->sc_hifn_commands[i]; 2245104477Ssam KASSERT(cmd != NULL, 2246104477Ssam ("hifn_intr: null command slot %u", i)); 2247213091Sgonzo sc->sc_hifn_commands[i] = NULL; 2248104477Ssam 2249104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2250104477Ssam macbuf = dma->result_bufs[i]; 2251104477Ssam macbuf += 12; 2252104477Ssam } 2253104477Ssam 2254104477Ssam hifn_callback(sc, cmd, macbuf); 2255104477Ssam hifnstats.hst_opackets++; 2256104477Ssam u--; 2257104477Ssam } 2258104477Ssam 2259104477Ssam if (++i == (HIFN_D_RES_RSIZE + 1)) 2260104477Ssam i = 0; 2261104477Ssam } 2262213091Sgonzo sc->sc_resk = i; sc->sc_resu = u; 2263104477Ssam 2264213091Sgonzo i = sc->sc_srck; u = sc->sc_srcu; 2265104477Ssam while (u != 0) { 2266104477Ssam if (i == HIFN_D_SRC_RSIZE) 2267104477Ssam i = 0; 2268104477Ssam HIFN_SRCR_SYNC(sc, i, 2269104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2270104477Ssam if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2271104477Ssam HIFN_SRCR_SYNC(sc, i, 2272104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2273104477Ssam break; 2274104477Ssam } 2275104477Ssam i++, u--; 2276104477Ssam } 2277213091Sgonzo sc->sc_srck = i; sc->sc_srcu = u; 2278104477Ssam 2279213091Sgonzo i = sc->sc_cmdk; u = sc->sc_cmdu; 2280104477Ssam while (u != 0) { 2281104477Ssam HIFN_CMDR_SYNC(sc, i, 2282104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2283104477Ssam if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2284104477Ssam HIFN_CMDR_SYNC(sc, i, 2285104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2286104477Ssam break; 2287104477Ssam } 2288104477Ssam if (i != HIFN_D_CMD_RSIZE) { 2289104477Ssam u--; 2290104477Ssam HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2291104477Ssam } 2292104477Ssam if (++i == (HIFN_D_CMD_RSIZE + 1)) 2293104477Ssam i = 0; 2294104477Ssam } 2295213091Sgonzo sc->sc_cmdk = i; sc->sc_cmdu = u; 2296104477Ssam 2297115748Ssam HIFN_UNLOCK(sc); 2298115748Ssam 2299104477Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 2300104477Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2301104477Ssam#ifdef HIFN_DEBUG 2302104477Ssam if (hifn_debug) 2303104477Ssam device_printf(sc->sc_dev, 2304104477Ssam "wakeup crypto (%x) u %d/%d/%d/%d\n", 2305104477Ssam sc->sc_needwakeup, 2306213091Sgonzo sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu); 2307104477Ssam#endif 2308104477Ssam sc->sc_needwakeup &= ~wakeup; 2309104477Ssam crypto_unblock(sc->sc_cid, wakeup); 2310104477Ssam } 2311104477Ssam} 2312104477Ssam 2313104477Ssam/* 2314104477Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 2315104477Ssam * contains our registration id, and should contain an encoded session 2316104477Ssam * id on successful allocation. 2317104477Ssam */ 2318104477Ssamstatic int 2319167755Ssamhifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) 2320104477Ssam{ 2321167755Ssam struct hifn_softc *sc = device_get_softc(dev); 2322104477Ssam struct cryptoini *c; 2323136526Ssam int mac = 0, cry = 0, sesn; 2324136532Ssam struct hifn_session *ses = NULL; 2325104477Ssam 2326104477Ssam KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2327104477Ssam if (sidp == NULL || cri == NULL || sc == NULL) 2328104477Ssam return (EINVAL); 2329104477Ssam 2330167755Ssam HIFN_LOCK(sc); 2331136526Ssam if (sc->sc_sessions == NULL) { 2332136526Ssam ses = sc->sc_sessions = (struct hifn_session *)malloc( 2333136526Ssam sizeof(*ses), M_DEVBUF, M_NOWAIT); 2334167755Ssam if (ses == NULL) { 2335167755Ssam HIFN_UNLOCK(sc); 2336136526Ssam return (ENOMEM); 2337167755Ssam } 2338136526Ssam sesn = 0; 2339136526Ssam sc->sc_nsessions = 1; 2340136526Ssam } else { 2341136526Ssam for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 2342136526Ssam if (!sc->sc_sessions[sesn].hs_used) { 2343136526Ssam ses = &sc->sc_sessions[sesn]; 2344136526Ssam break; 2345136526Ssam } 2346136526Ssam } 2347104477Ssam 2348136526Ssam if (ses == NULL) { 2349136526Ssam sesn = sc->sc_nsessions; 2350136526Ssam ses = (struct hifn_session *)malloc((sesn + 1) * 2351136526Ssam sizeof(*ses), M_DEVBUF, M_NOWAIT); 2352167755Ssam if (ses == NULL) { 2353167755Ssam HIFN_UNLOCK(sc); 2354136526Ssam return (ENOMEM); 2355167755Ssam } 2356136526Ssam bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); 2357136526Ssam bzero(sc->sc_sessions, sesn * sizeof(*ses)); 2358136526Ssam free(sc->sc_sessions, M_DEVBUF); 2359136526Ssam sc->sc_sessions = ses; 2360136526Ssam ses = &sc->sc_sessions[sesn]; 2361136526Ssam sc->sc_nsessions++; 2362136526Ssam } 2363136526Ssam } 2364167755Ssam HIFN_UNLOCK(sc); 2365167755Ssam 2366136526Ssam bzero(ses, sizeof(*ses)); 2367136526Ssam ses->hs_used = 1; 2368136526Ssam 2369104477Ssam for (c = cri; c != NULL; c = c->cri_next) { 2370104477Ssam switch (c->cri_alg) { 2371104477Ssam case CRYPTO_MD5: 2372104477Ssam case CRYPTO_SHA1: 2373104477Ssam case CRYPTO_MD5_HMAC: 2374104477Ssam case CRYPTO_SHA1_HMAC: 2375104477Ssam if (mac) 2376104477Ssam return (EINVAL); 2377104477Ssam mac = 1; 2378158705Spjd ses->hs_mlen = c->cri_mlen; 2379158705Spjd if (ses->hs_mlen == 0) { 2380158705Spjd switch (c->cri_alg) { 2381158705Spjd case CRYPTO_MD5: 2382158705Spjd case CRYPTO_MD5_HMAC: 2383158705Spjd ses->hs_mlen = 16; 2384158705Spjd break; 2385158705Spjd case CRYPTO_SHA1: 2386158705Spjd case CRYPTO_SHA1_HMAC: 2387158705Spjd ses->hs_mlen = 20; 2388158705Spjd break; 2389158705Spjd } 2390158705Spjd } 2391104477Ssam break; 2392104477Ssam case CRYPTO_DES_CBC: 2393104477Ssam case CRYPTO_3DES_CBC: 2394120915Ssam case CRYPTO_AES_CBC: 2395104477Ssam /* XXX this may read fewer, does it matter? */ 2396136526Ssam read_random(ses->hs_iv, 2397120915Ssam c->cri_alg == CRYPTO_AES_CBC ? 2398120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2399104477Ssam /*FALLTHROUGH*/ 2400104477Ssam case CRYPTO_ARC4: 2401104477Ssam if (cry) 2402104477Ssam return (EINVAL); 2403104477Ssam cry = 1; 2404104477Ssam break; 2405104477Ssam default: 2406104477Ssam return (EINVAL); 2407104477Ssam } 2408104477Ssam } 2409104477Ssam if (mac == 0 && cry == 0) 2410104477Ssam return (EINVAL); 2411104477Ssam 2412136526Ssam *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); 2413104477Ssam 2414104477Ssam return (0); 2415104477Ssam} 2416104477Ssam 2417104477Ssam/* 2418104477Ssam * Deallocate a session. 2419104477Ssam * XXX this routine should run a zero'd mac/encrypt key into context ram. 2420104477Ssam * XXX to blow away any keys already stored there. 2421104477Ssam */ 2422104477Ssamstatic int 2423167755Ssamhifn_freesession(device_t dev, u_int64_t tid) 2424104477Ssam{ 2425167755Ssam struct hifn_softc *sc = device_get_softc(dev); 2426167755Ssam int session, error; 2427116924Ssam u_int32_t sid = CRYPTO_SESID2LID(tid); 2428104477Ssam 2429104477Ssam KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2430104477Ssam if (sc == NULL) 2431104477Ssam return (EINVAL); 2432104477Ssam 2433167755Ssam HIFN_LOCK(sc); 2434104477Ssam session = HIFN_SESSION(sid); 2435167755Ssam if (session < sc->sc_nsessions) { 2436167755Ssam bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); 2437167755Ssam error = 0; 2438167755Ssam } else 2439167755Ssam error = EINVAL; 2440167755Ssam HIFN_UNLOCK(sc); 2441104477Ssam 2442167755Ssam return (error); 2443104477Ssam} 2444104477Ssam 2445104477Ssamstatic int 2446167755Ssamhifn_process(device_t dev, struct cryptop *crp, int hint) 2447104477Ssam{ 2448167755Ssam struct hifn_softc *sc = device_get_softc(dev); 2449104477Ssam struct hifn_command *cmd = NULL; 2450120915Ssam int session, err, ivlen; 2451104477Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2452104477Ssam 2453104477Ssam if (crp == NULL || crp->crp_callback == NULL) { 2454104477Ssam hifnstats.hst_invalid++; 2455104477Ssam return (EINVAL); 2456104477Ssam } 2457104477Ssam session = HIFN_SESSION(crp->crp_sid); 2458104477Ssam 2459136526Ssam if (sc == NULL || session >= sc->sc_nsessions) { 2460104477Ssam err = EINVAL; 2461104477Ssam goto errout; 2462104477Ssam } 2463104477Ssam 2464104477Ssam cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2465104477Ssam if (cmd == NULL) { 2466104477Ssam hifnstats.hst_nomem++; 2467104477Ssam err = ENOMEM; 2468104477Ssam goto errout; 2469104477Ssam } 2470104477Ssam 2471104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2472104477Ssam cmd->src_m = (struct mbuf *)crp->crp_buf; 2473104477Ssam cmd->dst_m = (struct mbuf *)crp->crp_buf; 2474104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 2475104477Ssam cmd->src_io = (struct uio *)crp->crp_buf; 2476104477Ssam cmd->dst_io = (struct uio *)crp->crp_buf; 2477104477Ssam } else { 2478104477Ssam err = EINVAL; 2479104477Ssam goto errout; /* XXX we don't handle contiguous buffers! */ 2480104477Ssam } 2481104477Ssam 2482104477Ssam crd1 = crp->crp_desc; 2483104477Ssam if (crd1 == NULL) { 2484104477Ssam err = EINVAL; 2485104477Ssam goto errout; 2486104477Ssam } 2487104477Ssam crd2 = crd1->crd_next; 2488104477Ssam 2489104477Ssam if (crd2 == NULL) { 2490104477Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2491104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2492104477Ssam crd1->crd_alg == CRYPTO_SHA1 || 2493104477Ssam crd1->crd_alg == CRYPTO_MD5) { 2494104477Ssam maccrd = crd1; 2495104477Ssam enccrd = NULL; 2496104477Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2497104477Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2498120915Ssam crd1->crd_alg == CRYPTO_AES_CBC || 2499104477Ssam crd1->crd_alg == CRYPTO_ARC4) { 2500104477Ssam if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2501104477Ssam cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2502104477Ssam maccrd = NULL; 2503104477Ssam enccrd = crd1; 2504104477Ssam } else { 2505104477Ssam err = EINVAL; 2506104477Ssam goto errout; 2507104477Ssam } 2508104477Ssam } else { 2509104477Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2510104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2511104477Ssam crd1->crd_alg == CRYPTO_MD5 || 2512104477Ssam crd1->crd_alg == CRYPTO_SHA1) && 2513104477Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 2514104477Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 2515120915Ssam crd2->crd_alg == CRYPTO_AES_CBC || 2516104477Ssam crd2->crd_alg == CRYPTO_ARC4) && 2517104477Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2518104477Ssam cmd->base_masks = HIFN_BASE_CMD_DECODE; 2519104477Ssam maccrd = crd1; 2520104477Ssam enccrd = crd2; 2521104477Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2522104477Ssam crd1->crd_alg == CRYPTO_ARC4 || 2523120915Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2524120915Ssam crd1->crd_alg == CRYPTO_AES_CBC) && 2525104477Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 2526104477Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 2527104477Ssam crd2->crd_alg == CRYPTO_MD5 || 2528104477Ssam crd2->crd_alg == CRYPTO_SHA1) && 2529104477Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 2530104477Ssam enccrd = crd1; 2531104477Ssam maccrd = crd2; 2532104477Ssam } else { 2533104477Ssam /* 2534104477Ssam * We cannot order the 7751 as requested 2535104477Ssam */ 2536104477Ssam err = EINVAL; 2537104477Ssam goto errout; 2538104477Ssam } 2539104477Ssam } 2540104477Ssam 2541104477Ssam if (enccrd) { 2542104477Ssam cmd->enccrd = enccrd; 2543104477Ssam cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2544104477Ssam switch (enccrd->crd_alg) { 2545104477Ssam case CRYPTO_ARC4: 2546104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2547104477Ssam break; 2548104477Ssam case CRYPTO_DES_CBC: 2549104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2550104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2551104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2552104477Ssam break; 2553104477Ssam case CRYPTO_3DES_CBC: 2554104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2555104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2556104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2557104477Ssam break; 2558120915Ssam case CRYPTO_AES_CBC: 2559120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | 2560120915Ssam HIFN_CRYPT_CMD_MODE_CBC | 2561120915Ssam HIFN_CRYPT_CMD_NEW_IV; 2562120915Ssam break; 2563104477Ssam default: 2564104477Ssam err = EINVAL; 2565104477Ssam goto errout; 2566104477Ssam } 2567104477Ssam if (enccrd->crd_alg != CRYPTO_ARC4) { 2568120915Ssam ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? 2569120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2570104477Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2571104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2572120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2573104477Ssam else 2574104477Ssam bcopy(sc->sc_sessions[session].hs_iv, 2575120915Ssam cmd->iv, ivlen); 2576104477Ssam 2577104477Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2578104477Ssam == 0) { 2579159242Spjd crypto_copyback(crp->crp_flags, 2580159242Spjd crp->crp_buf, enccrd->crd_inject, 2581159242Spjd ivlen, cmd->iv); 2582104477Ssam } 2583104477Ssam } else { 2584104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2585120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2586159242Spjd else { 2587159242Spjd crypto_copydata(crp->crp_flags, 2588159242Spjd crp->crp_buf, enccrd->crd_inject, 2589159242Spjd ivlen, cmd->iv); 2590159242Spjd } 2591104477Ssam } 2592104477Ssam } 2593104477Ssam 2594125330Sphk if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 2595125330Sphk cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2596104477Ssam cmd->ck = enccrd->crd_key; 2597104477Ssam cmd->cklen = enccrd->crd_klen >> 3; 2598136526Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2599104477Ssam 2600120915Ssam /* 2601120915Ssam * Need to specify the size for the AES key in the masks. 2602120915Ssam */ 2603120915Ssam if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == 2604120915Ssam HIFN_CRYPT_CMD_ALG_AES) { 2605120915Ssam switch (cmd->cklen) { 2606120915Ssam case 16: 2607120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; 2608120915Ssam break; 2609120915Ssam case 24: 2610120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; 2611120915Ssam break; 2612120915Ssam case 32: 2613120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; 2614120915Ssam break; 2615120915Ssam default: 2616120915Ssam err = EINVAL; 2617120915Ssam goto errout; 2618120915Ssam } 2619120915Ssam } 2620104477Ssam } 2621104477Ssam 2622104477Ssam if (maccrd) { 2623104477Ssam cmd->maccrd = maccrd; 2624104477Ssam cmd->base_masks |= HIFN_BASE_CMD_MAC; 2625104477Ssam 2626104477Ssam switch (maccrd->crd_alg) { 2627104477Ssam case CRYPTO_MD5: 2628104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2629104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2630104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2631104477Ssam break; 2632104477Ssam case CRYPTO_MD5_HMAC: 2633104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2634104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2635104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2636104477Ssam break; 2637104477Ssam case CRYPTO_SHA1: 2638104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2639104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2640104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2641104477Ssam break; 2642104477Ssam case CRYPTO_SHA1_HMAC: 2643104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2644104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2645104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2646104477Ssam break; 2647104477Ssam } 2648104477Ssam 2649136526Ssam if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2650136526Ssam maccrd->crd_alg == CRYPTO_MD5_HMAC) { 2651104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2652104477Ssam bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2653104477Ssam bzero(cmd->mac + (maccrd->crd_klen >> 3), 2654104477Ssam HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2655104477Ssam } 2656104477Ssam } 2657104477Ssam 2658104477Ssam cmd->crp = crp; 2659104477Ssam cmd->session_num = session; 2660104477Ssam cmd->softc = sc; 2661104477Ssam 2662104477Ssam err = hifn_crypto(sc, cmd, crp, hint); 2663104477Ssam if (!err) { 2664104477Ssam return 0; 2665104477Ssam } else if (err == ERESTART) { 2666104477Ssam /* 2667104477Ssam * There weren't enough resources to dispatch the request 2668104477Ssam * to the part. Notify the caller so they'll requeue this 2669104477Ssam * request and resubmit it again soon. 2670104477Ssam */ 2671104477Ssam#ifdef HIFN_DEBUG 2672104477Ssam if (hifn_debug) 2673104477Ssam device_printf(sc->sc_dev, "requeue request\n"); 2674104477Ssam#endif 2675104477Ssam free(cmd, M_DEVBUF); 2676104477Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 2677104477Ssam return (err); 2678104477Ssam } 2679104477Ssam 2680104477Ssamerrout: 2681104477Ssam if (cmd != NULL) 2682104477Ssam free(cmd, M_DEVBUF); 2683104477Ssam if (err == EINVAL) 2684104477Ssam hifnstats.hst_invalid++; 2685104477Ssam else 2686104477Ssam hifnstats.hst_nomem++; 2687104477Ssam crp->crp_etype = err; 2688104477Ssam crypto_done(crp); 2689104477Ssam return (err); 2690104477Ssam} 2691104477Ssam 2692104477Ssamstatic void 2693104477Ssamhifn_abort(struct hifn_softc *sc) 2694104477Ssam{ 2695104477Ssam struct hifn_dma *dma = sc->sc_dma; 2696104477Ssam struct hifn_command *cmd; 2697104477Ssam struct cryptop *crp; 2698104477Ssam int i, u; 2699104477Ssam 2700213091Sgonzo i = sc->sc_resk; u = sc->sc_resu; 2701104477Ssam while (u != 0) { 2702213091Sgonzo cmd = sc->sc_hifn_commands[i]; 2703104477Ssam KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2704213091Sgonzo sc->sc_hifn_commands[i] = NULL; 2705104477Ssam crp = cmd->crp; 2706104477Ssam 2707104477Ssam if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2708104477Ssam /* Salvage what we can. */ 2709104477Ssam u_int8_t *macbuf; 2710104477Ssam 2711104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2712104477Ssam macbuf = dma->result_bufs[i]; 2713104477Ssam macbuf += 12; 2714104477Ssam } else 2715104477Ssam macbuf = NULL; 2716104477Ssam hifnstats.hst_opackets++; 2717104477Ssam hifn_callback(sc, cmd, macbuf); 2718104477Ssam } else { 2719104477Ssam if (cmd->src_map == cmd->dst_map) { 2720104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2721104477Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2722104477Ssam } else { 2723104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2724104477Ssam BUS_DMASYNC_POSTWRITE); 2725104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2726104477Ssam BUS_DMASYNC_POSTREAD); 2727104477Ssam } 2728104477Ssam 2729104477Ssam if (cmd->src_m != cmd->dst_m) { 2730104477Ssam m_freem(cmd->src_m); 2731104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2732104477Ssam } 2733104477Ssam 2734104477Ssam /* non-shared buffers cannot be restarted */ 2735104477Ssam if (cmd->src_map != cmd->dst_map) { 2736104477Ssam /* 2737104477Ssam * XXX should be EAGAIN, delayed until 2738104477Ssam * after the reset. 2739104477Ssam */ 2740104477Ssam crp->crp_etype = ENOMEM; 2741104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2742104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2743104477Ssam } else 2744104477Ssam crp->crp_etype = ENOMEM; 2745104477Ssam 2746104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2747104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2748104477Ssam 2749104477Ssam free(cmd, M_DEVBUF); 2750104477Ssam if (crp->crp_etype != EAGAIN) 2751104477Ssam crypto_done(crp); 2752104477Ssam } 2753104477Ssam 2754104477Ssam if (++i == HIFN_D_RES_RSIZE) 2755104477Ssam i = 0; 2756104477Ssam u--; 2757104477Ssam } 2758213091Sgonzo sc->sc_resk = i; sc->sc_resu = u; 2759104477Ssam 2760104477Ssam hifn_reset_board(sc, 1); 2761104477Ssam hifn_init_dma(sc); 2762104477Ssam hifn_init_pci_registers(sc); 2763104477Ssam} 2764104477Ssam 2765104477Ssamstatic void 2766104477Ssamhifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2767104477Ssam{ 2768104477Ssam struct hifn_dma *dma = sc->sc_dma; 2769104477Ssam struct cryptop *crp = cmd->crp; 2770104477Ssam struct cryptodesc *crd; 2771104477Ssam struct mbuf *m; 2772120915Ssam int totlen, i, u, ivlen; 2773104477Ssam 2774104477Ssam if (cmd->src_map == cmd->dst_map) { 2775104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2776104477Ssam BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2777104477Ssam } else { 2778104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2779104477Ssam BUS_DMASYNC_POSTWRITE); 2780104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2781104477Ssam BUS_DMASYNC_POSTREAD); 2782104477Ssam } 2783104477Ssam 2784104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2785104477Ssam if (cmd->src_m != cmd->dst_m) { 2786104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2787104477Ssam totlen = cmd->src_mapsize; 2788104477Ssam for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2789104477Ssam if (totlen < m->m_len) { 2790104477Ssam m->m_len = totlen; 2791104477Ssam totlen = 0; 2792104477Ssam } else 2793104477Ssam totlen -= m->m_len; 2794104477Ssam } 2795104477Ssam cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2796104477Ssam m_freem(cmd->src_m); 2797104477Ssam } 2798104477Ssam } 2799104477Ssam 2800104477Ssam if (cmd->sloplen != 0) { 2801159242Spjd crypto_copyback(crp->crp_flags, crp->crp_buf, 2802159242Spjd cmd->src_mapsize - cmd->sloplen, cmd->sloplen, 2803159242Spjd (caddr_t)&dma->slop[cmd->slopidx]); 2804104477Ssam } 2805104477Ssam 2806213091Sgonzo i = sc->sc_dstk; u = sc->sc_dstu; 2807104477Ssam while (u != 0) { 2808104477Ssam if (i == HIFN_D_DST_RSIZE) 2809104477Ssam i = 0; 2810104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2811104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2812104477Ssam if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2813104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2814104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2815104477Ssam break; 2816104477Ssam } 2817104477Ssam i++, u--; 2818104477Ssam } 2819213091Sgonzo sc->sc_dstk = i; sc->sc_dstu = u; 2820104477Ssam 2821104477Ssam hifnstats.hst_obytes += cmd->dst_mapsize; 2822104477Ssam 2823104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2824104477Ssam HIFN_BASE_CMD_CRYPT) { 2825104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2826104477Ssam if (crd->crd_alg != CRYPTO_DES_CBC && 2827120915Ssam crd->crd_alg != CRYPTO_3DES_CBC && 2828120915Ssam crd->crd_alg != CRYPTO_AES_CBC) 2829104477Ssam continue; 2830120915Ssam ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? 2831120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2832159242Spjd crypto_copydata(crp->crp_flags, crp->crp_buf, 2833159242Spjd crd->crd_skip + crd->crd_len - ivlen, ivlen, 2834159242Spjd cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2835104477Ssam break; 2836104477Ssam } 2837104477Ssam } 2838104477Ssam 2839104477Ssam if (macbuf != NULL) { 2840104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2841105275Ssam int len; 2842104477Ssam 2843158705Spjd if (crd->crd_alg != CRYPTO_MD5 && 2844158705Spjd crd->crd_alg != CRYPTO_SHA1 && 2845158705Spjd crd->crd_alg != CRYPTO_MD5_HMAC && 2846158705Spjd crd->crd_alg != CRYPTO_SHA1_HMAC) { 2847104477Ssam continue; 2848158705Spjd } 2849158705Spjd len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; 2850159242Spjd crypto_copyback(crp->crp_flags, crp->crp_buf, 2851159242Spjd crd->crd_inject, len, macbuf); 2852104477Ssam break; 2853104477Ssam } 2854104477Ssam } 2855104477Ssam 2856104477Ssam if (cmd->src_map != cmd->dst_map) { 2857104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2858104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2859104477Ssam } 2860104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2861104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2862104477Ssam free(cmd, M_DEVBUF); 2863104477Ssam crypto_done(crp); 2864104477Ssam} 2865104477Ssam 2866104477Ssam/* 2867104477Ssam * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2868104477Ssam * and Group 1 registers; avoid conditions that could create 2869104477Ssam * burst writes by doing a read in between the writes. 2870104477Ssam * 2871104477Ssam * NB: The read we interpose is always to the same register; 2872104477Ssam * we do this because reading from an arbitrary (e.g. last) 2873104477Ssam * register may not always work. 2874104477Ssam */ 2875104477Ssamstatic void 2876104477Ssamhifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2877104477Ssam{ 2878104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2879104477Ssam if (sc->sc_bar0_lastreg == reg - 4) 2880104477Ssam bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2881104477Ssam sc->sc_bar0_lastreg = reg; 2882104477Ssam } 2883104477Ssam bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2884104477Ssam} 2885104477Ssam 2886104477Ssamstatic void 2887104477Ssamhifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2888104477Ssam{ 2889104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2890104477Ssam if (sc->sc_bar1_lastreg == reg - 4) 2891104477Ssam bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2892104477Ssam sc->sc_bar1_lastreg = reg; 2893104477Ssam } 2894104477Ssam bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2895104477Ssam} 2896167755Ssam 2897167755Ssam#ifdef HIFN_VULCANDEV 2898167755Ssam/* 2899167755Ssam * this code provides support for mapping the PK engine's register 2900167755Ssam * into a userspace program. 2901167755Ssam * 2902167755Ssam */ 2903167755Ssamstatic int 2904201223Srnolandvulcanpk_mmap(struct cdev *dev, vm_ooffset_t offset, 2905201223Srnoland vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr) 2906167755Ssam{ 2907167755Ssam struct hifn_softc *sc; 2908167755Ssam vm_paddr_t pd; 2909167755Ssam void *b; 2910167755Ssam 2911167755Ssam sc = dev->si_drv1; 2912167755Ssam 2913167755Ssam pd = rman_get_start(sc->sc_bar1res); 2914167755Ssam b = rman_get_virtual(sc->sc_bar1res); 2915167755Ssam 2916167755Ssam#if 0 2917201223Srnoland printf("vpk mmap: %p(%016llx) offset=%lld\n", b, 2918201223Srnoland (unsigned long long)pd, offset); 2919167755Ssam hexdump(b, HIFN_1_PUB_MEMEND, "vpk", 0); 2920167755Ssam#endif 2921167755Ssam 2922167755Ssam if (offset == 0) { 2923167755Ssam *paddr = pd; 2924167755Ssam return (0); 2925167755Ssam } 2926167755Ssam return (-1); 2927167755Ssam} 2928167755Ssam 2929167755Ssamstatic struct cdevsw vulcanpk_cdevsw = { 2930167755Ssam .d_version = D_VERSION, 2931167755Ssam .d_mmap = vulcanpk_mmap, 2932167755Ssam .d_name = "vulcanpk", 2933167755Ssam}; 2934167755Ssam#endif /* HIFN_VULCANDEV */ 2935