esp_sbus.c revision 130293
1/*- 2 * Copyright (c) 2004 Scott Long 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28/* $NetBSD: esp_sbus.c,v 1.27 2002/12/10 13:44:47 pk Exp $ */ 29 30/*- 31 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 36 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67#include <sys/cdefs.h> 68__FBSDID("$FreeBSD: head/sys/dev/esp/esp_sbus.c 130293 2004-06-10 05:11:39Z scottl $"); 69 70#include <sys/param.h> 71#include <sys/systm.h> 72#include <sys/bus.h> 73#include <sys/kernel.h> 74#include <sys/resource.h> 75#include <sys/lock.h> 76#include <sys/mutex.h> 77 78#include <machine/bus.h> 79#include <dev/ofw/openfirm.h> 80#include <machine/ofw_machdep.h> 81#include <machine/resource.h> 82#include <sys/rman.h> 83#include <sparc64/sbus/sbusvar.h> 84 85#include <cam/cam.h> 86#include <cam/cam_ccb.h> 87#include <cam/scsi/scsi_all.h> 88 89#include <dev/esp/lsi64854reg.h> 90#include <dev/esp/lsi64854var.h> 91 92#include <dev/esp/ncr53c9xreg.h> 93#include <dev/esp/ncr53c9xvar.h> 94 95/* #define ESP_SBUS_DEBUG */ 96 97struct esp_softc { 98 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 99 struct device *sc_dev; 100 101 int sc_rid; 102 struct resource *sc_res; 103 bus_space_handle_t sc_regh; 104 bus_space_tag_t sc_regt; 105 106 int sc_irqrid; 107 struct resource *sc_irqres; 108 void *sc_irq; 109 110 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 111 112 int sc_pri; /* SBUS priority */ 113}; 114 115static int esp_sbus_probe(device_t); 116static int esp_sbus_attach(device_t); 117static int esp_sbus_detach(device_t); 118static int esp_sbus_suspend(device_t); 119static int esp_sbus_resume(device_t); 120 121static device_method_t esp_sbus_methods[] = { 122 DEVMETHOD(device_probe, esp_sbus_probe), 123 DEVMETHOD(device_attach, esp_sbus_attach), 124 DEVMETHOD(device_detach, esp_sbus_detach), 125 DEVMETHOD(device_suspend, esp_sbus_suspend), 126 DEVMETHOD(device_resume, esp_sbus_resume), 127 {0, 0} 128}; 129 130static driver_t esp_sbus_driver = { 131 "esp", 132 esp_sbus_methods, 133 sizeof(struct esp_softc) 134}; 135 136static devclass_t esp_devclass; 137DRIVER_MODULE(esp, sbus, esp_sbus_driver, esp_devclass, 0, 0); 138 139/* 140 * Functions and the switch for the MI code. 141 */ 142static u_char esp_read_reg(struct ncr53c9x_softc *, int); 143static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 144static int esp_dma_isintr(struct ncr53c9x_softc *); 145static void esp_dma_reset(struct ncr53c9x_softc *); 146static int esp_dma_intr(struct ncr53c9x_softc *); 147static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, 148 int, size_t *); 149static void esp_dma_go(struct ncr53c9x_softc *); 150static void esp_dma_stop(struct ncr53c9x_softc *); 151static int esp_dma_isactive(struct ncr53c9x_softc *); 152static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 153 154static struct ncr53c9x_glue esp_sbus_glue = { 155 esp_read_reg, 156 esp_write_reg, 157 esp_dma_isintr, 158 esp_dma_reset, 159 esp_dma_intr, 160 esp_dma_setup, 161 esp_dma_go, 162 esp_dma_stop, 163 esp_dma_isactive, 164 NULL, /* gl_clear_latched_intr */ 165}; 166 167static int 168esp_sbus_probe(device_t dev) 169{ 170 char *name; 171 172 name = sbus_get_name(dev); 173 if (strcmp("SUNW,fas", name) == 0) { 174 device_set_desc(dev, "Sun FAS366 Fast-Wide SCSI"); 175 return (-10); 176 } 177 178 return (ENXIO); 179} 180 181static int 182esp_sbus_attach(device_t dev) 183{ 184 struct esp_softc *esc = device_get_softc(dev); 185 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 186 struct lsi64854_softc *lsc; 187 phandle_t node; 188 int burst; 189 190 esc->sc_dev = dev; 191 node = sbus_get_node(dev); 192 if (OF_getprop(node, "initiator-id", &sc->sc_id, 193 sizeof(sc->sc_id)) == -1) 194 sc->sc_id = 7;; 195 sc->sc_freq = sbus_get_clockfreq(dev); 196 197#ifdef ESP_SBUS_DEBUG 198 device_printf(dev, "espattach_sbus: sc_id %d, freq %d\n", 199 sc->sc_id, sc->sc_freq); 200#endif 201 202 /* 203 * allocate space for dma, in SUNW,fas there are no separate 204 * dma device 205 */ 206 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 207 208 if (lsc == NULL) { 209 device_printf(dev, "out of memory (lsi64854_softc)\n"); 210 return (ENOMEM); 211 } 212 esc->sc_dma = lsc; 213 214 /* 215 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 216 */ 217 218 /* Map dma registers */ 219 lsc->sc_rid = 0; 220 if ((lsc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 221 &lsc->sc_rid, RF_ACTIVE)) == NULL) { 222 device_printf(dev, "cannot map dma registers\n"); 223 free(lsc, M_DEVBUF); 224 return (ENXIO); 225 } 226 lsc->sc_regt = rman_get_bustag(lsc->sc_res); 227 lsc->sc_regh = rman_get_bushandle(lsc->sc_res); 228 229 /* Create a parent DMA tag based on this bus */ 230 if (bus_dma_tag_create(NULL, /* parent */ 231 PAGE_SIZE, 0, /* algnmnt, boundary */ 232 BUS_SPACE_MAXADDR, /* lowaddr */ 233 BUS_SPACE_MAXADDR, /* highaddr */ 234 NULL, NULL, /* filter, filterarg */ 235 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 236 0, /* nsegments */ 237 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 238 0, /* flags */ 239 NULL, NULL, /* No locking */ 240 &lsc->sc_parent_dmat)) { 241 device_printf(dev, "cannot allocate parent DMA tag\n"); 242 free(lsc, M_DEVBUF); 243 return (ENOMEM); 244 } 245 burst = sbus_get_burstsz(dev); 246 247#ifdef ESP_SBUS_DEBUG 248 printf("espattach_sbus: burst 0x%x\n", burst); 249#endif 250 251 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 252 (burst & SBUS_BURST_16) ? 16 : 0; 253 254 lsc->sc_channel = L64854_CHANNEL_SCSI; 255 lsc->sc_client = sc; 256 lsc->sc_dev = dev; 257 258 lsi64854_attach(lsc); 259 260 /* 261 * map SCSI core registers 262 */ 263 esc->sc_rid = 1; 264 if ((esc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 265 &esc->sc_rid, RF_ACTIVE)) == NULL) { 266 device_printf(dev, "cannot map scsi core registers\n"); 267 free(lsc, M_DEVBUF); 268 return (ENXIO); 269 } 270 esc->sc_regt = rman_get_bustag(esc->sc_res); 271 esc->sc_regh = rman_get_bushandle(esc->sc_res); 272 273#if 0 274 esc->sc_pri = sa->sa_pri; 275 276 /* add me to the sbus structures */ 277 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 278 sbus_establish(&esc->sc_sd, &sc->sc_dev); 279#endif 280 281 espattach(esc, &esp_sbus_glue); 282 283 return (0); 284} 285 286static int 287esp_sbus_detach(device_t dev) 288{ 289 struct ncr53c9x_softc *sc; 290 struct esp_softc *esc; 291 292 esc = device_get_softc(dev); 293 sc = &esc->sc_ncr53c9x; 294 return (ncr53c9x_detach(sc, 0)); 295} 296 297static int 298esp_sbus_suspend(device_t dev) 299{ 300 return (ENXIO); 301} 302 303static int 304esp_sbus_resume(device_t dev) 305{ 306 return (ENXIO); 307} 308 309/* 310 * Attach this instance, and then all the sub-devices 311 */ 312void 313espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep) 314{ 315 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 316 unsigned int uid = 0; 317 318 /* 319 * Set up glue for MI code early; we use some of it here. 320 */ 321 sc->sc_glue = gluep; 322 323 /* gimme MHz */ 324 sc->sc_freq /= 1000000; 325 326 /* 327 * XXX More of this should be in ncr53c9x_attach(), but 328 * XXX should we really poke around the chip that much in 329 * XXX the MI code? Think about this more... 330 */ 331 332 /* 333 * It is necessary to try to load the 2nd config register here, 334 * to find out what rev the esp chip is, else the ncr53c9x_reset 335 * will not set up the defaults correctly. 336 */ 337 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 338 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 339 sc->sc_cfg3 = NCRCFG3_CDB; 340 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 341 342 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 343 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 344 sc->sc_rev = NCR_VARIANT_ESP100; 345 } else { 346 sc->sc_cfg2 = NCRCFG2_SCSI2; 347 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 348 sc->sc_cfg3 = 0; 349 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 350 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 351 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 352 if (NCR_READ_REG(sc, NCR_CFG3) != 353 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 354 sc->sc_rev = NCR_VARIANT_ESP100A; 355 } else { 356 /* NCRCFG2_FE enables > 64K transfers */ 357 sc->sc_cfg2 |= NCRCFG2_FE; 358 sc->sc_cfg3 = 0; 359 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 360 sc->sc_rev = NCR_VARIANT_ESP200; 361 362 /* XXX spec says it's valid after power up or chip reset */ 363 uid = NCR_READ_REG(sc, NCR_UID); 364 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 365 sc->sc_rev = NCR_VARIANT_FAS366; 366 } 367 } 368 369#ifdef ESP_SBUS_DEBUG 370 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 371#endif 372 373 /* 374 * XXX minsync and maxxfer _should_ be set up in MI code, 375 * XXX but it appears to have some dependency on what sort 376 * XXX of DMA we're hooked up to, etc. 377 */ 378 379 /* 380 * This is the value used to start sync negotiations 381 * Note that the NCR register "SYNCTP" is programmed 382 * in "clocks per byte", and has a minimum value of 4. 383 * The SCSI period used in negotiation is one-fourth 384 * of the time (in nanoseconds) needed to transfer one byte. 385 * Since the chip's clock is given in MHz, we have the following 386 * formula: 4 * period = (1000 / freq) * 4 387 */ 388 sc->sc_minsync = 1000 / sc->sc_freq; 389 390 /* limit minsync due to unsolved performance issues */ 391 sc->sc_maxsync = sc->sc_minsync; 392 sc->sc_maxoffset = 15; 393 394 /* 395 * Alas, we must now modify the value a bit, because it's 396 * only valid when can switch on FASTCLK and FASTSCSI bits 397 * in config register 3... 398 */ 399 switch (sc->sc_rev) { 400 case NCR_VARIANT_ESP100: 401 sc->sc_maxwidth = 0; 402 sc->sc_maxxfer = 64 * 1024; 403 sc->sc_minsync = 0; /* No synch on old chip? */ 404 break; 405 406 case NCR_VARIANT_ESP100A: 407 sc->sc_maxwidth = 1; 408 sc->sc_maxxfer = 64 * 1024; 409 /* Min clocks/byte is 5 */ 410 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 411 break; 412 413 case NCR_VARIANT_ESP200: 414 case NCR_VARIANT_FAS366: 415 sc->sc_maxwidth = 1; 416 sc->sc_maxxfer = 16 * 1024 * 1024; 417 /* XXX - do actually set FAST* bits */ 418 break; 419 } 420 421 /* Establish interrupt channel */ 422 esc->sc_irqrid = 0; 423 if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ, 424 &esc->sc_irqrid, RF_SHAREABLE|RF_ACTIVE)) == NULL) { 425 device_printf(esc->sc_dev, "Cannot allocate interrupt\n"); 426 return; 427 } 428 if (bus_setup_intr(esc->sc_dev, esc->sc_irqres, 429 INTR_TYPE_BIO|INTR_ENTROPY, ncr53c9x_intr, sc, &esc->sc_irq)) { 430 device_printf(esc->sc_dev, "Cannot set up interrupt\n"); 431 return; 432 } 433 434 /* Turn on target selection using the `dma' method */ 435 if (sc->sc_rev != NCR_VARIANT_FAS366) 436 sc->sc_features |= NCR_F_DMASELECT; 437 438 /* Do the common parts of attachment. */ 439 sc->sc_dev = esc->sc_dev; 440 ncr53c9x_attach(sc); 441} 442 443/* 444 * Glue functions. 445 */ 446 447#ifdef ESP_SBUS_DEBUG 448int esp_sbus_debug = 0; 449 450static struct { 451 char *r_name; 452 int r_flag; 453} esp__read_regnames [] = { 454 { "TCL", 0}, /* 0/00 */ 455 { "TCM", 0}, /* 1/04 */ 456 { "FIFO", 0}, /* 2/08 */ 457 { "CMD", 0}, /* 3/0c */ 458 { "STAT", 0}, /* 4/10 */ 459 { "INTR", 0}, /* 5/14 */ 460 { "STEP", 0}, /* 6/18 */ 461 { "FFLAGS", 1}, /* 7/1c */ 462 { "CFG1", 1}, /* 8/20 */ 463 { "STAT2", 0}, /* 9/24 */ 464 { "CFG4", 1}, /* a/28 */ 465 { "CFG2", 1}, /* b/2c */ 466 { "CFG3", 1}, /* c/30 */ 467 { "-none", 1}, /* d/34 */ 468 { "TCH", 1}, /* e/38 */ 469 { "TCX", 1}, /* f/3c */ 470}; 471 472static struct { 473 char *r_name; 474 int r_flag; 475} esp__write_regnames[] = { 476 { "TCL", 1}, /* 0/00 */ 477 { "TCM", 1}, /* 1/04 */ 478 { "FIFO", 0}, /* 2/08 */ 479 { "CMD", 0}, /* 3/0c */ 480 { "SELID", 1}, /* 4/10 */ 481 { "TIMEOUT", 1}, /* 5/14 */ 482 { "SYNCTP", 1}, /* 6/18 */ 483 { "SYNCOFF", 1}, /* 7/1c */ 484 { "CFG1", 1}, /* 8/20 */ 485 { "CCF", 1}, /* 9/24 */ 486 { "TEST", 1}, /* a/28 */ 487 { "CFG2", 1}, /* b/2c */ 488 { "CFG3", 1}, /* c/30 */ 489 { "-none", 1}, /* d/34 */ 490 { "TCH", 1}, /* e/38 */ 491 { "TCX", 1}, /* f/3c */ 492}; 493#endif 494 495u_char 496esp_read_reg(struct ncr53c9x_softc *sc, int reg) 497{ 498 struct esp_softc *esc = (struct esp_softc *)sc; 499 u_char v; 500 501 v = bus_space_read_1(esc->sc_regt, esc->sc_regh, reg * 4); 502#ifdef ESP_SBUS_DEBUG 503 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 504 printf("RD:%x <%s> %x\n", reg * 4, 505 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 506#endif 507 return v; 508} 509 510void 511esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 512{ 513 struct esp_softc *esc = (struct esp_softc *)sc; 514 515#ifdef ESP_SBUS_DEBUG 516 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 517 printf("WR:%x <%s> %x\n", reg * 4, 518 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 519#endif 520 bus_space_write_1(esc->sc_regt, esc->sc_regh, reg * 4, v); 521} 522 523int 524esp_dma_isintr(struct ncr53c9x_softc *sc) 525{ 526 struct esp_softc *esc = (struct esp_softc *)sc; 527 528 return (DMA_ISINTR(esc->sc_dma)); 529} 530 531void 532esp_dma_reset(struct ncr53c9x_softc *sc) 533{ 534 struct esp_softc *esc = (struct esp_softc *)sc; 535 536 DMA_RESET(esc->sc_dma); 537} 538 539int 540esp_dma_intr(struct ncr53c9x_softc *sc) 541{ 542 struct esp_softc *esc = (struct esp_softc *)sc; 543 544 return (DMA_INTR(esc->sc_dma)); 545} 546 547int 548esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 549 int datain, size_t *dmasize) 550{ 551 struct esp_softc *esc = (struct esp_softc *)sc; 552 553 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 554} 555 556void 557esp_dma_go(struct ncr53c9x_softc *sc) 558{ 559 struct esp_softc *esc = (struct esp_softc *)sc; 560 561 DMA_GO(esc->sc_dma); 562} 563 564void 565esp_dma_stop(struct ncr53c9x_softc *sc) 566{ 567 struct esp_softc *esc = (struct esp_softc *)sc; 568 u_int32_t csr; 569 570 csr = L64854_GCSR(esc->sc_dma); 571 csr &= ~D_EN_DMA; 572 L64854_SCSR(esc->sc_dma, csr); 573} 574 575int 576esp_dma_isactive(struct ncr53c9x_softc *sc) 577{ 578 struct esp_softc *esc = (struct esp_softc *)sc; 579 580 return (DMA_ISACTIVE(esc->sc_dma)); 581} 582