if_ed.c revision 8486
162143Sarchie/* 262143Sarchie * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 362143Sarchie * adapters. By David Greenman, 29-April-1993 4139823Simp * 5139823Simp * Copyright (C) 1993, David Greenman. This software may be used, modified, 6139823Simp * copied, distributed, and sold, in both source and binary form provided 762143Sarchie * that the above copyright and these terms are retained. Under no 862143Sarchie * circumstances is the author responsible for the proper functioning 962143Sarchie * of this software, nor does the author assume any responsibility 1062143Sarchie * for damages incurred with its use. 1162143Sarchie * 1262143Sarchie * Currently supports the Western Digital/SMC 8003 and 8013 series, 1362143Sarchie * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 1462143Sarchie * and a variety of similar clones. 1562143Sarchie * 1662143Sarchie * $Id: if_ed.c,v 1.70 1995/05/04 07:56:23 davidg Exp $ 1762143Sarchie */ 1862143Sarchie 1962143Sarchie#include "ed.h" 2062143Sarchie#include "bpfilter.h" 2162143Sarchie 2262143Sarchie#include <sys/param.h> 2362143Sarchie#include <sys/systm.h> 2462143Sarchie#include <sys/errno.h> 2562143Sarchie#include <sys/ioctl.h> 2662143Sarchie#include <sys/mbuf.h> 2762143Sarchie#include <sys/socket.h> 2862143Sarchie#include <sys/syslog.h> 2962143Sarchie#include <sys/devconf.h> 3062143Sarchie 3162143Sarchie#include <net/if.h> 3262143Sarchie#include <net/if_dl.h> 3362143Sarchie#include <net/if_types.h> 3462143Sarchie 3562143Sarchie#ifdef INET 3662143Sarchie#include <netinet/in.h> 3762143Sarchie#include <netinet/in_systm.h> 3862143Sarchie#include <netinet/in_var.h> 3962143Sarchie#include <netinet/ip.h> 4062143Sarchie#include <netinet/if_ether.h> 4162143Sarchie#endif 4262143Sarchie 4362143Sarchie#ifdef NS 4462143Sarchie#include <netns/ns.h> 4562143Sarchie#include <netns/ns_if.h> 4662143Sarchie#endif 4762143Sarchie 4862143Sarchie#if NBPFILTER > 0 4962143Sarchie#include <net/bpf.h> 5062143Sarchie#include <net/bpfdesc.h> 5162143Sarchie#endif 5262143Sarchie 5362143Sarchie#include <machine/clock.h> 5462143Sarchie 5562143Sarchie#include <i386/isa/isa.h> 5662143Sarchie#include <i386/isa/isa_device.h> 57181803Sbz#include <i386/isa/icu.h> 5862143Sarchie#include <i386/isa/if_edreg.h> 5962143Sarchie 60141721Sglebius/* For backwards compatibility */ 6162143Sarchie#ifndef IFF_ALTPHYS 6262143Sarchie#define IFF_ALTPHYS IFF_LINK0 6362143Sarchie#endif 6462143Sarchie 65151305Sthompsa/* 66189106Sbz * ed_softc: per line info and status 67185571Sbz */ 6862143Sarchiestruct ed_softc { 6962143Sarchie struct arpcom arpcom; /* ethernet common */ 7062143Sarchie 7162143Sarchie char *type_str; /* pointer to type string */ 7262143Sarchie u_char vendor; /* interface vendor */ 7362143Sarchie u_char type; /* interface type code */ 74152243Sru 7562143Sarchie u_short asic_addr; /* ASIC I/O bus address */ 76191510Szec u_short nic_addr; /* NIC (DS8390) I/O bus address */ 77191510Szec 78191510Szec/* 79191510Szec * The following 'proto' variable is part of a work-around for 8013EBT asics 80191510Szec * being write-only. It's sort of a prototype/shadow of the real thing. 81191510Szec */ 82191510Szec u_char wd_laar_proto; 83191510Szec u_char cr_proto; 84191510Szec u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 85191510Szec int is790; /* set by the probe code if the card is 790 86191510Szec * based */ 87126035Spjd 88126035Spjd caddr_t bpf; /* BPF "magic cookie" */ 89126035Spjd caddr_t mem_start; /* NIC memory start address */ 90126035Spjd caddr_t mem_end; /* NIC memory end address */ 91129281Sarchie u_long mem_size; /* total NIC memory size */ 92129281Sarchie caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 93126035Spjd 94126035Spjd u_char mem_shared; /* NIC memory is shared with host */ 95126035Spjd u_char xmit_busy; /* transmitter is busy */ 96126035Spjd u_char txb_cnt; /* number of transmit buffers */ 97126035Spjd u_char txb_inuse; /* number of TX buffers currently in-use */ 98126035Spjd 9962143Sarchie u_char txb_new; /* pointer to where new buffer will be added */ 100106933Ssam u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 101106933Ssam u_short txb_len[8]; /* buffered xmit buffer lengths */ 102106933Ssam u_char tx_page_start; /* first page of TX buffer area */ 103106933Ssam u_char rec_page_start; /* first page of RX ring-buffer */ 104106933Ssam u_char rec_page_stop; /* last page of RX ring-buffer */ 105106933Ssam u_char next_packet; /* pointer to next unread RX packet */ 106139903Sglebius struct kern_devconf kdc; /* kernel configuration database info */ 107106933Ssam} ed_softc[NED]; 10862143Sarchie 109106933Ssamint ed_attach(struct isa_device *); 110106933Ssamvoid ed_init(int); 11162143Sarchievoid edintr(int); 11262143Sarchieint ed_ioctl(struct ifnet *, int, caddr_t); 11362143Sarchieint ed_probe(struct isa_device *); 114139903Sglebiusvoid ed_start(struct ifnet *); 11562143Sarchievoid ed_reset(int); 11662143Sarchievoid ed_watchdog(int); 117186488Sjulianint ed_probe_generic8390(struct ed_softc *); 118186488Sjulianint ed_probe_WD80x3(struct isa_device *); 11962143Sarchieint ed_probe_3Com(struct isa_device *); 12062143Sarchieint ed_probe_Novell(struct isa_device *); 12162143Sarchie 12262143Sarchievoid ds_getmcaf(); 12370700Sjulian 12462143Sarchiestatic void ed_get_packet(struct ed_softc *, char *, int /* u_short */ , int); 12562143Sarchiestatic void ed_stop(int); 12662143Sarchie 12762143Sarchiestatic inline void ed_rint(); 12862143Sarchiestatic inline void ed_xmit(); 12962143Sarchiestatic inline char *ed_ring_copy(); 13062143Sarchie 13162143Sarchievoid ed_pio_readmem(), ed_pio_writemem(); 13262143Sarchieu_short ed_pio_write_mbufs(); 13362143Sarchie 13462143Sarchievoid ed_setrcr(struct ifnet *, struct ed_softc *); 13562143Sarchie 13662143Sarchiestruct isa_driver eddriver = { 13762143Sarchie ed_probe, 13862143Sarchie ed_attach, 13962143Sarchie "ed", 14062143Sarchie 1 /* We are ultra sensitive */ 14162143Sarchie}; 14262143Sarchie 14362143Sarchie/* 14462143Sarchie * Interrupt conversion table for WD/SMC ASIC/83C584 14564358Sarchie * (IRQ* are defined in icu.h) 14664358Sarchie */ 14764358Sarchiestatic unsigned short ed_intr_mask[] = { 14864358Sarchie IRQ9, 14964358Sarchie IRQ3, 150123600Sru IRQ5, 15164358Sarchie IRQ7, 15264358Sarchie IRQ10, 15364358Sarchie IRQ11, 15464653Sarchie IRQ15, 15564653Sarchie IRQ4 156123600Sru}; 15764653Sarchie 15864653Sarchie/* 15964653Sarchie * Interrupt conversion table for 83C790 16064653Sarchie */ 16164653Sarchiestatic unsigned short ed_790_intr_mask[] = { 16264653Sarchie 0, 16364653Sarchie IRQ9, 16464653Sarchie IRQ3, 16564653Sarchie IRQ5, 16664653Sarchie IRQ7, 16764653Sarchie IRQ10, 16864358Sarchie IRQ11, 16964358Sarchie IRQ15 17064358Sarchie}; 17164358Sarchie 17264358Sarchie#define ETHER_MIN_LEN 64 17364358Sarchie#define ETHER_MAX_LEN 1518 17464358Sarchie#define ETHER_ADDR_LEN 6 17564653Sarchie#define ETHER_HDR_SIZE 14 17664653Sarchie 17764653Sarchiestatic struct kern_devconf kdc_ed_template = { 17864653Sarchie 0, 0, 0, /* filled in by dev_attach */ 17964653Sarchie "ed", 0, { MDDT_ISA, 0, "net" }, 18064653Sarchie isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 18164653Sarchie &kdc_isa0, /* parent */ 18264358Sarchie 0, /* parentdata */ 18364358Sarchie DC_UNCONFIGURED, /* state */ 18464358Sarchie "", /* description */ 18564358Sarchie DC_CLS_NETIF /* class */ 18664358Sarchie}; 187141721Sglebius 188141721Sglebiusstatic inline void 189141721Sglebiused_registerdev(struct isa_device *id, const char *descr) 190141721Sglebius{ 191141721Sglebius struct kern_devconf *kdc = &ed_softc[id->id_unit].kdc; 192141721Sglebius char *longdescr; 193141721Sglebius *kdc = kdc_ed_template; 194141721Sglebius kdc->kdc_unit = id->id_unit; 195141721Sglebius kdc->kdc_parentdata = id; 196141721Sglebius kdc->kdc_description = descr; 197141721Sglebius dev_attach(kdc); 198141721Sglebius} 199141721Sglebius 200141721Sglebius/* 201141910Sglebius * Determine if the device is present 202141910Sglebius * 203141910Sglebius * on entry: 204141910Sglebius * a pointer to an isa_device struct 205141910Sglebius * on exit: 206141910Sglebius * NULL if device not found 207141910Sglebius * or # of i/o addresses used (if found) 20862143Sarchie */ 20962143Sarchieint 21062143Sarchieed_probe(isa_dev) 21162143Sarchie struct isa_device *isa_dev; 212129823Sjulian{ 213129823Sjulian int nports; 214129823Sjulian 215129823Sjulian#ifndef DEV_LKM 216129823Sjulian ed_registerdev(isa_dev, "Ethernet adapter"); 217129823Sjulian#endif /* not DEV_LKM */ 218129823Sjulian 219129823Sjulian nports = ed_probe_WD80x3(isa_dev); 220129823Sjulian if (nports) 221129823Sjulian return (nports); 22262143Sarchie 22362143Sarchie nports = ed_probe_3Com(isa_dev); 22462143Sarchie if (nports) 22562143Sarchie return (nports); 22662143Sarchie 22762143Sarchie nports = ed_probe_Novell(isa_dev); 22862143Sarchie if (nports) 22962143Sarchie return (nports); 23062143Sarchie 23162143Sarchie return (0); 23262143Sarchie} 23362143Sarchie 23462143Sarchie/* 23562143Sarchie * Generic probe routine for testing for the existance of a DS8390. 236106933Ssam * Must be called after the NIC has just been reset. This routine 23762143Sarchie * works by looking at certain register values that are guaranteed 23862143Sarchie * to be initialized a certain way after power-up or reset. Seems 23970784Sjulian * not to currently work on the 83C690. 240129281Sarchie * 24162143Sarchie * Specifically: 24262143Sarchie * 243129281Sarchie * Register reset bits set bits 24462143Sarchie * Command Register (CR) TXP, STA RD2, STP 245129281Sarchie * Interrupt Status (ISR) RST 24662143Sarchie * Interrupt Mask (IMR) All bits 24762143Sarchie * Data Control (DCR) LAS 24862143Sarchie * Transmit Config. (TCR) LB1, LB0 24962143Sarchie * 25062143Sarchie * We only look at the CR and ISR registers, however, because looking at 25162143Sarchie * the others would require changing register pages (which would be 25262143Sarchie * intrusive if this isn't an 8390). 25362143Sarchie * 25462143Sarchie * Return 1 if 8390 was found, 0 if not. 255106933Ssam */ 25662143Sarchie 25762143Sarchieint 25870784Sjulianed_probe_generic8390(sc) 259129281Sarchie struct ed_softc *sc; 26062143Sarchie{ 261129281Sarchie if ((inb(sc->nic_addr + ED_P0_CR) & 262129281Sarchie (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 26362143Sarchie (ED_CR_RD2 | ED_CR_STP)) 26462143Sarchie return (0); 26562143Sarchie if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 266129281Sarchie return (0); 26762143Sarchie 26862143Sarchie return (1); 26962143Sarchie} 27062143Sarchie 27162143Sarchie/* 27262143Sarchie * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 27362143Sarchie */ 27462143Sarchieint 27562143Sarchieed_probe_WD80x3(isa_dev) 27662143Sarchie struct isa_device *isa_dev; 27770784Sjulian{ 27862143Sarchie struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 27962143Sarchie int i; 28062143Sarchie u_int memsize; 28162143Sarchie u_char iptr, isa16bit, sum; 28262143Sarchie 28362143Sarchie sc->asic_addr = isa_dev->id_iobase; 28462143Sarchie sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 285194012Szec sc->is790 = 0; 28670700Sjulian 287194012Szec#ifdef TOSH_ETHER 28862143Sarchie outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 28962143Sarchie DELAY(10000); 29062143Sarchie#endif 29162143Sarchie 29262143Sarchie /* 29362143Sarchie * Attempt to do a checksum over the station address PROM. If it 29462143Sarchie * fails, it's probably not a SMC/WD board. There is a problem with 29562143Sarchie * this, though: some clone WD boards don't pass the checksum test. 29662143Sarchie * Danpex boards for one. 29762143Sarchie */ 29862143Sarchie for (sum = 0, i = 0; i < 8; ++i) 29962143Sarchie sum += inb(sc->asic_addr + ED_WD_PROM + i); 30062143Sarchie 301191510Szec if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 302191510Szec 303191510Szec /* 304191510Szec * Checksum is invalid. This often happens with cheap WD8003E 305191510Szec * clones. In this case, the checksum byte (the eighth byte) 306191510Szec * seems to always be zero. 307191510Szec */ 308191510Szec if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 309191510Szec inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 310191510Szec return (0); 311191510Szec } 312191510Szec /* reset card to force it into a known state. */ 31362143Sarchie#ifdef TOSH_ETHER 31487599Sobrien outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 31562143Sarchie#else 31662143Sarchie outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 317121816Sbrooks#endif 31862143Sarchie DELAY(100); 31962143Sarchie outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 32062143Sarchie /* wait in the case this card is reading it's EEROM */ 32162143Sarchie DELAY(5000); 322184205Sdes 32362143Sarchie sc->vendor = ED_VENDOR_WD_SMC; 32462143Sarchie sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 325121816Sbrooks 32670784Sjulian /* 32762143Sarchie * Set initial values for width/size. 32862143Sarchie */ 32970784Sjulian memsize = 8192; 33062143Sarchie isa16bit = 0; 331152243Sru switch (sc->type) { 33290249Sarchie case ED_TYPE_WD8003S: 33362143Sarchie sc->type_str = "WD8003S"; 33462143Sarchie sc->kdc.kdc_description = "Ethernet adapter: WD 8003S"; 335121816Sbrooks break; 33662143Sarchie case ED_TYPE_WD8003E: 337121816Sbrooks sc->type_str = "WD8003E"; 33862143Sarchie sc->kdc.kdc_description = "Ethernet adapter: WD 8003E"; 33962143Sarchie break; 34062143Sarchie case ED_TYPE_WD8003EB: 34162143Sarchie sc->type_str = "WD8003EB"; 34262143Sarchie sc->kdc.kdc_description = "Ethernet adapter: WD 8003EB"; 34371849Sjulian break; 34462143Sarchie case ED_TYPE_WD8003W: 34562143Sarchie sc->type_str = "WD8003W"; 34662143Sarchie sc->kdc.kdc_description = "Ethernet adapter: WD 8003W"; 34762143Sarchie break; 34862143Sarchie case ED_TYPE_WD8013EBT: 34971849Sjulian sc->type_str = "WD8013EBT"; 35062143Sarchie sc->kdc.kdc_description = "Ethernet adapter: WD 8013EBT"; 35171849Sjulian memsize = 16384; 35271849Sjulian isa16bit = 1; 35371849Sjulian break; 35471849Sjulian case ED_TYPE_WD8013W: 35571849Sjulian sc->type_str = "WD8013W"; 35671849Sjulian sc->kdc.kdc_description = "Ethernet adapter: WD 8013W"; 357152243Sru memsize = 16384; 35871849Sjulian isa16bit = 1; 35971849Sjulian break; 36062143Sarchie case ED_TYPE_WD8013EP: /* also WD8003EP */ 36162143Sarchie if (inb(sc->asic_addr + ED_WD_ICR) 362139903Sglebius & ED_WD_ICR_16BIT) { 363139903Sglebius isa16bit = 1; 364139903Sglebius memsize = 16384; 365139903Sglebius sc->type_str = "WD8013EP"; 366139903Sglebius sc->kdc.kdc_description = 367139903Sglebius "Ethernet adapter: WD 8013EP"; 368139903Sglebius } else { 369139903Sglebius sc->type_str = "WD8003EP"; 370139903Sglebius sc->kdc.kdc_description = 371139903Sglebius "Ethernet adapter: WD 8003EP"; 372139903Sglebius } 373139903Sglebius break; 374139903Sglebius case ED_TYPE_WD8013WC: 375139903Sglebius sc->type_str = "WD8013WC"; 376139903Sglebius sc->kdc.kdc_description = "Ethernet adapter: WD 8013WC"; 377139903Sglebius memsize = 16384; 378139903Sglebius isa16bit = 1; 379139903Sglebius break; 380139903Sglebius case ED_TYPE_WD8013EBP: 381139903Sglebius sc->type_str = "WD8013EBP"; 382139903Sglebius sc->kdc.kdc_description = "Ethernet adapter: WD 8013EBP"; 383139903Sglebius memsize = 16384; 384139903Sglebius isa16bit = 1; 385139903Sglebius break; 386139903Sglebius case ED_TYPE_WD8013EPC: 387139903Sglebius sc->type_str = "WD8013EPC"; 388139903Sglebius sc->kdc.kdc_description = "Ethernet adapter: WD 8013EPC"; 38962143Sarchie memsize = 16384; 39062143Sarchie isa16bit = 1; 39162143Sarchie break; 39262143Sarchie case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 39362143Sarchie (unsigned int) *(isa_dev->id_maddr+8192) = (unsigned int)0; 39462143Sarchie if ((unsigned int) *(isa_dev->id_maddr+8192)) { 39562143Sarchie sc->type_str = "SMC8416C/SMC8416BT"; 39662143Sarchie sc->kdc.kdc_description = 39762143Sarchie "Ethernet adapter: SMC 8416C or 8416BT"; 39862143Sarchie memsize = 8192; 39970700Sjulian } else { 40062143Sarchie sc->type_str = "SMC8216/SMC8216C"; 40162143Sarchie sc->kdc.kdc_description = 40262143Sarchie "Ethernet adapter: SMC 8216 or 8216C"; 40362143Sarchie memsize = 16384; 40462143Sarchie } 40562143Sarchie isa16bit = 1; 40662143Sarchie sc->is790 = 1; 40762143Sarchie break; 40862143Sarchie case ED_TYPE_SMC8216T: 40962143Sarchie sc->type_str = "SMC8216T"; 41070784Sjulian sc->kdc.kdc_description = 41162143Sarchie "Ethernet adapter: SMC 8216T"; 41262143Sarchie 41362143Sarchie outb(sc->asic_addr + ED_WD790_HWR, 41462143Sarchie inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 41562143Sarchie switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 41662143Sarchie case ED_WD790_RAR_SZ64: 41762143Sarchie memsize = 65536; 418186488Sjulian break; 41962143Sarchie case ED_WD790_RAR_SZ32: 420186488Sjulian memsize = 32768; 421194012Szec break; 422186488Sjulian case ED_WD790_RAR_SZ16: 42362143Sarchie memsize = 16384; 424186488Sjulian break; 425186488Sjulian case ED_WD790_RAR_SZ8: 426129281Sarchie sc->type_str = "SMC8416T"; 427186488Sjulian sc->kdc.kdc_description = 428186488Sjulian "Ethernet adapter: SMC 8416T"; 42962143Sarchie memsize = 8192; 43062143Sarchie break; 43162143Sarchie } 43262143Sarchie outb(sc->asic_addr + ED_WD790_HWR, 43362143Sarchie inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 43462143Sarchie 43590249Sarchie isa16bit = 1; 43690249Sarchie sc->is790 = 1; 43790249Sarchie break; 43890249Sarchie#ifdef TOSH_ETHER 43962143Sarchie case ED_TYPE_TOSHIBA1: 44062143Sarchie sc->type_str = "Toshiba1"; 44162143Sarchie sc->kdc.kdc_description = "Ethernet adapter: Toshiba1"; 44262143Sarchie memsize = 32768; 44362143Sarchie isa16bit = 1; 44462143Sarchie break; 44562143Sarchie case ED_TYPE_TOSHIBA4: 44662143Sarchie sc->type_str = "Toshiba4"; 44762143Sarchie sc->kdc.kdc_description = "Ethernet adapter: Toshiba4"; 44870700Sjulian memsize = 32768; 44962143Sarchie isa16bit = 1; 45070784Sjulian break; 45162143Sarchie#endif 45262143Sarchie default: 45370700Sjulian sc->type_str = ""; 45462143Sarchie break; 45570700Sjulian } 45662143Sarchie 45762143Sarchie /* 45862143Sarchie * Make some adjustments to initial values depending on what is found 45962143Sarchie * in the ICR. 460141195Sru */ 46162143Sarchie if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 46262143Sarchie#ifdef TOSH_ETHER 46362143Sarchie && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 46462143Sarchie#endif 465141195Sru && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 46662143Sarchie isa16bit = 0; 46762143Sarchie memsize = 8192; 46862143Sarchie } 46962143Sarchie 47062143Sarchie#if ED_DEBUG 47162143Sarchie printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 47262143Sarchie sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize); 47362143Sarchie for (i = 0; i < 8; i++) 47462143Sarchie printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 47564358Sarchie#endif 47664358Sarchie 47764358Sarchie /* 47864358Sarchie * Allow the user to override the autoconfiguration 47964358Sarchie */ 48064358Sarchie if (isa_dev->id_msize) 481152315Sru memsize = isa_dev->id_msize; 48264358Sarchie 48364358Sarchie /* 48464653Sarchie * (note that if the user specifies both of the following flags that 48564653Sarchie * '8bit' mode intentionally has precedence) 48664653Sarchie */ 48764653Sarchie if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE) 48864653Sarchie isa16bit = 1; 48964653Sarchie if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE) 49064653Sarchie isa16bit = 0; 49164653Sarchie 49264653Sarchie /* 49364653Sarchie * If possible, get the assigned interrupt number from the card and 49464653Sarchie * use it. 49564653Sarchie */ 49664653Sarchie if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 49764653Sarchie 49864653Sarchie /* 49964653Sarchie * Assemble together the encoded interrupt number. 50064653Sarchie */ 50164653Sarchie iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 50264358Sarchie ((inb(isa_dev->id_iobase + ED_WD_IRR) & 50364358Sarchie (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 50464358Sarchie 50564358Sarchie /* 50664358Sarchie * If no interrupt specified (or "?"), use what the board tells us. 50764358Sarchie */ 50864358Sarchie if (isa_dev->id_irq <= 0) 50964358Sarchie isa_dev->id_irq = ed_intr_mask[iptr]; 51064358Sarchie 51164358Sarchie /* 51264358Sarchie * Enable the interrupt. 51364358Sarchie */ 51464358Sarchie outb(isa_dev->id_iobase + ED_WD_IRR, 51564358Sarchie inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 51664358Sarchie } 51764358Sarchie if (sc->is790) { 51864653Sarchie outb(isa_dev->id_iobase + ED_WD790_HWR, 51964653Sarchie inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); 52064653Sarchie iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 52164653Sarchie (inb(isa_dev->id_iobase + ED_WD790_GCR) & 52264653Sarchie (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 52364653Sarchie outb(isa_dev->id_iobase + ED_WD790_HWR, 52464653Sarchie inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 52564653Sarchie 52664358Sarchie /* 52764358Sarchie * If no interrupt specified (or "?"), use what the board tells us. 52864358Sarchie */ 52964358Sarchie if (isa_dev->id_irq <= 0) 53064358Sarchie isa_dev->id_irq = ed_790_intr_mask[iptr]; 53164358Sarchie 53264358Sarchie /* 533141721Sglebius * Enable interrupts. 534141721Sglebius */ 535141721Sglebius outb(isa_dev->id_iobase + ED_WD790_ICR, 536167729Sbms inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL); 537141721Sglebius } 538141721Sglebius if (isa_dev->id_irq <= 0) { 539141721Sglebius printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n", 540141721Sglebius isa_dev->id_unit, sc->type_str); 541141721Sglebius return (0); 542141755Sglebius } 543141721Sglebius sc->isa16bit = isa16bit; 544141721Sglebius sc->mem_shared = 1; 545141755Sglebius isa_dev->id_msize = memsize; 546141721Sglebius sc->mem_start = (caddr_t) isa_dev->id_maddr; 547141721Sglebius 548167729Sbms /* 549167729Sbms * allocate one xmit buffer if < 16k, two buffers otherwise 550167729Sbms */ 551167729Sbms if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 552167729Sbms sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 553167729Sbms sc->txb_cnt = 1; 554167729Sbms sc->rec_page_start = ED_TXBUF_SIZE; 555167729Sbms } else { 556167729Sbms sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2); 557167729Sbms sc->txb_cnt = 2; 558167729Sbms sc->rec_page_start = ED_TXBUF_SIZE * 2; 559167729Sbms } 560167729Sbms sc->mem_size = memsize; 561167729Sbms sc->mem_end = sc->mem_start + memsize; 562167729Sbms sc->rec_page_stop = memsize / ED_PAGE_SIZE; 563167729Sbms sc->tx_page_start = ED_WD_PAGE_OFFSET; 564167729Sbms 565141721Sglebius /* 566141721Sglebius * Get station address from on-board ROM 567141721Sglebius */ 568141721Sglebius for (i = 0; i < ETHER_ADDR_LEN; ++i) 569141721Sglebius sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 570141721Sglebius 571141721Sglebius /* 572141721Sglebius * Set upper address bits and 8/16 bit access to shared memory 573141721Sglebius */ 574141721Sglebius if (isa16bit) { 575141755Sglebius if (sc->is790) { 576141721Sglebius sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 577141721Sglebius outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN); 578141755Sglebius } else { 579141721Sglebius outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 580141721Sglebius ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN | 581141721Sglebius ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 582141721Sglebius } 583141721Sglebius } else { 584141721Sglebius if (((sc->type & ED_WD_SOFTCONFIG) || 585141910Sglebius#ifdef TOSH_ETHER 586141910Sglebius (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 587141910Sglebius#endif 58862143Sarchie (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 58962143Sarchie outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 59062143Sarchie ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 59162143Sarchie } 59262143Sarchie } 59362143Sarchie 59462143Sarchie /* 59562143Sarchie * Set address and enable interface shared memory. 59662143Sarchie */ 59770700Sjulian if (!sc->is790) { 59870700Sjulian#ifdef TOSH_ETHER 59962143Sarchie outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 60062143Sarchie outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 60162143Sarchie outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 60262143Sarchie 60362143Sarchie#else 604186488Sjulian outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 60562143Sarchie ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 60662143Sarchie#endif 60770700Sjulian sc->cr_proto = ED_CR_RD2; 60862143Sarchie } else { 60970700Sjulian outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 610131155Sjulian outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 61187599Sobrien outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 612129281Sarchie ((kvtop(sc->mem_start) >> 11) & 0x40) | 613136312Sdes (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 61483366Sjulian outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 61562143Sarchie sc->cr_proto = 0; 61662143Sarchie } 61762143Sarchie 618129281Sarchie#if 0 61962143Sarchie printf("starting memory performance test at 0x%x, size %d...\n", 62062143Sarchie sc->mem_start, memsize*16384); 621186488Sjulian for (i = 0; i < 16384; i++) 62262143Sarchie bzero(sc->mem_start, memsize); 623186488Sjulian printf("***DONE***\n"); 624186488Sjulian#endif 62570784Sjulian 62696265Sarchie /* 62762143Sarchie * Now zero memory and verify that it is clear 628186488Sjulian */ 629186488Sjulian bzero(sc->mem_start, memsize); 630186488Sjulian 63196265Sarchie for (i = 0; i < memsize; ++i) { 632186488Sjulian if (sc->mem_start[i]) { 633148887Srwatson printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 634148887Srwatson isa_dev->id_unit, kvtop(sc->mem_start + i)); 63596265Sarchie 63696265Sarchie /* 63796265Sarchie * Disable 16 bit access to shared memory 63896265Sarchie */ 63962143Sarchie if (isa16bit) { 64062143Sarchie if (sc->is790) { 64170700Sjulian outb(sc->asic_addr + ED_WD_MSR, 0x00); 64262143Sarchie } 64362143Sarchie outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 64462143Sarchie ~ED_WD_LAAR_M16EN)); 64597896Sarchie } 64662143Sarchie return (0); 64762143Sarchie } 64864358Sarchie } 64964358Sarchie 65097896Sarchie /* 65197896Sarchie * Disable 16bit access to shared memory - we leave it 65297896Sarchie * disabled so that 1) machines reboot properly when the board 65397896Sarchie * is set 16 bit mode and there are conflicting 8bit 65497896Sarchie * devices/ROMS in the same 128k address space as this boards 65597896Sarchie * shared memory. and 2) so that other 8 bit devices with 65697896Sarchie * shared memory can be used in this 128k region, too. 657152315Sru */ 65864358Sarchie if (isa16bit) { 65964358Sarchie if (sc->is790) { 66064358Sarchie outb(sc->asic_addr + ED_WD_MSR, 0x00); 66162678Sjulian } 66262143Sarchie outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 66396265Sarchie ~ED_WD_LAAR_M16EN)); 66462143Sarchie } 66562143Sarchie return (ED_WD_IO_PORTS); 66662143Sarchie} 66762143Sarchie 66862143Sarchie/* 66962143Sarchie * Probe and vendor-specific initialization routine for 3Com 3c503 boards 670186488Sjulian */ 67162143Sarchieint 672186488Sjulianed_probe_3Com(isa_dev) 673186488Sjulian struct isa_device *isa_dev; 67470784Sjulian{ 675151063Sglebius struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 67662143Sarchie int i; 677186488Sjulian u_int memsize; 678186488Sjulian u_char isa16bit; 679186488Sjulian 680152001Sru sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 681152001Sru sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 682152001Sru 683152001Sru /* 684152001Sru * Verify that the kernel configured I/O address matches the board 685152001Sru * configured address 686152001Sru */ 687152001Sru switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 688152001Sru case ED_3COM_BCFR_300: 689151063Sglebius if (isa_dev->id_iobase != 0x300) 69062143Sarchie return (0); 691151305Sthompsa break; 692151063Sglebius case ED_3COM_BCFR_310: 693151305Sthompsa if (isa_dev->id_iobase != 0x310) 694151063Sglebius return (0); 695151063Sglebius break; 696151063Sglebius case ED_3COM_BCFR_330: 697151063Sglebius if (isa_dev->id_iobase != 0x330) 69862143Sarchie return (0); 699151305Sthompsa break; 70062143Sarchie case ED_3COM_BCFR_350: 70162143Sarchie if (isa_dev->id_iobase != 0x350) 70262143Sarchie return (0); 70362143Sarchie break; 70471849Sjulian case ED_3COM_BCFR_250: 70571849Sjulian if (isa_dev->id_iobase != 0x250) 70662143Sarchie return (0); 70762143Sarchie break; 70870700Sjulian case ED_3COM_BCFR_280: 70962143Sarchie if (isa_dev->id_iobase != 0x280) 71070784Sjulian return (0); 71164358Sarchie break; 712132464Sjulian case ED_3COM_BCFR_2A0: 71371849Sjulian if (isa_dev->id_iobase != 0x2a0) 71471849Sjulian return (0); 71571849Sjulian break; 71671849Sjulian case ED_3COM_BCFR_2E0: 71771849Sjulian if (isa_dev->id_iobase != 0x2e0) 71871849Sjulian return (0); 71971849Sjulian break; 720184205Sdes default: 72171849Sjulian return (0); 72271849Sjulian } 72370700Sjulian 724124269Sgreen /* 725124269Sgreen * Verify that the kernel shared memory address matches the board 726124269Sgreen * configured address. 727124269Sgreen */ 72864358Sarchie switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 729132464Sjulian case ED_3COM_PCFR_DC000: 730132464Sjulian if (kvtop(isa_dev->id_maddr) != 0xdc000) 73162143Sarchie return (0); 73262143Sarchie break; 73362143Sarchie case ED_3COM_PCFR_D8000: 73462143Sarchie if (kvtop(isa_dev->id_maddr) != 0xd8000) 73562143Sarchie return (0); 73662143Sarchie break; 73762143Sarchie case ED_3COM_PCFR_CC000: 73862143Sarchie if (kvtop(isa_dev->id_maddr) != 0xcc000) 73962143Sarchie return (0); 74070784Sjulian break; 74162143Sarchie case ED_3COM_PCFR_C8000: 74290249Sarchie if (kvtop(isa_dev->id_maddr) != 0xc8000) 74362143Sarchie return (0); 744124270Sgreen break; 745124270Sgreen default: 746129281Sarchie return (0); 74762143Sarchie } 748129281Sarchie 749129281Sarchie 750129281Sarchie /* 75187599Sobrien * Reset NIC and ASIC. Enable on-board transceiver throughout reset 75270784Sjulian * sequence because it'll lock up if the cable isn't connected if we 75370784Sjulian * don't. 75470784Sjulian */ 75562143Sarchie outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 75662143Sarchie 75762143Sarchie /* 75862143Sarchie * Wait for a while, then un-reset it 75962143Sarchie */ 76062143Sarchie DELAY(50); 76162143Sarchie 76262143Sarchie /* 76362143Sarchie * The 3Com ASIC defaults to rather strange settings for the CR after 76462143Sarchie * a reset - it's important to set it again after the following outb 76562143Sarchie * (this is done when we map the PROM below). 76662143Sarchie */ 76762143Sarchie outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 76862143Sarchie 76962143Sarchie /* 77062143Sarchie * Wait a bit for the NIC to recover from the reset 77162143Sarchie */ 77262143Sarchie DELAY(5000); 77362143Sarchie 77462143Sarchie sc->vendor = ED_VENDOR_3COM; 77562143Sarchie sc->type_str = "3c503"; 77662143Sarchie sc->kdc.kdc_description = "Ethernet adapter: 3c503"; 77762143Sarchie sc->mem_shared = 1; 77862143Sarchie sc->cr_proto = ED_CR_RD2; 77962143Sarchie 78062143Sarchie /* 78162143Sarchie * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 78262143Sarchie * to it. 78362143Sarchie */ 78462143Sarchie memsize = 8192; 785139903Sglebius 78662143Sarchie /* 787191510Szec * Get station address from on-board ROM 788191510Szec */ 789191510Szec 790191510Szec /* 791191510Szec * First, map ethernet address PROM over the top of where the NIC 79262143Sarchie * registers normally appear. 79362143Sarchie */ 79462143Sarchie outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 79562143Sarchie 79662143Sarchie for (i = 0; i < ETHER_ADDR_LEN; ++i) 79762143Sarchie sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 79862143Sarchie 79962143Sarchie /* 80062143Sarchie * Unmap PROM - select NIC registers. The proper setting of the 80162143Sarchie * tranceiver is set in ed_init so that the attach code is given a 80262143Sarchie * chance to set the default based on a compile-time config option 80362143Sarchie */ 804191510Szec outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 805191510Szec 806191510Szec /* 807191510Szec * Determine if this is an 8bit or 16bit board 80862143Sarchie */ 80962143Sarchie 81062143Sarchie /* 81162143Sarchie * select page 0 registers 81262143Sarchie */ 81362143Sarchie outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 814139903Sglebius 81562143Sarchie /* 81662143Sarchie * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 81762143Sarchie * board. 81862143Sarchie */ 81962143Sarchie outb(sc->nic_addr + ED_P0_DCR, 0); 82062143Sarchie 82162143Sarchie /* 82262143Sarchie * select page 2 registers 82362143Sarchie */ 82462143Sarchie outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 825191510Szec 826191510Szec /* 827191510Szec * The 3c503 forces the WTS bit to a one if this is a 16bit board 828191510Szec */ 829191510Szec if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 830191510Szec isa16bit = 1; 831191510Szec else 832191510Szec isa16bit = 0; 833191510Szec 834191510Szec /* 835191510Szec * select page 0 registers 836191510Szec */ 837191510Szec outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 838191510Szec 839191510Szec sc->mem_start = (caddr_t) isa_dev->id_maddr; 840191510Szec sc->mem_size = memsize; 841 sc->mem_end = sc->mem_start + memsize; 842 843 /* 844 * We have an entire 8k window to put the transmit buffers on the 845 * 16bit boards. But since the 16bit 3c503's shared memory is only 846 * fast enough to overlap the loading of one full-size packet, trying 847 * to load more than 2 buffers can actually leave the transmitter idle 848 * during the load. So 2 seems the best value. (Although a mix of 849 * variable-sized packets might change this assumption. Nonetheless, 850 * we optimize for linear transfers of same-size packets.) 851 */ 852 if (isa16bit) { 853 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 854 sc->txb_cnt = 1; 855 else 856 sc->txb_cnt = 2; 857 858 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 859 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 860 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 861 ED_3COM_RX_PAGE_OFFSET_16BIT; 862 sc->mem_ring = sc->mem_start; 863 } else { 864 sc->txb_cnt = 1; 865 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 866 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 867 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 868 ED_3COM_TX_PAGE_OFFSET_8BIT; 869 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 870 } 871 872 sc->isa16bit = isa16bit; 873 874 /* 875 * Initialize GA page start/stop registers. Probably only needed if 876 * doing DMA, but what the hell. 877 */ 878 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 879 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 880 881 /* 882 * Set IRQ. 3c503 only allows a choice of irq 2-5. 883 */ 884 switch (isa_dev->id_irq) { 885 case IRQ2: 886 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 887 break; 888 case IRQ3: 889 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 890 break; 891 case IRQ4: 892 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 893 break; 894 case IRQ5: 895 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 896 break; 897 default: 898 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n", 899 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 900 return (0); 901 } 902 903 /* 904 * Initialize GA configuration register. Set bank and enable shared 905 * mem. 906 */ 907 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 908 ED_3COM_GACFR_MBS0); 909 910 /* 911 * Initialize "Vector Pointer" registers. These gawd-awful things are 912 * compared to 20 bits of the address on ISA, and if they match, the 913 * shared memory is disabled. We set them to 0xffff0...allegedly the 914 * reset vector. 915 */ 916 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 917 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 918 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 919 920 /* 921 * Zero memory and verify that it is clear 922 */ 923 bzero(sc->mem_start, memsize); 924 925 for (i = 0; i < memsize; ++i) 926 if (sc->mem_start[i]) { 927 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 928 isa_dev->id_unit, kvtop(sc->mem_start + i)); 929 return (0); 930 } 931 isa_dev->id_msize = memsize; 932 return (ED_3COM_IO_PORTS); 933} 934 935/* 936 * Probe and vendor-specific initialization routine for NE1000/2000 boards 937 */ 938int 939ed_probe_Novell(isa_dev) 940 struct isa_device *isa_dev; 941{ 942 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 943 u_int memsize, n; 944 u_char romdata[16], tmp; 945 static char test_pattern[32] = "THIS is A memory TEST pattern"; 946 char test_buffer[32]; 947 948 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET; 949 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET; 950 951 /* XXX - do Novell-specific probe here */ 952 953 /* Reset the board */ 954#ifdef GWETHER 955 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 956 DELAY(200); 957#endif /* GWETHER */ 958 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 959 960 /* 961 * I don't know if this is necessary; probably cruft leftover from 962 * Clarkson packet driver code. Doesn't do a thing on the boards I've 963 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 964 * non-invasive...but some boards don't seem to reset and I don't have 965 * complete documentation on what the 'right' thing to do is...so we 966 * do the invasive thing for now. Yuck.] 967 */ 968 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 969 DELAY(5000); 970 971 /* 972 * This is needed because some NE clones apparently don't reset the 973 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 974 * - this makes the probe invasive! ...Done against my better 975 * judgement. -DLG 976 */ 977 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 978 979 DELAY(5000); 980 981 /* Make sure that we really have an 8390 based board */ 982 if (!ed_probe_generic8390(sc)) 983 return (0); 984 985 sc->vendor = ED_VENDOR_NOVELL; 986 sc->mem_shared = 0; 987 sc->cr_proto = ED_CR_RD2; 988 isa_dev->id_maddr = 0; 989 990 /* 991 * Test the ability to read and write to the NIC memory. This has the 992 * side affect of determining if this is an NE1000 or an NE2000. 993 */ 994 995 /* 996 * This prevents packets from being stored in the NIC memory when the 997 * readmem routine turns on the start bit in the CR. 998 */ 999 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1000 1001 /* Temporarily initialize DCR for byte operations */ 1002 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1003 1004 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1005 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1006 1007 sc->isa16bit = 0; 1008 1009 /* 1010 * Write a test pattern in byte mode. If this fails, then there 1011 * probably isn't any memory at 8k - which likely means that the board 1012 * is an NE2000. 1013 */ 1014 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1015 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1016 1017 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 1018 /* not an NE1000 - try NE2000 */ 1019 1020 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1021 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1022 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1023 1024 sc->isa16bit = 1; 1025 1026 /* 1027 * Write a test pattern in word mode. If this also fails, then 1028 * we don't know what this board is. 1029 */ 1030 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1031 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1032 1033 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 1034 return (0); /* not an NE2000 either */ 1035 1036 sc->type = ED_TYPE_NE2000; 1037 sc->type_str = "NE2000"; 1038 sc->kdc.kdc_description = "Ethernet adapter: NE2000"; 1039 } else { 1040 sc->type = ED_TYPE_NE1000; 1041 sc->type_str = "NE1000"; 1042 sc->kdc.kdc_description = "Ethernet adapter: NE1000"; 1043 } 1044 1045 /* 8k of memory plus an additional 8k if 16bit */ 1046 memsize = 8192 + sc->isa16bit * 8192; 1047 1048#if 0 /* probably not useful - NE boards only come two ways */ 1049 /* allow kernel config file overrides */ 1050 if (isa_dev->id_msize) 1051 memsize = isa_dev->id_msize; 1052#endif 1053 1054 sc->mem_size = memsize; 1055 1056 /* NIC memory doesn't start at zero on an NE board */ 1057 /* The start address is tied to the bus width */ 1058 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1059 sc->mem_end = sc->mem_start + memsize; 1060 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1061 1062#ifdef GWETHER 1063 { 1064 int x, i, mstart = 0, msize = 0; 1065 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1066 1067 for (i = 0; i < ED_PAGE_SIZE; i++) 1068 pbuf0[i] = 0; 1069 1070 /* Clear all the memory. */ 1071 for (x = 1; x < 256; x++) 1072 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1073 1074 /* Search for the start of RAM. */ 1075 for (x = 1; x < 256; x++) { 1076 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1077 if (memcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1078 for (i = 0; i < ED_PAGE_SIZE; i++) 1079 pbuf[i] = 255 - x; 1080 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1081 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1082 if (memcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1083 mstart = x * ED_PAGE_SIZE; 1084 msize = ED_PAGE_SIZE; 1085 break; 1086 } 1087 } 1088 } 1089 1090 if (mstart == 0) { 1091 printf("ed%d: Cannot find start of RAM.\n", isa_dev->id_unit); 1092 return 0; 1093 } 1094 /* Search for the start of RAM. */ 1095 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1096 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1097 if (memcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1098 for (i = 0; i < ED_PAGE_SIZE; i++) 1099 pbuf[i] = 255 - x; 1100 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1101 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1102 if (memcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1103 msize += ED_PAGE_SIZE; 1104 else { 1105 break; 1106 } 1107 } else { 1108 break; 1109 } 1110 } 1111 1112 if (msize == 0) { 1113 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", isa_dev->id_unit, mstart, x); 1114 return 0; 1115 } 1116 printf("ed%d: RAM start at %d, size : %d.\n", isa_dev->id_unit, mstart, msize); 1117 1118 sc->mem_size = msize; 1119 sc->mem_start = (char *) mstart; 1120 sc->mem_end = (char *) (msize + mstart); 1121 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1122 } 1123#endif /* GWETHER */ 1124 1125 /* 1126 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1127 * otherwise). 1128 */ 1129 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1130 sc->txb_cnt = 1; 1131 else 1132 sc->txb_cnt = 2; 1133 1134 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1135 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1136 1137 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1138 1139 ed_pio_readmem(sc, 0, romdata, 16); 1140 for (n = 0; n < ETHER_ADDR_LEN; n++) 1141 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1142 1143#ifdef GWETHER 1144 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1145 sc->type_str = "Gateway AT"; 1146 sc->kdc.kdc_description = "Ethernet adapter: Gateway AT"; 1147 } 1148#endif /* GWETHER */ 1149 1150 /* clear any pending interrupts that might have occurred above */ 1151 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1152 1153 return (ED_NOVELL_IO_PORTS); 1154} 1155 1156/* 1157 * Install interface into kernel networking data structures 1158 */ 1159int 1160ed_attach(isa_dev) 1161 struct isa_device *isa_dev; 1162{ 1163 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1164 struct ifnet *ifp = &sc->arpcom.ac_if; 1165 1166 /* 1167 * Set interface to stopped condition (reset) 1168 */ 1169 ed_stop(isa_dev->id_unit); 1170 1171 /* 1172 * Initialize ifnet structure 1173 */ 1174 ifp->if_unit = isa_dev->id_unit; 1175 ifp->if_name = "ed"; 1176 ifp->if_init = ed_init; 1177 ifp->if_output = ether_output; 1178 ifp->if_start = ed_start; 1179 ifp->if_ioctl = ed_ioctl; 1180 ifp->if_reset = ed_reset; 1181 ifp->if_watchdog = ed_watchdog; 1182 1183 /* 1184 * Set default state for ALTPHYS flag (used to disable the tranceiver 1185 * for AUI operation), based on compile-time config option. 1186 */ 1187 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER) 1188 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 1189 IFF_MULTICAST | IFF_ALTPHYS); 1190 else 1191 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 1192 IFF_MULTICAST); 1193 1194 /* 1195 * Attach the interface 1196 */ 1197 if_attach(ifp); 1198 /* device attach does transition from UNCONFIGURED to IDLE state */ 1199 sc->kdc.kdc_state = DC_IDLE; 1200 1201 /* 1202 * Print additional info when attached 1203 */ 1204 printf("ed%d: address %s, ", isa_dev->id_unit, 1205 ether_sprintf(sc->arpcom.ac_enaddr)); 1206 1207 if (sc->type_str && (*sc->type_str != 0)) 1208 printf("type %s ", sc->type_str); 1209 else 1210 printf("type unknown (0x%x) ", sc->type); 1211 1212 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1213 1214 printf("%s\n", ((sc->vendor == ED_VENDOR_3COM) && 1215 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1216 1217 /* 1218 * If BPF is in the kernel, call the attach for it 1219 */ 1220#if NBPFILTER > 0 1221 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 1222#endif 1223 return 1; 1224} 1225 1226/* 1227 * Reset interface. 1228 */ 1229void 1230ed_reset(unit) 1231 int unit; 1232{ 1233 int s; 1234 1235 s = splimp(); 1236 1237 /* 1238 * Stop interface and re-initialize. 1239 */ 1240 ed_stop(unit); 1241 ed_init(unit); 1242 1243 (void) splx(s); 1244} 1245 1246/* 1247 * Take interface offline. 1248 */ 1249void 1250ed_stop(unit) 1251 int unit; 1252{ 1253 struct ed_softc *sc = &ed_softc[unit]; 1254 int n = 5000; 1255 1256 /* 1257 * Stop everything on the interface, and select page 0 registers. 1258 */ 1259 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1260 1261 /* 1262 * Wait for interface to enter stopped state, but limit # of checks to 1263 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1264 * just in case it's an old one. 1265 */ 1266 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1267} 1268 1269/* 1270 * Device timeout/watchdog routine. Entered if the device neglects to 1271 * generate an interrupt after a transmit has been started on it. 1272 */ 1273void 1274ed_watchdog(unit) 1275 int unit; 1276{ 1277 struct ed_softc *sc = &ed_softc[unit]; 1278 1279 log(LOG_ERR, "ed%d: device timeout\n", unit); 1280 ++sc->arpcom.ac_if.if_oerrors; 1281 1282 ed_reset(unit); 1283} 1284 1285/* 1286 * Initialize device. 1287 */ 1288void 1289ed_init(unit) 1290 int unit; 1291{ 1292 struct ed_softc *sc = &ed_softc[unit]; 1293 struct ifnet *ifp = &sc->arpcom.ac_if; 1294 int i, s; 1295 1296 1297 /* address not known */ 1298 if (ifp->if_addrlist == (struct ifaddr *) 0) 1299 return; 1300 1301 /* 1302 * Initialize the NIC in the exact order outlined in the NS manual. 1303 * This init procedure is "mandatory"...don't change what or when 1304 * things happen. 1305 */ 1306 s = splimp(); 1307 1308 /* reset transmitter flags */ 1309 sc->xmit_busy = 0; 1310 sc->arpcom.ac_if.if_timer = 0; 1311 1312 sc->txb_inuse = 0; 1313 sc->txb_new = 0; 1314 sc->txb_next_tx = 0; 1315 1316 /* This variable is used below - don't move this assignment */ 1317 sc->next_packet = sc->rec_page_start + 1; 1318 1319 /* 1320 * Set interface for page 0, Remote DMA complete, Stopped 1321 */ 1322 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1323 1324 if (sc->isa16bit) { 1325 1326 /* 1327 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1328 * order=80x86, word-wide DMA xfers, 1329 */ 1330 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1331 } else { 1332 1333 /* 1334 * Same as above, but byte-wide DMA xfers 1335 */ 1336 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1337 } 1338 1339 /* 1340 * Clear Remote Byte Count Registers 1341 */ 1342 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1343 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1344 1345 /* 1346 * For the moment, don't store incoming packets in memory. 1347 */ 1348 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1349 1350 /* 1351 * Place NIC in internal loopback mode 1352 */ 1353 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1354 1355 /* 1356 * Initialize transmit/receive (ring-buffer) Page Start 1357 */ 1358 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1359 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1360 /* Set lower bits of byte addressable framing to 0 */ 1361 if (sc->is790) 1362 outb(sc->nic_addr + 0x09, 0); 1363 1364 /* 1365 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1366 */ 1367 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1368 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1369 1370 /* 1371 * Clear all interrupts. A '1' in each bit position clears the 1372 * corresponding flag. 1373 */ 1374 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1375 1376 /* 1377 * Enable the following interrupts: receive/transmit complete, 1378 * receive/transmit error, and Receiver OverWrite. 1379 * 1380 * Counter overflow and Remote DMA complete are *not* enabled. 1381 */ 1382 outb(sc->nic_addr + ED_P0_IMR, 1383 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1384 1385 /* 1386 * Program Command Register for page 1 1387 */ 1388 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1389 1390 /* 1391 * Copy out our station address 1392 */ 1393 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1394 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1395 1396 /* 1397 * Set Current Page pointer to next_packet (initialized above) 1398 */ 1399 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1400 1401 /* 1402 * Program Receiver Configuration Register and multicast filter. CR is 1403 * set to page 0 on return. 1404 */ 1405 ed_setrcr(ifp, sc); 1406 1407 /* 1408 * Take interface out of loopback 1409 */ 1410 outb(sc->nic_addr + ED_P0_TCR, 0); 1411 1412 /* 1413 * If this is a 3Com board, the tranceiver must be software enabled 1414 * (there is no settable hardware default). 1415 */ 1416 if (sc->vendor == ED_VENDOR_3COM) { 1417 if (ifp->if_flags & IFF_ALTPHYS) { 1418 outb(sc->asic_addr + ED_3COM_CR, 0); 1419 } else { 1420 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1421 } 1422 } 1423 1424 /* 1425 * Set 'running' flag, and clear output active flag. 1426 */ 1427 ifp->if_flags |= IFF_RUNNING; 1428 ifp->if_flags &= ~IFF_OACTIVE; 1429 1430 /* 1431 * ...and attempt to start output 1432 */ 1433 ed_start(ifp); 1434 1435 (void) splx(s); 1436} 1437 1438/* 1439 * This routine actually starts the transmission on the interface 1440 */ 1441static inline void 1442ed_xmit(ifp) 1443 struct ifnet *ifp; 1444{ 1445 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1446 unsigned short len; 1447 1448 len = sc->txb_len[sc->txb_next_tx]; 1449 1450 /* 1451 * Set NIC for page 0 register access 1452 */ 1453 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1454 1455 /* 1456 * Set TX buffer start page 1457 */ 1458 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 1459 sc->txb_next_tx * ED_TXBUF_SIZE); 1460 1461 /* 1462 * Set TX length 1463 */ 1464 outb(sc->nic_addr + ED_P0_TBCR0, len); 1465 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 1466 1467 /* 1468 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 1469 */ 1470 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 1471 sc->xmit_busy = 1; 1472 1473 /* 1474 * Point to next transmit buffer slot and wrap if necessary. 1475 */ 1476 sc->txb_next_tx++; 1477 if (sc->txb_next_tx == sc->txb_cnt) 1478 sc->txb_next_tx = 0; 1479 1480 /* 1481 * Set a timer just in case we never hear from the board again 1482 */ 1483 ifp->if_timer = 2; 1484} 1485 1486/* 1487 * Start output on interface. 1488 * We make two assumptions here: 1489 * 1) that the current priority is set to splimp _before_ this code 1490 * is called *and* is returned to the appropriate priority after 1491 * return 1492 * 2) that the IFF_OACTIVE flag is checked before this code is called 1493 * (i.e. that the output part of the interface is idle) 1494 */ 1495void 1496ed_start(ifp) 1497 struct ifnet *ifp; 1498{ 1499 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1500 struct mbuf *m0, *m; 1501 caddr_t buffer; 1502 int len; 1503 1504outloop: 1505 1506 /* 1507 * First, see if there are buffered packets and an idle transmitter - 1508 * should never happen at this point. 1509 */ 1510 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 1511 printf("ed: packets buffered, but transmitter idle\n"); 1512 ed_xmit(ifp); 1513 } 1514 1515 /* 1516 * See if there is room to put another packet in the buffer. 1517 */ 1518 if (sc->txb_inuse == sc->txb_cnt) { 1519 1520 /* 1521 * No room. Indicate this to the outside world and exit. 1522 */ 1523 ifp->if_flags |= IFF_OACTIVE; 1524 return; 1525 } 1526 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 1527 if (m == 0) { 1528 1529 /* 1530 * We are using the !OACTIVE flag to indicate to the outside 1531 * world that we can accept an additional packet rather than 1532 * that the transmitter is _actually_ active. Indeed, the 1533 * transmitter may be active, but if we haven't filled all the 1534 * buffers with data then we still want to accept more. 1535 */ 1536 ifp->if_flags &= ~IFF_OACTIVE; 1537 return; 1538 } 1539 1540 /* 1541 * Copy the mbuf chain into the transmit buffer 1542 */ 1543 1544 m0 = m; 1545 1546 /* txb_new points to next open buffer slot */ 1547 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 1548 1549 if (sc->mem_shared) { 1550 1551 /* 1552 * Special case setup for 16 bit boards... 1553 */ 1554 if (sc->isa16bit) { 1555 switch (sc->vendor) { 1556 1557 /* 1558 * For 16bit 3Com boards (which have 16k of 1559 * memory), we have the xmit buffers in a 1560 * different page of memory ('page 0') - so 1561 * change pages. 1562 */ 1563 case ED_VENDOR_3COM: 1564 outb(sc->asic_addr + ED_3COM_GACFR, 1565 ED_3COM_GACFR_RSEL); 1566 break; 1567 1568 /* 1569 * Enable 16bit access to shared memory on 1570 * WD/SMC boards. 1571 */ 1572 case ED_VENDOR_WD_SMC:{ 1573 outb(sc->asic_addr + ED_WD_LAAR, 1574 (sc->wd_laar_proto | ED_WD_LAAR_M16EN)); 1575 if (sc->is790) { 1576 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 1577 } 1578 break; 1579 } 1580 } 1581 } 1582 for (len = 0; m != 0; m = m->m_next) { 1583 bcopy(mtod(m, caddr_t), buffer, m->m_len); 1584 buffer += m->m_len; 1585 len += m->m_len; 1586 } 1587 1588 /* 1589 * Restore previous shared memory access 1590 */ 1591 if (sc->isa16bit) { 1592 switch (sc->vendor) { 1593 case ED_VENDOR_3COM: 1594 outb(sc->asic_addr + ED_3COM_GACFR, 1595 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 1596 break; 1597 case ED_VENDOR_WD_SMC:{ 1598 if (sc->is790) { 1599 outb(sc->asic_addr + ED_WD_MSR, 0x00); 1600 } 1601 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 1602 break; 1603 } 1604 } 1605 } 1606 } else { 1607 len = ed_pio_write_mbufs(sc, m, buffer); 1608 if (len == 0) 1609 goto outloop; 1610 } 1611 1612 sc->txb_len[sc->txb_new] = max(len, ETHER_MIN_LEN); 1613 1614 sc->txb_inuse++; 1615 1616 /* 1617 * Point to next buffer slot and wrap if necessary. 1618 */ 1619 sc->txb_new++; 1620 if (sc->txb_new == sc->txb_cnt) 1621 sc->txb_new = 0; 1622 1623 if (sc->xmit_busy == 0) 1624 ed_xmit(ifp); 1625 1626 /* 1627 * Tap off here if there is a bpf listener. 1628 */ 1629#if NBPFILTER > 0 1630 if (sc->bpf) { 1631 bpf_mtap(sc->bpf, m0); 1632 } 1633#endif 1634 1635 m_freem(m0); 1636 1637 /* 1638 * Loop back to the top to possibly buffer more packets 1639 */ 1640 goto outloop; 1641} 1642 1643/* 1644 * Ethernet interface receiver interrupt. 1645 */ 1646static inline void 1647ed_rint(unit) 1648 int unit; 1649{ 1650 register struct ed_softc *sc = &ed_softc[unit]; 1651 u_char boundry; 1652 u_short len; 1653 struct ed_ring packet_hdr; 1654 char *packet_ptr; 1655 1656 /* 1657 * Set NIC to page 1 registers to get 'current' pointer 1658 */ 1659 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 1660 1661 /* 1662 * 'sc->next_packet' is the logical beginning of the ring-buffer - 1663 * i.e. it points to where new data has been buffered. The 'CURR' 1664 * (current) register points to the logical end of the ring-buffer - 1665 * i.e. it points to where additional new data will be added. We loop 1666 * here until the logical beginning equals the logical end (or in 1667 * other words, until the ring-buffer is empty). 1668 */ 1669 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 1670 1671 /* get pointer to this buffer's header structure */ 1672 packet_ptr = sc->mem_ring + 1673 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 1674 1675 /* 1676 * The byte count includes a 4 byte header that was added by 1677 * the NIC. 1678 */ 1679 if (sc->mem_shared) 1680 packet_hdr = *(struct ed_ring *) packet_ptr; 1681 else 1682 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr, 1683 sizeof(packet_hdr)); 1684 len = packet_hdr.count; 1685 if (len > ETHER_MAX_LEN) { 1686 /* 1687 * Length is a wild value. There's a good chance that 1688 * this was caused by the NIC being old and buggy. 1689 * The bug is that the length low byte is duplicated in 1690 * the high byte. Try to recalculate the length based on 1691 * the pointer to the next packet. 1692 */ 1693 /* 1694 * NOTE: sc->next_packet is pointing at the current packet. 1695 */ 1696 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 1697 if (packet_hdr.next_packet >= sc->next_packet) { 1698 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 1699 } else { 1700 len += ((packet_hdr.next_packet - sc->rec_page_start) + 1701 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 1702 } 1703 } 1704 /* 1705 * Be fairly liberal about what we allow as a "reasonable" length 1706 * so that a [crufty] packet will make it to BPF (and can thus 1707 * be analyzed). Note that all that is really important is that 1708 * we have a length that will fit into one mbuf cluster or less; 1709 * the upper layer protocols can then figure out the length from 1710 * their own length field(s). 1711 */ 1712 if ((len <= MCLBYTES) && 1713 (packet_hdr.next_packet >= sc->rec_page_start) && 1714 (packet_hdr.next_packet < sc->rec_page_stop)) { 1715 /* 1716 * Go get packet. 1717 */ 1718 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 1719 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 1720 ++sc->arpcom.ac_if.if_ipackets; 1721 } else { 1722 /* 1723 * Really BAD. The ring pointers are corrupted. 1724 */ 1725 log(LOG_ERR, 1726 "ed%d: NIC memory corrupt - invalid packet length %d\n", 1727 unit, len); 1728 ++sc->arpcom.ac_if.if_ierrors; 1729 ed_reset(unit); 1730 return; 1731 } 1732 1733 /* 1734 * Update next packet pointer 1735 */ 1736 sc->next_packet = packet_hdr.next_packet; 1737 1738 /* 1739 * Update NIC boundry pointer - being careful to keep it one 1740 * buffer behind. (as recommended by NS databook) 1741 */ 1742 boundry = sc->next_packet - 1; 1743 if (boundry < sc->rec_page_start) 1744 boundry = sc->rec_page_stop - 1; 1745 1746 /* 1747 * Set NIC to page 0 registers to update boundry register 1748 */ 1749 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1750 1751 outb(sc->nic_addr + ED_P0_BNRY, boundry); 1752 1753 /* 1754 * Set NIC to page 1 registers before looping to top (prepare 1755 * to get 'CURR' current pointer) 1756 */ 1757 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 1758 } 1759} 1760 1761/* 1762 * Ethernet interface interrupt processor 1763 */ 1764void 1765edintr(unit) 1766 int unit; 1767{ 1768 struct ed_softc *sc = &ed_softc[unit]; 1769 u_char isr; 1770 1771 /* 1772 * Set NIC to page 0 registers 1773 */ 1774 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1775 1776 /* 1777 * loop until there are no more new interrupts 1778 */ 1779 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 1780 1781 /* 1782 * reset all the bits that we are 'acknowledging' by writing a 1783 * '1' to each bit position that was set (writing a '1' 1784 * *clears* the bit) 1785 */ 1786 outb(sc->nic_addr + ED_P0_ISR, isr); 1787 1788 /* 1789 * Handle transmitter interrupts. Handle these first because 1790 * the receiver will reset the board under some conditions. 1791 */ 1792 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 1793 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 1794 1795 /* 1796 * Check for transmit error. If a TX completed with an 1797 * error, we end up throwing the packet away. Really 1798 * the only error that is possible is excessive 1799 * collisions, and in this case it is best to allow 1800 * the automatic mechanisms of TCP to backoff the 1801 * flow. Of course, with UDP we're screwed, but this 1802 * is expected when a network is heavily loaded. 1803 */ 1804 (void) inb(sc->nic_addr + ED_P0_TSR); 1805 if (isr & ED_ISR_TXE) { 1806 1807 /* 1808 * Excessive collisions (16) 1809 */ 1810 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT) 1811 && (collisions == 0)) { 1812 1813 /* 1814 * When collisions total 16, the 1815 * P0_NCR will indicate 0, and the 1816 * TSR_ABT is set. 1817 */ 1818 collisions = 16; 1819 } 1820 1821 /* 1822 * update output errors counter 1823 */ 1824 ++sc->arpcom.ac_if.if_oerrors; 1825 } else { 1826 1827 /* 1828 * Update total number of successfully 1829 * transmitted packets. 1830 */ 1831 ++sc->arpcom.ac_if.if_opackets; 1832 } 1833 1834 /* 1835 * reset tx busy and output active flags 1836 */ 1837 sc->xmit_busy = 0; 1838 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1839 1840 /* 1841 * clear watchdog timer 1842 */ 1843 sc->arpcom.ac_if.if_timer = 0; 1844 1845 /* 1846 * Add in total number of collisions on last 1847 * transmission. 1848 */ 1849 sc->arpcom.ac_if.if_collisions += collisions; 1850 1851 /* 1852 * Decrement buffer in-use count if not zero (can only 1853 * be zero if a transmitter interrupt occured while 1854 * not actually transmitting). If data is ready to 1855 * transmit, start it transmitting, otherwise defer 1856 * until after handling receiver 1857 */ 1858 if (sc->txb_inuse && --sc->txb_inuse) 1859 ed_xmit(&sc->arpcom.ac_if); 1860 } 1861 1862 /* 1863 * Handle receiver interrupts 1864 */ 1865 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 1866 1867 /* 1868 * Overwrite warning. In order to make sure that a 1869 * lockup of the local DMA hasn't occurred, we reset 1870 * and re-init the NIC. The NSC manual suggests only a 1871 * partial reset/re-init is necessary - but some chips 1872 * seem to want more. The DMA lockup has been seen 1873 * only with early rev chips - Methinks this bug was 1874 * fixed in later revs. -DG 1875 */ 1876 if (isr & ED_ISR_OVW) { 1877 ++sc->arpcom.ac_if.if_ierrors; 1878#ifdef DIAGNOSTIC 1879 log(LOG_WARNING, 1880 "ed%d: warning - receiver ring buffer overrun\n", 1881 unit); 1882#endif 1883 1884 /* 1885 * Stop/reset/re-init NIC 1886 */ 1887 ed_reset(unit); 1888 } else { 1889 1890 /* 1891 * Receiver Error. One or more of: CRC error, 1892 * frame alignment error FIFO overrun, or 1893 * missed packet. 1894 */ 1895 if (isr & ED_ISR_RXE) { 1896 ++sc->arpcom.ac_if.if_ierrors; 1897#ifdef ED_DEBUG 1898 printf("ed%d: receive error %x\n", unit, 1899 inb(sc->nic_addr + ED_P0_RSR)); 1900#endif 1901 } 1902 1903 /* 1904 * Go get the packet(s) XXX - Doing this on an 1905 * error is dubious because there shouldn't be 1906 * any data to get (we've configured the 1907 * interface to not accept packets with 1908 * errors). 1909 */ 1910 1911 /* 1912 * Enable 16bit access to shared memory first 1913 * on WD/SMC boards. 1914 */ 1915 if (sc->isa16bit && 1916 (sc->vendor == ED_VENDOR_WD_SMC)) { 1917 1918 outb(sc->asic_addr + ED_WD_LAAR, 1919 (sc->wd_laar_proto |= 1920 ED_WD_LAAR_M16EN)); 1921 if (sc->is790) { 1922 outb(sc->asic_addr + ED_WD_MSR, 1923 ED_WD_MSR_MENB); 1924 } 1925 } 1926 ed_rint(unit); 1927 1928 /* disable 16bit access */ 1929 if (sc->isa16bit && 1930 (sc->vendor == ED_VENDOR_WD_SMC)) { 1931 1932 if (sc->is790) { 1933 outb(sc->asic_addr + ED_WD_MSR, 0x00); 1934 } 1935 outb(sc->asic_addr + ED_WD_LAAR, 1936 (sc->wd_laar_proto &= 1937 ~ED_WD_LAAR_M16EN)); 1938 } 1939 } 1940 } 1941 1942 /* 1943 * If it looks like the transmitter can take more data, 1944 * attempt to start output on the interface. This is done 1945 * after handling the receiver to give the receiver priority. 1946 */ 1947 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0) 1948 ed_start(&sc->arpcom.ac_if); 1949 1950 /* 1951 * return NIC CR to standard state: page 0, remote DMA 1952 * complete, start (toggling the TXP bit off, even if was just 1953 * set in the transmit routine, is *okay* - it is 'edge' 1954 * triggered from low to high) 1955 */ 1956 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1957 1958 /* 1959 * If the Network Talley Counters overflow, read them to reset 1960 * them. It appears that old 8390's won't clear the ISR flag 1961 * otherwise - resulting in an infinite loop. 1962 */ 1963 if (isr & ED_ISR_CNT) { 1964 (void) inb(sc->nic_addr + ED_P0_CNTR0); 1965 (void) inb(sc->nic_addr + ED_P0_CNTR1); 1966 (void) inb(sc->nic_addr + ED_P0_CNTR2); 1967 } 1968 } 1969} 1970 1971/* 1972 * Process an ioctl request. This code needs some work - it looks 1973 * pretty ugly. 1974 */ 1975int 1976ed_ioctl(ifp, command, data) 1977 register struct ifnet *ifp; 1978 int command; 1979 caddr_t data; 1980{ 1981 register struct ifaddr *ifa = (struct ifaddr *) data; 1982 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1983 struct ifreq *ifr = (struct ifreq *) data; 1984 int s, error = 0; 1985 1986 s = splimp(); 1987 1988 switch (command) { 1989 1990 case SIOCSIFADDR: 1991 ifp->if_flags |= IFF_UP; 1992 /* netifs are BUSY when UP */ 1993 sc->kdc.kdc_state = DC_BUSY; 1994 1995 switch (ifa->ifa_addr->sa_family) { 1996#ifdef INET 1997 case AF_INET: 1998 ed_init(ifp->if_unit); /* before arpwhohas */ 1999 arp_ifinit((struct arpcom *)ifp, ifa); 2000 break; 2001#endif 2002#ifdef NS 2003 2004 /* 2005 * XXX - This code is probably wrong 2006 */ 2007 case AF_NS: 2008 { 2009 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr); 2010 2011 if (ns_nullhost(*ina)) 2012 ina->x_host = 2013 *(union ns_host *) (sc->arpcom.ac_enaddr); 2014 else { 2015 bcopy((caddr_t) ina->x_host.c_host, 2016 (caddr_t) sc->arpcom.ac_enaddr, 2017 sizeof(sc->arpcom.ac_enaddr)); 2018 } 2019 2020 /* 2021 * Set new address 2022 */ 2023 ed_init(ifp->if_unit); 2024 break; 2025 } 2026#endif 2027 default: 2028 ed_init(ifp->if_unit); 2029 break; 2030 } 2031 break; 2032 2033 case SIOCGIFADDR: 2034 { 2035 struct sockaddr *sa; 2036 2037 sa = (struct sockaddr *) & ifr->ifr_data; 2038 bcopy((caddr_t) sc->arpcom.ac_enaddr, 2039 (caddr_t) sa->sa_data, ETHER_ADDR_LEN); 2040 } 2041 break; 2042 2043 case SIOCSIFFLAGS: 2044 2045 /* 2046 * If interface is marked down and it is running, then stop it 2047 */ 2048 if (((ifp->if_flags & IFF_UP) == 0) && 2049 (ifp->if_flags & IFF_RUNNING)) { 2050 ed_stop(ifp->if_unit); 2051 ifp->if_flags &= ~IFF_RUNNING; 2052 } else { 2053 2054 /* 2055 * If interface is marked up and it is stopped, then 2056 * start it 2057 */ 2058 if ((ifp->if_flags & IFF_UP) && 2059 ((ifp->if_flags & IFF_RUNNING) == 0)) 2060 ed_init(ifp->if_unit); 2061 } 2062 /* UP controls BUSY/IDLE */ 2063 sc->kdc.kdc_state = ((ifp->if_flags & IFF_UP) 2064 ? DC_BUSY 2065 : DC_IDLE); 2066 2067#if NBPFILTER > 0 2068 2069 /* 2070 * Promiscuous flag may have changed, so reprogram the RCR. 2071 */ 2072 ed_setrcr(ifp, sc); 2073#endif 2074 2075 /* 2076 * An unfortunate hack to provide the (required) software 2077 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2078 * disables the tranceiver if set. 2079 */ 2080 if (sc->vendor == ED_VENDOR_3COM) { 2081 if (ifp->if_flags & IFF_ALTPHYS) { 2082 outb(sc->asic_addr + ED_3COM_CR, 0); 2083 } else { 2084 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2085 } 2086 } 2087 break; 2088 2089 case SIOCADDMULTI: 2090 case SIOCDELMULTI: 2091 /* 2092 * Update out multicast list. 2093 */ 2094 error = (command == SIOCADDMULTI) ? 2095 ether_addmulti(ifr, &sc->arpcom) : 2096 ether_delmulti(ifr, &sc->arpcom); 2097 2098 if (error == ENETRESET) { 2099 2100 /* 2101 * Multicast list has changed; set the hardware filter 2102 * accordingly. 2103 */ 2104 ed_setrcr(ifp, sc); 2105 error = 0; 2106 } 2107 break; 2108 2109 case SIOCSIFMTU: 2110 /* 2111 * Set the interface MTU. 2112 */ 2113 if (ifr->ifr_mtu > ETHERMTU) { 2114 error = EINVAL; 2115 } else { 2116 ifp->if_mtu = ifr->ifr_mtu; 2117 } 2118 break; 2119 2120 default: 2121 error = EINVAL; 2122 } 2123 (void) splx(s); 2124 return (error); 2125} 2126 2127/* 2128 * Retreive packet from shared memory and send to the next level up via 2129 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2130 */ 2131static void 2132ed_get_packet(sc, buf, len, multicast) 2133 struct ed_softc *sc; 2134 char *buf; 2135 u_short len; 2136 int multicast; 2137{ 2138 struct ether_header *eh; 2139 struct mbuf *m; 2140 2141 /* Allocate a header mbuf */ 2142 MGETHDR(m, M_DONTWAIT, MT_DATA); 2143 if (m == NULL) 2144 return; 2145 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2146 m->m_pkthdr.len = m->m_len = len; 2147 2148 /* Attach an mbuf cluster */ 2149 MCLGET(m, M_DONTWAIT); 2150 2151 /* Insist on getting a cluster */ 2152 if ((m->m_flags & M_EXT) == 0) { 2153 m_freem(m); 2154 return; 2155 } 2156 2157 /* 2158 * The +2 is to longword align the start of the real packet. 2159 * This is important for NFS. 2160 */ 2161 m->m_data += 2; 2162 eh = mtod(m, struct ether_header *); 2163 2164 /* 2165 * Get packet, including link layer address, from interface. 2166 */ 2167 ed_ring_copy(sc, buf, (char *)eh, len); 2168 2169#if NBPFILTER > 0 2170 2171 /* 2172 * Check if there's a BPF listener on this interface. If so, hand off 2173 * the raw packet to bpf. 2174 */ 2175 if (sc->bpf) { 2176 bpf_mtap(sc->bpf, m); 2177 2178 /* 2179 * Note that the interface cannot be in promiscuous mode if 2180 * there are no BPF listeners. And if we are in promiscuous 2181 * mode, we have to check if this packet is really ours. 2182 */ 2183 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2184 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2185 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2186 m_freem(m); 2187 return; 2188 } 2189 } 2190#endif 2191 2192 /* 2193 * Remove link layer address. 2194 */ 2195 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2196 m->m_data += sizeof(struct ether_header); 2197 2198 ether_input(&sc->arpcom.ac_if, eh, m); 2199 return; 2200} 2201 2202/* 2203 * Supporting routines 2204 */ 2205 2206/* 2207 * Given a NIC memory source address and a host memory destination 2208 * address, copy 'amount' from NIC to host using Programmed I/O. 2209 * The 'amount' is rounded up to a word - okay as long as mbufs 2210 * are word sized. 2211 * This routine is currently Novell-specific. 2212 */ 2213void 2214ed_pio_readmem(sc, src, dst, amount) 2215 struct ed_softc *sc; 2216 unsigned short src; 2217 unsigned char *dst; 2218 unsigned short amount; 2219{ 2220 /* select page 0 registers */ 2221 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2222 2223 /* round up to a word */ 2224 if (amount & 1) 2225 ++amount; 2226 2227 /* set up DMA byte count */ 2228 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2229 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2230 2231 /* set up source address in NIC mem */ 2232 outb(sc->nic_addr + ED_P0_RSAR0, src); 2233 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2234 2235 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2236 2237 if (sc->isa16bit) { 2238 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2239 } else 2240 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2241 2242} 2243 2244/* 2245 * Stripped down routine for writing a linear buffer to NIC memory. 2246 * Only used in the probe routine to test the memory. 'len' must 2247 * be even. 2248 */ 2249void 2250ed_pio_writemem(sc, src, dst, len) 2251 struct ed_softc *sc; 2252 char *src; 2253 unsigned short dst; 2254 unsigned short len; 2255{ 2256 int maxwait = 200; /* about 240us */ 2257 2258 /* select page 0 registers */ 2259 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2260 2261 /* reset remote DMA complete flag */ 2262 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2263 2264 /* set up DMA byte count */ 2265 outb(sc->nic_addr + ED_P0_RBCR0, len); 2266 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2267 2268 /* set up destination address in NIC mem */ 2269 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2270 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2271 2272 /* set remote DMA write */ 2273 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2274 2275 if (sc->isa16bit) 2276 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2277 else 2278 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2279 2280 /* 2281 * Wait for remote DMA complete. This is necessary because on the 2282 * transmit side, data is handled internally by the NIC in bursts and 2283 * we can't start another remote DMA until this one completes. Not 2284 * waiting causes really bad things to happen - like the NIC 2285 * irrecoverably jamming the ISA bus. 2286 */ 2287 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2288} 2289 2290/* 2291 * Write an mbuf chain to the destination NIC memory address using 2292 * programmed I/O. 2293 */ 2294u_short 2295ed_pio_write_mbufs(sc, m, dst) 2296 struct ed_softc *sc; 2297 struct mbuf *m; 2298 unsigned short dst; 2299{ 2300 unsigned short total_len, dma_len; 2301 struct mbuf *mp; 2302 int maxwait = 200; /* about 240us */ 2303 2304 /* First, count up the total number of bytes to copy */ 2305 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2306 total_len += mp->m_len; 2307 2308 dma_len = total_len; 2309 if (sc->isa16bit && (dma_len & 1)) 2310 dma_len++; 2311 2312 /* select page 0 registers */ 2313 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2314 2315 /* reset remote DMA complete flag */ 2316 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2317 2318 /* set up DMA byte count */ 2319 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 2320 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 2321 2322 /* set up destination address in NIC mem */ 2323 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2324 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2325 2326 /* set remote DMA write */ 2327 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2328 2329 /* 2330 * Transfer the mbuf chain to the NIC memory. 2331 * 16-bit cards require that data be transferred as words, and only words. 2332 * So that case requires some extra code to patch over odd-length mbufs. 2333 */ 2334 2335 if (!sc->isa16bit) { 2336 /* NE1000s are easy */ 2337 while (m) { 2338 if (m->m_len) { 2339 outsb(sc->asic_addr + ED_NOVELL_DATA, 2340 m->m_data, m->m_len); 2341 } 2342 m = m->m_next; 2343 } 2344 } else { 2345 /* NE2000s are a pain */ 2346 unsigned char *data; 2347 int len, wantbyte; 2348 unsigned char savebyte[2]; 2349 2350 wantbyte = 0; 2351 2352 while (m) { 2353 len = m->m_len; 2354 if (len) { 2355 data = mtod(m, caddr_t); 2356 /* finish the last word */ 2357 if (wantbyte) { 2358 savebyte[1] = *data; 2359 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2360 data++; 2361 len--; 2362 wantbyte = 0; 2363 } 2364 /* output contiguous words */ 2365 if (len > 1) { 2366 outsw(sc->asic_addr + ED_NOVELL_DATA, 2367 data, len >> 1); 2368 data += len & ~1; 2369 len &= 1; 2370 } 2371 /* save last byte, if necessary */ 2372 if (len == 1) { 2373 savebyte[0] = *data; 2374 wantbyte = 1; 2375 } 2376 } 2377 m = m->m_next; 2378 } 2379 /* spit last byte */ 2380 if (wantbyte) { 2381 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2382 } 2383 } 2384 2385 /* 2386 * Wait for remote DMA complete. This is necessary because on the 2387 * transmit side, data is handled internally by the NIC in bursts and 2388 * we can't start another remote DMA until this one completes. Not 2389 * waiting causes really bad things to happen - like the NIC 2390 * irrecoverably jamming the ISA bus. 2391 */ 2392 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2393 2394 if (!maxwait) { 2395 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 2396 sc->arpcom.ac_if.if_unit); 2397 ed_reset(sc->arpcom.ac_if.if_unit); 2398 return(0); 2399 } 2400 return (total_len); 2401} 2402 2403/* 2404 * Given a source and destination address, copy 'amount' of a packet from 2405 * the ring buffer into a linear destination buffer. Takes into account 2406 * ring-wrap. 2407 */ 2408static inline char * 2409ed_ring_copy(sc, src, dst, amount) 2410 struct ed_softc *sc; 2411 char *src; 2412 char *dst; 2413 u_short amount; 2414{ 2415 u_short tmp_amount; 2416 2417 /* does copy wrap to lower addr in ring buffer? */ 2418 if (src + amount > sc->mem_end) { 2419 tmp_amount = sc->mem_end - src; 2420 2421 /* copy amount up to end of NIC memory */ 2422 if (sc->mem_shared) 2423 bcopy(src, dst, tmp_amount); 2424 else 2425 ed_pio_readmem(sc, src, dst, tmp_amount); 2426 2427 amount -= tmp_amount; 2428 src = sc->mem_ring; 2429 dst += tmp_amount; 2430 } 2431 if (sc->mem_shared) 2432 bcopy(src, dst, amount); 2433 else 2434 ed_pio_readmem(sc, src, dst, amount); 2435 2436 return (src + amount); 2437} 2438 2439void 2440ed_setrcr(ifp, sc) 2441 struct ifnet *ifp; 2442 struct ed_softc *sc; 2443{ 2444 int i; 2445 2446 /* set page 1 registers */ 2447 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 2448 2449 if (ifp->if_flags & IFF_PROMISC) { 2450 2451 /* 2452 * Reconfigure the multicast filter. 2453 */ 2454 for (i = 0; i < 8; i++) 2455 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff); 2456 2457 /* 2458 * And turn on promiscuous mode. Also enable reception of 2459 * runts and packets with CRC & alignment errors. 2460 */ 2461 /* Set page 0 registers */ 2462 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2463 2464 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 2465 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 2466 } else { 2467 /* set up multicast addresses and filter modes */ 2468 if (ifp->if_flags & IFF_MULTICAST) { 2469 u_long mcaf[2]; 2470 2471 if (ifp->if_flags & IFF_ALLMULTI) { 2472 mcaf[0] = 0xffffffff; 2473 mcaf[1] = 0xffffffff; 2474 } else 2475 ds_getmcaf(sc, mcaf); 2476 2477 /* 2478 * Set multicast filter on chip. 2479 */ 2480 for (i = 0; i < 8; i++) 2481 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]); 2482 2483 /* Set page 0 registers */ 2484 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2485 2486 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 2487 } else { 2488 2489 /* 2490 * Initialize multicast address hashing registers to 2491 * not accept multicasts. 2492 */ 2493 for (i = 0; i < 8; ++i) 2494 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00); 2495 2496 /* Set page 0 registers */ 2497 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2498 2499 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 2500 } 2501 } 2502 2503 /* 2504 * Start interface. 2505 */ 2506 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2507} 2508 2509/* 2510 * Compute crc for ethernet address 2511 */ 2512u_long 2513ds_crc(ep) 2514 u_char *ep; 2515{ 2516#define POLYNOMIAL 0x04c11db6 2517 register u_long crc = 0xffffffffL; 2518 register int carry, i, j; 2519 register u_char b; 2520 2521 for (i = 6; --i >= 0;) { 2522 b = *ep++; 2523 for (j = 8; --j >= 0;) { 2524 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 2525 crc <<= 1; 2526 b >>= 1; 2527 if (carry) 2528 crc = ((crc ^ POLYNOMIAL) | carry); 2529 } 2530 } 2531 return crc; 2532#undef POLYNOMIAL 2533} 2534 2535/* 2536 * Compute the multicast address filter from the 2537 * list of multicast addresses we need to listen to. 2538 */ 2539void 2540ds_getmcaf(sc, mcaf) 2541 struct ed_softc *sc; 2542 u_long *mcaf; 2543{ 2544 register u_int index; 2545 register u_char *af = (u_char *) mcaf; 2546 register struct ether_multi *enm; 2547 register struct ether_multistep step; 2548 2549 mcaf[0] = 0; 2550 mcaf[1] = 0; 2551 2552 ETHER_FIRST_MULTI(step, &sc->arpcom, enm); 2553 while (enm != NULL) { 2554 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2555 mcaf[0] = 0xffffffff; 2556 mcaf[1] = 0xffffffff; 2557 return; 2558 } 2559 index = ds_crc(enm->enm_addrlo, 6) >> 26; 2560 af[index >> 3] |= 1 << (index & 7); 2561 2562 ETHER_NEXT_MULTI(step, enm); 2563 } 2564} 2565