if_ed.c revision 5807
1/* 2 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 3 * adapters. By David Greenman, 29-April-1993 4 * 5 * Copyright (C) 1993, David Greenman. This software may be used, modified, 6 * copied, distributed, and sold, in both source and binary form provided 7 * that the above copyright and these terms are retained. Under no 8 * circumstances is the author responsible for the proper functioning 9 * of this software, nor does the author assume any responsibility 10 * for damages incurred with its use. 11 * 12 * Currently supports the Western Digital/SMC 8003 and 8013 series, 13 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 14 * and a variety of similar clones. 15 * 16 * $Id: if_ed.c,v 1.64 1995/01/15 00:18:17 wollman Exp $ 17 */ 18 19#include "ed.h" 20#include "bpfilter.h" 21 22#include <sys/param.h> 23#include <sys/systm.h> 24#include <sys/errno.h> 25#include <sys/ioctl.h> 26#include <sys/mbuf.h> 27#include <sys/socket.h> 28#include <sys/syslog.h> 29#include <sys/devconf.h> 30 31#include <net/if.h> 32#include <net/if_dl.h> 33#include <net/if_types.h> 34 35#ifdef INET 36#include <netinet/in.h> 37#include <netinet/in_systm.h> 38#include <netinet/in_var.h> 39#include <netinet/ip.h> 40#include <netinet/if_ether.h> 41#endif 42 43#ifdef NS 44#include <netns/ns.h> 45#include <netns/ns_if.h> 46#endif 47 48#if NBPFILTER > 0 49#include <net/bpf.h> 50#include <net/bpfdesc.h> 51#endif 52 53#include <i386/isa/isa.h> 54#include <i386/isa/isa_device.h> 55#include <i386/isa/icu.h> 56#include <i386/isa/if_edreg.h> 57 58/* For backwards compatibility */ 59#ifndef IFF_ALTPHYS 60#define IFF_ALTPHYS IFF_LINK0 61#endif 62 63/* 64 * ed_softc: per line info and status 65 */ 66struct ed_softc { 67 struct arpcom arpcom; /* ethernet common */ 68 69 char *type_str; /* pointer to type string */ 70 u_char vendor; /* interface vendor */ 71 u_char type; /* interface type code */ 72 73 u_short asic_addr; /* ASIC I/O bus address */ 74 u_short nic_addr; /* NIC (DS8390) I/O bus address */ 75 76/* 77 * The following 'proto' variable is part of a work-around for 8013EBT asics 78 * being write-only. It's sort of a prototype/shadow of the real thing. 79 */ 80 u_char wd_laar_proto; 81 u_char cr_proto; 82 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 83 int is790; /* set by the probe code if the card is 790 84 * based */ 85 86 caddr_t bpf; /* BPF "magic cookie" */ 87 caddr_t mem_start; /* NIC memory start address */ 88 caddr_t mem_end; /* NIC memory end address */ 89 u_long mem_size; /* total NIC memory size */ 90 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 91 92 u_char mem_shared; /* NIC memory is shared with host */ 93 u_char xmit_busy; /* transmitter is busy */ 94 u_char txb_cnt; /* number of transmit buffers */ 95 u_char txb_inuse; /* number of TX buffers currently in-use */ 96 97 u_char txb_new; /* pointer to where new buffer will be added */ 98 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 99 u_short txb_len[8]; /* buffered xmit buffer lengths */ 100 u_char tx_page_start; /* first page of TX buffer area */ 101 u_char rec_page_start; /* first page of RX ring-buffer */ 102 u_char rec_page_stop; /* last page of RX ring-buffer */ 103 u_char next_packet; /* pointer to next unread RX packet */ 104 struct kern_devconf kdc; /* kernel configuration database info */ 105} ed_softc[NED]; 106 107int ed_attach(struct isa_device *); 108void ed_init(int); 109void edintr(int); 110int ed_ioctl(struct ifnet *, int, caddr_t); 111int ed_probe(struct isa_device *); 112void ed_start(struct ifnet *); 113void ed_reset(int); 114void ed_watchdog(int); 115int ed_probe_generic8390(struct ed_softc *); 116int ed_probe_WD80x3(struct isa_device *); 117int ed_probe_3Com(struct isa_device *); 118int ed_probe_Novell(struct isa_device *); 119 120void ds_getmcaf(); 121 122static void ed_get_packet(struct ed_softc *, char *, int /* u_short */ , int); 123static void ed_stop(int); 124 125static inline void ed_rint(); 126static inline void ed_xmit(); 127static inline char *ed_ring_copy(); 128 129void ed_pio_readmem(), ed_pio_writemem(); 130u_short ed_pio_write_mbufs(); 131 132void ed_setrcr(struct ifnet *, struct ed_softc *); 133 134struct isa_driver eddriver = { 135 ed_probe, 136 ed_attach, 137 "ed", 138 1 /* We are ultra sensitive */ 139}; 140 141/* 142 * Interrupt conversion table for WD/SMC ASIC/83C584 143 * (IRQ* are defined in icu.h) 144 */ 145static unsigned short ed_intr_mask[] = { 146 IRQ9, 147 IRQ3, 148 IRQ5, 149 IRQ7, 150 IRQ10, 151 IRQ11, 152 IRQ15, 153 IRQ4 154}; 155 156/* 157 * Interrupt conversion table for 83C790 158 */ 159static unsigned short ed_790_intr_mask[] = { 160 0, 161 IRQ9, 162 IRQ3, 163 IRQ5, 164 IRQ7, 165 IRQ10, 166 IRQ11, 167 IRQ15 168}; 169 170#define ETHER_MIN_LEN 64 171#define ETHER_MAX_LEN 1518 172#define ETHER_ADDR_LEN 6 173#define ETHER_HDR_SIZE 14 174 175static struct kern_devconf kdc_ed_template = { 176 0, 0, 0, /* filled in by dev_attach */ 177 "ed", 0, { MDDT_ISA, 0, "net" }, 178 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 179 &kdc_isa0, /* parent */ 180 0, /* parentdata */ 181 DC_UNCONFIGURED, 182 "" /* description */ 183}; 184 185static inline void 186ed_registerdev(struct isa_device *id, const char *descr) 187{ 188 struct kern_devconf *kdc = &ed_softc[id->id_unit].kdc; 189 char *longdescr; 190 *kdc = kdc_ed_template; 191 kdc->kdc_unit = id->id_unit; 192 kdc->kdc_parentdata = id; 193 kdc->kdc_description = descr; 194 dev_attach(kdc); 195} 196 197/* 198 * Determine if the device is present 199 * 200 * on entry: 201 * a pointer to an isa_device struct 202 * on exit: 203 * NULL if device not found 204 * or # of i/o addresses used (if found) 205 */ 206int 207ed_probe(isa_dev) 208 struct isa_device *isa_dev; 209{ 210 int nports; 211 212 ed_registerdev(isa_dev, "Ethernet adapter"); 213 214 nports = ed_probe_WD80x3(isa_dev); 215 if (nports) 216 return (nports); 217 218 nports = ed_probe_3Com(isa_dev); 219 if (nports) 220 return (nports); 221 222 nports = ed_probe_Novell(isa_dev); 223 if (nports) 224 return (nports); 225 226 return (0); 227} 228 229/* 230 * Generic probe routine for testing for the existance of a DS8390. 231 * Must be called after the NIC has just been reset. This routine 232 * works by looking at certain register values that are gauranteed 233 * to be initialized a certain way after power-up or reset. Seems 234 * not to currently work on the 83C690. 235 * 236 * Specifically: 237 * 238 * Register reset bits set bits 239 * Command Register (CR) TXP, STA RD2, STP 240 * Interrupt Status (ISR) RST 241 * Interrupt Mask (IMR) All bits 242 * Data Control (DCR) LAS 243 * Transmit Config. (TCR) LB1, LB0 244 * 245 * We only look at the CR and ISR registers, however, because looking at 246 * the others would require changing register pages (which would be 247 * intrusive if this isn't an 8390). 248 * 249 * Return 1 if 8390 was found, 0 if not. 250 */ 251 252int 253ed_probe_generic8390(sc) 254 struct ed_softc *sc; 255{ 256 if ((inb(sc->nic_addr + ED_P0_CR) & 257 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 258 (ED_CR_RD2 | ED_CR_STP)) 259 return (0); 260 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 261 return (0); 262 263 return (1); 264} 265 266/* 267 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 268 */ 269int 270ed_probe_WD80x3(isa_dev) 271 struct isa_device *isa_dev; 272{ 273 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 274 int i; 275 u_int memsize; 276 u_char iptr, isa16bit, sum; 277 278 sc->asic_addr = isa_dev->id_iobase; 279 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 280 sc->is790 = 0; 281 282#ifdef TOSH_ETHER 283 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 284 DELAY(10000); 285#endif 286 287 /* 288 * Attempt to do a checksum over the station address PROM. If it 289 * fails, it's probably not a SMC/WD board. There is a problem with 290 * this, though: some clone WD boards don't pass the checksum test. 291 * Danpex boards for one. 292 */ 293 for (sum = 0, i = 0; i < 8; ++i) 294 sum += inb(sc->asic_addr + ED_WD_PROM + i); 295 296 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 297 298 /* 299 * Checksum is invalid. This often happens with cheap WD8003E 300 * clones. In this case, the checksum byte (the eighth byte) 301 * seems to always be zero. 302 */ 303 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 304 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 305 return (0); 306 } 307 /* reset card to force it into a known state. */ 308#ifdef TOSH_ETHER 309 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 310#else 311 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 312#endif 313 DELAY(100); 314 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 315 /* wait in the case this card is reading it's EEROM */ 316 DELAY(5000); 317 318 sc->vendor = ED_VENDOR_WD_SMC; 319 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 320 321 /* 322 * Set initial values for width/size. 323 */ 324 memsize = 8192; 325 isa16bit = 0; 326 switch (sc->type) { 327 case ED_TYPE_WD8003S: 328 sc->type_str = "WD8003S"; 329 sc->kdc.kdc_description = "Ethernet adapter: WD 8003S"; 330 break; 331 case ED_TYPE_WD8003E: 332 sc->type_str = "WD8003E"; 333 sc->kdc.kdc_description = "Ethernet adapter: WD 8003E"; 334 break; 335 case ED_TYPE_WD8003EB: 336 sc->type_str = "WD8003EB"; 337 sc->kdc.kdc_description = "Ethernet adapter: WD 8003EB"; 338 break; 339 case ED_TYPE_WD8003W: 340 sc->type_str = "WD8003W"; 341 sc->kdc.kdc_description = "Ethernet adapter: WD 8003W"; 342 break; 343 case ED_TYPE_WD8013EBT: 344 sc->type_str = "WD8013EBT"; 345 sc->kdc.kdc_description = "Ethernet adapter: WD 8013EBT"; 346 memsize = 16384; 347 isa16bit = 1; 348 break; 349 case ED_TYPE_WD8013W: 350 sc->type_str = "WD8013W"; 351 sc->kdc.kdc_description = "Ethernet adapter: WD 8013W"; 352 memsize = 16384; 353 isa16bit = 1; 354 break; 355 case ED_TYPE_WD8013EP: /* also WD8003EP */ 356 if (inb(sc->asic_addr + ED_WD_ICR) 357 & ED_WD_ICR_16BIT) { 358 isa16bit = 1; 359 memsize = 16384; 360 sc->type_str = "WD8013EP"; 361 sc->kdc.kdc_description = 362 "Ethernet adapter: WD 8013EP"; 363 } else { 364 sc->type_str = "WD8003EP"; 365 sc->kdc.kdc_description = 366 "Ethernet adapter: WD 8003EP"; 367 } 368 break; 369 case ED_TYPE_WD8013WC: 370 sc->type_str = "WD8013WC"; 371 sc->kdc.kdc_description = "Ethernet adapter: WD 8013WC"; 372 memsize = 16384; 373 isa16bit = 1; 374 break; 375 case ED_TYPE_WD8013EBP: 376 sc->type_str = "WD8013EBP"; 377 sc->kdc.kdc_description = "Ethernet adapter: WD 8013EBP"; 378 memsize = 16384; 379 isa16bit = 1; 380 break; 381 case ED_TYPE_WD8013EPC: 382 sc->type_str = "WD8013EPC"; 383 sc->kdc.kdc_description = "Ethernet adapter: WD 8013EPC"; 384 memsize = 16384; 385 isa16bit = 1; 386 break; 387 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 388 (unsigned int) *(isa_dev->id_maddr+8192) = (unsigned int)0; 389 if ((unsigned int) *(isa_dev->id_maddr+8192)) { 390 sc->type_str = "SMC8416C/SMC8416BT"; 391 sc->kdc.kdc_description = 392 "Ethernet adapter: SMC 8416C or 8416BT"; 393 memsize = 8192; 394 } else { 395 sc->type_str = "SMC8216/SMC8216C"; 396 sc->kdc.kdc_description = 397 "Ethernet adapter: SMC 8216 or 8216C"; 398 memsize = 16384; 399 } 400 isa16bit = 1; 401 sc->is790 = 1; 402 break; 403 case ED_TYPE_SMC8216T: 404 sc->type_str = "SMC8216T"; 405 sc->kdc.kdc_description = 406 "Ethernet adapter: SMC 8216T"; 407 408 outb(sc->asic_addr + ED_WD790_HWR, 409 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 410 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 411 case ED_WD790_RAR_SZ64: 412 memsize = 65536; 413 break; 414 case ED_WD790_RAR_SZ32: 415 memsize = 32768; 416 break; 417 case ED_WD790_RAR_SZ16: 418 memsize = 16384; 419 break; 420 case ED_WD790_RAR_SZ8: 421 sc->type_str = "SMC8416T"; 422 sc->kdc.kdc_description = 423 "Ethernet adapter: SMC 8416T"; 424 memsize = 8192; 425 break; 426 } 427 outb(sc->asic_addr + ED_WD790_HWR, 428 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 429 430 isa16bit = 1; 431 sc->is790 = 1; 432 break; 433#ifdef TOSH_ETHER 434 case ED_TYPE_TOSHIBA1: 435 sc->type_str = "Toshiba1"; 436 sc->kdc.kdc_description = "Ethernet adapter: Toshiba1"; 437 memsize = 32768; 438 isa16bit = 1; 439 break; 440 case ED_TYPE_TOSHIBA4: 441 sc->type_str = "Toshiba4"; 442 sc->kdc.kdc_description = "Ethernet adapter: Toshiba4"; 443 memsize = 32768; 444 isa16bit = 1; 445 break; 446#endif 447 default: 448 sc->type_str = ""; 449 break; 450 } 451 452 /* 453 * Make some adjustments to initial values depending on what is found 454 * in the ICR. 455 */ 456 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 457#ifdef TOSH_ETHER 458 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 459#endif 460 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 461 isa16bit = 0; 462 memsize = 8192; 463 } 464 465 466 if (sc->is790) { 467 outb(sc->asic_addr + ED_WD790_HWR, 468 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 469 470 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 471 case ED_WD790_RAR_SZ64: 472 memsize = 65536; 473 break; 474 case ED_WD790_RAR_SZ32: 475 memsize = 32768; 476 break; 477 case ED_WD790_RAR_SZ16: 478 memsize = 16384; 479 break; 480 case ED_WD790_RAR_SZ8: 481 memsize = 8192; 482 break; 483 } 484 outb(sc->asic_addr + ED_WD790_HWR, 485 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 486 } 487 488#if ED_DEBUG 489 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 490 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize); 491 for (i = 0; i < 8; i++) 492 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 493#endif 494 495 /* 496 * Allow the user to override the autoconfiguration 497 */ 498 if (isa_dev->id_msize) 499 memsize = isa_dev->id_msize; 500 501 /* 502 * (note that if the user specifies both of the following flags that 503 * '8bit' mode intentionally has precedence) 504 */ 505 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE) 506 isa16bit = 1; 507 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE) 508 isa16bit = 0; 509 510 /* 511 * If possible, get the assigned interrupt number from the card and 512 * use it. 513 */ 514 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 515 516 /* 517 * Assemble together the encoded interrupt number. 518 */ 519 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 520 ((inb(isa_dev->id_iobase + ED_WD_IRR) & 521 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 522 523 /* 524 * Use what the board tells us. 525 */ 526 isa_dev->id_irq = ed_intr_mask[iptr]; 527 528 /* 529 * Enable the interrupt. 530 */ 531 outb(isa_dev->id_iobase + ED_WD_IRR, 532 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 533 } 534 if (sc->is790) { 535 outb(isa_dev->id_iobase + ED_WD790_HWR, 536 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); 537 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 538 (inb(isa_dev->id_iobase + ED_WD790_GCR) & 539 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 540 outb(isa_dev->id_iobase + ED_WD790_HWR, 541 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 542 543 /* 544 * Use what the board tells us. 545 */ 546 isa_dev->id_irq = ed_790_intr_mask[iptr]; 547 548 /* 549 * Enable interrupts. 550 */ 551 outb(isa_dev->id_iobase + ED_WD790_ICR, 552 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL); 553 } 554 if (isa_dev->id_irq <= 0) { 555 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n", 556 isa_dev->id_unit, sc->type_str); 557 return (0); 558 } 559 sc->isa16bit = isa16bit; 560 sc->mem_shared = 1; 561 isa_dev->id_msize = memsize; 562 sc->mem_start = (caddr_t) isa_dev->id_maddr; 563 564 /* 565 * allocate one xmit buffer if < 16k, two buffers otherwise 566 */ 567 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 568 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 569 sc->txb_cnt = 1; 570 sc->rec_page_start = ED_TXBUF_SIZE; 571 } else { 572 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2); 573 sc->txb_cnt = 2; 574 sc->rec_page_start = ED_TXBUF_SIZE * 2; 575 } 576 sc->mem_size = memsize; 577 sc->mem_end = sc->mem_start + memsize; 578 sc->rec_page_stop = memsize / ED_PAGE_SIZE; 579 sc->tx_page_start = ED_WD_PAGE_OFFSET; 580 581 /* 582 * Get station address from on-board ROM 583 */ 584 for (i = 0; i < ETHER_ADDR_LEN; ++i) 585 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 586 587 /* 588 * Set upper address bits and 8/16 bit access to shared memory 589 */ 590 if (isa16bit) { 591 if (sc->is790) { 592 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 593 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN); 594 } else { 595 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 596 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN | 597 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 598 } 599 } else { 600 if (((sc->type & ED_WD_SOFTCONFIG) || 601#ifdef TOSH_ETHER 602 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 603#endif 604 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 605 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 606 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 607 } 608 } 609 610 /* 611 * Set address and enable interface shared memory. 612 */ 613 if (!sc->is790) { 614#ifdef TOSH_ETHER 615 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 616 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 617 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 618 619#else 620 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 621 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 622#endif 623 sc->cr_proto = ED_CR_RD2; 624 } else { 625 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 626 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 627 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 628 ((kvtop(sc->mem_start) >> 11) & 0x40) | 629 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 630 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 631 sc->cr_proto = 0; 632 } 633 634#if 0 635 printf("starting memory performance test at 0x%x, size %d...\n", 636 sc->mem_start, memsize*16384); 637 for (i = 0; i < 16384; i++) 638 bzero(sc->mem_start, memsize); 639 printf("***DONE***\n"); 640#endif 641 642 /* 643 * Now zero memory and verify that it is clear 644 */ 645 bzero(sc->mem_start, memsize); 646 647 for (i = 0; i < memsize; ++i) { 648 if (sc->mem_start[i]) { 649 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 650 isa_dev->id_unit, kvtop(sc->mem_start + i)); 651 652 /* 653 * Disable 16 bit access to shared memory 654 */ 655 if (isa16bit) { 656 if (sc->is790) { 657 outb(sc->asic_addr + ED_WD_MSR, 0x00); 658 } 659 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 660 ~ED_WD_LAAR_M16EN)); 661 } 662 return (0); 663 } 664 } 665 666 /* 667 * Disable 16bit access to shared memory - we leave it 668 * disabled so that 1) machines reboot properly when the board 669 * is set 16 bit mode and there are conflicting 8bit 670 * devices/ROMS in the same 128k address space as this boards 671 * shared memory. and 2) so that other 8 bit devices with 672 * shared memory can be used in this 128k region, too. 673 */ 674 if (isa16bit) { 675 if (sc->is790) { 676 outb(sc->asic_addr + ED_WD_MSR, 0x00); 677 } 678 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 679 ~ED_WD_LAAR_M16EN)); 680 } 681 return (ED_WD_IO_PORTS); 682} 683 684/* 685 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 686 */ 687int 688ed_probe_3Com(isa_dev) 689 struct isa_device *isa_dev; 690{ 691 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 692 int i; 693 u_int memsize; 694 u_char isa16bit; 695 696 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 697 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 698 699 /* 700 * Verify that the kernel configured I/O address matches the board 701 * configured address 702 */ 703 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 704 case ED_3COM_BCFR_300: 705 if (isa_dev->id_iobase != 0x300) 706 return (0); 707 break; 708 case ED_3COM_BCFR_310: 709 if (isa_dev->id_iobase != 0x310) 710 return (0); 711 break; 712 case ED_3COM_BCFR_330: 713 if (isa_dev->id_iobase != 0x330) 714 return (0); 715 break; 716 case ED_3COM_BCFR_350: 717 if (isa_dev->id_iobase != 0x350) 718 return (0); 719 break; 720 case ED_3COM_BCFR_250: 721 if (isa_dev->id_iobase != 0x250) 722 return (0); 723 break; 724 case ED_3COM_BCFR_280: 725 if (isa_dev->id_iobase != 0x280) 726 return (0); 727 break; 728 case ED_3COM_BCFR_2A0: 729 if (isa_dev->id_iobase != 0x2a0) 730 return (0); 731 break; 732 case ED_3COM_BCFR_2E0: 733 if (isa_dev->id_iobase != 0x2e0) 734 return (0); 735 break; 736 default: 737 return (0); 738 } 739 740 /* 741 * Verify that the kernel shared memory address matches the board 742 * configured address. 743 */ 744 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 745 case ED_3COM_PCFR_DC000: 746 if (kvtop(isa_dev->id_maddr) != 0xdc000) 747 return (0); 748 break; 749 case ED_3COM_PCFR_D8000: 750 if (kvtop(isa_dev->id_maddr) != 0xd8000) 751 return (0); 752 break; 753 case ED_3COM_PCFR_CC000: 754 if (kvtop(isa_dev->id_maddr) != 0xcc000) 755 return (0); 756 break; 757 case ED_3COM_PCFR_C8000: 758 if (kvtop(isa_dev->id_maddr) != 0xc8000) 759 return (0); 760 break; 761 default: 762 return (0); 763 } 764 765 766 /* 767 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 768 * sequence because it'll lock up if the cable isn't connected if we 769 * don't. 770 */ 771 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 772 773 /* 774 * Wait for a while, then un-reset it 775 */ 776 DELAY(50); 777 778 /* 779 * The 3Com ASIC defaults to rather strange settings for the CR after 780 * a reset - it's important to set it again after the following outb 781 * (this is done when we map the PROM below). 782 */ 783 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 784 785 /* 786 * Wait a bit for the NIC to recover from the reset 787 */ 788 DELAY(5000); 789 790 sc->vendor = ED_VENDOR_3COM; 791 sc->type_str = "3c503"; 792 sc->kdc.kdc_description = "Ethernet adapter: 3c503"; 793 sc->mem_shared = 1; 794 sc->cr_proto = ED_CR_RD2; 795 796 /* 797 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 798 * to it. 799 */ 800 memsize = 8192; 801 802 /* 803 * Get station address from on-board ROM 804 */ 805 806 /* 807 * First, map ethernet address PROM over the top of where the NIC 808 * registers normally appear. 809 */ 810 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 811 812 for (i = 0; i < ETHER_ADDR_LEN; ++i) 813 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 814 815 /* 816 * Unmap PROM - select NIC registers. The proper setting of the 817 * tranceiver is set in ed_init so that the attach code is given a 818 * chance to set the default based on a compile-time config option 819 */ 820 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 821 822 /* 823 * Determine if this is an 8bit or 16bit board 824 */ 825 826 /* 827 * select page 0 registers 828 */ 829 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 830 831 /* 832 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 833 * board. 834 */ 835 outb(sc->nic_addr + ED_P0_DCR, 0); 836 837 /* 838 * select page 2 registers 839 */ 840 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 841 842 /* 843 * The 3c503 forces the WTS bit to a one if this is a 16bit board 844 */ 845 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 846 isa16bit = 1; 847 else 848 isa16bit = 0; 849 850 /* 851 * select page 0 registers 852 */ 853 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 854 855 sc->mem_start = (caddr_t) isa_dev->id_maddr; 856 sc->mem_size = memsize; 857 sc->mem_end = sc->mem_start + memsize; 858 859 /* 860 * We have an entire 8k window to put the transmit buffers on the 861 * 16bit boards. But since the 16bit 3c503's shared memory is only 862 * fast enough to overlap the loading of one full-size packet, trying 863 * to load more than 2 buffers can actually leave the transmitter idle 864 * during the load. So 2 seems the best value. (Although a mix of 865 * variable-sized packets might change this assumption. Nonetheless, 866 * we optimize for linear transfers of same-size packets.) 867 */ 868 if (isa16bit) { 869 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 870 sc->txb_cnt = 1; 871 else 872 sc->txb_cnt = 2; 873 874 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 875 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 876 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 877 ED_3COM_RX_PAGE_OFFSET_16BIT; 878 sc->mem_ring = sc->mem_start; 879 } else { 880 sc->txb_cnt = 1; 881 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 882 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 883 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 884 ED_3COM_TX_PAGE_OFFSET_8BIT; 885 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 886 } 887 888 sc->isa16bit = isa16bit; 889 890 /* 891 * Initialize GA page start/stop registers. Probably only needed if 892 * doing DMA, but what the hell. 893 */ 894 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 895 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 896 897 /* 898 * Set IRQ. 3c503 only allows a choice of irq 2-5. 899 */ 900 switch (isa_dev->id_irq) { 901 case IRQ2: 902 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 903 break; 904 case IRQ3: 905 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 906 break; 907 case IRQ4: 908 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 909 break; 910 case IRQ5: 911 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 912 break; 913 default: 914 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n", 915 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 916 return (0); 917 } 918 919 /* 920 * Initialize GA configuration register. Set bank and enable shared 921 * mem. 922 */ 923 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 924 ED_3COM_GACFR_MBS0); 925 926 /* 927 * Initialize "Vector Pointer" registers. These gawd-awful things are 928 * compared to 20 bits of the address on ISA, and if they match, the 929 * shared memory is disabled. We set them to 0xffff0...allegedly the 930 * reset vector. 931 */ 932 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 933 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 934 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 935 936 /* 937 * Zero memory and verify that it is clear 938 */ 939 bzero(sc->mem_start, memsize); 940 941 for (i = 0; i < memsize; ++i) 942 if (sc->mem_start[i]) { 943 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 944 isa_dev->id_unit, kvtop(sc->mem_start + i)); 945 return (0); 946 } 947 isa_dev->id_msize = memsize; 948 return (ED_3COM_IO_PORTS); 949} 950 951/* 952 * Probe and vendor-specific initialization routine for NE1000/2000 boards 953 */ 954int 955ed_probe_Novell(isa_dev) 956 struct isa_device *isa_dev; 957{ 958 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 959 u_int memsize, n; 960 u_char romdata[16], tmp; 961 static char test_pattern[32] = "THIS is A memory TEST pattern"; 962 char test_buffer[32]; 963 964 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET; 965 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET; 966 967 /* XXX - do Novell-specific probe here */ 968 969 /* Reset the board */ 970#ifdef GWETHER 971 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 972 DELAY(200); 973#endif /* GWETHER */ 974 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 975 976 /* 977 * I don't know if this is necessary; probably cruft leftover from 978 * Clarkson packet driver code. Doesn't do a thing on the boards I've 979 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 980 * non-invasive...but some boards don't seem to reset and I don't have 981 * complete documentation on what the 'right' thing to do is...so we 982 * do the invasive thing for now. Yuck.] 983 */ 984 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 985 DELAY(5000); 986 987 /* 988 * This is needed because some NE clones apparently don't reset the 989 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 990 * - this makes the probe invasive! ...Done against my better 991 * judgement. -DLG 992 */ 993 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 994 995 DELAY(5000); 996 997 /* Make sure that we really have an 8390 based board */ 998 if (!ed_probe_generic8390(sc)) 999 return (0); 1000 1001 sc->vendor = ED_VENDOR_NOVELL; 1002 sc->mem_shared = 0; 1003 sc->cr_proto = ED_CR_RD2; 1004 isa_dev->id_maddr = 0; 1005 1006 /* 1007 * Test the ability to read and write to the NIC memory. This has the 1008 * side affect of determining if this is an NE1000 or an NE2000. 1009 */ 1010 1011 /* 1012 * This prevents packets from being stored in the NIC memory when the 1013 * readmem routine turns on the start bit in the CR. 1014 */ 1015 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1016 1017 /* Temporarily initialize DCR for byte operations */ 1018 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1019 1020 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1021 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1022 1023 sc->isa16bit = 0; 1024 1025 /* 1026 * Write a test pattern in byte mode. If this fails, then there 1027 * probably isn't any memory at 8k - which likely means that the board 1028 * is an NE2000. 1029 */ 1030 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1031 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1032 1033 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 1034 /* not an NE1000 - try NE2000 */ 1035 1036 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1037 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1038 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1039 1040 sc->isa16bit = 1; 1041 1042 /* 1043 * Write a test pattern in word mode. If this also fails, then 1044 * we don't know what this board is. 1045 */ 1046 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1047 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1048 1049 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 1050 return (0); /* not an NE2000 either */ 1051 1052 sc->type = ED_TYPE_NE2000; 1053 sc->type_str = "NE2000"; 1054 sc->kdc.kdc_description = "Ethernet adapter: NE2000"; 1055 } else { 1056 sc->type = ED_TYPE_NE1000; 1057 sc->type_str = "NE1000"; 1058 sc->kdc.kdc_description = "Ethernet adapter: NE1000"; 1059 } 1060 1061 /* 8k of memory plus an additional 8k if 16bit */ 1062 memsize = 8192 + sc->isa16bit * 8192; 1063 1064#if 0 /* probably not useful - NE boards only come two ways */ 1065 /* allow kernel config file overrides */ 1066 if (isa_dev->id_msize) 1067 memsize = isa_dev->id_msize; 1068#endif 1069 1070 sc->mem_size = memsize; 1071 1072 /* NIC memory doesn't start at zero on an NE board */ 1073 /* The start address is tied to the bus width */ 1074 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1075 sc->mem_end = sc->mem_start + memsize; 1076 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1077 1078#ifdef GWETHER 1079 { 1080 int x, i, mstart = 0, msize = 0; 1081 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1082 1083 for (i = 0; i < ED_PAGE_SIZE; i++) 1084 pbuf0[i] = 0; 1085 1086 /* Clear all the memory. */ 1087 for (x = 1; x < 256; x++) 1088 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1089 1090 /* Search for the start of RAM. */ 1091 for (x = 1; x < 256; x++) { 1092 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1093 if (memcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1094 for (i = 0; i < ED_PAGE_SIZE; i++) 1095 pbuf[i] = 255 - x; 1096 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1097 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1098 if (memcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1099 mstart = x * ED_PAGE_SIZE; 1100 msize = ED_PAGE_SIZE; 1101 break; 1102 } 1103 } 1104 } 1105 1106 if (mstart == 0) { 1107 printf("ed%d: Cannot find start of RAM.\n", isa_dev->id_unit); 1108 return 0; 1109 } 1110 /* Search for the start of RAM. */ 1111 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1112 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1113 if (memcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1114 for (i = 0; i < ED_PAGE_SIZE; i++) 1115 pbuf[i] = 255 - x; 1116 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1117 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1118 if (memcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1119 msize += ED_PAGE_SIZE; 1120 else { 1121 break; 1122 } 1123 } else { 1124 break; 1125 } 1126 } 1127 1128 if (msize == 0) { 1129 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", isa_dev->id_unit, mstart, x); 1130 return 0; 1131 } 1132 printf("ed%d: RAM start at %d, size : %d.\n", isa_dev->id_unit, mstart, msize); 1133 1134 sc->mem_size = msize; 1135 sc->mem_start = (char *) mstart; 1136 sc->mem_end = (char *) (msize + mstart); 1137 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1138 } 1139#endif /* GWETHER */ 1140 1141 /* 1142 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1143 * otherwise). 1144 */ 1145 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1146 sc->txb_cnt = 1; 1147 else 1148 sc->txb_cnt = 2; 1149 1150 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1151 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1152 1153 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1154 1155 ed_pio_readmem(sc, 0, romdata, 16); 1156 for (n = 0; n < ETHER_ADDR_LEN; n++) 1157 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1158 1159#ifdef GWETHER 1160 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1161 sc->type_str = "Gateway AT"; 1162 sc->kdc.kdc_description = "Ethernet adapter: Gateway AT"; 1163 } 1164#endif /* GWETHER */ 1165 1166 /* clear any pending interrupts that might have occurred above */ 1167 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1168 1169 return (ED_NOVELL_IO_PORTS); 1170} 1171 1172/* 1173 * Install interface into kernel networking data structures 1174 */ 1175int 1176ed_attach(isa_dev) 1177 struct isa_device *isa_dev; 1178{ 1179 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1180 struct ifnet *ifp = &sc->arpcom.ac_if; 1181 1182 /* 1183 * Set interface to stopped condition (reset) 1184 */ 1185 ed_stop(isa_dev->id_unit); 1186 1187 /* 1188 * Initialize ifnet structure 1189 */ 1190 ifp->if_unit = isa_dev->id_unit; 1191 ifp->if_name = "ed"; 1192 ifp->if_init = ed_init; 1193 ifp->if_output = ether_output; 1194 ifp->if_start = ed_start; 1195 ifp->if_ioctl = ed_ioctl; 1196 ifp->if_reset = ed_reset; 1197 ifp->if_watchdog = ed_watchdog; 1198 1199 /* 1200 * Set default state for ALTPHYS flag (used to disable the tranceiver 1201 * for AUI operation), based on compile-time config option. 1202 */ 1203 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER) 1204 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 1205 IFF_MULTICAST | IFF_ALTPHYS); 1206 else 1207 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 1208 IFF_MULTICAST); 1209 1210 /* 1211 * Attach the interface 1212 */ 1213 if_attach(ifp); 1214 /* device attach does transition from UNCONFIGURED to IDLE state */ 1215 sc->kdc.kdc_state = DC_IDLE; 1216 1217 /* 1218 * Print additional info when attached 1219 */ 1220 printf("ed%d: address %s, ", isa_dev->id_unit, 1221 ether_sprintf(sc->arpcom.ac_enaddr)); 1222 1223 if (sc->type_str && (*sc->type_str != 0)) 1224 printf("type %s ", sc->type_str); 1225 else 1226 printf("type unknown (0x%x) ", sc->type); 1227 1228 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1229 1230 printf("%s\n", ((sc->vendor == ED_VENDOR_3COM) && 1231 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1232 1233 /* 1234 * If BPF is in the kernel, call the attach for it 1235 */ 1236#if NBPFILTER > 0 1237 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 1238#endif 1239 return 1; 1240} 1241 1242/* 1243 * Reset interface. 1244 */ 1245void 1246ed_reset(unit) 1247 int unit; 1248{ 1249 int s; 1250 1251 s = splimp(); 1252 1253 /* 1254 * Stop interface and re-initialize. 1255 */ 1256 ed_stop(unit); 1257 ed_init(unit); 1258 1259 (void) splx(s); 1260} 1261 1262/* 1263 * Take interface offline. 1264 */ 1265void 1266ed_stop(unit) 1267 int unit; 1268{ 1269 struct ed_softc *sc = &ed_softc[unit]; 1270 int n = 5000; 1271 1272 /* 1273 * Stop everything on the interface, and select page 0 registers. 1274 */ 1275 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1276 1277 /* 1278 * Wait for interface to enter stopped state, but limit # of checks to 1279 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1280 * just in case it's an old one. 1281 */ 1282 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1283} 1284 1285/* 1286 * Device timeout/watchdog routine. Entered if the device neglects to 1287 * generate an interrupt after a transmit has been started on it. 1288 */ 1289void 1290ed_watchdog(unit) 1291 int unit; 1292{ 1293 struct ed_softc *sc = &ed_softc[unit]; 1294 1295 log(LOG_ERR, "ed%d: device timeout\n", unit); 1296 ++sc->arpcom.ac_if.if_oerrors; 1297 1298 ed_reset(unit); 1299} 1300 1301/* 1302 * Initialize device. 1303 */ 1304void 1305ed_init(unit) 1306 int unit; 1307{ 1308 struct ed_softc *sc = &ed_softc[unit]; 1309 struct ifnet *ifp = &sc->arpcom.ac_if; 1310 int i, s; 1311 1312 1313 /* address not known */ 1314 if (ifp->if_addrlist == (struct ifaddr *) 0) 1315 return; 1316 1317 /* 1318 * Initialize the NIC in the exact order outlined in the NS manual. 1319 * This init procedure is "mandatory"...don't change what or when 1320 * things happen. 1321 */ 1322 s = splimp(); 1323 1324 /* reset transmitter flags */ 1325 sc->xmit_busy = 0; 1326 sc->arpcom.ac_if.if_timer = 0; 1327 1328 sc->txb_inuse = 0; 1329 sc->txb_new = 0; 1330 sc->txb_next_tx = 0; 1331 1332 /* This variable is used below - don't move this assignment */ 1333 sc->next_packet = sc->rec_page_start + 1; 1334 1335 /* 1336 * Set interface for page 0, Remote DMA complete, Stopped 1337 */ 1338 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1339 1340 if (sc->isa16bit) { 1341 1342 /* 1343 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1344 * order=80x86, word-wide DMA xfers, 1345 */ 1346 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1347 } else { 1348 1349 /* 1350 * Same as above, but byte-wide DMA xfers 1351 */ 1352 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1353 } 1354 1355 /* 1356 * Clear Remote Byte Count Registers 1357 */ 1358 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1359 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1360 1361 /* 1362 * For the moment, don't store incoming packets in memory. 1363 */ 1364 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1365 1366 /* 1367 * Place NIC in internal loopback mode 1368 */ 1369 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1370 1371 /* 1372 * Initialize transmit/receive (ring-buffer) Page Start 1373 */ 1374 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1375 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1376 /* Set lower bits of byte addressable framing to 0 */ 1377 if (sc->is790) 1378 outb(sc->nic_addr + 0x09, 0); 1379 1380 /* 1381 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1382 */ 1383 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1384 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1385 1386 /* 1387 * Clear all interrupts. A '1' in each bit position clears the 1388 * corresponding flag. 1389 */ 1390 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1391 1392 /* 1393 * Enable the following interrupts: receive/transmit complete, 1394 * receive/transmit error, and Receiver OverWrite. 1395 * 1396 * Counter overflow and Remote DMA complete are *not* enabled. 1397 */ 1398 outb(sc->nic_addr + ED_P0_IMR, 1399 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1400 1401 /* 1402 * Program Command Register for page 1 1403 */ 1404 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1405 1406 /* 1407 * Copy out our station address 1408 */ 1409 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1410 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1411 1412 /* 1413 * Set Current Page pointer to next_packet (initialized above) 1414 */ 1415 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1416 1417 /* 1418 * Program Receiver Configuration Register and multicast filter. CR is 1419 * set to page 0 on return. 1420 */ 1421 ed_setrcr(ifp, sc); 1422 1423 /* 1424 * Take interface out of loopback 1425 */ 1426 outb(sc->nic_addr + ED_P0_TCR, 0); 1427 1428 /* 1429 * If this is a 3Com board, the tranceiver must be software enabled 1430 * (there is no settable hardware default). 1431 */ 1432 if (sc->vendor == ED_VENDOR_3COM) { 1433 if (ifp->if_flags & IFF_ALTPHYS) { 1434 outb(sc->asic_addr + ED_3COM_CR, 0); 1435 } else { 1436 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1437 } 1438 } 1439 1440 /* 1441 * Set 'running' flag, and clear output active flag. 1442 */ 1443 ifp->if_flags |= IFF_RUNNING; 1444 ifp->if_flags &= ~IFF_OACTIVE; 1445 1446 /* 1447 * ...and attempt to start output 1448 */ 1449 ed_start(ifp); 1450 1451 (void) splx(s); 1452} 1453 1454/* 1455 * This routine actually starts the transmission on the interface 1456 */ 1457static inline void 1458ed_xmit(ifp) 1459 struct ifnet *ifp; 1460{ 1461 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1462 unsigned short len; 1463 1464 len = sc->txb_len[sc->txb_next_tx]; 1465 1466 /* 1467 * Set NIC for page 0 register access 1468 */ 1469 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1470 1471 /* 1472 * Set TX buffer start page 1473 */ 1474 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 1475 sc->txb_next_tx * ED_TXBUF_SIZE); 1476 1477 /* 1478 * Set TX length 1479 */ 1480 outb(sc->nic_addr + ED_P0_TBCR0, len); 1481 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 1482 1483 /* 1484 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 1485 */ 1486 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 1487 sc->xmit_busy = 1; 1488 1489 /* 1490 * Point to next transmit buffer slot and wrap if necessary. 1491 */ 1492 sc->txb_next_tx++; 1493 if (sc->txb_next_tx == sc->txb_cnt) 1494 sc->txb_next_tx = 0; 1495 1496 /* 1497 * Set a timer just in case we never hear from the board again 1498 */ 1499 ifp->if_timer = 2; 1500} 1501 1502/* 1503 * Start output on interface. 1504 * We make two assumptions here: 1505 * 1) that the current priority is set to splimp _before_ this code 1506 * is called *and* is returned to the appropriate priority after 1507 * return 1508 * 2) that the IFF_OACTIVE flag is checked before this code is called 1509 * (i.e. that the output part of the interface is idle) 1510 */ 1511void 1512ed_start(ifp) 1513 struct ifnet *ifp; 1514{ 1515 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1516 struct mbuf *m0, *m; 1517 caddr_t buffer; 1518 int len; 1519 1520outloop: 1521 1522 /* 1523 * First, see if there are buffered packets and an idle transmitter - 1524 * should never happen at this point. 1525 */ 1526 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 1527 printf("ed: packets buffered, but transmitter idle\n"); 1528 ed_xmit(ifp); 1529 } 1530 1531 /* 1532 * See if there is room to put another packet in the buffer. 1533 */ 1534 if (sc->txb_inuse == sc->txb_cnt) { 1535 1536 /* 1537 * No room. Indicate this to the outside world and exit. 1538 */ 1539 ifp->if_flags |= IFF_OACTIVE; 1540 return; 1541 } 1542 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 1543 if (m == 0) { 1544 1545 /* 1546 * We are using the !OACTIVE flag to indicate to the outside 1547 * world that we can accept an additional packet rather than 1548 * that the transmitter is _actually_ active. Indeed, the 1549 * transmitter may be active, but if we haven't filled all the 1550 * buffers with data then we still want to accept more. 1551 */ 1552 ifp->if_flags &= ~IFF_OACTIVE; 1553 return; 1554 } 1555 1556 /* 1557 * Copy the mbuf chain into the transmit buffer 1558 */ 1559 1560 m0 = m; 1561 1562 /* txb_new points to next open buffer slot */ 1563 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 1564 1565 if (sc->mem_shared) { 1566 1567 /* 1568 * Special case setup for 16 bit boards... 1569 */ 1570 if (sc->isa16bit) { 1571 switch (sc->vendor) { 1572 1573 /* 1574 * For 16bit 3Com boards (which have 16k of 1575 * memory), we have the xmit buffers in a 1576 * different page of memory ('page 0') - so 1577 * change pages. 1578 */ 1579 case ED_VENDOR_3COM: 1580 outb(sc->asic_addr + ED_3COM_GACFR, 1581 ED_3COM_GACFR_RSEL); 1582 break; 1583 1584 /* 1585 * Enable 16bit access to shared memory on 1586 * WD/SMC boards. 1587 */ 1588 case ED_VENDOR_WD_SMC:{ 1589 outb(sc->asic_addr + ED_WD_LAAR, 1590 (sc->wd_laar_proto | ED_WD_LAAR_M16EN)); 1591 if (sc->is790) { 1592 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 1593 } 1594 break; 1595 } 1596 } 1597 } 1598 for (len = 0; m != 0; m = m->m_next) { 1599 bcopy(mtod(m, caddr_t), buffer, m->m_len); 1600 buffer += m->m_len; 1601 len += m->m_len; 1602 } 1603 1604 /* 1605 * Restore previous shared memory access 1606 */ 1607 if (sc->isa16bit) { 1608 switch (sc->vendor) { 1609 case ED_VENDOR_3COM: 1610 outb(sc->asic_addr + ED_3COM_GACFR, 1611 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 1612 break; 1613 case ED_VENDOR_WD_SMC:{ 1614 if (sc->is790) { 1615 outb(sc->asic_addr + ED_WD_MSR, 0x00); 1616 } 1617 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 1618 break; 1619 } 1620 } 1621 } 1622 } else { 1623 len = ed_pio_write_mbufs(sc, m, buffer); 1624 if (len == 0) 1625 goto outloop; 1626 } 1627 1628 sc->txb_len[sc->txb_new] = max(len, ETHER_MIN_LEN); 1629 1630 sc->txb_inuse++; 1631 1632 /* 1633 * Point to next buffer slot and wrap if necessary. 1634 */ 1635 sc->txb_new++; 1636 if (sc->txb_new == sc->txb_cnt) 1637 sc->txb_new = 0; 1638 1639 if (sc->xmit_busy == 0) 1640 ed_xmit(ifp); 1641 1642 /* 1643 * Tap off here if there is a bpf listener. 1644 */ 1645#if NBPFILTER > 0 1646 if (sc->bpf) { 1647 bpf_mtap(sc->bpf, m0); 1648 } 1649#endif 1650 1651 m_freem(m0); 1652 1653 /* 1654 * Loop back to the top to possibly buffer more packets 1655 */ 1656 goto outloop; 1657} 1658 1659/* 1660 * Ethernet interface receiver interrupt. 1661 */ 1662static inline void 1663ed_rint(unit) 1664 int unit; 1665{ 1666 register struct ed_softc *sc = &ed_softc[unit]; 1667 u_char boundry; 1668 u_short len; 1669 struct ed_ring packet_hdr; 1670 char *packet_ptr; 1671 1672 /* 1673 * Set NIC to page 1 registers to get 'current' pointer 1674 */ 1675 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 1676 1677 /* 1678 * 'sc->next_packet' is the logical beginning of the ring-buffer - 1679 * i.e. it points to where new data has been buffered. The 'CURR' 1680 * (current) register points to the logical end of the ring-buffer - 1681 * i.e. it points to where additional new data will be added. We loop 1682 * here until the logical beginning equals the logical end (or in 1683 * other words, until the ring-buffer is empty). 1684 */ 1685 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 1686 1687 /* get pointer to this buffer's header structure */ 1688 packet_ptr = sc->mem_ring + 1689 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 1690 1691 /* 1692 * The byte count includes a 4 byte header that was added by 1693 * the NIC. 1694 */ 1695 if (sc->mem_shared) 1696 packet_hdr = *(struct ed_ring *) packet_ptr; 1697 else 1698 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr, 1699 sizeof(packet_hdr)); 1700 len = packet_hdr.count; 1701 if (len > ETHER_MAX_LEN) { 1702 /* 1703 * Length is a wild value. There's a good chance that 1704 * this was caused by the NIC being old and buggy. 1705 * The bug is that the length low byte is duplicated in 1706 * the high byte. Try to recalculate the length based on 1707 * the pointer to the next packet. 1708 */ 1709 /* 1710 * NOTE: sc->next_packet is pointing at the current packet. 1711 */ 1712 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 1713 if (packet_hdr.next_packet >= sc->next_packet) { 1714 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 1715 } else { 1716 len += ((packet_hdr.next_packet - sc->rec_page_start) + 1717 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 1718 } 1719 } 1720 /* 1721 * Be fairly liberal about what we allow as a "reasonable" length 1722 * so that a [crufty] packet will make it to BPF (and can thus 1723 * be analyzed). Note that all that is really important is that 1724 * we have a length that will fit into one mbuf cluster or less; 1725 * the upper layer protocols can then figure out the length from 1726 * their own length field(s). 1727 */ 1728 if ((len <= MCLBYTES) && 1729 (packet_hdr.next_packet >= sc->rec_page_start) && 1730 (packet_hdr.next_packet < sc->rec_page_stop)) { 1731 /* 1732 * Go get packet. 1733 */ 1734 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 1735 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 1736 ++sc->arpcom.ac_if.if_ipackets; 1737 } else { 1738 /* 1739 * Really BAD. The ring pointers are corrupted. 1740 */ 1741 log(LOG_ERR, 1742 "ed%d: NIC memory corrupt - invalid packet length %d\n", 1743 unit, len); 1744 ++sc->arpcom.ac_if.if_ierrors; 1745 ed_reset(unit); 1746 return; 1747 } 1748 1749 /* 1750 * Update next packet pointer 1751 */ 1752 sc->next_packet = packet_hdr.next_packet; 1753 1754 /* 1755 * Update NIC boundry pointer - being careful to keep it one 1756 * buffer behind. (as recommended by NS databook) 1757 */ 1758 boundry = sc->next_packet - 1; 1759 if (boundry < sc->rec_page_start) 1760 boundry = sc->rec_page_stop - 1; 1761 1762 /* 1763 * Set NIC to page 0 registers to update boundry register 1764 */ 1765 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1766 1767 outb(sc->nic_addr + ED_P0_BNRY, boundry); 1768 1769 /* 1770 * Set NIC to page 1 registers before looping to top (prepare 1771 * to get 'CURR' current pointer) 1772 */ 1773 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 1774 } 1775} 1776 1777/* 1778 * Ethernet interface interrupt processor 1779 */ 1780void 1781edintr(unit) 1782 int unit; 1783{ 1784 struct ed_softc *sc = &ed_softc[unit]; 1785 u_char isr; 1786 1787 /* 1788 * Set NIC to page 0 registers 1789 */ 1790 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1791 1792 /* 1793 * loop until there are no more new interrupts 1794 */ 1795 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 1796 1797 /* 1798 * reset all the bits that we are 'acknowledging' by writing a 1799 * '1' to each bit position that was set (writing a '1' 1800 * *clears* the bit) 1801 */ 1802 outb(sc->nic_addr + ED_P0_ISR, isr); 1803 1804 /* 1805 * Handle transmitter interrupts. Handle these first because 1806 * the receiver will reset the board under some conditions. 1807 */ 1808 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 1809 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 1810 1811 /* 1812 * Check for transmit error. If a TX completed with an 1813 * error, we end up throwing the packet away. Really 1814 * the only error that is possible is excessive 1815 * collisions, and in this case it is best to allow 1816 * the automatic mechanisms of TCP to backoff the 1817 * flow. Of course, with UDP we're screwed, but this 1818 * is expected when a network is heavily loaded. 1819 */ 1820 (void) inb(sc->nic_addr + ED_P0_TSR); 1821 if (isr & ED_ISR_TXE) { 1822 1823 /* 1824 * Excessive collisions (16) 1825 */ 1826 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT) 1827 && (collisions == 0)) { 1828 1829 /* 1830 * When collisions total 16, the 1831 * P0_NCR will indicate 0, and the 1832 * TSR_ABT is set. 1833 */ 1834 collisions = 16; 1835 } 1836 1837 /* 1838 * update output errors counter 1839 */ 1840 ++sc->arpcom.ac_if.if_oerrors; 1841 } else { 1842 1843 /* 1844 * Update total number of successfully 1845 * transmitted packets. 1846 */ 1847 ++sc->arpcom.ac_if.if_opackets; 1848 } 1849 1850 /* 1851 * reset tx busy and output active flags 1852 */ 1853 sc->xmit_busy = 0; 1854 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1855 1856 /* 1857 * clear watchdog timer 1858 */ 1859 sc->arpcom.ac_if.if_timer = 0; 1860 1861 /* 1862 * Add in total number of collisions on last 1863 * transmission. 1864 */ 1865 sc->arpcom.ac_if.if_collisions += collisions; 1866 1867 /* 1868 * Decrement buffer in-use count if not zero (can only 1869 * be zero if a transmitter interrupt occured while 1870 * not actually transmitting). If data is ready to 1871 * transmit, start it transmitting, otherwise defer 1872 * until after handling receiver 1873 */ 1874 if (sc->txb_inuse && --sc->txb_inuse) 1875 ed_xmit(&sc->arpcom.ac_if); 1876 } 1877 1878 /* 1879 * Handle receiver interrupts 1880 */ 1881 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 1882 1883 /* 1884 * Overwrite warning. In order to make sure that a 1885 * lockup of the local DMA hasn't occurred, we reset 1886 * and re-init the NIC. The NSC manual suggests only a 1887 * partial reset/re-init is necessary - but some chips 1888 * seem to want more. The DMA lockup has been seen 1889 * only with early rev chips - Methinks this bug was 1890 * fixed in later revs. -DG 1891 */ 1892 if (isr & ED_ISR_OVW) { 1893 ++sc->arpcom.ac_if.if_ierrors; 1894#ifdef DIAGNOSTIC 1895 log(LOG_WARNING, 1896 "ed%d: warning - receiver ring buffer overrun\n", 1897 unit); 1898#endif 1899 1900 /* 1901 * Stop/reset/re-init NIC 1902 */ 1903 ed_reset(unit); 1904 } else { 1905 1906 /* 1907 * Receiver Error. One or more of: CRC error, 1908 * frame alignment error FIFO overrun, or 1909 * missed packet. 1910 */ 1911 if (isr & ED_ISR_RXE) { 1912 ++sc->arpcom.ac_if.if_ierrors; 1913#ifdef ED_DEBUG 1914 printf("ed%d: receive error %x\n", unit, 1915 inb(sc->nic_addr + ED_P0_RSR)); 1916#endif 1917 } 1918 1919 /* 1920 * Go get the packet(s) XXX - Doing this on an 1921 * error is dubious because there shouldn't be 1922 * any data to get (we've configured the 1923 * interface to not accept packets with 1924 * errors). 1925 */ 1926 1927 /* 1928 * Enable 16bit access to shared memory first 1929 * on WD/SMC boards. 1930 */ 1931 if (sc->isa16bit && 1932 (sc->vendor == ED_VENDOR_WD_SMC)) { 1933 1934 outb(sc->asic_addr + ED_WD_LAAR, 1935 (sc->wd_laar_proto |= 1936 ED_WD_LAAR_M16EN)); 1937 if (sc->is790) { 1938 outb(sc->asic_addr + ED_WD_MSR, 1939 ED_WD_MSR_MENB); 1940 } 1941 } 1942 ed_rint(unit); 1943 1944 /* disable 16bit access */ 1945 if (sc->isa16bit && 1946 (sc->vendor == ED_VENDOR_WD_SMC)) { 1947 1948 if (sc->is790) { 1949 outb(sc->asic_addr + ED_WD_MSR, 0x00); 1950 } 1951 outb(sc->asic_addr + ED_WD_LAAR, 1952 (sc->wd_laar_proto &= 1953 ~ED_WD_LAAR_M16EN)); 1954 } 1955 } 1956 } 1957 1958 /* 1959 * If it looks like the transmitter can take more data, 1960 * attempt to start output on the interface. This is done 1961 * after handling the receiver to give the receiver priority. 1962 */ 1963 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0) 1964 ed_start(&sc->arpcom.ac_if); 1965 1966 /* 1967 * return NIC CR to standard state: page 0, remote DMA 1968 * complete, start (toggling the TXP bit off, even if was just 1969 * set in the transmit routine, is *okay* - it is 'edge' 1970 * triggered from low to high) 1971 */ 1972 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1973 1974 /* 1975 * If the Network Talley Counters overflow, read them to reset 1976 * them. It appears that old 8390's won't clear the ISR flag 1977 * otherwise - resulting in an infinite loop. 1978 */ 1979 if (isr & ED_ISR_CNT) { 1980 (void) inb(sc->nic_addr + ED_P0_CNTR0); 1981 (void) inb(sc->nic_addr + ED_P0_CNTR1); 1982 (void) inb(sc->nic_addr + ED_P0_CNTR2); 1983 } 1984 } 1985} 1986 1987/* 1988 * Process an ioctl request. This code needs some work - it looks 1989 * pretty ugly. 1990 */ 1991int 1992ed_ioctl(ifp, command, data) 1993 register struct ifnet *ifp; 1994 int command; 1995 caddr_t data; 1996{ 1997 register struct ifaddr *ifa = (struct ifaddr *) data; 1998 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1999 struct ifreq *ifr = (struct ifreq *) data; 2000 int s, error = 0; 2001 2002 s = splimp(); 2003 2004 switch (command) { 2005 2006 case SIOCSIFADDR: 2007 ifp->if_flags |= IFF_UP; 2008 /* netifs are BUSY when UP */ 2009 sc->kdc.kdc_state = DC_BUSY; 2010 2011 switch (ifa->ifa_addr->sa_family) { 2012#ifdef INET 2013 case AF_INET: 2014 ed_init(ifp->if_unit); /* before arpwhohas */ 2015 arp_ifinit((struct arpcom *)ifp, ifa); 2016 break; 2017#endif 2018#ifdef NS 2019 2020 /* 2021 * XXX - This code is probably wrong 2022 */ 2023 case AF_NS: 2024 { 2025 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr); 2026 2027 if (ns_nullhost(*ina)) 2028 ina->x_host = 2029 *(union ns_host *) (sc->arpcom.ac_enaddr); 2030 else { 2031 bcopy((caddr_t) ina->x_host.c_host, 2032 (caddr_t) sc->arpcom.ac_enaddr, 2033 sizeof(sc->arpcom.ac_enaddr)); 2034 } 2035 2036 /* 2037 * Set new address 2038 */ 2039 ed_init(ifp->if_unit); 2040 break; 2041 } 2042#endif 2043 default: 2044 ed_init(ifp->if_unit); 2045 break; 2046 } 2047 break; 2048 2049 case SIOCGIFADDR: 2050 { 2051 struct sockaddr *sa; 2052 2053 sa = (struct sockaddr *) & ifr->ifr_data; 2054 bcopy((caddr_t) sc->arpcom.ac_enaddr, 2055 (caddr_t) sa->sa_data, ETHER_ADDR_LEN); 2056 } 2057 break; 2058 2059 case SIOCSIFFLAGS: 2060 2061 /* 2062 * If interface is marked down and it is running, then stop it 2063 */ 2064 if (((ifp->if_flags & IFF_UP) == 0) && 2065 (ifp->if_flags & IFF_RUNNING)) { 2066 ed_stop(ifp->if_unit); 2067 ifp->if_flags &= ~IFF_RUNNING; 2068 } else { 2069 2070 /* 2071 * If interface is marked up and it is stopped, then 2072 * start it 2073 */ 2074 if ((ifp->if_flags & IFF_UP) && 2075 ((ifp->if_flags & IFF_RUNNING) == 0)) 2076 ed_init(ifp->if_unit); 2077 } 2078 /* UP controls BUSY/IDLE */ 2079 sc->kdc.kdc_state = ((ifp->if_flags & IFF_UP) 2080 ? DC_BUSY 2081 : DC_IDLE); 2082 2083#if NBPFILTER > 0 2084 2085 /* 2086 * Promiscuous flag may have changed, so reprogram the RCR. 2087 */ 2088 ed_setrcr(ifp, sc); 2089#endif 2090 2091 /* 2092 * An unfortunate hack to provide the (required) software 2093 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2094 * disables the tranceiver if set. 2095 */ 2096 if (sc->vendor == ED_VENDOR_3COM) { 2097 if (ifp->if_flags & IFF_ALTPHYS) { 2098 outb(sc->asic_addr + ED_3COM_CR, 0); 2099 } else { 2100 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2101 } 2102 } 2103 break; 2104 2105 case SIOCADDMULTI: 2106 case SIOCDELMULTI: 2107 /* 2108 * Update out multicast list. 2109 */ 2110 error = (command == SIOCADDMULTI) ? 2111 ether_addmulti(ifr, &sc->arpcom) : 2112 ether_delmulti(ifr, &sc->arpcom); 2113 2114 if (error == ENETRESET) { 2115 2116 /* 2117 * Multicast list has changed; set the hardware filter 2118 * accordingly. 2119 */ 2120 ed_setrcr(ifp, sc); 2121 error = 0; 2122 } 2123 break; 2124 2125 case SIOCSIFMTU: 2126 /* 2127 * Set the interface MTU. 2128 */ 2129 if (ifr->ifr_mtu > ETHERMTU) { 2130 error = EINVAL; 2131 } else { 2132 ifp->if_mtu = ifr->ifr_mtu; 2133 } 2134 break; 2135 2136 default: 2137 error = EINVAL; 2138 } 2139 (void) splx(s); 2140 return (error); 2141} 2142 2143/* 2144 * Retreive packet from shared memory and send to the next level up via 2145 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2146 */ 2147static void 2148ed_get_packet(sc, buf, len, multicast) 2149 struct ed_softc *sc; 2150 char *buf; 2151 u_short len; 2152 int multicast; 2153{ 2154 struct ether_header *eh; 2155 struct mbuf *m; 2156 2157 /* Allocate a header mbuf */ 2158 MGETHDR(m, M_DONTWAIT, MT_DATA); 2159 if (m == NULL) 2160 return; 2161 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2162 m->m_pkthdr.len = m->m_len = len; 2163 2164 /* Attach an mbuf cluster */ 2165 MCLGET(m, M_DONTWAIT); 2166 2167 /* Insist on getting a cluster */ 2168 if ((m->m_flags & M_EXT) == 0) { 2169 m_freem(m); 2170 return; 2171 } 2172 2173 /* 2174 * The +2 is to longword align the start of the real packet. 2175 * This is important for NFS. 2176 */ 2177 m->m_data += 2; 2178 eh = mtod(m, struct ether_header *); 2179 2180 /* 2181 * Get packet, including link layer address, from interface. 2182 */ 2183 ed_ring_copy(sc, buf, (char *)eh, len); 2184 2185#if NBPFILTER > 0 2186 2187 /* 2188 * Check if there's a BPF listener on this interface. If so, hand off 2189 * the raw packet to bpf. 2190 */ 2191 if (sc->bpf) { 2192 bpf_mtap(sc->bpf, m); 2193 2194 /* 2195 * Note that the interface cannot be in promiscuous mode if 2196 * there are no BPF listeners. And if we are in promiscuous 2197 * mode, we have to check if this packet is really ours. 2198 */ 2199 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2200 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2201 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2202 m_freem(m); 2203 return; 2204 } 2205 } 2206#endif 2207 2208 /* 2209 * Remove link layer address. 2210 */ 2211 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2212 m->m_data += sizeof(struct ether_header); 2213 2214 ether_input(&sc->arpcom.ac_if, eh, m); 2215 return; 2216} 2217 2218/* 2219 * Supporting routines 2220 */ 2221 2222/* 2223 * Given a NIC memory source address and a host memory destination 2224 * address, copy 'amount' from NIC to host using Programmed I/O. 2225 * The 'amount' is rounded up to a word - okay as long as mbufs 2226 * are word sized. 2227 * This routine is currently Novell-specific. 2228 */ 2229void 2230ed_pio_readmem(sc, src, dst, amount) 2231 struct ed_softc *sc; 2232 unsigned short src; 2233 unsigned char *dst; 2234 unsigned short amount; 2235{ 2236 /* select page 0 registers */ 2237 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2238 2239 /* round up to a word */ 2240 if (amount & 1) 2241 ++amount; 2242 2243 /* set up DMA byte count */ 2244 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2245 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2246 2247 /* set up source address in NIC mem */ 2248 outb(sc->nic_addr + ED_P0_RSAR0, src); 2249 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2250 2251 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2252 2253 if (sc->isa16bit) { 2254 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2255 } else 2256 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2257 2258} 2259 2260/* 2261 * Stripped down routine for writing a linear buffer to NIC memory. 2262 * Only used in the probe routine to test the memory. 'len' must 2263 * be even. 2264 */ 2265void 2266ed_pio_writemem(sc, src, dst, len) 2267 struct ed_softc *sc; 2268 char *src; 2269 unsigned short dst; 2270 unsigned short len; 2271{ 2272 int maxwait = 100; /* about 120us */ 2273 2274 /* select page 0 registers */ 2275 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2276 2277 /* reset remote DMA complete flag */ 2278 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2279 2280 /* set up DMA byte count */ 2281 outb(sc->nic_addr + ED_P0_RBCR0, len); 2282 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2283 2284 /* set up destination address in NIC mem */ 2285 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2286 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2287 2288 /* set remote DMA write */ 2289 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2290 2291 if (sc->isa16bit) 2292 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2293 else 2294 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2295 2296 /* 2297 * Wait for remote DMA complete. This is necessary because on the 2298 * transmit side, data is handled internally by the NIC in bursts and 2299 * we can't start another remote DMA until this one completes. Not 2300 * waiting causes really bad things to happen - like the NIC 2301 * irrecoverably jamming the ISA bus. 2302 */ 2303 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2304} 2305 2306/* 2307 * Write an mbuf chain to the destination NIC memory address using 2308 * programmed I/O. 2309 */ 2310u_short 2311ed_pio_write_mbufs(sc, m, dst) 2312 struct ed_softc *sc; 2313 struct mbuf *m; 2314 unsigned short dst; 2315{ 2316 unsigned short total_len, dma_len; 2317 struct mbuf *mp; 2318 int maxwait = 100; /* about 120us */ 2319 2320 /* First, count up the total number of bytes to copy */ 2321 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2322 total_len += mp->m_len; 2323 2324 dma_len = total_len; 2325 if (sc->isa16bit && (dma_len & 1)) 2326 dma_len++; 2327 2328 /* select page 0 registers */ 2329 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2330 2331 /* reset remote DMA complete flag */ 2332 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2333 2334 /* set up DMA byte count */ 2335 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 2336 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 2337 2338 /* set up destination address in NIC mem */ 2339 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2340 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2341 2342 /* set remote DMA write */ 2343 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2344 2345 /* 2346 * Transfer the mbuf chain to the NIC memory. 2347 * 16-bit cards require that data be transferred as words, and only words. 2348 * So that case requires some extra code to patch over odd-length mbufs. 2349 */ 2350 2351 if (!sc->isa16bit) { 2352 /* NE1000s are easy */ 2353 while (m) { 2354 if (m->m_len) { 2355 outsb(sc->asic_addr + ED_NOVELL_DATA, 2356 m->m_data, m->m_len); 2357 } 2358 m = m->m_next; 2359 } 2360 } else { 2361 /* NE2000s are a pain */ 2362 unsigned char *data; 2363 int len, wantbyte; 2364 unsigned char savebyte[2]; 2365 2366 wantbyte = 0; 2367 2368 while (m) { 2369 len = m->m_len; 2370 if (len) { 2371 data = mtod(m, caddr_t); 2372 /* finish the last word */ 2373 if (wantbyte) { 2374 savebyte[1] = *data; 2375 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2376 data++; 2377 len--; 2378 wantbyte = 0; 2379 } 2380 /* output contiguous words */ 2381 if (len > 1) { 2382 outsw(sc->asic_addr + ED_NOVELL_DATA, 2383 data, len >> 1); 2384 data += len & ~1; 2385 len &= 1; 2386 } 2387 /* save last byte, if necessary */ 2388 if (len == 1) { 2389 savebyte[0] = *data; 2390 wantbyte = 1; 2391 } 2392 } 2393 m = m->m_next; 2394 } 2395 /* spit last byte */ 2396 if (wantbyte) { 2397 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2398 } 2399 } 2400 2401 /* 2402 * Wait for remote DMA complete. This is necessary because on the 2403 * transmit side, data is handled internally by the NIC in bursts and 2404 * we can't start another remote DMA until this one completes. Not 2405 * waiting causes really bad things to happen - like the NIC 2406 * irrecoverably jamming the ISA bus. 2407 */ 2408 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2409 2410 if (!maxwait) { 2411 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 2412 sc->arpcom.ac_if.if_unit); 2413 ed_reset(sc->arpcom.ac_if.if_unit); 2414 return(0); 2415 } 2416 return (total_len); 2417} 2418 2419/* 2420 * Given a source and destination address, copy 'amount' of a packet from 2421 * the ring buffer into a linear destination buffer. Takes into account 2422 * ring-wrap. 2423 */ 2424static inline char * 2425ed_ring_copy(sc, src, dst, amount) 2426 struct ed_softc *sc; 2427 char *src; 2428 char *dst; 2429 u_short amount; 2430{ 2431 u_short tmp_amount; 2432 2433 /* does copy wrap to lower addr in ring buffer? */ 2434 if (src + amount > sc->mem_end) { 2435 tmp_amount = sc->mem_end - src; 2436 2437 /* copy amount up to end of NIC memory */ 2438 if (sc->mem_shared) 2439 bcopy(src, dst, tmp_amount); 2440 else 2441 ed_pio_readmem(sc, src, dst, tmp_amount); 2442 2443 amount -= tmp_amount; 2444 src = sc->mem_ring; 2445 dst += tmp_amount; 2446 } 2447 if (sc->mem_shared) 2448 bcopy(src, dst, amount); 2449 else 2450 ed_pio_readmem(sc, src, dst, amount); 2451 2452 return (src + amount); 2453} 2454 2455void 2456ed_setrcr(ifp, sc) 2457 struct ifnet *ifp; 2458 struct ed_softc *sc; 2459{ 2460 int i; 2461 2462 /* set page 1 registers */ 2463 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 2464 2465 if (ifp->if_flags & IFF_PROMISC) { 2466 2467 /* 2468 * Reconfigure the multicast filter. 2469 */ 2470 for (i = 0; i < 8; i++) 2471 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff); 2472 2473 /* 2474 * And turn on promiscuous mode. Also enable reception of 2475 * runts and packets with CRC & alignment errors. 2476 */ 2477 /* Set page 0 registers */ 2478 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2479 2480 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 2481 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 2482 } else { 2483 /* set up multicast addresses and filter modes */ 2484 if (ifp->if_flags & IFF_MULTICAST) { 2485 u_long mcaf[2]; 2486 2487 if (ifp->if_flags & IFF_ALLMULTI) { 2488 mcaf[0] = 0xffffffff; 2489 mcaf[1] = 0xffffffff; 2490 } else 2491 ds_getmcaf(sc, mcaf); 2492 2493 /* 2494 * Set multicast filter on chip. 2495 */ 2496 for (i = 0; i < 8; i++) 2497 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]); 2498 2499 /* Set page 0 registers */ 2500 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2501 2502 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 2503 } else { 2504 2505 /* 2506 * Initialize multicast address hashing registers to 2507 * not accept multicasts. 2508 */ 2509 for (i = 0; i < 8; ++i) 2510 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00); 2511 2512 /* Set page 0 registers */ 2513 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2514 2515 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 2516 } 2517 } 2518 2519 /* 2520 * Start interface. 2521 */ 2522 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2523} 2524 2525/* 2526 * Compute crc for ethernet address 2527 */ 2528u_long 2529ds_crc(ep) 2530 u_char *ep; 2531{ 2532#define POLYNOMIAL 0x04c11db6 2533 register u_long crc = 0xffffffffL; 2534 register int carry, i, j; 2535 register u_char b; 2536 2537 for (i = 6; --i >= 0;) { 2538 b = *ep++; 2539 for (j = 8; --j >= 0;) { 2540 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 2541 crc <<= 1; 2542 b >>= 1; 2543 if (carry) 2544 crc = ((crc ^ POLYNOMIAL) | carry); 2545 } 2546 } 2547 return crc; 2548#undef POLYNOMIAL 2549} 2550 2551/* 2552 * Compute the multicast address filter from the 2553 * list of multicast addresses we need to listen to. 2554 */ 2555void 2556ds_getmcaf(sc, mcaf) 2557 struct ed_softc *sc; 2558 u_long *mcaf; 2559{ 2560 register u_int index; 2561 register u_char *af = (u_char *) mcaf; 2562 register struct ether_multi *enm; 2563 register struct ether_multistep step; 2564 2565 mcaf[0] = 0; 2566 mcaf[1] = 0; 2567 2568 ETHER_FIRST_MULTI(step, &sc->arpcom, enm); 2569 while (enm != NULL) { 2570 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2571 mcaf[0] = 0xffffffff; 2572 mcaf[1] = 0xffffffff; 2573 return; 2574 } 2575 index = ds_crc(enm->enm_addrlo, 6) >> 26; 2576 af[index >> 3] |= 1 << (index & 7); 2577 2578 ETHER_NEXT_MULTI(step, enm); 2579 } 2580} 2581