if_ed.c revision 5333
1/* 2 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 3 * adapters. By David Greenman, 29-April-1993 4 * 5 * Copyright (C) 1993, David Greenman. This software may be used, modified, 6 * copied, distributed, and sold, in both source and binary form provided 7 * that the above copyright and these terms are retained. Under no 8 * circumstances is the author responsible for the proper functioning 9 * of this software, nor does the author assume any responsibility 10 * for damages incurred with its use. 11 * 12 * Currently supports the Western Digital/SMC 8003 and 8013 series, 13 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 14 * and a variety of similar clones. 15 * 16 * $Id: if_ed.c,v 1.61 1995/01/01 03:54:34 davidg Exp $ 17 */ 18 19#include "ed.h" 20#include "bpfilter.h" 21 22#include <sys/param.h> 23#include <sys/systm.h> 24#include <sys/errno.h> 25#include <sys/ioctl.h> 26#include <sys/mbuf.h> 27#include <sys/socket.h> 28#include <sys/syslog.h> 29#include <sys/devconf.h> 30 31#include <net/if.h> 32#include <net/if_dl.h> 33#include <net/if_types.h> 34 35#ifdef INET 36#include <netinet/in.h> 37#include <netinet/in_systm.h> 38#include <netinet/in_var.h> 39#include <netinet/ip.h> 40#include <netinet/if_ether.h> 41#endif 42 43#ifdef NS 44#include <netns/ns.h> 45#include <netns/ns_if.h> 46#endif 47 48#if NBPFILTER > 0 49#include <net/bpf.h> 50#include <net/bpfdesc.h> 51#endif 52 53#include <i386/isa/isa.h> 54#include <i386/isa/isa_device.h> 55#include <i386/isa/icu.h> 56#include <i386/isa/if_edreg.h> 57 58/* For backwards compatibility */ 59#ifndef IFF_ALTPHYS 60#define IFF_ALTPHYS IFF_LINK0 61#endif 62 63/* 64 * ed_softc: per line info and status 65 */ 66struct ed_softc { 67 struct arpcom arpcom; /* ethernet common */ 68 69 char *type_str; /* pointer to type string */ 70 u_char vendor; /* interface vendor */ 71 u_char type; /* interface type code */ 72 73 u_short asic_addr; /* ASIC I/O bus address */ 74 u_short nic_addr; /* NIC (DS8390) I/O bus address */ 75 76/* 77 * The following 'proto' variable is part of a work-around for 8013EBT asics 78 * being write-only. It's sort of a prototype/shadow of the real thing. 79 */ 80 u_char wd_laar_proto; 81 u_char cr_proto; 82 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 83 int is790; /* set by the probe code if the card is 790 84 * based */ 85 86 caddr_t bpf; /* BPF "magic cookie" */ 87 caddr_t mem_start; /* NIC memory start address */ 88 caddr_t mem_end; /* NIC memory end address */ 89 u_long mem_size; /* total NIC memory size */ 90 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 91 92 u_char mem_shared; /* NIC memory is shared with host */ 93 u_char xmit_busy; /* transmitter is busy */ 94 u_char txb_cnt; /* number of transmit buffers */ 95 u_char txb_inuse; /* number of TX buffers currently in-use */ 96 97 u_char txb_new; /* pointer to where new buffer will be added */ 98 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 99 u_short txb_len[8]; /* buffered xmit buffer lengths */ 100 u_char tx_page_start; /* first page of TX buffer area */ 101 u_char rec_page_start; /* first page of RX ring-buffer */ 102 u_char rec_page_stop; /* last page of RX ring-buffer */ 103 u_char next_packet; /* pointer to next unread RX packet */ 104} ed_softc[NED]; 105 106int ed_attach(struct isa_device *); 107void ed_init(int); 108void edintr(int); 109int ed_ioctl(struct ifnet *, int, caddr_t); 110int ed_probe(struct isa_device *); 111void ed_start(struct ifnet *); 112void ed_reset(int); 113void ed_watchdog(int); 114int ed_probe_generic8390(struct ed_softc *); 115int ed_probe_WD80x3(struct isa_device *); 116int ed_probe_3Com(struct isa_device *); 117int ed_probe_Novell(struct isa_device *); 118 119void ds_getmcaf(); 120 121static void ed_get_packet(struct ed_softc *, char *, int /* u_short */ , int); 122static void ed_stop(int); 123 124static inline void ed_rint(); 125static inline void ed_xmit(); 126static inline char *ed_ring_copy(); 127 128void ed_pio_readmem(), ed_pio_writemem(); 129u_short ed_pio_write_mbufs(); 130 131void ed_setrcr(struct ifnet *, struct ed_softc *); 132 133struct isa_driver eddriver = { 134 ed_probe, 135 ed_attach, 136 "ed", 137 1 /* We are ultra sensitive */ 138}; 139 140/* 141 * Interrupt conversion table for WD/SMC ASIC/83C584 142 * (IRQ* are defined in icu.h) 143 */ 144static unsigned short ed_intr_mask[] = { 145 IRQ9, 146 IRQ3, 147 IRQ5, 148 IRQ7, 149 IRQ10, 150 IRQ11, 151 IRQ15, 152 IRQ4 153}; 154 155/* 156 * Interrupt conversion table for 83C790 157 */ 158static unsigned short ed_790_intr_mask[] = { 159 0, 160 IRQ9, 161 IRQ3, 162 IRQ5, 163 IRQ7, 164 IRQ10, 165 IRQ11, 166 IRQ15 167}; 168 169#define ETHER_MIN_LEN 64 170#define ETHER_MAX_LEN 1518 171#define ETHER_ADDR_LEN 6 172#define ETHER_HDR_SIZE 14 173 174static struct kern_devconf kdc_ed[NED] = { { 175 0, 0, 0, /* filled in by dev_attach */ 176 "ed", 0, { MDDT_ISA, 0, "net" }, 177 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 178 &kdc_isa0, /* parent */ 179 0, /* parentdata */ 180 DC_BUSY, /* network interfaces are always ``open'' */ 181 "" /* description */ 182} }; 183 184static inline void 185ed_registerdev(struct isa_device *id, const char *descr) 186{ 187 if(id->id_unit) 188 kdc_ed[id->id_unit] = kdc_ed[0]; 189 kdc_ed[id->id_unit].kdc_unit = id->id_unit; 190 kdc_ed[id->id_unit].kdc_parentdata = id; 191 kdc_ed[id->id_unit].kdc_description = descr; 192 dev_attach(&kdc_ed[id->id_unit]); 193} 194 195/* 196 * Determine if the device is present 197 * 198 * on entry: 199 * a pointer to an isa_device struct 200 * on exit: 201 * NULL if device not found 202 * or # of i/o addresses used (if found) 203 */ 204int 205ed_probe(isa_dev) 206 struct isa_device *isa_dev; 207{ 208 int nports; 209 210 nports = ed_probe_WD80x3(isa_dev); 211 if (nports) 212 return (nports); 213 214 nports = ed_probe_3Com(isa_dev); 215 if (nports) 216 return (nports); 217 218 nports = ed_probe_Novell(isa_dev); 219 if (nports) 220 return (nports); 221 222 return (0); 223} 224 225/* 226 * Generic probe routine for testing for the existance of a DS8390. 227 * Must be called after the NIC has just been reset. This routine 228 * works by looking at certain register values that are gauranteed 229 * to be initialized a certain way after power-up or reset. Seems 230 * not to currently work on the 83C690. 231 * 232 * Specifically: 233 * 234 * Register reset bits set bits 235 * Command Register (CR) TXP, STA RD2, STP 236 * Interrupt Status (ISR) RST 237 * Interrupt Mask (IMR) All bits 238 * Data Control (DCR) LAS 239 * Transmit Config. (TCR) LB1, LB0 240 * 241 * We only look at the CR and ISR registers, however, because looking at 242 * the others would require changing register pages (which would be 243 * intrusive if this isn't an 8390). 244 * 245 * Return 1 if 8390 was found, 0 if not. 246 */ 247 248int 249ed_probe_generic8390(sc) 250 struct ed_softc *sc; 251{ 252 if ((inb(sc->nic_addr + ED_P0_CR) & 253 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 254 (ED_CR_RD2 | ED_CR_STP)) 255 return (0); 256 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 257 return (0); 258 259 return (1); 260} 261 262/* 263 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 264 */ 265int 266ed_probe_WD80x3(isa_dev) 267 struct isa_device *isa_dev; 268{ 269 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 270 int i; 271 u_int memsize; 272 u_char iptr, isa16bit, sum; 273 274 sc->asic_addr = isa_dev->id_iobase; 275 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 276 sc->is790 = 0; 277 278#ifdef TOSH_ETHER 279 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 280 DELAY(10000); 281#endif 282 283 /* 284 * Attempt to do a checksum over the station address PROM. If it 285 * fails, it's probably not a SMC/WD board. There is a problem with 286 * this, though: some clone WD boards don't pass the checksum test. 287 * Danpex boards for one. 288 */ 289 for (sum = 0, i = 0; i < 8; ++i) 290 sum += inb(sc->asic_addr + ED_WD_PROM + i); 291 292 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 293 294 /* 295 * Checksum is invalid. This often happens with cheap WD8003E 296 * clones. In this case, the checksum byte (the eighth byte) 297 * seems to always be zero. 298 */ 299 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 300 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 301 return (0); 302 } 303 /* reset card to force it into a known state. */ 304#ifdef TOSH_ETHER 305 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 306#else 307 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 308#endif 309 DELAY(100); 310 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 311 /* wait in the case this card is reading it's EEROM */ 312 DELAY(5000); 313 314 sc->vendor = ED_VENDOR_WD_SMC; 315 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 316 317 /* 318 * Set initial values for width/size. 319 */ 320 memsize = 8192; 321 isa16bit = 0; 322 switch (sc->type) { 323 case ED_TYPE_WD8003S: 324 sc->type_str = "WD8003S"; 325 break; 326 case ED_TYPE_WD8003E: 327 sc->type_str = "WD8003E"; 328 break; 329 case ED_TYPE_WD8003EB: 330 sc->type_str = "WD8003EB"; 331 break; 332 case ED_TYPE_WD8003W: 333 sc->type_str = "WD8003W"; 334 break; 335 case ED_TYPE_WD8013EBT: 336 sc->type_str = "WD8013EBT"; 337 memsize = 16384; 338 isa16bit = 1; 339 break; 340 case ED_TYPE_WD8013W: 341 sc->type_str = "WD8013W"; 342 memsize = 16384; 343 isa16bit = 1; 344 break; 345 case ED_TYPE_WD8013EP: /* also WD8003EP */ 346 if (inb(sc->asic_addr + ED_WD_ICR) 347 & ED_WD_ICR_16BIT) { 348 isa16bit = 1; 349 memsize = 16384; 350 sc->type_str = "WD8013EP"; 351 } else { 352 sc->type_str = "WD8003EP"; 353 } 354 break; 355 case ED_TYPE_WD8013WC: 356 sc->type_str = "WD8013WC"; 357 memsize = 16384; 358 isa16bit = 1; 359 break; 360 case ED_TYPE_WD8013EBP: 361 sc->type_str = "WD8013EBP"; 362 memsize = 16384; 363 isa16bit = 1; 364 break; 365 case ED_TYPE_WD8013EPC: 366 sc->type_str = "WD8013EPC"; 367 memsize = 16384; 368 isa16bit = 1; 369 break; 370 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 371 (unsigned int) *(isa_dev->id_maddr+8192) = (unsigned int)0; 372 if ((unsigned int) *(isa_dev->id_maddr+8192)) { 373 sc->type_str = "SMC8416C/SMC8416BT"; 374 memsize = 8192; 375 } else { 376 sc->type_str = "SMC8216/SMC8216C"; 377 memsize = 16384; 378 } 379 isa16bit = 1; 380 sc->is790 = 1; 381 break; 382 case ED_TYPE_SMC8216T: 383 (unsigned int) *(isa_dev->id_maddr+8192) = (unsigned int)0; 384 if ((unsigned int) *(isa_dev->id_maddr+8192)) { 385 sc->type_str = "SMC8416T"; 386 memsize = 8192; 387 } else { 388 sc->type_str = "SMC8216T"; 389 memsize = 16384; 390 } 391 isa16bit = 1; 392 sc->is790 = 1; 393 break; 394#ifdef TOSH_ETHER 395 case ED_TYPE_TOSHIBA1: 396 sc->type_str = "Toshiba1"; 397 memsize = 32768; 398 isa16bit = 1; 399 break; 400 case ED_TYPE_TOSHIBA4: 401 sc->type_str = "Toshiba4"; 402 memsize = 32768; 403 isa16bit = 1; 404 break; 405#endif 406 default: 407 sc->type_str = ""; 408 break; 409 } 410 411 /* 412 * Make some adjustments to initial values depending on what is found 413 * in the ICR. 414 */ 415 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 416#ifdef TOSH_ETHER 417 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 418#endif 419 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 420 isa16bit = 0; 421 memsize = 8192; 422 } 423#if ED_DEBUG 424 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 425 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize); 426 for (i = 0; i < 8; i++) 427 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 428#endif 429 430 /* 431 * Allow the user to override the autoconfiguration 432 */ 433 if (isa_dev->id_msize) 434 memsize = isa_dev->id_msize; 435 436 /* 437 * (note that if the user specifies both of the following flags that 438 * '8bit' mode intentionally has precedence) 439 */ 440 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE) 441 isa16bit = 1; 442 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE) 443 isa16bit = 0; 444 445 /* 446 * If possible, get the assigned interrupt number from the card and 447 * use it. 448 */ 449 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 450 451 /* 452 * Assemble together the encoded interrupt number. 453 */ 454 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 455 ((inb(isa_dev->id_iobase + ED_WD_IRR) & 456 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 457 458 /* 459 * Use what the board tells us. 460 */ 461 isa_dev->id_irq = ed_intr_mask[iptr]; 462 463 /* 464 * Enable the interrupt. 465 */ 466 outb(isa_dev->id_iobase + ED_WD_IRR, 467 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 468 } 469 if (sc->is790) { 470 outb(isa_dev->id_iobase + ED_WD790_HWR, 471 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); 472 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 473 (inb(isa_dev->id_iobase + ED_WD790_GCR) & 474 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 475 outb(isa_dev->id_iobase + ED_WD790_HWR, 476 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 477 478 /* 479 * Use what the board tells us. 480 */ 481 isa_dev->id_irq = ed_790_intr_mask[iptr]; 482 483 /* 484 * Enable interrupts. 485 */ 486 outb(isa_dev->id_iobase + ED_WD790_ICR, 487 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL); 488 } 489 if (isa_dev->id_irq <= 0) { 490 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n", 491 isa_dev->id_unit, sc->type_str); 492 return (0); 493 } 494 sc->isa16bit = isa16bit; 495 sc->mem_shared = 1; 496 isa_dev->id_msize = memsize; 497 sc->mem_start = (caddr_t) isa_dev->id_maddr; 498 499 /* 500 * allocate one xmit buffer if < 16k, two buffers otherwise 501 */ 502 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 503 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 504 sc->txb_cnt = 1; 505 sc->rec_page_start = ED_TXBUF_SIZE; 506 } else { 507 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2); 508 sc->txb_cnt = 2; 509 sc->rec_page_start = ED_TXBUF_SIZE * 2; 510 } 511 sc->mem_size = memsize; 512 sc->mem_end = sc->mem_start + memsize; 513 sc->rec_page_stop = memsize / ED_PAGE_SIZE; 514 sc->tx_page_start = ED_WD_PAGE_OFFSET; 515 516 /* 517 * Get station address from on-board ROM 518 */ 519 for (i = 0; i < ETHER_ADDR_LEN; ++i) 520 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 521 522 /* 523 * Set upper address bits and 8/16 bit access to shared memory 524 */ 525 if (isa16bit) { 526 if (sc->is790) { 527 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 528 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN); 529 } else { 530 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 531 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN | 532 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 533 } 534 } else { 535 if (((sc->type & ED_WD_SOFTCONFIG) || 536#ifdef TOSH_ETHER 537 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 538#endif 539 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 540 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 541 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 542 } 543 } 544 545 /* 546 * Set address and enable interface shared memory. 547 */ 548 if (!sc->is790) { 549#ifdef TOSH_ETHER 550 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 551 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 552 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 553 554#else 555 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 556 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 557#endif 558 sc->cr_proto = ED_CR_RD2; 559 } else { 560 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 561 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80)); 562 outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 563 ((kvtop(sc->mem_start) >> 11) & 0x40) | 564 (inb(sc->asic_addr + 0x0b) & 0xb0)); 565 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80)); 566 sc->cr_proto = 0; 567 } 568 569#if 0 570 printf("starting memory performance test at 0x%x, size %d...\n", 571 sc->mem_start, memsize*16384); 572 for (i = 0; i < 16384; i++) 573 bzero(sc->mem_start, memsize); 574 printf("***DONE***\n"); 575#endif 576 577 /* 578 * Now zero memory and verify that it is clear 579 */ 580 bzero(sc->mem_start, memsize); 581 582 for (i = 0; i < memsize; ++i) { 583 if (sc->mem_start[i]) { 584 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 585 isa_dev->id_unit, kvtop(sc->mem_start + i)); 586 587 /* 588 * Disable 16 bit access to shared memory 589 */ 590 if (isa16bit) { 591 if (sc->is790) { 592 outb(sc->asic_addr + ED_WD_MSR, 0x00); 593 } 594 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 595 ~ED_WD_LAAR_M16EN)); 596 } 597 return (0); 598 } 599 } 600 601 /* 602 * Disable 16bit access to shared memory - we leave it 603 * disabled so that 1) machines reboot properly when the board 604 * is set 16 bit mode and there are conflicting 8bit 605 * devices/ROMS in the same 128k address space as this boards 606 * shared memory. and 2) so that other 8 bit devices with 607 * shared memory can be used in this 128k region, too. 608 */ 609 if (isa16bit) { 610 if (sc->is790) { 611 outb(sc->asic_addr + ED_WD_MSR, 0x00); 612 } 613 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 614 ~ED_WD_LAAR_M16EN)); 615 } 616 return (ED_WD_IO_PORTS); 617} 618 619/* 620 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 621 */ 622int 623ed_probe_3Com(isa_dev) 624 struct isa_device *isa_dev; 625{ 626 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 627 int i; 628 u_int memsize; 629 u_char isa16bit; 630 631 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 632 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 633 634 /* 635 * Verify that the kernel configured I/O address matches the board 636 * configured address 637 */ 638 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 639 case ED_3COM_BCFR_300: 640 if (isa_dev->id_iobase != 0x300) 641 return (0); 642 break; 643 case ED_3COM_BCFR_310: 644 if (isa_dev->id_iobase != 0x310) 645 return (0); 646 break; 647 case ED_3COM_BCFR_330: 648 if (isa_dev->id_iobase != 0x330) 649 return (0); 650 break; 651 case ED_3COM_BCFR_350: 652 if (isa_dev->id_iobase != 0x350) 653 return (0); 654 break; 655 case ED_3COM_BCFR_250: 656 if (isa_dev->id_iobase != 0x250) 657 return (0); 658 break; 659 case ED_3COM_BCFR_280: 660 if (isa_dev->id_iobase != 0x280) 661 return (0); 662 break; 663 case ED_3COM_BCFR_2A0: 664 if (isa_dev->id_iobase != 0x2a0) 665 return (0); 666 break; 667 case ED_3COM_BCFR_2E0: 668 if (isa_dev->id_iobase != 0x2e0) 669 return (0); 670 break; 671 default: 672 return (0); 673 } 674 675 /* 676 * Verify that the kernel shared memory address matches the board 677 * configured address. 678 */ 679 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 680 case ED_3COM_PCFR_DC000: 681 if (kvtop(isa_dev->id_maddr) != 0xdc000) 682 return (0); 683 break; 684 case ED_3COM_PCFR_D8000: 685 if (kvtop(isa_dev->id_maddr) != 0xd8000) 686 return (0); 687 break; 688 case ED_3COM_PCFR_CC000: 689 if (kvtop(isa_dev->id_maddr) != 0xcc000) 690 return (0); 691 break; 692 case ED_3COM_PCFR_C8000: 693 if (kvtop(isa_dev->id_maddr) != 0xc8000) 694 return (0); 695 break; 696 default: 697 return (0); 698 } 699 700 701 /* 702 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 703 * sequence because it'll lock up if the cable isn't connected if we 704 * don't. 705 */ 706 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 707 708 /* 709 * Wait for a while, then un-reset it 710 */ 711 DELAY(50); 712 713 /* 714 * The 3Com ASIC defaults to rather strange settings for the CR after 715 * a reset - it's important to set it again after the following outb 716 * (this is done when we map the PROM below). 717 */ 718 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 719 720 /* 721 * Wait a bit for the NIC to recover from the reset 722 */ 723 DELAY(5000); 724 725 sc->vendor = ED_VENDOR_3COM; 726 sc->type_str = "3c503"; 727 sc->mem_shared = 1; 728 sc->cr_proto = ED_CR_RD2; 729 730 /* 731 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 732 * to it. 733 */ 734 memsize = 8192; 735 736 /* 737 * Get station address from on-board ROM 738 */ 739 740 /* 741 * First, map ethernet address PROM over the top of where the NIC 742 * registers normally appear. 743 */ 744 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 745 746 for (i = 0; i < ETHER_ADDR_LEN; ++i) 747 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 748 749 /* 750 * Unmap PROM - select NIC registers. The proper setting of the 751 * tranceiver is set in ed_init so that the attach code is given a 752 * chance to set the default based on a compile-time config option 753 */ 754 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 755 756 /* 757 * Determine if this is an 8bit or 16bit board 758 */ 759 760 /* 761 * select page 0 registers 762 */ 763 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 764 765 /* 766 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 767 * board. 768 */ 769 outb(sc->nic_addr + ED_P0_DCR, 0); 770 771 /* 772 * select page 2 registers 773 */ 774 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 775 776 /* 777 * The 3c503 forces the WTS bit to a one if this is a 16bit board 778 */ 779 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 780 isa16bit = 1; 781 else 782 isa16bit = 0; 783 784 /* 785 * select page 0 registers 786 */ 787 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 788 789 sc->mem_start = (caddr_t) isa_dev->id_maddr; 790 sc->mem_size = memsize; 791 sc->mem_end = sc->mem_start + memsize; 792 793 /* 794 * We have an entire 8k window to put the transmit buffers on the 795 * 16bit boards. But since the 16bit 3c503's shared memory is only 796 * fast enough to overlap the loading of one full-size packet, trying 797 * to load more than 2 buffers can actually leave the transmitter idle 798 * during the load. So 2 seems the best value. (Although a mix of 799 * variable-sized packets might change this assumption. Nonetheless, 800 * we optimize for linear transfers of same-size packets.) 801 */ 802 if (isa16bit) { 803 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 804 sc->txb_cnt = 1; 805 else 806 sc->txb_cnt = 2; 807 808 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 809 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 810 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 811 ED_3COM_RX_PAGE_OFFSET_16BIT; 812 sc->mem_ring = sc->mem_start; 813 } else { 814 sc->txb_cnt = 1; 815 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 816 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 817 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 818 ED_3COM_TX_PAGE_OFFSET_8BIT; 819 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 820 } 821 822 sc->isa16bit = isa16bit; 823 824 /* 825 * Initialize GA page start/stop registers. Probably only needed if 826 * doing DMA, but what the hell. 827 */ 828 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 829 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 830 831 /* 832 * Set IRQ. 3c503 only allows a choice of irq 2-5. 833 */ 834 switch (isa_dev->id_irq) { 835 case IRQ2: 836 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 837 break; 838 case IRQ3: 839 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 840 break; 841 case IRQ4: 842 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 843 break; 844 case IRQ5: 845 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 846 break; 847 default: 848 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n", 849 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 850 return (0); 851 } 852 853 /* 854 * Initialize GA configuration register. Set bank and enable shared 855 * mem. 856 */ 857 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 858 ED_3COM_GACFR_MBS0); 859 860 /* 861 * Initialize "Vector Pointer" registers. These gawd-awful things are 862 * compared to 20 bits of the address on ISA, and if they match, the 863 * shared memory is disabled. We set them to 0xffff0...allegedly the 864 * reset vector. 865 */ 866 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 867 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 868 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 869 870 /* 871 * Zero memory and verify that it is clear 872 */ 873 bzero(sc->mem_start, memsize); 874 875 for (i = 0; i < memsize; ++i) 876 if (sc->mem_start[i]) { 877 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 878 isa_dev->id_unit, kvtop(sc->mem_start + i)); 879 return (0); 880 } 881 isa_dev->id_msize = memsize; 882 return (ED_3COM_IO_PORTS); 883} 884 885/* 886 * Probe and vendor-specific initialization routine for NE1000/2000 boards 887 */ 888int 889ed_probe_Novell(isa_dev) 890 struct isa_device *isa_dev; 891{ 892 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 893 u_int memsize, n; 894 u_char romdata[16], tmp; 895 static char test_pattern[32] = "THIS is A memory TEST pattern"; 896 char test_buffer[32]; 897 898 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET; 899 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET; 900 901 /* XXX - do Novell-specific probe here */ 902 903 /* Reset the board */ 904#ifdef GWETHER 905 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 906 DELAY(200); 907#endif /* GWETHER */ 908 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 909 910 /* 911 * I don't know if this is necessary; probably cruft leftover from 912 * Clarkson packet driver code. Doesn't do a thing on the boards I've 913 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 914 * non-invasive...but some boards don't seem to reset and I don't have 915 * complete documentation on what the 'right' thing to do is...so we 916 * do the invasive thing for now. Yuck.] 917 */ 918 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 919 DELAY(5000); 920 921 /* 922 * This is needed because some NE clones apparently don't reset the 923 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 924 * - this makes the probe invasive! ...Done against my better 925 * judgement. -DLG 926 */ 927 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 928 929 DELAY(5000); 930 931 /* Make sure that we really have an 8390 based board */ 932 if (!ed_probe_generic8390(sc)) 933 return (0); 934 935 sc->vendor = ED_VENDOR_NOVELL; 936 sc->mem_shared = 0; 937 sc->cr_proto = ED_CR_RD2; 938 isa_dev->id_maddr = 0; 939 940 /* 941 * Test the ability to read and write to the NIC memory. This has the 942 * side affect of determining if this is an NE1000 or an NE2000. 943 */ 944 945 /* 946 * This prevents packets from being stored in the NIC memory when the 947 * readmem routine turns on the start bit in the CR. 948 */ 949 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 950 951 /* Temporarily initialize DCR for byte operations */ 952 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 953 954 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 955 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 956 957 sc->isa16bit = 0; 958 959 /* 960 * Write a test pattern in byte mode. If this fails, then there 961 * probably isn't any memory at 8k - which likely means that the board 962 * is an NE2000. 963 */ 964 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 965 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 966 967 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 968 /* not an NE1000 - try NE2000 */ 969 970 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 971 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 972 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 973 974 sc->isa16bit = 1; 975 976 /* 977 * Write a test pattern in word mode. If this also fails, then 978 * we don't know what this board is. 979 */ 980 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 981 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 982 983 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 984 return (0); /* not an NE2000 either */ 985 986 sc->type = ED_TYPE_NE2000; 987 sc->type_str = "NE2000"; 988 } else { 989 sc->type = ED_TYPE_NE1000; 990 sc->type_str = "NE1000"; 991 } 992 993 /* 8k of memory plus an additional 8k if 16bit */ 994 memsize = 8192 + sc->isa16bit * 8192; 995 996#if 0 /* probably not useful - NE boards only come two ways */ 997 /* allow kernel config file overrides */ 998 if (isa_dev->id_msize) 999 memsize = isa_dev->id_msize; 1000#endif 1001 1002 sc->mem_size = memsize; 1003 1004 /* NIC memory doesn't start at zero on an NE board */ 1005 /* The start address is tied to the bus width */ 1006 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1007 sc->mem_end = sc->mem_start + memsize; 1008 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1009 1010#ifdef GWETHER 1011 { 1012 int x, i, mstart = 0, msize = 0; 1013 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1014 1015 for (i = 0; i < ED_PAGE_SIZE; i++) 1016 pbuf0[i] = 0; 1017 1018 /* Clear all the memory. */ 1019 for (x = 1; x < 256; x++) 1020 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1021 1022 /* Search for the start of RAM. */ 1023 for (x = 1; x < 256; x++) { 1024 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1025 if (memcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1026 for (i = 0; i < ED_PAGE_SIZE; i++) 1027 pbuf[i] = 255 - x; 1028 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1029 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1030 if (memcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1031 mstart = x * ED_PAGE_SIZE; 1032 msize = ED_PAGE_SIZE; 1033 break; 1034 } 1035 } 1036 } 1037 1038 if (mstart == 0) { 1039 printf("ed%d: Cannot find start of RAM.\n", isa_dev->id_unit); 1040 return 0; 1041 } 1042 /* Search for the start of RAM. */ 1043 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1044 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1045 if (memcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1046 for (i = 0; i < ED_PAGE_SIZE; i++) 1047 pbuf[i] = 255 - x; 1048 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1049 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1050 if (memcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1051 msize += ED_PAGE_SIZE; 1052 else { 1053 break; 1054 } 1055 } else { 1056 break; 1057 } 1058 } 1059 1060 if (msize == 0) { 1061 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", isa_dev->id_unit, mstart, x); 1062 return 0; 1063 } 1064 printf("ed%d: RAM start at %d, size : %d.\n", isa_dev->id_unit, mstart, msize); 1065 1066 sc->mem_size = msize; 1067 sc->mem_start = (char *) mstart; 1068 sc->mem_end = (char *) (msize + mstart); 1069 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1070 } 1071#endif /* GWETHER */ 1072 1073 /* 1074 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1075 * otherwise). 1076 */ 1077 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1078 sc->txb_cnt = 1; 1079 else 1080 sc->txb_cnt = 2; 1081 1082 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1083 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1084 1085 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1086 1087 ed_pio_readmem(sc, 0, romdata, 16); 1088 for (n = 0; n < ETHER_ADDR_LEN; n++) 1089 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1090 1091#ifdef GWETHER 1092 if (sc->arpcom.ac_enaddr[2] == 0x86) 1093 sc->type_str = "Gateway AT"; 1094#endif /* GWETHER */ 1095 1096 /* clear any pending interrupts that might have occurred above */ 1097 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1098 1099 return (ED_NOVELL_IO_PORTS); 1100} 1101 1102/* 1103 * Install interface into kernel networking data structures 1104 */ 1105int 1106ed_attach(isa_dev) 1107 struct isa_device *isa_dev; 1108{ 1109 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1110 struct ifnet *ifp = &sc->arpcom.ac_if; 1111 1112 /* 1113 * Set interface to stopped condition (reset) 1114 */ 1115 ed_stop(isa_dev->id_unit); 1116 1117 /* 1118 * Initialize ifnet structure 1119 */ 1120 ifp->if_unit = isa_dev->id_unit; 1121 ifp->if_name = "ed"; 1122 ifp->if_init = ed_init; 1123 ifp->if_output = ether_output; 1124 ifp->if_start = ed_start; 1125 ifp->if_ioctl = ed_ioctl; 1126 ifp->if_reset = ed_reset; 1127 ifp->if_watchdog = ed_watchdog; 1128 1129 /* 1130 * Set default state for ALTPHYS flag (used to disable the tranceiver 1131 * for AUI operation), based on compile-time config option. 1132 */ 1133 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER) 1134 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 1135 IFF_MULTICAST | IFF_ALTPHYS); 1136 else 1137 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 1138 IFF_MULTICAST); 1139 1140 /* 1141 * Attach the interface 1142 */ 1143 if_attach(ifp); 1144 ed_registerdev(isa_dev, sc->type_str ? sc->type_str : "Ethernet adapter"); 1145 1146 /* 1147 * Print additional info when attached 1148 */ 1149 printf("ed%d: address %s, ", isa_dev->id_unit, 1150 ether_sprintf(sc->arpcom.ac_enaddr)); 1151 1152 if (sc->type_str && (*sc->type_str != 0)) 1153 printf("type %s ", sc->type_str); 1154 else 1155 printf("type unknown (0x%x) ", sc->type); 1156 1157 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1158 1159 printf("%s\n", ((sc->vendor == ED_VENDOR_3COM) && 1160 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1161 1162 /* 1163 * If BPF is in the kernel, call the attach for it 1164 */ 1165#if NBPFILTER > 0 1166 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 1167#endif 1168 return 1; 1169} 1170 1171/* 1172 * Reset interface. 1173 */ 1174void 1175ed_reset(unit) 1176 int unit; 1177{ 1178 int s; 1179 1180 s = splimp(); 1181 1182 /* 1183 * Stop interface and re-initialize. 1184 */ 1185 ed_stop(unit); 1186 ed_init(unit); 1187 1188 (void) splx(s); 1189} 1190 1191/* 1192 * Take interface offline. 1193 */ 1194void 1195ed_stop(unit) 1196 int unit; 1197{ 1198 struct ed_softc *sc = &ed_softc[unit]; 1199 int n = 5000; 1200 1201 /* 1202 * Stop everything on the interface, and select page 0 registers. 1203 */ 1204 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1205 1206 /* 1207 * Wait for interface to enter stopped state, but limit # of checks to 1208 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1209 * just in case it's an old one. 1210 */ 1211 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1212} 1213 1214/* 1215 * Device timeout/watchdog routine. Entered if the device neglects to 1216 * generate an interrupt after a transmit has been started on it. 1217 */ 1218void 1219ed_watchdog(unit) 1220 int unit; 1221{ 1222 struct ed_softc *sc = &ed_softc[unit]; 1223 1224 log(LOG_ERR, "ed%d: device timeout\n", unit); 1225 ++sc->arpcom.ac_if.if_oerrors; 1226 1227 ed_reset(unit); 1228} 1229 1230/* 1231 * Initialize device. 1232 */ 1233void 1234ed_init(unit) 1235 int unit; 1236{ 1237 struct ed_softc *sc = &ed_softc[unit]; 1238 struct ifnet *ifp = &sc->arpcom.ac_if; 1239 int i, s; 1240 1241 1242 /* address not known */ 1243 if (ifp->if_addrlist == (struct ifaddr *) 0) 1244 return; 1245 1246 /* 1247 * Initialize the NIC in the exact order outlined in the NS manual. 1248 * This init procedure is "mandatory"...don't change what or when 1249 * things happen. 1250 */ 1251 s = splimp(); 1252 1253 /* reset transmitter flags */ 1254 sc->xmit_busy = 0; 1255 sc->arpcom.ac_if.if_timer = 0; 1256 1257 sc->txb_inuse = 0; 1258 sc->txb_new = 0; 1259 sc->txb_next_tx = 0; 1260 1261 /* This variable is used below - don't move this assignment */ 1262 sc->next_packet = sc->rec_page_start + 1; 1263 1264 /* 1265 * Set interface for page 0, Remote DMA complete, Stopped 1266 */ 1267 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1268 1269 if (sc->isa16bit) { 1270 1271 /* 1272 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1273 * order=80x86, word-wide DMA xfers, 1274 */ 1275 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1276 } else { 1277 1278 /* 1279 * Same as above, but byte-wide DMA xfers 1280 */ 1281 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1282 } 1283 1284 /* 1285 * Clear Remote Byte Count Registers 1286 */ 1287 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1288 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1289 1290 /* 1291 * For the moment, don't store incoming packets in memory. 1292 */ 1293 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1294 1295 /* 1296 * Place NIC in internal loopback mode 1297 */ 1298 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1299 1300 /* 1301 * Initialize transmit/receive (ring-buffer) Page Start 1302 */ 1303 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1304 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1305 /* Set lower bits of byte addressable framing to 0 */ 1306 if (sc->is790) 1307 outb(sc->nic_addr + 0x09, 0); 1308 1309 /* 1310 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1311 */ 1312 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1313 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1314 1315 /* 1316 * Clear all interrupts. A '1' in each bit position clears the 1317 * corresponding flag. 1318 */ 1319 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1320 1321 /* 1322 * Enable the following interrupts: receive/transmit complete, 1323 * receive/transmit error, and Receiver OverWrite. 1324 * 1325 * Counter overflow and Remote DMA complete are *not* enabled. 1326 */ 1327 outb(sc->nic_addr + ED_P0_IMR, 1328 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1329 1330 /* 1331 * Program Command Register for page 1 1332 */ 1333 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1334 1335 /* 1336 * Copy out our station address 1337 */ 1338 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1339 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1340 1341 /* 1342 * Set Current Page pointer to next_packet (initialized above) 1343 */ 1344 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1345 1346 /* 1347 * Program Receiver Configuration Register and multicast filter. CR is 1348 * set to page 0 on return. 1349 */ 1350 ed_setrcr(ifp, sc); 1351 1352 /* 1353 * Take interface out of loopback 1354 */ 1355 outb(sc->nic_addr + ED_P0_TCR, 0); 1356 1357 /* 1358 * If this is a 3Com board, the tranceiver must be software enabled 1359 * (there is no settable hardware default). 1360 */ 1361 if (sc->vendor == ED_VENDOR_3COM) { 1362 if (ifp->if_flags & IFF_ALTPHYS) { 1363 outb(sc->asic_addr + ED_3COM_CR, 0); 1364 } else { 1365 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1366 } 1367 } 1368 1369 /* 1370 * Set 'running' flag, and clear output active flag. 1371 */ 1372 ifp->if_flags |= IFF_RUNNING; 1373 ifp->if_flags &= ~IFF_OACTIVE; 1374 1375 /* 1376 * ...and attempt to start output 1377 */ 1378 ed_start(ifp); 1379 1380 (void) splx(s); 1381} 1382 1383/* 1384 * This routine actually starts the transmission on the interface 1385 */ 1386static inline void 1387ed_xmit(ifp) 1388 struct ifnet *ifp; 1389{ 1390 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1391 unsigned short len; 1392 1393 len = sc->txb_len[sc->txb_next_tx]; 1394 1395 /* 1396 * Set NIC for page 0 register access 1397 */ 1398 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1399 1400 /* 1401 * Set TX buffer start page 1402 */ 1403 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 1404 sc->txb_next_tx * ED_TXBUF_SIZE); 1405 1406 /* 1407 * Set TX length 1408 */ 1409 outb(sc->nic_addr + ED_P0_TBCR0, len); 1410 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 1411 1412 /* 1413 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 1414 */ 1415 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 1416 sc->xmit_busy = 1; 1417 1418 /* 1419 * Point to next transmit buffer slot and wrap if necessary. 1420 */ 1421 sc->txb_next_tx++; 1422 if (sc->txb_next_tx == sc->txb_cnt) 1423 sc->txb_next_tx = 0; 1424 1425 /* 1426 * Set a timer just in case we never hear from the board again 1427 */ 1428 ifp->if_timer = 2; 1429} 1430 1431/* 1432 * Start output on interface. 1433 * We make two assumptions here: 1434 * 1) that the current priority is set to splimp _before_ this code 1435 * is called *and* is returned to the appropriate priority after 1436 * return 1437 * 2) that the IFF_OACTIVE flag is checked before this code is called 1438 * (i.e. that the output part of the interface is idle) 1439 */ 1440void 1441ed_start(ifp) 1442 struct ifnet *ifp; 1443{ 1444 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1445 struct mbuf *m0, *m; 1446 caddr_t buffer; 1447 int len; 1448 1449outloop: 1450 1451 /* 1452 * First, see if there are buffered packets and an idle transmitter - 1453 * should never happen at this point. 1454 */ 1455 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 1456 printf("ed: packets buffered, but transmitter idle\n"); 1457 ed_xmit(ifp); 1458 } 1459 1460 /* 1461 * See if there is room to put another packet in the buffer. 1462 */ 1463 if (sc->txb_inuse == sc->txb_cnt) { 1464 1465 /* 1466 * No room. Indicate this to the outside world and exit. 1467 */ 1468 ifp->if_flags |= IFF_OACTIVE; 1469 return; 1470 } 1471 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 1472 if (m == 0) { 1473 1474 /* 1475 * We are using the !OACTIVE flag to indicate to the outside 1476 * world that we can accept an additional packet rather than 1477 * that the transmitter is _actually_ active. Indeed, the 1478 * transmitter may be active, but if we haven't filled all the 1479 * buffers with data then we still want to accept more. 1480 */ 1481 ifp->if_flags &= ~IFF_OACTIVE; 1482 return; 1483 } 1484 1485 /* 1486 * Copy the mbuf chain into the transmit buffer 1487 */ 1488 1489 m0 = m; 1490 1491 /* txb_new points to next open buffer slot */ 1492 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 1493 1494 if (sc->mem_shared) { 1495 1496 /* 1497 * Special case setup for 16 bit boards... 1498 */ 1499 if (sc->isa16bit) { 1500 switch (sc->vendor) { 1501 1502 /* 1503 * For 16bit 3Com boards (which have 16k of 1504 * memory), we have the xmit buffers in a 1505 * different page of memory ('page 0') - so 1506 * change pages. 1507 */ 1508 case ED_VENDOR_3COM: 1509 outb(sc->asic_addr + ED_3COM_GACFR, 1510 ED_3COM_GACFR_RSEL); 1511 break; 1512 1513 /* 1514 * Enable 16bit access to shared memory on 1515 * WD/SMC boards. 1516 */ 1517 case ED_VENDOR_WD_SMC:{ 1518 outb(sc->asic_addr + ED_WD_LAAR, 1519 (sc->wd_laar_proto | ED_WD_LAAR_M16EN)); 1520 if (sc->is790) { 1521 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 1522 } 1523 break; 1524 } 1525 } 1526 } 1527 for (len = 0; m != 0; m = m->m_next) { 1528 bcopy(mtod(m, caddr_t), buffer, m->m_len); 1529 buffer += m->m_len; 1530 len += m->m_len; 1531 } 1532 1533 /* 1534 * Restore previous shared memory access 1535 */ 1536 if (sc->isa16bit) { 1537 switch (sc->vendor) { 1538 case ED_VENDOR_3COM: 1539 outb(sc->asic_addr + ED_3COM_GACFR, 1540 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 1541 break; 1542 case ED_VENDOR_WD_SMC:{ 1543 if (sc->is790) { 1544 outb(sc->asic_addr + ED_WD_MSR, 0x00); 1545 } 1546 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 1547 break; 1548 } 1549 } 1550 } 1551 } else { 1552 len = ed_pio_write_mbufs(sc, m, buffer); 1553 } 1554 1555 sc->txb_len[sc->txb_new] = max(len, ETHER_MIN_LEN); 1556 1557 sc->txb_inuse++; 1558 1559 /* 1560 * Point to next buffer slot and wrap if necessary. 1561 */ 1562 sc->txb_new++; 1563 if (sc->txb_new == sc->txb_cnt) 1564 sc->txb_new = 0; 1565 1566 if (sc->xmit_busy == 0) 1567 ed_xmit(ifp); 1568 1569 /* 1570 * Tap off here if there is a bpf listener. 1571 */ 1572#if NBPFILTER > 0 1573 if (sc->bpf) { 1574 bpf_mtap(sc->bpf, m0); 1575 } 1576#endif 1577 1578 m_freem(m0); 1579 1580 /* 1581 * Loop back to the top to possibly buffer more packets 1582 */ 1583 goto outloop; 1584} 1585 1586/* 1587 * Ethernet interface receiver interrupt. 1588 */ 1589static inline void 1590ed_rint(unit) 1591 int unit; 1592{ 1593 register struct ed_softc *sc = &ed_softc[unit]; 1594 u_char boundry; 1595 u_short len; 1596 struct ed_ring packet_hdr; 1597 char *packet_ptr; 1598 1599 /* 1600 * Set NIC to page 1 registers to get 'current' pointer 1601 */ 1602 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 1603 1604 /* 1605 * 'sc->next_packet' is the logical beginning of the ring-buffer - 1606 * i.e. it points to where new data has been buffered. The 'CURR' 1607 * (current) register points to the logical end of the ring-buffer - 1608 * i.e. it points to where additional new data will be added. We loop 1609 * here until the logical beginning equals the logical end (or in 1610 * other words, until the ring-buffer is empty). 1611 */ 1612 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 1613 1614 /* get pointer to this buffer's header structure */ 1615 packet_ptr = sc->mem_ring + 1616 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 1617 1618 /* 1619 * The byte count includes a 4 byte header that was added by 1620 * the NIC. 1621 */ 1622 if (sc->mem_shared) 1623 packet_hdr = *(struct ed_ring *) packet_ptr; 1624 else 1625 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr, 1626 sizeof(packet_hdr)); 1627 len = packet_hdr.count; 1628 if (len > ETHER_MAX_LEN) { 1629 /* 1630 * Length is a wild value. There's a good chance that 1631 * this was caused by the NIC being old and buggy. 1632 * The bug is that the length low byte is duplicated in 1633 * the high byte. Try to recalculate the length based on 1634 * the pointer to the next packet. 1635 */ 1636 /* 1637 * NOTE: sc->next_packet is pointing at the current packet. 1638 */ 1639 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 1640 if (packet_hdr.next_packet >= sc->next_packet) { 1641 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 1642 } else { 1643 len += ((packet_hdr.next_packet - sc->rec_page_start) + 1644 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 1645 } 1646 } 1647 /* 1648 * Be fairly liberal about what we allow as a "reasonable" length 1649 * so that a [crufty] packet will make it to BPF (and can thus 1650 * be analyzed). Note that all that is really important is that 1651 * we have a length that will fit into one mbuf cluster or less; 1652 * the upper layer protocols can then figure out the length from 1653 * their own length field(s). 1654 */ 1655 if ((len <= MCLBYTES) && 1656 (packet_hdr.next_packet >= sc->rec_page_start) && 1657 (packet_hdr.next_packet < sc->rec_page_stop)) { 1658 /* 1659 * Go get packet. 1660 */ 1661 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 1662 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 1663 ++sc->arpcom.ac_if.if_ipackets; 1664 } else { 1665 /* 1666 * Really BAD. The ring pointers are corrupted. 1667 */ 1668 log(LOG_ERR, 1669 "ed%d: NIC memory corrupt - invalid packet length %d\n", 1670 unit, len); 1671 ++sc->arpcom.ac_if.if_ierrors; 1672 ed_reset(unit); 1673 return; 1674 } 1675 1676 /* 1677 * Update next packet pointer 1678 */ 1679 sc->next_packet = packet_hdr.next_packet; 1680 1681 /* 1682 * Update NIC boundry pointer - being careful to keep it one 1683 * buffer behind. (as recommended by NS databook) 1684 */ 1685 boundry = sc->next_packet - 1; 1686 if (boundry < sc->rec_page_start) 1687 boundry = sc->rec_page_stop - 1; 1688 1689 /* 1690 * Set NIC to page 0 registers to update boundry register 1691 */ 1692 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1693 1694 outb(sc->nic_addr + ED_P0_BNRY, boundry); 1695 1696 /* 1697 * Set NIC to page 1 registers before looping to top (prepare 1698 * to get 'CURR' current pointer) 1699 */ 1700 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 1701 } 1702} 1703 1704/* 1705 * Ethernet interface interrupt processor 1706 */ 1707void 1708edintr(unit) 1709 int unit; 1710{ 1711 struct ed_softc *sc = &ed_softc[unit]; 1712 u_char isr; 1713 1714 /* 1715 * Set NIC to page 0 registers 1716 */ 1717 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1718 1719 /* 1720 * loop until there are no more new interrupts 1721 */ 1722 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 1723 1724 /* 1725 * reset all the bits that we are 'acknowledging' by writing a 1726 * '1' to each bit position that was set (writing a '1' 1727 * *clears* the bit) 1728 */ 1729 outb(sc->nic_addr + ED_P0_ISR, isr); 1730 1731 /* 1732 * Handle transmitter interrupts. Handle these first because 1733 * the receiver will reset the board under some conditions. 1734 */ 1735 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 1736 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 1737 1738 /* 1739 * Check for transmit error. If a TX completed with an 1740 * error, we end up throwing the packet away. Really 1741 * the only error that is possible is excessive 1742 * collisions, and in this case it is best to allow 1743 * the automatic mechanisms of TCP to backoff the 1744 * flow. Of course, with UDP we're screwed, but this 1745 * is expected when a network is heavily loaded. 1746 */ 1747 (void) inb(sc->nic_addr + ED_P0_TSR); 1748 if (isr & ED_ISR_TXE) { 1749 1750 /* 1751 * Excessive collisions (16) 1752 */ 1753 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT) 1754 && (collisions == 0)) { 1755 1756 /* 1757 * When collisions total 16, the 1758 * P0_NCR will indicate 0, and the 1759 * TSR_ABT is set. 1760 */ 1761 collisions = 16; 1762 } 1763 1764 /* 1765 * update output errors counter 1766 */ 1767 ++sc->arpcom.ac_if.if_oerrors; 1768 } else { 1769 1770 /* 1771 * Update total number of successfully 1772 * transmitted packets. 1773 */ 1774 ++sc->arpcom.ac_if.if_opackets; 1775 } 1776 1777 /* 1778 * reset tx busy and output active flags 1779 */ 1780 sc->xmit_busy = 0; 1781 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1782 1783 /* 1784 * clear watchdog timer 1785 */ 1786 sc->arpcom.ac_if.if_timer = 0; 1787 1788 /* 1789 * Add in total number of collisions on last 1790 * transmission. 1791 */ 1792 sc->arpcom.ac_if.if_collisions += collisions; 1793 1794 /* 1795 * Decrement buffer in-use count if not zero (can only 1796 * be zero if a transmitter interrupt occured while 1797 * not actually transmitting). If data is ready to 1798 * transmit, start it transmitting, otherwise defer 1799 * until after handling receiver 1800 */ 1801 if (sc->txb_inuse && --sc->txb_inuse) 1802 ed_xmit(&sc->arpcom.ac_if); 1803 } 1804 1805 /* 1806 * Handle receiver interrupts 1807 */ 1808 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 1809 1810 /* 1811 * Overwrite warning. In order to make sure that a 1812 * lockup of the local DMA hasn't occurred, we reset 1813 * and re-init the NIC. The NSC manual suggests only a 1814 * partial reset/re-init is necessary - but some chips 1815 * seem to want more. The DMA lockup has been seen 1816 * only with early rev chips - Methinks this bug was 1817 * fixed in later revs. -DG 1818 */ 1819 if (isr & ED_ISR_OVW) { 1820 ++sc->arpcom.ac_if.if_ierrors; 1821#ifdef DIAGNOSTIC 1822 log(LOG_WARNING, 1823 "ed%d: warning - receiver ring buffer overrun\n", 1824 unit); 1825#endif 1826 1827 /* 1828 * Stop/reset/re-init NIC 1829 */ 1830 ed_reset(unit); 1831 } else { 1832 1833 /* 1834 * Receiver Error. One or more of: CRC error, 1835 * frame alignment error FIFO overrun, or 1836 * missed packet. 1837 */ 1838 if (isr & ED_ISR_RXE) { 1839 ++sc->arpcom.ac_if.if_ierrors; 1840#ifdef ED_DEBUG 1841 printf("ed%d: receive error %x\n", unit, 1842 inb(sc->nic_addr + ED_P0_RSR)); 1843#endif 1844 } 1845 1846 /* 1847 * Go get the packet(s) XXX - Doing this on an 1848 * error is dubious because there shouldn't be 1849 * any data to get (we've configured the 1850 * interface to not accept packets with 1851 * errors). 1852 */ 1853 1854 /* 1855 * Enable 16bit access to shared memory first 1856 * on WD/SMC boards. 1857 */ 1858 if (sc->isa16bit && 1859 (sc->vendor == ED_VENDOR_WD_SMC)) { 1860 1861 outb(sc->asic_addr + ED_WD_LAAR, 1862 (sc->wd_laar_proto |= 1863 ED_WD_LAAR_M16EN)); 1864 if (sc->is790) { 1865 outb(sc->asic_addr + ED_WD_MSR, 1866 ED_WD_MSR_MENB); 1867 } 1868 } 1869 ed_rint(unit); 1870 1871 /* disable 16bit access */ 1872 if (sc->isa16bit && 1873 (sc->vendor == ED_VENDOR_WD_SMC)) { 1874 1875 if (sc->is790) { 1876 outb(sc->asic_addr + ED_WD_MSR, 0x00); 1877 } 1878 outb(sc->asic_addr + ED_WD_LAAR, 1879 (sc->wd_laar_proto &= 1880 ~ED_WD_LAAR_M16EN)); 1881 } 1882 } 1883 } 1884 1885 /* 1886 * If it looks like the transmitter can take more data, 1887 * attempt to start output on the interface. This is done 1888 * after handling the receiver to give the receiver priority. 1889 */ 1890 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0) 1891 ed_start(&sc->arpcom.ac_if); 1892 1893 /* 1894 * return NIC CR to standard state: page 0, remote DMA 1895 * complete, start (toggling the TXP bit off, even if was just 1896 * set in the transmit routine, is *okay* - it is 'edge' 1897 * triggered from low to high) 1898 */ 1899 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1900 1901 /* 1902 * If the Network Talley Counters overflow, read them to reset 1903 * them. It appears that old 8390's won't clear the ISR flag 1904 * otherwise - resulting in an infinite loop. 1905 */ 1906 if (isr & ED_ISR_CNT) { 1907 (void) inb(sc->nic_addr + ED_P0_CNTR0); 1908 (void) inb(sc->nic_addr + ED_P0_CNTR1); 1909 (void) inb(sc->nic_addr + ED_P0_CNTR2); 1910 } 1911 } 1912} 1913 1914/* 1915 * Process an ioctl request. This code needs some work - it looks 1916 * pretty ugly. 1917 */ 1918int 1919ed_ioctl(ifp, command, data) 1920 register struct ifnet *ifp; 1921 int command; 1922 caddr_t data; 1923{ 1924 register struct ifaddr *ifa = (struct ifaddr *) data; 1925 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1926 struct ifreq *ifr = (struct ifreq *) data; 1927 int s, error = 0; 1928 1929 s = splimp(); 1930 1931 switch (command) { 1932 1933 case SIOCSIFADDR: 1934 ifp->if_flags |= IFF_UP; 1935 1936 switch (ifa->ifa_addr->sa_family) { 1937#ifdef INET 1938 case AF_INET: 1939 ed_init(ifp->if_unit); /* before arpwhohas */ 1940 arp_ifinit((struct arpcom *)ifp, ifa); 1941 break; 1942#endif 1943#ifdef NS 1944 1945 /* 1946 * XXX - This code is probably wrong 1947 */ 1948 case AF_NS: 1949 { 1950 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr); 1951 1952 if (ns_nullhost(*ina)) 1953 ina->x_host = 1954 *(union ns_host *) (sc->arpcom.ac_enaddr); 1955 else { 1956 bcopy((caddr_t) ina->x_host.c_host, 1957 (caddr_t) sc->arpcom.ac_enaddr, 1958 sizeof(sc->arpcom.ac_enaddr)); 1959 } 1960 1961 /* 1962 * Set new address 1963 */ 1964 ed_init(ifp->if_unit); 1965 break; 1966 } 1967#endif 1968 default: 1969 ed_init(ifp->if_unit); 1970 break; 1971 } 1972 break; 1973 1974 case SIOCGIFADDR: 1975 { 1976 struct sockaddr *sa; 1977 1978 sa = (struct sockaddr *) & ifr->ifr_data; 1979 bcopy((caddr_t) sc->arpcom.ac_enaddr, 1980 (caddr_t) sa->sa_data, ETHER_ADDR_LEN); 1981 } 1982 break; 1983 1984 case SIOCSIFFLAGS: 1985 1986 /* 1987 * If interface is marked down and it is running, then stop it 1988 */ 1989 if (((ifp->if_flags & IFF_UP) == 0) && 1990 (ifp->if_flags & IFF_RUNNING)) { 1991 ed_stop(ifp->if_unit); 1992 ifp->if_flags &= ~IFF_RUNNING; 1993 } else { 1994 1995 /* 1996 * If interface is marked up and it is stopped, then 1997 * start it 1998 */ 1999 if ((ifp->if_flags & IFF_UP) && 2000 ((ifp->if_flags & IFF_RUNNING) == 0)) 2001 ed_init(ifp->if_unit); 2002 } 2003 2004#if NBPFILTER > 0 2005 2006 /* 2007 * Promiscuous flag may have changed, so reprogram the RCR. 2008 */ 2009 ed_setrcr(ifp, sc); 2010#endif 2011 2012 /* 2013 * An unfortunate hack to provide the (required) software 2014 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2015 * disables the tranceiver if set. 2016 */ 2017 if (sc->vendor == ED_VENDOR_3COM) { 2018 if (ifp->if_flags & IFF_ALTPHYS) { 2019 outb(sc->asic_addr + ED_3COM_CR, 0); 2020 } else { 2021 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2022 } 2023 } 2024 break; 2025 2026 case SIOCADDMULTI: 2027 case SIOCDELMULTI: 2028 /* 2029 * Update out multicast list. 2030 */ 2031 error = (command == SIOCADDMULTI) ? 2032 ether_addmulti(ifr, &sc->arpcom) : 2033 ether_delmulti(ifr, &sc->arpcom); 2034 2035 if (error == ENETRESET) { 2036 2037 /* 2038 * Multicast list has changed; set the hardware filter 2039 * accordingly. 2040 */ 2041 ed_setrcr(ifp, sc); 2042 error = 0; 2043 } 2044 break; 2045 2046 case SIOCSIFMTU: 2047 /* 2048 * Set the interface MTU. 2049 */ 2050 if (ifr->ifr_mtu > ETHERMTU) { 2051 error = EINVAL; 2052 } else { 2053 ifp->if_mtu = ifr->ifr_mtu; 2054 } 2055 break; 2056 2057 default: 2058 error = EINVAL; 2059 } 2060 (void) splx(s); 2061 return (error); 2062} 2063 2064/* 2065 * Retreive packet from shared memory and send to the next level up via 2066 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2067 */ 2068static void 2069ed_get_packet(sc, buf, len, multicast) 2070 struct ed_softc *sc; 2071 char *buf; 2072 u_short len; 2073 int multicast; 2074{ 2075 struct ether_header *eh; 2076 struct mbuf *m; 2077 2078 /* Allocate a header mbuf */ 2079 MGETHDR(m, M_DONTWAIT, MT_DATA); 2080 if (m == NULL) 2081 return; 2082 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2083 m->m_pkthdr.len = m->m_len = len; 2084 2085 /* Attach an mbuf cluster */ 2086 MCLGET(m, M_DONTWAIT); 2087 2088 /* Insist on getting a cluster */ 2089 if ((m->m_flags & M_EXT) == 0) { 2090 m_freem(m); 2091 return; 2092 } 2093 2094 /* 2095 * The +2 is to longword align the start of the real packet. 2096 * This is important for NFS. 2097 */ 2098 m->m_data += 2; 2099 eh = mtod(m, struct ether_header *); 2100 2101 /* 2102 * Get packet, including link layer address, from interface. 2103 */ 2104 ed_ring_copy(sc, buf, (char *)eh, len); 2105 2106#if NBPFILTER > 0 2107 2108 /* 2109 * Check if there's a BPF listener on this interface. If so, hand off 2110 * the raw packet to bpf. 2111 */ 2112 if (sc->bpf) { 2113 bpf_mtap(sc->bpf, m); 2114 2115 /* 2116 * Note that the interface cannot be in promiscuous mode if 2117 * there are no BPF listeners. And if we are in promiscuous 2118 * mode, we have to check if this packet is really ours. 2119 */ 2120 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2121 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2122 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2123 m_freem(m); 2124 return; 2125 } 2126 } 2127#endif 2128 2129 /* 2130 * Remove link layer address. 2131 */ 2132 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2133 m->m_data += sizeof(struct ether_header); 2134 2135 ether_input(&sc->arpcom.ac_if, eh, m); 2136 return; 2137} 2138 2139/* 2140 * Supporting routines 2141 */ 2142 2143/* 2144 * Given a NIC memory source address and a host memory destination 2145 * address, copy 'amount' from NIC to host using Programmed I/O. 2146 * The 'amount' is rounded up to a word - okay as long as mbufs 2147 * are word sized. 2148 * This routine is currently Novell-specific. 2149 */ 2150void 2151ed_pio_readmem(sc, src, dst, amount) 2152 struct ed_softc *sc; 2153 unsigned short src; 2154 unsigned char *dst; 2155 unsigned short amount; 2156{ 2157 /* select page 0 registers */ 2158 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2159 2160 /* round up to a word */ 2161 if (amount & 1) 2162 ++amount; 2163 2164 /* set up DMA byte count */ 2165 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2166 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2167 2168 /* set up source address in NIC mem */ 2169 outb(sc->nic_addr + ED_P0_RSAR0, src); 2170 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2171 2172 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2173 2174 if (sc->isa16bit) { 2175 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2176 } else 2177 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2178 2179} 2180 2181/* 2182 * Stripped down routine for writing a linear buffer to NIC memory. 2183 * Only used in the probe routine to test the memory. 'len' must 2184 * be even. 2185 */ 2186void 2187ed_pio_writemem(sc, src, dst, len) 2188 struct ed_softc *sc; 2189 char *src; 2190 unsigned short dst; 2191 unsigned short len; 2192{ 2193 int maxwait = 100; /* about 120us */ 2194 2195 /* select page 0 registers */ 2196 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2197 2198 /* reset remote DMA complete flag */ 2199 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2200 2201 /* set up DMA byte count */ 2202 outb(sc->nic_addr + ED_P0_RBCR0, len); 2203 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2204 2205 /* set up destination address in NIC mem */ 2206 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2207 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2208 2209 /* set remote DMA write */ 2210 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2211 2212 if (sc->isa16bit) 2213 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2214 else 2215 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2216 2217 /* 2218 * Wait for remote DMA complete. This is necessary because on the 2219 * transmit side, data is handled internally by the NIC in bursts and 2220 * we can't start another remote DMA until this one completes. Not 2221 * waiting causes really bad things to happen - like the NIC 2222 * irrecoverably jamming the ISA bus. 2223 */ 2224 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2225} 2226 2227/* 2228 * Write an mbuf chain to the destination NIC memory address using 2229 * programmed I/O. 2230 */ 2231u_short 2232ed_pio_write_mbufs(sc, m, dst) 2233 struct ed_softc *sc; 2234 struct mbuf *m; 2235 unsigned short dst; 2236{ 2237 unsigned short len, dma_len; 2238 struct mbuf *mp; 2239 int maxwait = 100; /* about 120us */ 2240 2241 /* First, count up the total number of bytes to copy */ 2242 for (len = 0, mp = m; mp; mp = mp->m_next) 2243 len += mp->m_len; 2244 2245 dma_len = len; 2246 if (sc->isa16bit && (dma_len & 1)) 2247 dma_len++; 2248 2249 /* select page 0 registers */ 2250 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2251 2252 /* reset remote DMA complete flag */ 2253 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2254 2255 /* set up DMA byte count */ 2256 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 2257 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 2258 2259 /* set up destination address in NIC mem */ 2260 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2261 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2262 2263 /* set remote DMA write */ 2264 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2265 2266 /* 2267 * Transfer the mbuf chain to the NIC memory. 2268 * 16-bit cards require that data be transferred as words, and only words. 2269 * So that case requires some extra code to patch over odd-length mbufs. 2270 */ 2271 2272 if (!sc->isa16bit) { 2273 /* NE1000s are easy */ 2274 while (m) { 2275 if (m->m_len) { 2276 outsb(sc->asic_addr + ED_NOVELL_DATA, 2277 m->m_data, m->m_len); 2278 } 2279 m = m->m_next; 2280 } 2281 } else { 2282 /* NE2000s are a pain */ 2283 unsigned char *data; 2284 int len, wantbyte; 2285 unsigned char savebyte[2]; 2286 2287 wantbyte = 0; 2288 2289 while (m) { 2290 data = mtod(m, caddr_t); 2291 len = m->m_len; 2292 if (len) { 2293 /* finish the last word */ 2294 if (wantbyte) { 2295 savebyte[1] = *data; 2296 outw(sc->asic_addr + ED_NOVELL_DATA, 2297 *((unsigned short *) savebyte)); 2298 data++; 2299 len--; 2300 wantbyte = 0; 2301 } 2302 /* output contiguous words */ 2303 if (len > 1) { 2304 outsw(sc->asic_addr + ED_NOVELL_DATA, 2305 data, len >> 1); 2306 data += len & ~1; 2307 len &= 1; 2308 } 2309 /* save last byte, if necessary */ 2310 if (len == 1) { 2311 savebyte[0] = *data; 2312 wantbyte = 1; 2313 } 2314 } 2315 m = m->m_next; 2316 } 2317 /* spit last byte */ 2318 if (wantbyte) 2319 outw(sc->asic_addr + ED_NOVELL_DATA, 2320 *((unsigned short *) savebyte)); 2321 } 2322 2323 /* 2324 * Wait for remote DMA complete. This is necessary because on the 2325 * transmit side, data is handled internally by the NIC in bursts and 2326 * we can't start another remote DMA until this one completes. Not 2327 * waiting causes really bad things to happen - like the NIC 2328 * irrecoverably jamming the ISA bus. 2329 */ 2330 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2331 2332 if (!maxwait) { 2333 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 2334 sc->arpcom.ac_if.if_unit); 2335 ed_reset(sc->arpcom.ac_if.if_unit); 2336 } 2337 return (len); 2338} 2339 2340/* 2341 * Given a source and destination address, copy 'amount' of a packet from 2342 * the ring buffer into a linear destination buffer. Takes into account 2343 * ring-wrap. 2344 */ 2345static inline char * 2346ed_ring_copy(sc, src, dst, amount) 2347 struct ed_softc *sc; 2348 char *src; 2349 char *dst; 2350 u_short amount; 2351{ 2352 u_short tmp_amount; 2353 2354 /* does copy wrap to lower addr in ring buffer? */ 2355 if (src + amount > sc->mem_end) { 2356 tmp_amount = sc->mem_end - src; 2357 2358 /* copy amount up to end of NIC memory */ 2359 if (sc->mem_shared) 2360 bcopy(src, dst, tmp_amount); 2361 else 2362 ed_pio_readmem(sc, src, dst, tmp_amount); 2363 2364 amount -= tmp_amount; 2365 src = sc->mem_ring; 2366 dst += tmp_amount; 2367 } 2368 if (sc->mem_shared) 2369 bcopy(src, dst, amount); 2370 else 2371 ed_pio_readmem(sc, src, dst, amount); 2372 2373 return (src + amount); 2374} 2375 2376void 2377ed_setrcr(ifp, sc) 2378 struct ifnet *ifp; 2379 struct ed_softc *sc; 2380{ 2381 int i; 2382 2383 /* set page 1 registers */ 2384 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 2385 2386 if (ifp->if_flags & IFF_PROMISC) { 2387 2388 /* 2389 * Reconfigure the multicast filter. 2390 */ 2391 for (i = 0; i < 8; i++) 2392 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff); 2393 2394 /* 2395 * And turn on promiscuous mode. Also enable reception of 2396 * runts and packets with CRC & alignment errors. 2397 */ 2398 /* Set page 0 registers */ 2399 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2400 2401 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 2402 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 2403 } else { 2404 /* set up multicast addresses and filter modes */ 2405 if (ifp->if_flags & IFF_MULTICAST) { 2406 u_long mcaf[2]; 2407 2408 if (ifp->if_flags & IFF_ALLMULTI) { 2409 mcaf[0] = 0xffffffff; 2410 mcaf[1] = 0xffffffff; 2411 } else 2412 ds_getmcaf(sc, mcaf); 2413 2414 /* 2415 * Set multicast filter on chip. 2416 */ 2417 for (i = 0; i < 8; i++) 2418 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]); 2419 2420 /* Set page 0 registers */ 2421 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2422 2423 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 2424 } else { 2425 2426 /* 2427 * Initialize multicast address hashing registers to 2428 * not accept multicasts. 2429 */ 2430 for (i = 0; i < 8; ++i) 2431 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00); 2432 2433 /* Set page 0 registers */ 2434 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2435 2436 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 2437 } 2438 } 2439 2440 /* 2441 * Start interface. 2442 */ 2443 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2444} 2445 2446/* 2447 * Compute crc for ethernet address 2448 */ 2449u_long 2450ds_crc(ep) 2451 u_char *ep; 2452{ 2453#define POLYNOMIAL 0x04c11db6 2454 register u_long crc = 0xffffffffL; 2455 register int carry, i, j; 2456 register u_char b; 2457 2458 for (i = 6; --i >= 0;) { 2459 b = *ep++; 2460 for (j = 8; --j >= 0;) { 2461 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 2462 crc <<= 1; 2463 b >>= 1; 2464 if (carry) 2465 crc = ((crc ^ POLYNOMIAL) | carry); 2466 } 2467 } 2468 return crc; 2469#undef POLYNOMIAL 2470} 2471 2472/* 2473 * Compute the multicast address filter from the 2474 * list of multicast addresses we need to listen to. 2475 */ 2476void 2477ds_getmcaf(sc, mcaf) 2478 struct ed_softc *sc; 2479 u_long *mcaf; 2480{ 2481 register u_int index; 2482 register u_char *af = (u_char *) mcaf; 2483 register struct ether_multi *enm; 2484 register struct ether_multistep step; 2485 2486 mcaf[0] = 0; 2487 mcaf[1] = 0; 2488 2489 ETHER_FIRST_MULTI(step, &sc->arpcom, enm); 2490 while (enm != NULL) { 2491 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2492 mcaf[0] = 0xffffffff; 2493 mcaf[1] = 0xffffffff; 2494 return; 2495 } 2496 index = ds_crc(enm->enm_addrlo, 6) >> 26; 2497 af[index >> 3] |= 1 << (index & 7); 2498 2499 ETHER_NEXT_MULTI(step, enm); 2500 } 2501} 2502